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#include <18F4550.h> |
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#include <16F887.h> |
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#device adc=8 |
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#device adc=8 |
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#FUSES NOWDT //No Watch Dog Timer |
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#FUSES WDT //Watch Dog Timer |
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#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale |
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#FUSES HS //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD) |
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#FUSES INTRC //Internal RC Osc |
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#FUSES PUT //Power Up Timer |
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#FUSES NOPROTECT //Code not protected from reading |
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#FUSES NOBROWNOUT //No brownout reset |
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#FUSES BORV20 //Brownout reset at 2.0V |
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#FUSES MCLR //Master Clear pin enabled |
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#FUSES NOPUT //No Power Up Timer |
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#FUSES NOPROTECT //Code not protected from reading |
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#FUSES NOCPD //No EE protection |
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#FUSES NOCPD //No EE protection |
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#FUSES STVREN //Stack full/underflow will cause reset |
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#FUSES NODEBUG //No Debug mode for ICD |
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#FUSES NOBROWNOUT //No brownout reset |
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#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O |
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#FUSES NOWRT //Program memory not write protected |
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#FUSES NOWRTD //Data EEPROM not write protected |
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#FUSES IESO //Internal External Switch Over mode enabled |
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#FUSES IESO //Internal External Switch Over mode enabled |
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#FUSES FCMEN //Fail-safe clock monitor enabled |
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#FUSES FCMEN //Fail-safe clock monitor enabled |
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#FUSES PBADEN //PORTB pins are configured as analog input channels on RESET |
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#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O |
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#FUSES NOWRTC //configuration not registers write protected |
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#FUSES NODEBUG //No Debug mode for ICD |
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#FUSES NOWRTB //Boot block not write protected |
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#FUSES NOWRT //Program memory not write protected |
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#FUSES NOEBTR //Memory not protected from table reads |
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#FUSES NOEBTRB //Boot block not protected from table reads |
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#FUSES NOCPB //No Boot Block code protection |
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#FUSES MCLR //Master Clear pin enabled |
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#FUSES LPT1OSC //Timer1 configured for low-power operation |
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#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode) |
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#FUSES PLL1 //No PLL PreScaler |
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#FUSES BORV40 //Brownout reset at 4.0V |
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#FUSES CPUDIV1 //No System Clock Postscaler |
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#FUSES USBDIV //USB clock source comes from PLL divide by 2 |
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#FUSES VREGEN //USB voltage regulator enabled |
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#FUSES ICPRT //ICPRT enabled |
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#use delay(clock=8000000) |
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#use delay(clock=8000000,RESTART_WDT) |
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#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8) |
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#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8,restart_wdt) |
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