Rev 3206 Rev 3208
Line 116... Line 116...
116 end entity AtomicCounter; 116 end entity AtomicCounter;
117   117  
118   118  
119 architecture AtomicCounter_a of AtomicCounter is 119 architecture AtomicCounter_a of AtomicCounter is
120   120  
121 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is 121 function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is
122 variable i : integer:=0; 122 variable i : integer:=0;
123 variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); 123 variable mybcd : std_logic_vector(35 downto 0) := (others => '0');
124 variable bint : std_logic_vector(15 downto 0) := bin; 124 variable bint : std_logic_vector(31 downto 0) := bin;
125 begin 125 begin
126 for i in 0 to 15 loop -- repeating 16 times. 126 for i in 0 to 31 loop -- repeating 16 times.
127 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. 127 mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits.
128 mybcd(0) := bint(15); 128 mybcd(0) := bint(31);
129 bint(15 downto 1) := bint(14 downto 0); 129 bint(31 downto 1) := bint(30 downto 0);
130 bint(0) :='0'; 130 bint(0) :='0';
131   131  
132   132  
133 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. 133 if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); 134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
135 end if; 135 end if;
136   136  
137 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. 137 if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); 138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
139 end if; 139 end if;
140   140  
141 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. 141 if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); 142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
143 end if; 143 end if;
144   144  
145 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. 145 if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
146 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); 146 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
147 end if; 147 end if;
148   148  
149 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. 149 if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
150 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); 150 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
151 end if; 151 end if;
152   152  
-   153 if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4.
-   154 mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3);
-   155 end if;
-   156  
-   157 if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4.
-   158 mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3);
-   159 end if;
-   160  
-   161 if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4.
-   162 mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3);
-   163 end if;
-   164  
-   165 if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4.
-   166 mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3);
-   167 end if;
-   168  
153 end loop; 169 end loop;
154 170
155 return mybcd; 171 return mybcd;
156 end to_bcd; 172 end to_bcd;
157   173  
158   174  
159 -- Counters 175 -- Counters
160 -- ---------------- 176 -- ----------------
161   177  
162 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) 178 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
163 signal CounterMaxcount: unsigned(15 downto 0) := "0000000000000000"; -- Main Counter 10 kHz, max. 655.35 MHz (binary) -  
164   179  
165   180  
166 -- LED Display 181 -- LED Display
167 -- ----------- 182 -- -----------
168   183  
169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- Variable for bin/BCD conversion -  
170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input 184 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency 185 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
172 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 186 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
173 signal Enable: std_logic; 187 signal Enable: std_logic;
174 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 188 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
Line 198... Line 212...
198 begin 212 begin
199 213
200 if rising_edge(LO_CLOCK) then 214 if rising_edge(LO_CLOCK) then
201 215
202 if (State = 3) or (State = 0) then 216 if (State = 3) or (State = 0) then
203 if Counter < MAXCOUNT-1 then 217 if DIPSW(7) = '0' then -- Half/Full frequency
204 Counter <= Counter + 1; 218 Counter <= Counter + 1;
205 else 219 else
206 Counter <= (others => '0'); 220 Counter <= Counter + 2;
207 CounterMaxcount <= CounterMaxcount + 1; -  
208 end if; 221 end if;
209 end if; 222 end if;
210 if (State = 1) then 223 if (State = 1) then
211 Freq(15 downto 0) <= std_logic_vector("00"&Counter); 224 Freq(31 downto 0) <= std_logic_vector(Counter);
212 Freq(31 downto 16) <= std_logic_vector(CounterMaxcount); -  
213 end if; 225 end if;
214 if (State = 2) then 226 if (State = 2) then
215 CounterMaxcount <= (others => '0'); -  
216 Counter <= (others => '0'); 227 Counter <= (others => '0');
217 end if; 228 end if;
218 end if; 229 end if;
219   230  
220 end process; 231 end process;
Line 245... Line 256...
245 -- Coding to BCD for LED Display 256 -- Coding to BCD for LED Display
246   257  
247 process (Decko) 258 process (Decko)
248 begin 259 begin
249 if falling_edge(Decko) then 260 if falling_edge(Decko) then
250 if DIPSW(7) = '0' then -  
251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); -- Half frequency -  
252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0); 261 Number(35 downto 0) <= to_bcd(Freq(31 downto 0));
253 else -  
254 NumberPom(15 downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0); -- Full frequency -  
255 NumberPom(35 downto 16) <= to_bcd(Freq(30 downto 15))(19 downto 0); -  
256 end if; -  
257 end if; 262 end if;
258 end process; 263 end process;
259   264  
260 Number(35 downto 0) <= NumberPom(35 downto 0); 265 -- Number(35 downto 0) <= NumberPom(35 downto 0);
261 266
262 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar 267 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
263 LED(6 downto 4) <= (others => '0'); 268 LED(6 downto 4) <= (others => '0');
264 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar 269 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
265   270