Rev 3172 Rev 3173
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8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3172 2013-07-15 19:19:25Z kakl $ 13 -- Version: $Id: gtime.vhd 3173 2013-07-15 21:17:51Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
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23   23  
24 entity gtime is 24 entity gtime is
25 generic ( 25 generic (
26 -- Top Value for 100MHz Clock Counter 26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000; 27 --!!!KAKL MAXCOUNT: integer := 30_000_000;
28 MAXCOUNT: integer := 3_000_000; 28 MAXCOUNT: integer := 10_000;
29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 ); 30 );
31 port ( 31 port (
32 -- Main Clock 32 -- Main Clock
33 CLK100MHz: in std_logic; 33 CLK100MHz: in std_logic;
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147   147  
148   148  
149 -- LED Demo Signals 149 -- LED Demo Signals
150 -- ---------------- 150 -- ----------------
151   151  
152 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary) 152 signal Counter: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
-   153 signal CounterMaxcount: unsigned(15 downto 0) := X"0000"; -- Main Counter (binary)
153 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary) 154 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
154   155  
155 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz) 156 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
156   157  
157 -- LED Display 158 -- LED Display
158 -- ----------- 159 -- -----------
159   160  
160 signal Number: std_logic_vector(32 downto 0); -- LED Display Input 161 signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input
161 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 162 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
162 signal Enable: std_logic; 163 signal Enable: std_logic;
163 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 164 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
164 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 165 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
165 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 166 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
166   167  
167 168
168 signal LO_CLOCK: std_logic; 169 signal LO_CLOCK: std_logic;
169   170  
170 signal Decko: std_logic; 171 signal Decko: std_logic;
171 signal Disp: std_logic := '0'; -  
172 signal Reset: std_logic := '0'; 172 signal State: unsigned(2 downto 0) := (others => '0');
173 173
174 begin 174 begin
175   175  
176 -- Basic LED Blinking Test 176 -- Basic LED Blinking Test
177 -- ======================= 177 -- =======================
178   178  
179 -- LED Bar Counter 179 -- LED Bar Counter
180 process (LO_CLOCK) 180 process (LO_CLOCK)
181 begin 181 begin
182 if Reset = '0' then 182
183 if rising_edge(LO_CLOCK) then 183 if rising_edge(LO_CLOCK) then
184 184
185 if Disp = '1' then 185 if (State = 3) or (State = 0) then
186 Reset <= '1'; -  
187 end if; -  
188   -  
189 Decko <= DIPSW(0); -  
190   -  
191 if Counter < MAXCOUNT-1 then 186 if Counter < MAXCOUNT-1 then
192 Counter <= Counter + 1; 187 Counter <= Counter + 1;
193 else 188 else
194 Counter <= (others => '0'); 189 Counter <= (others => '0');
195 Bar <= Bar + 1; 190 CounterMaxcount <= CounterMaxcount + 1;
196 end if; 191 end if;
197 end if; 192 end if;
198   -  
-   193 if (State = 1) then
-   194 Number(15 downto 0) <= std_logic_vector(Counter(15 downto 0));
-   195 Number(31 downto 16) <= std_logic_vector(CounterMaxcount(15 downto 0));
199 else 196 end if;
-   197 if (State = 2) then
-   198 CounterMaxcount <= (others => '0');
200 Bar <= (others => '0'); 199 Counter <= (others => '0');
201 Reset <= '0'; 200 end if;
202 end if; 201 end if;
203 202  
204 end process; 203 end process;
205   204  
-   205  
206 process (LO_CLOCK) 206 process (LO_CLOCK)
207 begin 207 begin
208 if rising_edge(LO_CLOCK) then 208 if rising_edge(LO_CLOCK) then
209 if Decko = '1' then 209 Decko <= DIPSW(0);
210 if Disp = '0' then 210 end if;
211 Number(3 downto 0) <= std_logic_vector(Bar(3 downto 0)); 211 end process;
-   212  
212 Number(7 downto 4) <= std_logic_vector(Bar(7 downto 4)); 213 process (LO_CLOCK)
-   214 begin
213 Number(15 downto 8) <= (others=>'0'); 215 if rising_edge(LO_CLOCK) then
214 Number(19 downto 16) <= (others=>'0'); 216 if (Decko = '1') then
215 Number(31 downto 20) <= (others=>'0'); --to_bcd(std_logic_vector(T1)); 217 if (State < 3) then
216 Disp <= '1'; 218 State <= State + 1;
217 end if; 219 end if;
218 else 220 else
219 Disp <= '0'; 221 State <= (others => '0');
220 end if; 222 end if;
221 end if; 223 end if;
222 end process; 224 end process;
-   225  
-   226
223 227
224 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter 228 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
225   229  
226 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity 230 -- FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
227   231  
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309   313  
310 -- Diferencial In/Outs 314 -- Diferencial In/Outs
311 -- ======================== 315 -- ========================
312 DIFbuffer1 : IBUFGDS 316 DIFbuffer1 : IBUFGDS
313 generic map ( 317 generic map (
314 DIFF_TERM => TRUE, -- Differential Termination 318 DIFF_TERM => FALSE, -- Differential Termination
315 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 319 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
316 -- "0"-"16" 320 -- "0"-"16"
317 IOSTANDARD => "DEFAULT") 321 IOSTANDARD => "DEFAULT")
318 port map ( 322 port map (
319 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 323 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)