Rev 3177 Rev 3219
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8 -- Tool versions: ISE 13.3 8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A. 9 -- Description: Time and frequency synchronisation for RDMS01A.
10 -- 10 --
11 -- Dependencies: CLKGEN01B, GPS01A 11 -- Dependencies: CLKGEN01B, GPS01A
12 -- 12 --
13 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ 13 -- Version: $Id: gtime.vhd 3219 2013-07-25 09:13:34Z kakl $
14 -- 14 --
15 ---------------------------------------------------------------------------------- 15 ----------------------------------------------------------------------------------
16   16  
17 library IEEE; 17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL; 18 use IEEE.STD_LOGIC_1164.ALL;
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22 use UNISIM.vcomponents.all; 22 use UNISIM.vcomponents.all;
23   23  
24 entity gtime is 24 entity gtime is
25 generic ( 25 generic (
26 -- Top Value for 100MHz Clock Counter 26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000; -  
28 MAXCOUNT: integer := 10_000; 27 MAXCOUNT: integer := 10_000; -- Maximum for the first counter
29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider 28 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 ); 29 );
31 port ( 30 port (
32 -- Main Clock 31 -- Clock on PCB
33 CLK100MHz: in std_logic; 32 CLK100MHz: in std_logic;
34   33
35 -- Mode Signals (usualy not used) 34 -- Mode Signals (usualy not used)
36 M: in std_logic_vector(2 downto 0); 35 M: in std_logic_vector(2 downto 0);
37 VS: in std_logic_vector(2 downto 0); 36 VS: in std_logic_vector(2 downto 0);
38   37  
39 -- Dipswitch Inputs 38 -- Dipswitch Inputs
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72   71  
73 -- Bank 1 Pins - Inputs for this Test 72 -- Bank 1 Pins - Inputs for this Test
74 B: inout std_logic_vector(24 downto 0); 73 B: inout std_logic_vector(24 downto 0);
75 74
76 -- PS/2 Bidirectional Port (open collector, J31 and J32) 75 -- PS/2 Bidirectional Port (open collector, J31 and J32)
77 -- PS2_CLK1: inout std_logic; 76 PS2_CLK1: inout std_logic;
78 -- PS2_DATA1: inout std_logic; 77 PS2_DATA1: inout std_logic;
79 PS2_CLK2: inout std_logic; 78 PS2_CLK2: inout std_logic;
80 PS2_DATA2: inout std_logic; 79 PS2_DATA2: inout std_logic;
81   80  
82 -- Diferencial Signals on 4 pin header (J7) 81 -- Diferencial Signals on 4 pin header (J7)
83 DIF1P: inout std_logic; 82 DIF1P: inout std_logic;
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115 end entity gtime; 114 end entity gtime;
116   115  
117   116  
118 architecture gtime_a of gtime is 117 architecture gtime_a of gtime is
119   118  
120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is -  
121 variable i : integer:=0; -  
122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0'); -  
123 variable bint : std_logic_vector(15 downto 0) := bin; -  
124 begin -  
125 for i in 0 to 15 loop -- repeating 16 times. -  
126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits. -  
127 mybcd(0) := bint(15); -  
128 bint(15 downto 1) := bint(14 downto 0); -  
129 bint(0) :='0'; -  
130   -  
131   -  
132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. -  
133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); -  
134 end if; -  
135   -  
136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. -  
137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); -  
138 end if; -  
139   -  
140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. -  
141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); -  
142 end if; -  
143   -  
144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. -  
145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); -  
146 end if; -  
147   -  
148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. -  
149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); -  
150 end if; -  
151   -  
152 end loop; -  
153 -  
154 return mybcd; -  
155 end to_bcd; -  
156   119  
157   -  
158 -- LED Demo Signals 120 -- Counter
159 -- ---------------- 121 -- ----------------
160   122  
161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) 123 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 2 Hz (binary)
162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary) -  
163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary) -  
164   124  
165   125  
166 -- LED Display 126 -- LED Display
167 -- ----------- 127 -- -----------
168   128  
169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input -  
170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input 129 signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input
171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency 130 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
172 signal HalfFreq: std_logic_vector(31 downto 0); -  
173 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider 131 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
174 signal Enable: std_logic; 132 signal Enable: std_logic;
175 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output 133 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
176 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output 134 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
177 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output 135 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
178   136  
179 137
180 signal LO_CLOCK: std_logic; 138 -- signal LO_CLOCK: std_logic; -- Frequency divided by 2
181 signal EXT_CLOCK: std_logic; 139 signal EXT_CLOCK: std_logic; -- Input Frequency
182   140  
183 signal Decko: std_logic; 141 signal Decko: std_logic; -- D flip-flop
184 signal State: unsigned(2 downto 0) := (others => '0'); 142 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata
185 143
186 begin 144 signal SCLK: std_logic;
-   145 signal SCLK2: std_logic;
187   146  
188 process (EXT_CLOCK) -  
189 begin -  
190 -  
191 if rising_edge(EXT_CLOCK) then -  
192 LO_CLOCK <= not LO_CLOCK; -  
193 end if; -  
194 end process; -  
195   147  
-   148 begin
196   149  
197 -- Counter 150 -- Counter
198 process (LO_CLOCK) 151 process (EXT_CLOCK)
199 begin 152 begin
200 153
201 if rising_edge(LO_CLOCK) then 154 if rising_edge(EXT_CLOCK) then
202 155
203 if (State = 3) or (State = 0) then 156 if (State = 2) or (State = 0) then
204 if Counter < MAXCOUNT-1 then -  
205 Counter <= Counter + 1; 157 Counter <= Counter + 1;
206 else -  
207 Counter <= (others => '0'); -  
208 CounterMaxcount <= CounterMaxcount + 1; -  
209 end if; -  
210 end if; 158 end if;
211 if (State = 1) then 159 if (State = 1) then
212 Freq(15 downto 0) <= std_logic_vector("00"&Counter); 160 Freq(31 downto 0) <= std_logic_vector(Counter);
213 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount); -  
214 end if; -  
215 if (State = 2) then -  
216 CounterMaxcount <= (others => '0'); -  
217 Counter <= (others => '0'); 161 Counter <= (others => '0');
218 end if; 162 end if;
219 end if; 163 end if;
220   164  
221 end process; 165 end process;
222   166  
223   167  
224 -- Sampling 1PPS signal 168 -- Sampling 1PPS signal
225 process (LO_CLOCK) 169 process (EXT_CLOCK)
226 begin 170 begin
227 if rising_edge(LO_CLOCK) then 171 if rising_edge(EXT_CLOCK) then
228 Decko <= B(22); 172 Decko <= B(22);
229 end if; 173 end if;
230 end process; 174 end process;
231   175  
232 -- Automata for controling the Counter 176 -- Automata for controlling the Counter
233 process (LO_CLOCK) 177 process (EXT_CLOCK)
234 begin 178 begin
235 if rising_edge(LO_CLOCK) then 179 if rising_edge(EXT_CLOCK) then
236 if (Decko = '1') then 180 if (Decko = '1') then
237 if (State < 3) then 181 if (State < 2) then
238 State <= State + 1; 182 State <= State + 1;
239 end if; 183 end if;
240 else 184 else
241 State <= (others => '0'); 185 State <= (others => '0');
242 end if; 186 end if;
Line 245... Line 189...
245   189  
246 -- Coding to BCD for LED Display 190 -- Coding to BCD for LED Display
247   191  
248 process (Decko) 192 process (Decko)
249 begin 193 begin
250 if falling_edge(Decko) then 194 if Decko = '0' then
251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); 195 LED(6) <= '1';
-   196 else
252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0); 197 LED(6) <= '0';
253 end if; 198 end if;
254 end process; 199 end process;
255   -  
256 Number(35 downto 0) <= NumberPom(35 downto 0); -  
257 200
-   201 SCLK <= B(0);
-   202 -- SCLK2 <= ((not Decko) OR SCLK);
-   203
-   204 process (Decko,SCLK)
-   205 begin
-   206 if (Decko = '0') then
-   207 Number(31 downto 0) <= Freq(31 downto 0);
-   208 else
-   209 if rising_edge(SCLK) then
-   210 Number(30 downto 0) <= Number(31 downto 1);
-   211 end if;
-   212 end if;
-   213 end process;
-   214  
-   215 B(1) <= Number(0);
-   216 B(2) <= Decko;
-   217  
258 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar 218 LED(7) <= Decko; -- Display 1PPS pulse on LEDbar
259 LED(6 downto 4) <= (others => '0'); 219 LED(5 downto 0) <= (others => '0');
260 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar -  
261   220  
262 -- LED Display (multiplexed) 221 -- LED Display (multiplexed)
263 -- ========================= 222 -- =========================
264   223  
265 -- Connect LED Display Output Ports (negative outputs) 224 -- Connect LED Display Output Ports (negative outputs)
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332 Number(27 downto 24) when Digits="01000000" else 291 Number(27 downto 24) when Digits="01000000" else
333 Number(31 downto 28) when Digits="10000000" else 292 Number(31 downto 28) when Digits="10000000" else
334 "0000"; 293 "0000";
335   294  
336   295  
337   -  
338 -- Diferencial In/Outs 296 -- Diferencial In/Outs
339 -- ======================== 297 -- ========================
340 DIFbuffer1 : IBUFGDS 298 DIFbuffer1 : IBUFGDS
341 generic map ( 299 generic map (
342 DIFF_TERM => FALSE, -- Differential Termination 300 DIFF_TERM => FALSE, -- Differential Termination
343 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer, 301 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
344 -- "0"-"16" 302 -- "0"-"16"
345 IOSTANDARD => "DEFAULT") 303 IOSTANDARD => "LVPECL_33")
346 port map ( 304 port map (
347 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) 305 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
348 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) 306 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
349 O => EXT_CLOCK -- Buffer output 307 O => EXT_CLOCK -- Buffer output - Counter INPUT
350 ); 308 );
351   309  
352 OBUFDS_inst : OBUFDS 310 OBUFDS_inst : OBUFDS
353 generic map ( 311 generic map (
354 IOSTANDARD => "DEFAULT") 312 IOSTANDARD => "LVDS_33")
355 port map ( 313 port map (
356 O => SD2AP, -- Diff_p output (connect directly to top-level port) 314 O => SD2AP, -- Diff_p output (connect directly to top-level port)
357 OB => SD2AN, -- Diff_n output (connect directly to top-level port) 315 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
358 I => EXT_CLOCK -- Buffer input 316 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS
359 ); 317 );
360 318
361 -- Output Signal on SATA Connector 319 -- Output Signal on SATA Connector
362 -- SD1AP <= 'Z'; 320 -- SD1AP <= 'Z'; -- Counter INPUT
363 -- SD1AN <= 'Z'; 321 -- SD1AN <= 'Z';
364 SD1BP <= 'Z'; 322 SD1BP <= 'Z';
365 SD1BN <= 'Z'; 323 SD1BN <= 'Z';
366   324  
367 -- Input Here via SATA Cable 325 -- Input Here via SATA Cable
368 -- SD2AP <= 'Z'; 326 -- SD2AP <= 'Z'; -- Counter OUTPUT
369 -- SD2AN <= 'Z'; 327 -- SD2AN <= 'Z';
370 SD2BP <= 'Z'; 328 SD2BP <= 'Z';
371 SD2BN <= 'Z'; 329 SD2BN <= 'Z';
372   330  
373   331  
374 -- Unused Signals 332 -- Unused Signals
375 -- ============== 333 -- ==============
376   334  
-   335 -- Differential inputs onn header
-   336 DIF1N <= 'Z';
-   337 DIF1P <= 'Z';
-   338 DIF2N <= 'Z';
-   339 DIF2P <= 'Z';
-   340  
377 -- I2C Signals (on connector J30) 341 -- I2C Signals (on connector J30)
378 I2C_SCL <= 'Z'; 342 I2C_SCL <= 'Z';
379 I2C_SDA <= 'Z'; 343 I2C_SDA <= 'Z';
380   344  
381 -- SPI Memory Interface 345 -- SPI Memory Interface
Line 383... Line 347...
383 SPI_DO <= 'Z'; 347 SPI_DO <= 'Z';
384 SPI_DI <= 'Z'; 348 SPI_DI <= 'Z';
385 SPI_CLK <= 'Z'; 349 SPI_CLK <= 'Z';
386 SPI_WP_n <= 'Z'; 350 SPI_WP_n <= 'Z';
387   351  
-   352 -- A/D
388 ANA_OUTD <= 'Z'; 353 ANA_OUTD <= 'Z';
389 ANA_REFD <= 'Z'; 354 ANA_REFD <= 'Z';
390   355  
-   356 -- VGA
391 VGA_R <= "ZZ"; 357 VGA_R <= "ZZ";
392 VGA_G <= "ZZ"; 358 VGA_G <= "ZZ";
393 VGA_B <= "ZZ"; 359 VGA_B <= "ZZ";
394 VGA_VS <= 'Z'; 360 VGA_VS <= 'Z';
395 VGA_HS <= 'Z'; 361 VGA_HS <= 'Z';
396   362  
-   363 -- PS2
-   364 PS2_DATA2 <= 'Z';
-   365 PS2_CLK2 <='Z';
-   366  
397 end architecture gtime_a; 367 end architecture gtime_a;