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1 /********************************************* 1 /*********************************************
2 * 2 *
-   3 * RFM01 simple library
-   4 *
-   5 * $HeadURL: svn://www.mlab.cz/home/MLAB/Designs/duckweed_collector/SW/library/RF02/RF02.cpp $
3 * draft version v 0.1, experimental 6 * $Id: RF02.cpp 2129 2011-08-18 18:40:43Z kakl $
4 * 7 *
5 * code based on the code of "benedikt k." 8 * code based on the code of "benedikt k." and "contrechoc"
6 * this was an avr project from the site: http://www.mikrocontroller.net/topic/65984#541030 -  
7 * -  
8 * -  
9 * code should be matched with RF01 -  
10 * -  
11 * up to now no transmission between the RF12 modules and Jeelabs.com RF12 lib -  
12 * -  
13 * this code has worked: transmitting using atmega168 and atmega328 in combination with RF01s and RF02s -  
14 * -  
15 * arduino 18 -  
16 * -  
17 * five march, contrechoc.com, june 2010 , october 2010 -  
18 * 9 *
-   10 * tested on arduino 22
19 * 11 *
20 *********************************************/ 12 *********************************************/
21   13  
22 #include <avr/io.h> 14 #include <avr/io.h>
23 #include <avr/interrupt.h> -  
24 #include <avr/pgmspace.h> -  
25 #include <avr/eeprom.h> -  
26 #include <stdlib.h> 15 #include <stdlib.h>
27   16  
28 #include "rf01.h" 17 #include "rf01.h"
29   18  
30 #define F_CPU 16000000UL 19 #define F_CPU 16000000UL
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36   25  
37 #define SDI 5 // RF01 SDI, arduino 13 cannot be changed 26 #define SDI 5 // RF01 SDI, arduino 13 cannot be changed
38 #define SCK 4 // RF01 SCK, arduino 12 cannot be changed 27 #define SCK 4 // RF01 SCK, arduino 12 cannot be changed
39 #define CS 3 // RF01 nSEL, arduino 11 cannot be changed 28 #define CS 3 // RF01 nSEL, arduino 11 cannot be changed
40 #define SDO 2 // RF01 SDO, arduino 10 cannot be changed 29 #define SDO 2 // RF01 SDO, arduino 10 cannot be changed
41 //----------------- // RF01 niRQ, arduino 02 cannot be changed 30 //----------------- // RF01 niRQ, arduino 2 cannot be changed
42 //------------------// RF01 nFFS: 1-10k Pullup too Vcc 31 //------------------// RF01 nFFS: 1-10k Pullup too Vcc
43   32  
44   33  
45 #ifndef cbi 34 #ifndef cbi
46 #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) 35 #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
47 #endif 36 #endif
48 #ifndef sbi 37 #ifndef sbi
49 #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) 38 #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
50 #endif 39 #endif
51   40  
52 // maximum receive buffer -  
53 #define RF_MAX 32 -  
54 unsigned char rf01_buf[RF_MAX]; // recv buf 41 unsigned char _rx_buffer[32]; // recv buf
55   42  
56 #include <util/delay.h> 43 #include <util/delay.h>
57   44  
58 void rf01_receive(){ -  
59 rf01_rxdata(rf01_data, 23); //!!!32 -  
60 } -  
61   -  
62 static unsigned char sdrssi, sgain; -  
63   -  
64 void rf01_prepAll() 45 void rf01_prepAll()
65 { 46 {
66 RF_PORT=(1<<CS); 47 RF_PORT=(1<<CS);
67 RF_DDR=(1<<SDI)|(1<<SCK)|(1<<CS); 48 RF_DDR=(1<<SDI)|(1<<SCK)|(1<<CS);
68   49  
69 for (unsigned char i=0; i<11; i++) _delay_ms(10); // wait until POR done 50 for (unsigned char i=0; i<11; i++) _delay_ms(10); // wait until POR done
70   51  
71 // rf01_trans(0xC2E0); // AVR CLK: 10MHz -  
72 // rf01_trans(0xC42B); // Data Filter: internal -  
73 // rf01_trans(0xC6F7); // AFC settings: autotuning: -10kHz...+7,5kHz -  
74 // rf01_trans(0xE000); // disable wakeuptimer -  
75 // rf01_trans(0xCC00); // disable low duty cycle -  
76 // rf01_trans(0x8978); // band 433MHz, enable crystal + 12pF, 200kHz bandwidth -  
77   -  
78 rf01_trans(0x0000); 52 rf01_trans(0x0000);
79 // rf01_trans(0x898A); // band 433MHz, 134kHz bandwidth -  
80 rf01_trans(0x8000|0x1000|0x70|0x02); //band 53 rf01_trans(0x8000|0x1000|0x70|0x02); //band
81 rf01_trans(0xA640); //434MHz 54 rf01_trans(0xA640); // freq
82 rf01_trans(0xC823); //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 9600 Bd 55 rf01_trans(0xC823); //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 9600 Bd
83 rf01_trans(0xC69B); 56 rf01_trans(0xC69B);
84 rf01_trans(0xC42A); 57 rf01_trans(0xC42A);
85 rf01_trans(0xC240); //* 58 rf01_trans(0xC240); //*
86 rf01_trans(0xC080); //* 59 rf01_trans(0xC080); //*
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97 { if (wert&32768) 70 { if (wert&32768)
98 sbi(RF_PORT, SDI); 71 sbi(RF_PORT, SDI);
99 else 72 else
100 cbi(RF_PORT, SDI); 73 cbi(RF_PORT, SDI);
101 sbi(RF_PORT, SCK); 74 sbi(RF_PORT, SCK);
-   75 sbi(RF_PORT, SCK);
-   76 sbi(RF_PORT, SCK);
102 wert<<=1; 77 wert<<=1;
103 _delay_us(0.2); -  
104 cbi(RF_PORT, SCK); 78 cbi(RF_PORT, SCK);
105 } 79 }
106 sbi(RF_PORT, CS); 80 sbi(RF_PORT, CS);
107 } 81 }
108   82  
109 void rf01_rxdata(unsigned char *data, unsigned char number) 83 void rf01_rxdata(unsigned char *data, unsigned char number)
110 { unsigned char i,j,c; 84 { unsigned char i,j,c;
111   85  
112 //!!! -  
113 // sgain=2; //2,4 -6dB LNA gain, DRSSI threshold: -79dBm -  
114 // sdrssi=4; -  
115 //!!! rf01_trans(0xC0C1|((sgain&3)<<4)|((sdrssi&7)<<1)); // RX on -  
116 rf01_trans(0xCE89); // set FIFO mode 86 rf01_trans(0xCE89); // set FIFO mode
117 rf01_trans(0xCE8B); // enable FIFO 87 rf01_trans(0xCE8B); // enable FIFO
118 cbi(RF_PORT, SDI); 88 cbi(RF_PORT, SDI);
119 asm("nop"); 89 asm("nop");
120 asm("nop"); 90 asm("nop");
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143 c|=1; 113 c|=1;
144 sbi(RF_PORT, SCK); 114 sbi(RF_PORT, SCK);
145 asm("nop"); 115 asm("nop");
146 asm("nop"); 116 asm("nop");
147 asm("nop"); 117 asm("nop");
148 //!!! _delay_us(0.2); -  
149 cbi(RF_PORT, SCK); 118 cbi(RF_PORT, SCK);
150 asm("nop"); 119 asm("nop");
151 asm("nop"); 120 asm("nop");
152 asm("nop"); 121 asm("nop");
153 } 122 }
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155 sbi(RF_PORT, CS); 124 sbi(RF_PORT, CS);
156 asm("nop"); 125 asm("nop");
157 asm("nop"); 126 asm("nop");
158 asm("nop"); 127 asm("nop");
159 } 128 }
160 //!!! rf01_trans(0xC0C0|((sgain&3)<<4)|((sdrssi&7)<<1)); // RX off -  
161 } 129 }