// ------------------------------------------------------------------
//
// TRAIN01A and TRAN02A MLAB Module Hardware Definition
//
// (c) miho WWW.MLAB.CZ/PermaLink/TRAIN
//
// ------------------------------------------------------------------
// Timer
#define F_CPU 8000000UL // Internal RC Oscillator 8MHz
// Input bits port definitions
#define SW_PORT_0 C // Port PC5
#define SW_DATA_0 5
#define SW_PORT_1 C // Port PC4
#define SW_DATA_1 4
#define SW_PORT_2 C // Port PC3
#define SW_DATA_2 3
#define SW_PORT_3 C // Port PC2
#define SW_DATA_3 2
#define SW_PORT_4 C // Port PC1
#define SW_DATA_4 1
#define SW_PORT_5 C // Port PC0
#define SW_DATA_5 0
#define SW_PORT_6 B // Port PB5
#define SW_DATA_6 5
#define SW_PORT_7 B // Port PB2
#define SW_DATA_7 2
// Output bits port definitions
#define RE_PORT_0 B // Port PB1
#define RE_DATA_0 1
#define RE_PORT_1 B // Port PB0
#define RE_DATA_1 0
#define RE_PORT_2 D // Port PD7
#define RE_DATA_2 7
#define RE_PORT_3 D // Port PD6
#define RE_DATA_3 6
#define RE_PORT_4 D // Port PD5
#define RE_DATA_4 5
#define RE_PORT_5 D // Port PD4
#define RE_DATA_5 4
#define RE_PORT_6 D // Port PD3
#define RE_DATA_6 3
#define RE_PORT_7 D // Port PD2
#define RE_DATA_7 2
//--------------------------------------------------------
// Macros
#define GLUE(a,b) a##b
#define PORT(a) GLUE(PORT,a)
#define PIN(a) GLUE(PIN,a)
#define DDR(a) GLUE(DDR,a)
// Output port tables - DDR
volatile uint8_t * RE_DDR_Table[8] =
{
&DDR(RE_PORT_0),
&DDR(RE_PORT_1),
&DDR(RE_PORT_2),
&DDR(RE_PORT_3),
&DDR(RE_PORT_4),
&DDR(RE_PORT_5),
&DDR(RE_PORT_6),
&DDR(RE_PORT_7)
};
// Output port tables - PORT
volatile uint8_t * RE_PORT_Table[8] =
{
&PORT(RE_PORT_0),
&PORT(RE_PORT_1),
&PORT(RE_PORT_2),
&PORT(RE_PORT_3),
&PORT(RE_PORT_4),
&PORT(RE_PORT_5),
&PORT(RE_PORT_6),
&PORT(RE_PORT_7)
};
// Output port tables - MASK
unsigned char RE_BIT_MASK[8] =
{
1<<RE_DATA_0,
1<<RE_DATA_1,
1<<RE_DATA_2,
1<<RE_DATA_3,
1<<RE_DATA_4,
1<<RE_DATA_5,
1<<RE_DATA_6,
1<<RE_DATA_7
};
// Input port tables - PORT
volatile uint8_t * SW_PORT_Table[8] =
{
&PORT(SW_PORT_0),
&PORT(SW_PORT_1),
&PORT(SW_PORT_2),
&PORT(SW_PORT_3),
&PORT(SW_PORT_4),
&PORT(SW_PORT_5),
&PORT(SW_PORT_6),
&PORT(SW_PORT_7)
};
// Input port tables - PIN
volatile uint8_t * SW_PIN_Table[8] =
{
&PIN(SW_PORT_0),
&PIN(SW_PORT_1),
&PIN(SW_PORT_2),
&PIN(SW_PORT_3),
&PIN(SW_PORT_4),
&PIN(SW_PORT_5),
&PIN(SW_PORT_6),
&PIN(SW_PORT_7)
};
// Input port tables - MASK
unsigned char SW_BIT_MASK[8] =
{
1<<SW_DATA_0,
1<<SW_DATA_1,
1<<SW_DATA_2,
1<<SW_DATA_3,
1<<SW_DATA_4,
1<<SW_DATA_5,
1<<SW_DATA_6,
1<<SW_DATA_7
};