--------------------------------------------
-- wrapper for the local oscillator division logic
--
library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

library sychro1;

entity lo_divider_wrapper is
        generic (
                G_DIVISOR : integer
        );
  port (
                
                -- input clock:
                IN_CLK_LO_N : IN std_logic;
                IN_CLK_LO_P : IN std_logic;  
                
                in_clk_enable : in std_logic;
                
                -- divided clock
                OUT_CLK_LO_DIVIDED_N : OUT std_logic;
                OUT_CLK_LO_DIVIDED_P : OUT std_logic
  
  );
                
end lo_divider_wrapper;

architecture behavioral of lo_divider_wrapper is

        -- clock signals for in->divide->out clock:     
        signal s_in_clk_lo : std_logic;
        signal s_in_clk_lo_bufred : std_logic;
        signal s_divided_lo : std_logic;
        attribute clock_signal : string;
        attribute clock_signal of s_divided_lo : signal is "yes";

begin
        
        IBUFGDS_inst : IBUFGDS
        generic map (
                DIFF_TERM  => TRUE
                --IBUF_LOW_PWR => TRUE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
                )
        port map (
                O => s_in_clk_lo, -- Clock buffer output
                I => IN_CLK_LO_P, -- Diff_p clock buffer input (connect directly to top-level port)
                IB => IN_CLK_LO_N -- Diff_n clock buffer input (connect directly to top-level port)
        );
        
        -- TEST2: misto counteru pouziju deleni v BUFR
        BUFR_inst : BUFR
        generic map (
                BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
                SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
        port map (
                O => s_in_clk_lo_bufred, -- Clock buffer output
                CE => in_clk_enable, -- Clock enable input
                CLR => '0', -- Clock buffer reset input
                I => s_in_clk_lo -- Clock buffer input
        );
        
        -- TEST3: opravil jsem clock_divider, zkusim ho sem dat zpatky
        -- -> BUFR -> BYPASS
        -- zpatky clock_divider

        -- TEMP1: vyhozeni counteru
        divider_inst : entity sychro1.clock_divider
        generic map( G_DIVISOR => G_DIVISOR )
        port map( i_clk => s_in_clk_lo_bufred, i_rst => '0', o_clk => s_divided_lo );
        --s_divided_lo <= s_in_clk_lo_bufred;

        OBUFDS_inst : OBUFDS
        generic map (
                IOSTANDARD => "DEFAULT" )
        port map (
                O => OUT_CLK_LO_DIVIDED_P, -- Diff_p output (connect directly to top-level port)
                OB => OUT_CLK_LO_DIVIDED_N, -- Diff_n output (connect directly to top-level port)
                I => s_divided_lo -- Buffer input
        );

end architecture;