--------------------------------------------
-- wrapper for the iserdes_ddr and pack_data
--
library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity myserdes_ddr_wrapper is
generic
(-- width of the data for the system
sys_w       : integer := 1;
-- width of the data for the device
dev_w       : integer := 8);
  port (
  
                -- CLOCK:
                clk_in : in std_logic;
                clk_in_div : in std_logic;
                
                -- PADS IN:
                data_in_from_pins_p : in std_logic;
                data_in_from_pins_n : in std_logic;
                
                data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 );
                
                bitslip : in std_logic;
                                
                rst_in : in std_logic );
                
end myserdes_ddr_wrapper;

architecture behavioral of myserdes_ddr_wrapper is

component myserdes_ddr is
generic
(-- width of the data for the system
sys_w       : integer := 1;
-- width of the data for the device
dev_w       : integer := 8);
port
(
-- From the system into the device
DATA_IN_FROM_PINS_P     : in    std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N     : in    std_logic_vector(sys_w-1 downto 0);
DATA_IN_TO_DEVICE       : out   std_logic_vector(dev_w-1 downto 0);

BITSLIP                 : in    std_logic;                    -- Bitslip module is enabled in NETWORKING mode
-- User should tie it to '0' if not needed

-- Clock and reset signals
CLK_IN                                                                  : in    std_logic;  -- Fast clock from IOB, after IBUFGDS and BUFIO
CLK_DIV_IN                                                      : in            std_logic;  -- Divided fast clock from IBUFGDS and BUFR

IO_RESET                : in    std_logic);                   -- Reset signal for IO circuit
end component;

        -- data in signal:
        signal s_data_in_from_pins_p : std_logic_vector( sys_w-1 downto 0 );
        signal s_data_in_from_pins_n : std_logic_vector( sys_w-1 downto 0 );
                        
begin
        
        -- convert std_logic to std_logic_vector
        s_data_in_from_pins_n(0) <= data_in_from_pins_n;
        s_data_in_from_pins_p(0) <= data_in_from_pins_p;
        
        -- instantiate the myserdes_ddr
        myserdes_ddr_inst : myserdes_ddr
        port map (
                DATA_IN_FROM_PINS_P => s_data_in_from_pins_p, DATA_IN_FROM_PINS_N => s_data_in_from_pins_n,
                DATA_IN_TO_DEVICE => data_in_to_device,
                BITSLIP => bitslip, CLK_IN => clk_in, CLK_DIV_IN => clk_in_div, IO_RESET => rst_in );
                
        
end architecture;