/* mija 2008defines for module RFM12B - RX/TX 868MHz*/#define CMD_SETTING 0x8000 // el, ef, b1, b0, x3, x2, x1, x0#define CMD_POWER 0x8200 // er, ebb, et, es, ex, eb, ew, dc#define CMD_FREQUENCY 0xA000 // f11..f0 860+F*0.005 MHz 36..3903#define CMD_RATE 0xC600 // cs, r6..r0 BR=10M/29/(R+1)/1+cs*7)#define CMD_RX 0x9000 // P16, d1, d0, i2..i0, g1, g0, r2..r0#define CMD_FILTER 0xC228 // al, ml, s, f2..f0#define CMD_FIFO 0xCA00 // f3..f0, sp, al, ff, dr#define CMD_SYNCFIFO 0xCE00 // b7..b0#define CMD_READ_FIFO 0xB000 // use for read FIFO#define CMD_AFC 0xC400 // a1, a0, rl1, rl0, st, fi, oe, en#define CMD_TX 0x9800 // mp, m3..m0, p2..p0#define CMD_PLL 0xCC02 // ob1, ob0, lpx, ddy, ddit, bw0#define CMD_TX_DATA 0xB800 // t7..t0#define CMD_WAKE_UP 0xE000 // r4..r0, m7..m0 T=M*2^R [ms]#define CMD_DUTY 0xC800 // d6..d0 D.C.= (D*2+1)/M*100%#define CMD_BATTERY 0xC000 // d2..d0, v3..v0#define CMD_STATUS 0x0000 // for read status// CMD_SETTING#define SETTING_EL 0x80 // enable TX register#define SETTING_EF 0x40 // enable TX FIFO buffer#define SETTING_B1 0x20 // select band#define SETTING_B0 0x10 // select band#define BAND_868 0x20#define SETTING_X3 0x08 // select capacitor#define SETTING_X2 0x04 // select capacitor#define SETTING_X1 0x02 // select capacitor#define SETTING_X0 0x01 // select capacitor#define C_8_5pF 0x0#define C_9pF 0x1#define C_9_5pF 0x2#define C_10pF 0x3#define C_10_5pF 0x4#define C_11pF 0x5#define C_11_5pF 0x6#define C_12pF 0x7#define C_12_5pF 0x8#define C_13pF 0x9#define C_13_5pF 0xA#define C_14pF 0xB#define C_14_5pF 0xC#define C_15pF 0xD#define C_15_5pF 0xE#define C_16pF 0xF// CMD_POWER#define POWER_ER 0x80 // enable receiver#define POWER_EBB 0x40 // enable base band block#define POWER_ET 0x20 // enable transmitter#define POWER_ES 0x10 // enable synthesizer#define POWER_EX 0x08 // enable crystal oscillator#define POWER_EB 0x04 // enable low battery detector#define POWER_EW 0x02 // enable wake up timer#define POWER_DC 0x01 // disable clock output of CLK pin// CMD_FREQUENCY#define FREQUENCY_867 0x578#define FREQUENCY_868 0x640#define FREQUENCY_869 0x708// CMD_RATE#define RATE_1200 0x123#define RATE_2400 0x8F#define RATE_4800 0x47#define RATE_CS_4800 0x108#define RATE_9600 0x23#define RATE_19200 0x11#define RATE_38400 0x8#define RATE_57600 0x5#define RATE_115200 0x2// CMD_RX#define RX_P16 10 // VDI output / interrupt input#define VDI_FAST 0x000 // VDI response time#define VDI_MEDIUM 0x100#define VDI_SLOW 0x200#define VDI_ALWAYS_ON 0x300#define BANDWIDTH_400 0x20 // baseband bandwidth[kHz]#define BANDWIDTH_340 0x40#define BANDWIDTH_270 0x60#define BANDWIDTH_200 0x80#define BANDWIDTH_134 0xA0#define BANDWIDTH_67 0xC0#define LNA_GAIN_0 0x00 // LNA_GAIN#define LNA_GAIN_6 0x08 // -6dBm#define LNA_GAIN_14 0x10 // -14dBm#define LNA_GAIN_20 0x18 // -20dBm#define DRSSI_103 0x0 // RSSI= DRSSI + LNA_GAIN -103dBm#define DRSSI_97 0x1 // -97dBm#define DRSSI_91 0x2 // -91dBm#define DRSSI_85 0x3 // -85dBm#define DRSSI_79 0x4 // -79dBm#define DRSSI_73 0x5 // -73dBm#define DRSSI_67 0x6 // -67dBm#define DRSSI_61 0x7 // -61dBm// CMD_FILTER#define FILTER_AL 0x80 // enable clock recovery atuo-lock#define FILTER_ML 0x40 // enable clock recovery fast mode#define FILTER_S 0x10 // enable analog RC filter#define DQD_7 0x7#define DQD_6 0x6#define DQD_5 0x5#define DQD_4 0x4#define DQD_3 0x3#define DQD_2 0x2#define DQD_1 0x1#define DQD_0 0x0// CMD_FIFO#define FIFO_16 0x00 // FIFO level#define FIFO_15 0xF0#define FIFO_14 0xE0#define FIFO_13 0xD0#define FIFO_12 0xC0#define FIFO_11 0xB0#define FIFO_10 0xA0#define FIFO_9 0x90#define FIFO_8 0x80#define FIFO_7 0x70#define FIFO_6 0x60#define FIFO_5 0x50#define FIFO_4 0x40#define FIFO_3 0x30#define FIFO_2 0x20#define FIFO_1 0x10#define FIFO_SP 0x8 // select 1 byte sync.pattern#define FIFO_AL 0x4 // start FIFO always#define FIFO_FF 0x2 // enable FIFO fill#define FIFO_DR 0x1 // disable hi sensitivity reset// CMD_AFC#define AFC_MCU 0x00 // AFC auto_mode by MCU#define AFC_POWER_ON 0x40 // AFC at poweron#define AFC_OFFSET 0x80 // AFC keep offset when VDI hi#define AFC_VDI 0xC0 // AFC keeps independently from VDI#define AFC_NORESTR 0x00 // range limit no restriction#define AFC_RANG_16 0x10 // range limit +15/-16#define AFC_RANG_8 0x20 // range limit +7/-8#define AFC_RANG_4 0x30 // range limit +3/-4#define AFC_ST 0x08 // store offset into outpur register#define AFC_FI 0x04 // enable AFC hi accuracy mode#define AFC_OE 0x02 // enable AFC output register#define AFC_EN 0x01 // enable AFC function// CMD_TX#define TX_MP 0x100 // modulation polarity#define TX_DEV_15 0x00 // select frequency deviation#define TX_DEV_30 0x10#define TX_DEV_45 0x20#define TX_DEV_60 0x30#define TX_DEV_75 0x40#define TX_DEV_90 0x50#define TX_DEV_105 0x60#define TX_DEV_120 0x70#define TX_DEV_135 0x80#define TX_DEV_150 0x90#define TX_DEV_165 0xA0#define TX_DEV_180 0xB0#define TX_DEV_195 0xC0#define TX_DEV_210 0xD0#define TX_DEV_225 0xE0#define TX_DEV_240 0xF0#define TX_POWER_0 0x00 // 0 select output power#define TX_POWER_3 0x01 // -3dBm#define TX_POWER_6 0x02 // -6dBm#define TX_POWER_9 0x03 // -9Bm#define TX_POWER_12 0x04 // -12dBm#define TX_POWER_15 0x05 // -15dBm#define TX_POWER_18 0x06 // -18dBm#define TX_POWER_21 0x07 // -21dBm// CMD_PLL#define PLL_CLK_5_10 0x00 // microcontroller output clock 5-10Mhz#define PLL_CLK_33 0x20 // 3.3MHz#define PLL_CLK_25 0x40 // 2.5Mhz#define PLL_LPX 0x10 // low power mode#define PLL_DDY 0x08 // phase detector delay enable#define PLL_DDIT 0x04 // disable the dithering in the PLL loop#define PLL_BW0 0x01 // PLL bandwidth (max rate 256)