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_DLIB_ALLOW_LARGE_CONSTANT_TABLES_FOR_MATH __HAS_WEAK__ __WEAK _HAS_PRAGMA_PRINTF_ARGS _NO_RETURN __FLOAT_SIZE__ __DOUBLE_SIZE__ _F_FNAME _F_FUN _F_TYPE _F_PTRCAST _F_CAST __LONG_DOUBLE_SIZE__ _LONG_DOUBLE_IS_DOUBLE _L_FNAME _L_FUN _L_TYPE _L_PTRCAST _L_CAST _D_FNAME _D_FUN _D_TYPE _HAS_STRICT_LINKAGE _HAS_FIXED_POINT _HAS_SECURE _SECURE_PARAM _HAS_DINKUM_COMPLEX _IS_EMBEDDED _IS_CPP_LANGUAGE _HAS_EXCEPTIONS _HAS_NAMESPACE _HAS_GENERIC_TEMPLATES _STD_BEGIN _STD_END _STD _C_STD_BEGIN _C_STD_END _CSTD _X_STD_BEGIN _X_STD_END _XSTD _C_LIB_DECL _END_C_LIB_DECL _EXTERN_C _END_EXTERN_C _EXTERN_CPP _END_EXTERN_CPP xencoding_limits.h _XENCODING_LIMITS_H _EncodingSb_LenMax __WCHAR_T_MAX__ _EncodingUtf8_LenMax _ENCODING_WITH_USED _ENCODING_LEN_MAX _ENCODING_CUR_MAX _FBIAS _FOFF _FMANTISSA __LITTLE_ENDIAN__ _F0 _DBIAS _DOFF _LOFF _DMANTISSA _D0 _DLONG _LBIAS _LMANTISSA _L0 _C2 _MBMAX _MAX_EXP_DIG _MAX_INT_DIG _MAX_SIG_DIG __WCHAR_T_TYPE__ _WCMIN _WIMIN _WCMAX _WIMAX _ILONG _NULL __PTRDIFF_T_TYPE__ __SIZE_T_TYPE__ _Restrict _FPOSOFF DLib_Threads.h _DLIB_THREADS_H _DLIB_COMPILER_TLS _DLIB_TLS_QUAL _DLIB_MULTI_THREAD _DLIB_GLOBAL_VARIABLES _DLIB_FILE_OP_LOCKS _DLIB_THREAD_MACRO_SETUP_DONE _DLIB_TLS_MEMORY _DLIB_TLS_MEMORY_GLUE _DLIB_TLS_REQUIRE_INIT _DLIB_TLS_REQUIRE_CSTART_INIT _DLIB_TLS_INITIALIZER_MEMORY _DLIB_TLS_SEGMENT_DATA _DLIB_TLS_SEGMENT_INIT __IAR_DLIB_PERTHREAD_SIZE __IAR_DLIB_PERTHREAD_INIT_SIZE __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET _TLS_CONST_DECLARATION _TLS_LOCATION_HELPER0 _TLS_LOCATION_HELPER1 _TLS_LOCATION_HELPER2 _TLS_DEFINITION _TLS_REFERENCE _TLS_REFERENCE_DEF _TLS_DATA_DECL _TLS_DEFINE_INIT _TLS_DEFINE_NO_INIT _TLS_DATA_DEF _TLS_DATA_DEF_DT _TLS_DATA_PTR _TLS_ARR_DEF _TLS_ARR _DLIB_THREAD_LOCK_ONCE_TYPE _DLIB_THREAD_LOCK_ONCE_MACRO _DLIB_THREAD_LOCK_ONCE_TYPE_INIT _Once _ONCE_T_INIT _MULTI_THREAD _GLOBAL_LOCALE _FILE_OP_LOCKS _COMPILER_TLS _TLS_QUAL _LOCK_LOCALE _LOCK_MALLOC _LOCK_STREAM _LOCK_DEBUG _LOCK_STATIC_GUARD _MAX_LOCK _Mbstinit _MAX _MIN ysizet.h _YSIZET_H _SIZE_T _SIZET _STD_USING_SIZE_T __DATA_PTR_MEM_HELPER1__ __DATA_PTR_MEMORY_LIST1__ NULL offsetof _PTRDIFF_T _PTRDIFFT _STD_USING_PTRDIFF_T _WCHART stdint.h _STDINT __INT8_T_TYPE__ __UINT8_T_TYPE__ __INT16_T_TYPE__ __UINT16_T_TYPE__ __INT32_T_TYPE__ __UINT32_T_TYPE__ __INT64_T_TYPE__ __UINT64_T_TYPE__ __INT_LEAST8_T_TYPE__ __UINT_LEAST8_T_TYPE__ __INT_LEAST16_T_TYPE__ __UINT_LEAST16_T_TYPE__ __INT_LEAST32_T_TYPE__ __UINT_LEAST32_T_TYPE__ __INT_LEAST64_T_TYPE__ __UINT_LEAST64_T_TYPE__ __INT_FAST8_T_TYPE__ __UINT_FAST8_T_TYPE__ __INT_FAST16_T_TYPE__ __UINT_FAST16_T_TYPE__ __INT_FAST32_T_TYPE__ __UINT_FAST32_T_TYPE__ __INT_FAST64_T_TYPE__ __UINT_FAST64_T_TYPE__ __INTMAX_T_TYPE__ __UINTMAX_T_TYPE__ __INTPTR_T_TYPE__ __UINTPTR_T_TYPE__ INT8_MAX INT8_MIN UINT8_MAX INT16_MAX INT16_MIN UINT16_MAX INT32_MAX INT32_MIN UINT32_MAX INT64_MAX INT64_MIN UINT64_MAX INT_LEAST8_MAX INT_LEAST8_MIN UINT_LEAST8_MAX INT_LEAST16_MAX INT_LEAST16_MIN UINT_LEAST16_MAX INT_LEAST32_MAX INT_LEAST32_MIN UINT_LEAST32_MAX INT_LEAST64_MAX INT_LEAST64_MIN UINT_LEAST64_MAX INT_FAST8_MAX INT_FAST8_MIN UINT_FAST8_MAX INT_FAST16_MAX INT_FAST16_MIN UINT_FAST16_MAX INT_FAST32_MAX INT_FAST32_MIN UINT_FAST32_MAX INT_FAST64_MAX INT_FAST64_MIN UINT_FAST64_MAX INTMAX_MAX INTMAX_MIN UINTMAX_MAX SIZE_MAX PTRDIFF_MAX PTRDIFF_MIN INTPTR_MAX INTPTR_MIN UINTPTR_MAX WCHAR_MIN WCHAR_MAX WINT_MIN WINT_MAX SIG_ATOMIC_MIN SIG_ATOMIC_MAX INT8_C UINT8_C INT16_C UINT16_C INT32_C UINT32_C INT64_C UINT64_C INTMAX_C UINTMAX_C stdbool.h _STDBOOL bool true false __bool_true_false_are_defined INLINE ROMCONST PACK_STRUCT_STRUCT PACK_STRUCT_BEGIN PACK_STRUCT_END chlists.h _CHLISTS_H_ queue_init list_init isempty notempty _THREADSQUEUE_DATA THREADSQUEUE_DECL chcore.h _CHCORE_H_ CORTEX_M0 CORTEX_M1 CORTEX_M3 CORTEX_M4 cmparams.h _CMPARAMS_H_ CORTEX_MODEL CORTEX_HAS_ST CORTEX_HAS_MPU CORTEX_HAS_FPU CORTEX_PRIORITY_BITS CORTEX_PRIORITY_LEVELS CORTEX_MINIMUM_PRIORITY CORTEX_MAXIMUM_PRIORITY CORTEX_IS_VALID_PRIORITY CORTEX_IS_VALID_KERNEL_PRIORITY CORTEX_PRIORITY_MASK CH_ARCHITECTURE_ARM CH_COMPILER_NAME chcore_v7m.h _CHCORE_V7M_H_ CORTEX_BASEPRI_DISABLED PORT_IDLE_THREAD_STACK_SIZE PORT_INT_REQUIRED_STACK CORTEX_ENABLE_WFI_IDLE CORTEX_PRIORITY_SYSTICK CORTEX_USE_FPU CORTEX_SIMPLIFIED_PRIORITY CORTEX_PRIORITY_SVCALL CORTEX_VTOR_INIT CORTEX_PRIGROUP_INIT CORTEX_MAX_KERNEL_PRIORITY CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_PENDSV CH_ARCHITECTURE_ARM_v7M CH_ARCHITECTURE_NAME CH_CORE_VARIANT_NAME CH_PORT_INFO SETUP_CONTEXT STACK_ALIGN THD_WA_SIZE WORKING_AREA PORT_IRQ_PROLOGUE PORT_IRQ_EPILOGUE PORT_IRQ_HANDLER PORT_FAST_IRQ_HANDLER port_init port_lock port_unlock port_lock_from_isr port_unlock_from_isr port_disable port_suspend port_enable port_wait_for_interrupt port_switch intrinsics.h __INTRINSICS_INCLUDED __TID__ __cpid __cpreg __cpopc __constrange __fabs __fabsf nvic.h _NVIC_H_ HANDLER_MEM_MANAGE HANDLER_BUS_FAULT HANDLER_USAGE_FAULT HANDLER_RESERVED_3 HANDLER_RESERVED_4 HANDLER_RESERVED_5 HANDLER_RESERVED_6 HANDLER_SVCALL HANDLER_DEBUG_MONITOR HANDLER_RESERVED_9 HANDLER_PENDSV HANDLER_SYSTICK NVIC_ITCR STBase ST_CSR ST_RVR ST_CVR ST_CBVR CSR_ENABLE_MASK ENABLE_OFF_BITS ENABLE_ON_BITS CSR_TICKINT_MASK TICKINT_DISABLED_BITS TICKINT_ENABLED_BITS CSR_CLKSOURCE_MASK CLKSOURCE_EXT_BITS CLKSOURCE_CORE_BITS CSR_COUNTFLAG_MASK RVR_RELOAD_MASK CVR_CURRENT_MASK CBVR_TENMS_MASK CBVR_SKEW_MASK CBVR_NOREF_MASK NVICBase NVIC_ISER NVIC_ICER NVIC_ISPR NVIC_ICPR NVIC_IABR NVIC_IPR NVIC_STIR SCBBase SCB_CPUID SCB_ICSR SCB_VTOR SCB_AIRCR SCB_SCR SCB_CCR SCB_SHPR SCB_SHCSR SCB_CFSR SCB_HFSR SCB_DFSR SCB_MMFAR SCB_BFAR SCB_AFSR SCB_PFR SCB_DFR SCB_ADR SCB_MMFR SCB_SAR SCB_CPACR ICSR_VECTACTIVE_MASK ICSR_RETTOBASE ICSR_VECTPENDING_MASK ICSR_ISRPENDING ICSR_ISRPREEMPT ICSR_PENDSTCLR ICSR_PENDSTSET ICSR_PENDSVCLR ICSR_PENDSVSET ICSR_NMIPENDSET AIRCR_VECTKEY AIRCR_PRIGROUP_MASK AIRCR_PRIGROUP FPUBase SCB_FPCCR SCB_FPCAR SCB_FPDSCR SCB_MVFR0 SCB_MVFR1 FPCCR_ASPEN FPCCR_LSPEN FPCCR_MONRDY FPCCR_BFRDY FPCCR_MMRDY FPCCR_HFRDY FPCCR_THREAD FPCCR_USER FPCCR_LSPACT FPDSCR_AHP FPDSCR_DN FPDSCR_FZ FPDSCR_RMODE SCSBase SCS_DHCSR SCS_DCRSR SCS_DCRDR SCS_DEMCR SCS_DEMCR_TRCENA DWTBase DWT_CTRL DWT_CYCCNT DWT_CPICNT DWT_EXCCNT DWT_SLEEPCNT DWT_LSUCNT DWT_FOLDCNT DWT_PCSR DWT_CTRL_CYCCNTENA PORT_OPTIMIZED_ISPREEMPTIONREQUIRED chSchIsPreemptionRequired chsys.h _CHSYS_H_ chSysGetIdleThread chSysHalt chSysSwitch chSysDisable chSysSuspend chSysEnable chSysLock chSysUnlock chSysLockFromIsr chSysUnlockFromIsr CH_IRQ_PROLOGUE CH_IRQ_EPILOGUE CH_IRQ_HANDLER CH_FAST_IRQ_HANDLER chvt.h _CHVT_H_ S2ST MS2ST US2ST chVTDoTickI chVTIsArmedI chVTSet chVTReset chTimeNow chschd.h _CHSCHD_H_ RDY_OK RDY_TIMEOUT RDY_RESET NOPRIO IDLEPRIO LOWPRIO NORMALPRIO HIGHPRIO ABSPRIO TIME_IMMEDIATE TIME_INFINITE firstprio currp setcurrp chSchIsRescRequiredI chSchCanYieldS chSchDoYieldS chSchPreemption chsem.h _CHSEM_H_ _SEMAPHORE_DATA SEMAPHORE_DECL chSemFastWaitI chSemFastSignalI chSemGetCounterI chbsem.h _CHBSEM_H_ _BSEMAPHORE_DATA BSEMAPHORE_DECL chBSemInit chBSemWait chBSemWaitS chBSemWaitTimeout chBSemWaitTimeoutS chBSemReset chBSemResetI chBSemSignal chBSemSignalI chBSemGetStateI chmtx.h _CHMTX_H_ _MUTEX_DATA MUTEX_DECL chMtxQueueNotEmptyS chcond.h _CHCOND_H_ _CONDVAR_DATA CONDVAR_DECL chevents.h _CHEVENTS_H_ _EVENTSOURCE_DATA EVENTSOURCE_DECL ALL_EVENTS EVENT_MASK chEvtRegister chEvtInit chEvtIsListeningI chEvtBroadcast chEvtBroadcastI chmsg.h _CHMSG_H_ chMsgIsPendingI chMsgGet chMsgReleaseS chmboxes.h _CHMBOXES_H_ chMBSizeI chMBGetFreeCountI chMBGetUsedCountI chMBPeekI _MAILBOX_DATA MAILBOX_DECL chmemcore.h _CHMEMCORE_H_ MEM_ALIGN_SIZE MEM_ALIGN_MASK MEM_ALIGN_PREV MEM_ALIGN_NEXT MEM_IS_ALIGNED chheap.h _CHHEAP_H_ chmempools.h _CHMEMPOOLS_H_ _MEMORYPOOL_DATA MEMORYPOOL_DECL chPoolAdd chPoolAddI chthreads.h _CHTHREADS_H_ THD_STATE_READY THD_STATE_CURRENT THD_STATE_SUSPENDED THD_STATE_WTSEM THD_STATE_WTMTX THD_STATE_WTCOND THD_STATE_SLEEPING THD_STATE_WTEXIT THD_STATE_WTOREVT THD_STATE_WTANDEVT THD_STATE_SNDMSGQ THD_STATE_SNDMSG THD_STATE_WTMSG THD_STATE_WTQUEUE THD_STATE_FINAL THD_STATE_NAMES THD_MEM_MODE_MASK THD_MEM_MODE_STATIC THD_MEM_MODE_HEAP THD_MEM_MODE_MEMPOOL THD_TERMINATE chThdSelf chThdGetPriority chThdGetTicks chThdLS chThdTerminated chThdShouldTerminate chThdResumeI chThdSleepS chThdSleepSeconds chThdSleepMilliseconds chThdSleepMicroseconds chdynamic.h _CHDYNAMIC_H_ chregistry.h _CHREGISTRY_H_ chRegSetThreadName chRegGetThreadName REG_REMOVE REG_INSERT chinline.h _CHINLINE_H_ chqueues.h _CHQUEUES_H_ Q_OK Q_TIMEOUT Q_RESET Q_EMPTY Q_FULL chQSizeI chQSpaceI chQGetLink chIQGetFullI chIQGetEmptyI chIQIsEmptyI chIQIsFullI chIQGet _INPUTQUEUE_DATA INPUTQUEUE_DECL chOQGetFullI chOQGetEmptyI chOQIsEmptyI chOQIsFullI chOQPut _OUTPUTQUEUE_DATA OUTPUTQUEUE_DECL chstreams.h _CHSTREAMS_H_ _base_sequential_stream_methods _base_sequential_stream_data chSequentialStreamWrite chSequentialStreamRead chSequentialStreamPut chSequentialStreamGet chfiles.h _CHFILES_H_ FILE_OK FILE_ERROR _base_file_stream_methods _base_file_stream_data chFileStreamClose chFileStreamGetError chFileStreamGetSize chFileStreamGetPosition chFileStreamSeek chdebug.h _CHDEBUG_H_ CH_DBG_ENABLED __QUOTE_THIS CH_TRACE_BUFFER_SIZE CH_STACK_FILL_VALUE CH_THREAD_FILL_VALUE dbg_enter_lock dbg_leave_lock dbg_check_disable dbg_check_suspend dbg_check_enable dbg_check_lock dbg_check_unlock dbg_check_lock_from_isr dbg_check_unlock_from_isr dbg_check_enter_isr dbg_check_leave_isr chDbgCheckClassI chDbgCheckClassS dbg_trace chDbgCheck chDbgAssert chDbgPanic hal.h _HAL_H_ board.h _BOARD_H_ BOARD_ST_STM32L_DISCOVERY BOARD_NAME STM32_LSECLK STM32_HSECLK STM32_HSE_BYPASS STM32L1XX_MD GPIOA_BUTTON GPIOA_PIN1 GPIOA_PIN2 GPIOA_PIN3 GPIOA_PIN4 GPIOA_PIN5 GPIOA_PIN6 GPIOA_PIN7 GPIOA_PIN8 GPIOA_PIN9 GPIOA_PIN10 GPIOA_PIN11 GPIOA_PIN12 GPIOA_JTAG_TMS GPIOA_JTAG_TCK GPIOA_JTAG_TDI GPIOB_PIN0 GPIOB_PIN1 GPIOB_BOOT1 GPIOB_JTAG_TDO GPIOB_JTAG_TRST GPIOB_PIN5 GPIOB_LED4 GPIOB_LED3 GPIOB_PIN8 GPIOB_PIN9 GPIOB_PIN10 GPIOB_PIN11 GPIOB_PIN12 GPIOB_PIN13 GPIOB_PIN14 GPIOB_PIN15 GPIOC_PIN0 GPIOC_PIN1 GPIOC_PIN2 GPIOC_PIN3 GPIOC_PIN4 GPIOC_PIN5 GPIOC_PIN6 GPIOC_PIN7 GPIOC_PIN8 GPIOC_PIN9 GPIOC_PIN10 GPIOC_PIN11 GPIOC_PIN12 GPIOC_PIN13 GPIOC_OSC32_IN GPIOC_OSC32_OUT GPIOD_PIN0 GPIOD_PIN1 GPIOD_PIN2 GPIOD_PIN3 GPIOD_PIN4 GPIOD_PIN5 GPIOD_PIN6 GPIOD_PIN7 GPIOD_PIN8 GPIOD_PIN9 GPIOD_PIN10 GPIOD_PIN11 GPIOD_PIN12 GPIOD_PIN13 GPIOD_PIN14 GPIOD_PIN15 GPIOE_PIN0 GPIOE_PIN1 GPIOE_PIN2 GPIOE_PIN3 GPIOE_PIN4 GPIOE_PIN5 GPIOE_PIN6 GPIOE_PIN7 GPIOE_PIN8 GPIOE_PIN9 GPIOE_PIN10 GPIOE_PIN11 GPIOE_PIN12 GPIOE_PIN13 GPIOE_PIN14 GPIOE_PIN15 GPIOH_OSC_IN GPIOH_OSC_OUT GPIOH_PIN2 GPIOH_PIN3 GPIOH_PIN4 GPIOH_PIN5 GPIOH_PIN6 GPIOH_PIN7 GPIOH_PIN8 GPIOH_PIN9 GPIOH_PIN10 GPIOH_PIN11 GPIOH_PIN12 GPIOH_PIN13 GPIOH_PIN14 GPIOH_PIN15 PIN_MODE_INPUT PIN_MODE_OUTPUT PIN_MODE_ALTERNATE PIN_MODE_ANALOG PIN_ODR_LOW PIN_ODR_HIGH PIN_OTYPE_PUSHPULL PIN_OTYPE_OPENDRAIN PIN_OSPEED_400K PIN_OSPEED_2M PIN_OSPEED_10M PIN_OSPEED_40M PIN_PUPDR_FLOATING PIN_PUPDR_PULLUP PIN_PUPDR_PULLDOWN PIN_AFIO_AF VAL_GPIOA_MODER VAL_GPIOA_OTYPER VAL_GPIOA_OSPEEDR VAL_GPIOA_PUPDR VAL_GPIOA_ODR VAL_GPIOA_AFRL VAL_GPIOA_AFRH VAL_GPIOB_MODER VAL_GPIOB_OTYPER VAL_GPIOB_OSPEEDR VAL_GPIOB_PUPDR VAL_GPIOB_ODR VAL_GPIOB_AFRL VAL_GPIOB_AFRH VAL_GPIOC_MODER VAL_GPIOC_OTYPER VAL_GPIOC_OSPEEDR VAL_GPIOC_PUPDR VAL_GPIOC_ODR VAL_GPIOC_AFRL VAL_GPIOC_AFRH VAL_GPIOD_MODER VAL_GPIOD_OTYPER VAL_GPIOD_OSPEEDR VAL_GPIOD_PUPDR VAL_GPIOD_ODR VAL_GPIOD_AFRL VAL_GPIOD_AFRH VAL_GPIOE_MODER VAL_GPIOE_OTYPER VAL_GPIOE_OSPEEDR VAL_GPIOE_PUPDR VAL_GPIOE_ODR VAL_GPIOE_AFRL VAL_GPIOE_AFRH VAL_GPIOH_MODER VAL_GPIOH_OTYPER VAL_GPIOH_OSPEEDR VAL_GPIOH_PUPDR VAL_GPIOH_ODR VAL_GPIOH_AFRL VAL_GPIOH_AFRH halconf.h _HALCONF_H_ mcuconf.h STM32L1xx_MCUCONF STM32_NO_INIT STM32_HSI_ENABLED STM32_LSI_ENABLED STM32_HSE_ENABLED STM32_LSE_ENABLED STM32_ADC_CLOCK_ENABLED STM32_USB_CLOCK_ENABLED STM32_MSIRANGE STM32_SW STM32_PLLSRC STM32_PLLMUL_VALUE STM32_PLLDIV_VALUE STM32_HPRE STM32_PPRE1 STM32_PPRE2 STM32_MCOSEL STM32_MCOPRE STM32_RTCSEL STM32_RTCPRE STM32_VOS STM32_PVD_ENABLE STM32_PLS STM32_ADC_USE_ADC1 STM32_ADC_ADC1_DMA_PRIORITY STM32_ADC_IRQ_PRIORITY STM32_ADC_ADC1_DMA_IRQ_PRIORITY STM32_EXT_EXTI0_IRQ_PRIORITY STM32_EXT_EXTI1_IRQ_PRIORITY STM32_EXT_EXTI2_IRQ_PRIORITY STM32_EXT_EXTI3_IRQ_PRIORITY STM32_EXT_EXTI4_IRQ_PRIORITY STM32_EXT_EXTI5_9_IRQ_PRIORITY STM32_EXT_EXTI10_15_IRQ_PRIORITY STM32_EXT_EXTI16_IRQ_PRIORITY STM32_EXT_EXTI17_IRQ_PRIORITY STM32_EXT_EXTI18_IRQ_PRIORITY STM32_EXT_EXTI19_IRQ_PRIORITY STM32_EXT_EXTI20_IRQ_PRIORITY STM32_EXT_EXTI21_22_IRQ_PRIORITY STM32_GPT_USE_TIM2 STM32_GPT_USE_TIM3 STM32_GPT_USE_TIM4 STM32_GPT_TIM2_IRQ_PRIORITY STM32_GPT_TIM3_IRQ_PRIORITY STM32_GPT_TIM4_IRQ_PRIORITY STM32_I2C_USE_I2C1 STM32_I2C_USE_I2C2 STM32_I2C_I2C1_IRQ_PRIORITY STM32_I2C_I2C2_IRQ_PRIORITY STM32_I2C_I2C1_DMA_PRIORITY STM32_I2C_I2C2_DMA_PRIORITY STM32_I2C_I2C1_DMA_ERROR_HOOK STM32_I2C_I2C2_DMA_ERROR_HOOK STM32_ICU_USE_TIM2 STM32_ICU_USE_TIM3 STM32_ICU_USE_TIM4 STM32_ICU_TIM2_IRQ_PRIORITY STM32_ICU_TIM3_IRQ_PRIORITY STM32_ICU_TIM4_IRQ_PRIORITY STM32_PWM_USE_TIM2 STM32_PWM_USE_TIM3 STM32_PWM_USE_TIM4 STM32_PWM_TIM2_IRQ_PRIORITY STM32_PWM_TIM3_IRQ_PRIORITY STM32_PWM_TIM4_IRQ_PRIORITY STM32_SERIAL_USE_USART1 STM32_SERIAL_USE_USART2 STM32_SERIAL_USE_USART3 STM32_SERIAL_USART1_PRIORITY STM32_SERIAL_USART2_PRIORITY STM32_SERIAL_USART3_PRIORITY STM32_SPI_USE_SPI1 STM32_SPI_USE_SPI2 STM32_SPI_SPI1_DMA_PRIORITY STM32_SPI_SPI2_DMA_PRIORITY STM32_SPI_SPI1_IRQ_PRIORITY STM32_SPI_SPI2_IRQ_PRIORITY STM32_SPI_DMA_ERROR_HOOK STM32_UART_USE_USART1 STM32_UART_USE_USART2 STM32_UART_USE_USART3 STM32_UART_USART1_IRQ_PRIORITY STM32_UART_USART2_IRQ_PRIORITY STM32_UART_USART3_IRQ_PRIORITY STM32_UART_USART1_DMA_PRIORITY STM32_UART_USART2_DMA_PRIORITY STM32_UART_USART3_DMA_PRIORITY STM32_UART_DMA_ERROR_HOOK STM32_USB_USE_USB1 STM32_USB_LOW_POWER_ON_SUSPEND STM32_USB_USB1_HP_IRQ_PRIORITY STM32_USB_USB1_LP_IRQ_PRIORITY HAL_USE_TM HAL_USE_PAL HAL_USE_ADC HAL_USE_CAN HAL_USE_EXT HAL_USE_GPT HAL_USE_I2C HAL_USE_ICU HAL_USE_MAC HAL_USE_MMC_SPI HAL_USE_PWM HAL_USE_RTC HAL_USE_SDC HAL_USE_SERIAL HAL_USE_SERIAL_USB HAL_USE_SPI HAL_USE_UART HAL_USE_USB ADC_USE_WAIT ADC_USE_MUTUAL_EXCLUSION CAN_USE_SLEEP_MODE I2C_USE_MUTUAL_EXCLUSION MAC_USE_ZERO_COPY MAC_USE_EVENTS MMC_NICE_WAITING SDC_INIT_RETRY SDC_MMC_SUPPORT SDC_NICE_WAITING SERIAL_DEFAULT_BITRATE SERIAL_BUFFERS_SIZE SPI_USE_WAIT SPI_USE_MUTUAL_EXCLUSION hal_lld.h _HAL_LLD_H_ stm32.h _STM32_H_ stm32l1xx.h __STM32L1XX_H HSE_VALUE HSE_STARTUP_TIMEOUT HSI_STARTUP_TIMEOUT HSI_VALUE LSI_VALUE LSE_VALUE __STM32L1XX_STDPERIPH_VERSION_MAIN __STM32L1XX_STDPERIPH_VERSION_SUB1 __STM32L1XX_STDPERIPH_VERSION_SUB2 __STM32L1XX_STDPERIPH_VERSION_RC __STM32L1XX_STDPERIPH_VERSION __CM3_REV __MPU_PRESENT __NVIC_PRIO_BITS __Vendor_SysTickConfig core_cm3.h __CORE_CM3_H_GENERIC __CM3_CMSIS_VERSION_MAIN __CM3_CMSIS_VERSION_SUB __CM3_CMSIS_VERSION __CORTEX_M __ASM __INLINE __STATIC_INLINE __FPU_USED core_cmInstr.h __CORE_CMINSTR_H cmsis_iar.h __CMSIS_IAR_H__ __CORE__ __ARM6M__ __enable_irq __disable_irq __NOP __VER__ __BKPT __LDREXW __STREXW __enable_fault_irq __disable_fault_irq core_cmFunc.h __CORE_CMFUNC_H __CORE_CM3_H_DEPENDANT __I __O __IO NVIC_STIR_INTID_Pos NVIC_STIR_INTID_Msk SCB_CPUID_IMPLEMENTER_Pos SCB_CPUID_IMPLEMENTER_Msk SCB_CPUID_VARIANT_Pos SCB_CPUID_VARIANT_Msk SCB_CPUID_ARCHITECTURE_Pos SCB_CPUID_ARCHITECTURE_Msk SCB_CPUID_PARTNO_Pos SCB_CPUID_PARTNO_Msk SCB_CPUID_REVISION_Pos SCB_CPUID_REVISION_Msk SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDSVSET_Pos SCB_ICSR_PENDSVSET_Msk SCB_ICSR_PENDSVCLR_Pos SCB_ICSR_PENDSVCLR_Msk SCB_ICSR_PENDSTSET_Pos SCB_ICSR_PENDSTSET_Msk SCB_ICSR_PENDSTCLR_Pos SCB_ICSR_PENDSTCLR_Msk SCB_ICSR_ISRPREEMPT_Pos SCB_ICSR_ISRPREEMPT_Msk SCB_ICSR_ISRPENDING_Pos SCB_ICSR_ISRPENDING_Msk SCB_ICSR_VECTPENDING_Pos SCB_ICSR_VECTPENDING_Msk SCB_ICSR_RETTOBASE_Pos SCB_ICSR_RETTOBASE_Msk SCB_ICSR_VECTACTIVE_Pos SCB_ICSR_VECTACTIVE_Msk SCB_VTOR_TBLBASE_Pos SCB_VTOR_TBLBASE_Msk SCB_VTOR_TBLOFF_Pos SCB_VTOR_TBLOFF_Msk SCB_AIRCR_VECTKEY_Pos SCB_AIRCR_VECTKEY_Msk SCB_AIRCR_VECTKEYSTAT_Pos SCB_AIRCR_VECTKEYSTAT_Msk SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_PRIGROUP_Pos SCB_AIRCR_PRIGROUP_Msk SCB_AIRCR_SYSRESETREQ_Pos SCB_AIRCR_SYSRESETREQ_Msk SCB_AIRCR_VECTCLRACTIVE_Pos SCB_AIRCR_VECTCLRACTIVE_Msk SCB_AIRCR_VECTRESET_Pos SCB_AIRCR_VECTRESET_Msk SCB_SCR_SEVONPEND_Pos SCB_SCR_SEVONPEND_Msk SCB_SCR_SLEEPDEEP_Pos SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPONEXIT_Pos SCB_SCR_SLEEPONEXIT_Msk SCB_CCR_STKALIGN_Pos SCB_CCR_STKALIGN_Msk SCB_CCR_BFHFNMIGN_Pos SCB_CCR_BFHFNMIGN_Msk SCB_CCR_DIV_0_TRP_Pos SCB_CCR_DIV_0_TRP_Msk SCB_CCR_UNALIGN_TRP_Pos SCB_CCR_UNALIGN_TRP_Msk SCB_CCR_USERSETMPEND_Pos SCB_CCR_USERSETMPEND_Msk SCB_CCR_NONBASETHRDENA_Pos SCB_CCR_NONBASETHRDENA_Msk SCB_SHCSR_USGFAULTENA_Pos SCB_SHCSR_USGFAULTENA_Msk SCB_SHCSR_BUSFAULTENA_Pos SCB_SHCSR_BUSFAULTENA_Msk SCB_SHCSR_MEMFAULTENA_Pos SCB_SHCSR_MEMFAULTENA_Msk SCB_SHCSR_SVCALLPENDED_Pos SCB_SHCSR_SVCALLPENDED_Msk SCB_SHCSR_BUSFAULTPENDED_Pos SCB_SHCSR_BUSFAULTPENDED_Msk SCB_SHCSR_MEMFAULTPENDED_Pos SCB_SHCSR_MEMFAULTPENDED_Msk SCB_SHCSR_USGFAULTPENDED_Pos SCB_SHCSR_USGFAULTPENDED_Msk SCB_SHCSR_SYSTICKACT_Pos SCB_SHCSR_SYSTICKACT_Msk SCB_SHCSR_PENDSVACT_Pos SCB_SHCSR_PENDSVACT_Msk SCB_SHCSR_MONITORACT_Pos SCB_SHCSR_MONITORACT_Msk SCB_SHCSR_SVCALLACT_Pos SCB_SHCSR_SVCALLACT_Msk SCB_SHCSR_USGFAULTACT_Pos SCB_SHCSR_USGFAULTACT_Msk SCB_SHCSR_BUSFAULTACT_Pos SCB_SHCSR_BUSFAULTACT_Msk SCB_SHCSR_MEMFAULTACT_Pos SCB_SHCSR_MEMFAULTACT_Msk SCB_CFSR_USGFAULTSR_Pos SCB_CFSR_USGFAULTSR_Msk SCB_CFSR_BUSFAULTSR_Pos SCB_CFSR_BUSFAULTSR_Msk SCB_CFSR_MEMFAULTSR_Pos SCB_CFSR_MEMFAULTSR_Msk SCB_HFSR_DEBUGEVT_Pos SCB_HFSR_DEBUGEVT_Msk SCB_HFSR_FORCED_Pos SCB_HFSR_FORCED_Msk SCB_HFSR_VECTTBL_Pos SCB_HFSR_VECTTBL_Msk SCB_DFSR_EXTERNAL_Pos SCB_DFSR_EXTERNAL_Msk SCB_DFSR_VCATCH_Pos SCB_DFSR_VCATCH_Msk SCB_DFSR_DWTTRAP_Pos SCB_DFSR_DWTTRAP_Msk SCB_DFSR_BKPT_Pos SCB_DFSR_BKPT_Msk SCB_DFSR_HALTED_Pos SCB_DFSR_HALTED_Msk SCnSCB_ICTR_INTLINESNUM_Pos SCnSCB_ICTR_INTLINESNUM_Msk SCnSCB_ACTLR_DISFOLD_Pos SCnSCB_ACTLR_DISFOLD_Msk SCnSCB_ACTLR_DISDEFWBUF_Pos SCnSCB_ACTLR_DISDEFWBUF_Msk SCnSCB_ACTLR_DISMCYCINT_Pos SCnSCB_ACTLR_DISMCYCINT_Msk SysTick_CTRL_COUNTFLAG_Pos SysTick_CTRL_COUNTFLAG_Msk SysTick_CTRL_CLKSOURCE_Pos SysTick_CTRL_CLKSOURCE_Msk SysTick_CTRL_TICKINT_Pos SysTick_CTRL_TICKINT_Msk SysTick_CTRL_ENABLE_Pos SysTick_CTRL_ENABLE_Msk SysTick_LOAD_RELOAD_Pos SysTick_LOAD_RELOAD_Msk SysTick_VAL_CURRENT_Pos SysTick_VAL_CURRENT_Msk SysTick_CALIB_NOREF_Pos SysTick_CALIB_NOREF_Msk SysTick_CALIB_SKEW_Pos SysTick_CALIB_SKEW_Msk SysTick_CALIB_TENMS_Pos SysTick_CALIB_TENMS_Msk ITM_TPR_PRIVMASK_Pos ITM_TPR_PRIVMASK_Msk ITM_TCR_BUSY_Pos ITM_TCR_BUSY_Msk ITM_TCR_TraceBusID_Pos ITM_TCR_TraceBusID_Msk ITM_TCR_GTSFREQ_Pos ITM_TCR_GTSFREQ_Msk ITM_TCR_TSPrescale_Pos ITM_TCR_TSPrescale_Msk ITM_TCR_SWOENA_Pos ITM_TCR_SWOENA_Msk ITM_TCR_DWTENA_Pos ITM_TCR_DWTENA_Msk ITM_TCR_SYNCENA_Pos ITM_TCR_SYNCENA_Msk ITM_TCR_TSENA_Pos ITM_TCR_TSENA_Msk ITM_TCR_ITMENA_Pos ITM_TCR_ITMENA_Msk ITM_IWR_ATVALIDM_Pos ITM_IWR_ATVALIDM_Msk ITM_IRR_ATREADYM_Pos ITM_IRR_ATREADYM_Msk ITM_IMCR_INTEGRATION_Pos ITM_IMCR_INTEGRATION_Msk ITM_LSR_ByteAcc_Pos ITM_LSR_ByteAcc_Msk ITM_LSR_Access_Pos ITM_LSR_Access_Msk ITM_LSR_Present_Pos ITM_LSR_Present_Msk DWT_CTRL_NUMCOMP_Pos DWT_CTRL_NUMCOMP_Msk DWT_CTRL_NOTRCPKT_Pos DWT_CTRL_NOTRCPKT_Msk DWT_CTRL_NOEXTTRIG_Pos DWT_CTRL_NOEXTTRIG_Msk DWT_CTRL_NOCYCCNT_Pos DWT_CTRL_NOCYCCNT_Msk DWT_CTRL_NOPRFCNT_Pos DWT_CTRL_NOPRFCNT_Msk DWT_CTRL_CYCEVTENA_Pos DWT_CTRL_CYCEVTENA_Msk DWT_CTRL_FOLDEVTENA_Pos DWT_CTRL_FOLDEVTENA_Msk DWT_CTRL_LSUEVTENA_Pos DWT_CTRL_LSUEVTENA_Msk DWT_CTRL_SLEEPEVTENA_Pos DWT_CTRL_SLEEPEVTENA_Msk DWT_CTRL_EXCEVTENA_Pos DWT_CTRL_EXCEVTENA_Msk DWT_CTRL_CPIEVTENA_Pos DWT_CTRL_CPIEVTENA_Msk DWT_CTRL_EXCTRCENA_Pos DWT_CTRL_EXCTRCENA_Msk DWT_CTRL_PCSAMPLENA_Pos DWT_CTRL_PCSAMPLENA_Msk DWT_CTRL_SYNCTAP_Pos DWT_CTRL_SYNCTAP_Msk DWT_CTRL_CYCTAP_Pos DWT_CTRL_CYCTAP_Msk DWT_CTRL_POSTINIT_Pos DWT_CTRL_POSTINIT_Msk DWT_CTRL_POSTPRESET_Pos DWT_CTRL_POSTPRESET_Msk DWT_CTRL_CYCCNTENA_Pos DWT_CTRL_CYCCNTENA_Msk DWT_CPICNT_CPICNT_Pos DWT_CPICNT_CPICNT_Msk DWT_EXCCNT_EXCCNT_Pos DWT_EXCCNT_EXCCNT_Msk DWT_SLEEPCNT_SLEEPCNT_Pos DWT_SLEEPCNT_SLEEPCNT_Msk DWT_LSUCNT_LSUCNT_Pos DWT_LSUCNT_LSUCNT_Msk DWT_FOLDCNT_FOLDCNT_Pos DWT_FOLDCNT_FOLDCNT_Msk DWT_MASK_MASK_Pos DWT_MASK_MASK_Msk DWT_FUNCTION_MATCHED_Pos DWT_FUNCTION_MATCHED_Msk DWT_FUNCTION_DATAVADDR1_Pos DWT_FUNCTION_DATAVADDR1_Msk DWT_FUNCTION_DATAVADDR0_Pos DWT_FUNCTION_DATAVADDR0_Msk DWT_FUNCTION_DATAVSIZE_Pos DWT_FUNCTION_DATAVSIZE_Msk DWT_FUNCTION_LNK1ENA_Pos DWT_FUNCTION_LNK1ENA_Msk DWT_FUNCTION_DATAVMATCH_Pos DWT_FUNCTION_DATAVMATCH_Msk DWT_FUNCTION_CYCMATCH_Pos DWT_FUNCTION_CYCMATCH_Msk DWT_FUNCTION_EMITRANGE_Pos DWT_FUNCTION_EMITRANGE_Msk DWT_FUNCTION_FUNCTION_Pos DWT_FUNCTION_FUNCTION_Msk TPI_ACPR_PRESCALER_Pos TPI_ACPR_PRESCALER_Msk TPI_SPPR_TXMODE_Pos TPI_SPPR_TXMODE_Msk TPI_FFSR_FtNonStop_Pos TPI_FFSR_FtNonStop_Msk TPI_FFSR_TCPresent_Pos TPI_FFSR_TCPresent_Msk TPI_FFSR_FtStopped_Pos TPI_FFSR_FtStopped_Msk TPI_FFSR_FlInProg_Pos TPI_FFSR_FlInProg_Msk TPI_FFCR_TrigIn_Pos TPI_FFCR_TrigIn_Msk TPI_FFCR_EnFCont_Pos TPI_FFCR_EnFCont_Msk TPI_TRIGGER_TRIGGER_Pos TPI_TRIGGER_TRIGGER_Msk TPI_FIFO0_ITM_ATVALID_Pos TPI_FIFO0_ITM_ATVALID_Msk TPI_FIFO0_ITM_bytecount_Pos TPI_FIFO0_ITM_bytecount_Msk TPI_FIFO0_ETM_ATVALID_Pos TPI_FIFO0_ETM_ATVALID_Msk TPI_FIFO0_ETM_bytecount_Pos TPI_FIFO0_ETM_bytecount_Msk TPI_FIFO0_ETM2_Pos TPI_FIFO0_ETM2_Msk TPI_FIFO0_ETM1_Pos TPI_FIFO0_ETM1_Msk TPI_FIFO0_ETM0_Pos TPI_FIFO0_ETM0_Msk TPI_ITATBCTR2_ATREADY_Pos TPI_ITATBCTR2_ATREADY_Msk TPI_FIFO1_ITM_ATVALID_Pos TPI_FIFO1_ITM_ATVALID_Msk TPI_FIFO1_ITM_bytecount_Pos TPI_FIFO1_ITM_bytecount_Msk TPI_FIFO1_ETM_ATVALID_Pos TPI_FIFO1_ETM_ATVALID_Msk TPI_FIFO1_ETM_bytecount_Pos TPI_FIFO1_ETM_bytecount_Msk TPI_FIFO1_ITM2_Pos TPI_FIFO1_ITM2_Msk TPI_FIFO1_ITM1_Pos TPI_FIFO1_ITM1_Msk TPI_FIFO1_ITM0_Pos TPI_FIFO1_ITM0_Msk TPI_ITATBCTR0_ATREADY_Pos TPI_ITATBCTR0_ATREADY_Msk TPI_ITCTRL_Mode_Pos TPI_ITCTRL_Mode_Msk TPI_DEVID_NRZVALID_Pos TPI_DEVID_NRZVALID_Msk TPI_DEVID_MANCVALID_Pos TPI_DEVID_MANCVALID_Msk TPI_DEVID_PTINVALID_Pos TPI_DEVID_PTINVALID_Msk TPI_DEVID_MinBufSz_Pos TPI_DEVID_MinBufSz_Msk TPI_DEVID_AsynClkIn_Pos TPI_DEVID_AsynClkIn_Msk TPI_DEVID_NrTraceInput_Pos TPI_DEVID_NrTraceInput_Msk TPI_DEVTYPE_SubType_Pos TPI_DEVTYPE_SubType_Msk TPI_DEVTYPE_MajorType_Pos TPI_DEVTYPE_MajorType_Msk MPU_TYPE_IREGION_Pos MPU_TYPE_IREGION_Msk MPU_TYPE_DREGION_Pos MPU_TYPE_DREGION_Msk MPU_TYPE_SEPARATE_Pos MPU_TYPE_SEPARATE_Msk MPU_CTRL_PRIVDEFENA_Pos MPU_CTRL_PRIVDEFENA_Msk MPU_CTRL_HFNMIENA_Pos MPU_CTRL_HFNMIENA_Msk MPU_CTRL_ENABLE_Pos MPU_CTRL_ENABLE_Msk MPU_RNR_REGION_Pos MPU_RNR_REGION_Msk MPU_RBAR_ADDR_Pos MPU_RBAR_ADDR_Msk MPU_RBAR_VALID_Pos MPU_RBAR_VALID_Msk MPU_RBAR_REGION_Pos MPU_RBAR_REGION_Msk MPU_RASR_ATTRS_Pos MPU_RASR_ATTRS_Msk MPU_RASR_XN_Pos MPU_RASR_XN_Msk MPU_RASR_AP_Pos MPU_RASR_AP_Msk MPU_RASR_TEX_Pos MPU_RASR_TEX_Msk MPU_RASR_S_Pos MPU_RASR_S_Msk MPU_RASR_C_Pos MPU_RASR_C_Msk MPU_RASR_B_Pos MPU_RASR_B_Msk MPU_RASR_SRD_Pos MPU_RASR_SRD_Msk MPU_RASR_SIZE_Pos MPU_RASR_SIZE_Msk MPU_RASR_ENABLE_Pos MPU_RASR_ENABLE_Msk CoreDebug_DHCSR_DBGKEY_Pos CoreDebug_DHCSR_DBGKEY_Msk CoreDebug_DHCSR_S_RESET_ST_Pos CoreDebug_DHCSR_S_RESET_ST_Msk CoreDebug_DHCSR_S_RETIRE_ST_Pos CoreDebug_DHCSR_S_RETIRE_ST_Msk CoreDebug_DHCSR_S_LOCKUP_Pos CoreDebug_DHCSR_S_LOCKUP_Msk CoreDebug_DHCSR_S_SLEEP_Pos CoreDebug_DHCSR_S_SLEEP_Msk CoreDebug_DHCSR_S_HALT_Pos CoreDebug_DHCSR_S_HALT_Msk CoreDebug_DHCSR_S_REGRDY_Pos CoreDebug_DHCSR_S_REGRDY_Msk CoreDebug_DHCSR_C_SNAPSTALL_Pos CoreDebug_DHCSR_C_SNAPSTALL_Msk CoreDebug_DHCSR_C_MASKINTS_Pos CoreDebug_DHCSR_C_MASKINTS_Msk CoreDebug_DHCSR_C_STEP_Pos CoreDebug_DHCSR_C_STEP_Msk CoreDebug_DHCSR_C_HALT_Pos CoreDebug_DHCSR_C_HALT_Msk CoreDebug_DHCSR_C_DEBUGEN_Pos CoreDebug_DHCSR_C_DEBUGEN_Msk CoreDebug_DCRSR_REGWnR_Pos CoreDebug_DCRSR_REGWnR_Msk CoreDebug_DCRSR_REGSEL_Pos CoreDebug_DCRSR_REGSEL_Msk CoreDebug_DEMCR_TRCENA_Pos CoreDebug_DEMCR_TRCENA_Msk CoreDebug_DEMCR_MON_REQ_Pos CoreDebug_DEMCR_MON_REQ_Msk CoreDebug_DEMCR_MON_STEP_Pos CoreDebug_DEMCR_MON_STEP_Msk CoreDebug_DEMCR_MON_PEND_Pos CoreDebug_DEMCR_MON_PEND_Msk CoreDebug_DEMCR_MON_EN_Pos CoreDebug_DEMCR_MON_EN_Msk CoreDebug_DEMCR_VC_HARDERR_Pos CoreDebug_DEMCR_VC_HARDERR_Msk CoreDebug_DEMCR_VC_INTERR_Pos CoreDebug_DEMCR_VC_INTERR_Msk CoreDebug_DEMCR_VC_BUSERR_Pos CoreDebug_DEMCR_VC_BUSERR_Msk CoreDebug_DEMCR_VC_STATERR_Pos CoreDebug_DEMCR_VC_STATERR_Msk CoreDebug_DEMCR_VC_CHKERR_Pos CoreDebug_DEMCR_VC_CHKERR_Msk CoreDebug_DEMCR_VC_NOCPERR_Pos CoreDebug_DEMCR_VC_NOCPERR_Msk CoreDebug_DEMCR_VC_MMERR_Pos CoreDebug_DEMCR_VC_MMERR_Msk CoreDebug_DEMCR_VC_CORERESET_Pos CoreDebug_DEMCR_VC_CORERESET_Msk SCS_BASE ITM_BASE DWT_BASE TPI_BASE CoreDebug_BASE SysTick_BASE NVIC_BASE SCB_BASE SCnSCB SCB SysTick NVIC ITM DWT TPI CoreDebug MPU_BASE MPU ITM_RXBUFFER_EMPTY IS_FUNCTIONAL_STATE __RAM_FUNC FLASH_BASE SRAM_BASE PERIPH_BASE SRAM_BB_BASE PERIPH_BB_BASE FSMC_R_BASE APB1PERIPH_BASE APB2PERIPH_BASE AHBPERIPH_BASE TIM2_BASE TIM3_BASE TIM4_BASE TIM5_BASE TIM6_BASE TIM7_BASE LCD_BASE RTC_BASE WWDG_BASE IWDG_BASE SPI2_BASE SPI3_BASE USART2_BASE USART3_BASE UART4_BASE UART5_BASE I2C1_BASE I2C2_BASE PWR_BASE DAC_BASE COMP_BASE RI_BASE OPAMP_BASE SYSCFG_BASE EXTI_BASE TIM9_BASE TIM10_BASE TIM11_BASE ADC1_BASE ADC_BASE SDIO_BASE SPI1_BASE USART1_BASE GPIOA_BASE GPIOB_BASE GPIOC_BASE GPIOD_BASE GPIOE_BASE GPIOH_BASE GPIOF_BASE GPIOG_BASE CRC_BASE RCC_BASE FLASH_R_BASE OB_BASE DMA1_BASE DMA1_Channel1_BASE DMA1_Channel2_BASE DMA1_Channel3_BASE DMA1_Channel4_BASE DMA1_Channel5_BASE DMA1_Channel6_BASE DMA1_Channel7_BASE DMA2_BASE DMA2_Channel1_BASE DMA2_Channel2_BASE DMA2_Channel3_BASE DMA2_Channel4_BASE DMA2_Channel5_BASE AES_BASE FSMC_Bank1_R_BASE FSMC_Bank1E_R_BASE DBGMCU_BASE TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 LCD RTC WWDG IWDG SPI2 SPI3 USART2 USART3 UART4 UART5 I2C1 I2C2 PWR DAC COMP RI OPAMP SYSCFG EXTI ADC1 ADC SDIO TIM9 TIM10 TIM11 SPI1 USART1 DMA1 DMA1_Channel1 DMA1_Channel2 DMA1_Channel3 DMA1_Channel4 DMA1_Channel5 DMA1_Channel6 DMA1_Channel7 DMA2 DMA2_Channel1 DMA2_Channel2 DMA2_Channel3 DMA2_Channel4 DMA2_Channel5 RCC CRC GPIOA GPIOB GPIOC GPIOD GPIOE GPIOH GPIOF GPIOG FLASH OB AES FSMC_Bank1 FSMC_Bank1E DBGMCU ADC_SR_AWD ADC_SR_EOC ADC_SR_JEOC ADC_SR_JSTRT ADC_SR_STRT ADC_SR_OVR ADC_SR_ADONS ADC_SR_RCNR ADC_SR_JCNR ADC_CR1_AWDCH ADC_CR1_AWDCH_0 ADC_CR1_AWDCH_1 ADC_CR1_AWDCH_2 ADC_CR1_AWDCH_3 ADC_CR1_AWDCH_4 ADC_CR1_EOCIE ADC_CR1_AWDIE ADC_CR1_JEOCIE ADC_CR1_SCAN ADC_CR1_AWDSGL ADC_CR1_JAUTO ADC_CR1_DISCEN ADC_CR1_JDISCEN ADC_CR1_DISCNUM ADC_CR1_DISCNUM_0 ADC_CR1_DISCNUM_1 ADC_CR1_DISCNUM_2 ADC_CR1_PDD ADC_CR1_PDI ADC_CR1_JAWDEN ADC_CR1_AWDEN ADC_CR1_RES ADC_CR1_RES_0 ADC_CR1_RES_1 ADC_CR1_OVRIE ADC_CR2_ADON ADC_CR2_CONT ADC_CR2_CFG ADC_CR2_DELS ADC_CR2_DELS_0 ADC_CR2_DELS_1 ADC_CR2_DELS_2 ADC_CR2_DMA ADC_CR2_DDS ADC_CR2_EOCS ADC_CR2_ALIGN ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_0 ADC_CR2_JEXTSEL_1 ADC_CR2_JEXTSEL_2 ADC_CR2_JEXTSEL_3 ADC_CR2_JEXTEN ADC_CR2_JEXTEN_0 ADC_CR2_JEXTEN_1 ADC_CR2_JSWSTART ADC_CR2_EXTSEL ADC_CR2_EXTSEL_0 ADC_CR2_EXTSEL_1 ADC_CR2_EXTSEL_2 ADC_CR2_EXTSEL_3 ADC_CR2_EXTEN ADC_CR2_EXTEN_0 ADC_CR2_EXTEN_1 ADC_CR2_SWSTART ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_0 ADC_SMPR1_SMP20_1 ADC_SMPR1_SMP20_2 ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_0 ADC_SMPR1_SMP21_1 ADC_SMPR1_SMP21_2 ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_0 ADC_SMPR1_SMP22_1 ADC_SMPR1_SMP22_2 ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_0 ADC_SMPR1_SMP23_1 ADC_SMPR1_SMP23_2 ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_0 ADC_SMPR1_SMP24_1 ADC_SMPR1_SMP24_2 ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_0 ADC_SMPR1_SMP25_1 ADC_SMPR1_SMP25_2 ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_0 ADC_SMPR1_SMP26_1 ADC_SMPR1_SMP26_2 ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_0 ADC_SMPR1_SMP27_1 ADC_SMPR1_SMP27_2 ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_0 ADC_SMPR1_SMP28_1 ADC_SMPR1_SMP28_2 ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_0 ADC_SMPR1_SMP29_1 ADC_SMPR1_SMP29_2 ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_0 ADC_SMPR2_SMP10_1 ADC_SMPR2_SMP10_2 ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_0 ADC_SMPR2_SMP11_1 ADC_SMPR2_SMP11_2 ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_0 ADC_SMPR2_SMP12_1 ADC_SMPR2_SMP12_2 ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_0 ADC_SMPR2_SMP13_1 ADC_SMPR2_SMP13_2 ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_0 ADC_SMPR2_SMP14_1 ADC_SMPR2_SMP14_2 ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_0 ADC_SMPR2_SMP15_1 ADC_SMPR2_SMP15_2 ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_0 ADC_SMPR2_SMP16_1 ADC_SMPR2_SMP16_2 ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_0 ADC_SMPR2_SMP17_1 ADC_SMPR2_SMP17_2 ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_0 ADC_SMPR2_SMP18_1 ADC_SMPR2_SMP18_2 ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_0 ADC_SMPR2_SMP19_1 ADC_SMPR2_SMP19_2 ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_0 ADC_SMPR3_SMP0_1 ADC_SMPR3_SMP0_2 ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_0 ADC_SMPR3_SMP1_1 ADC_SMPR3_SMP1_2 ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_0 ADC_SMPR3_SMP2_1 ADC_SMPR3_SMP2_2 ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_0 ADC_SMPR3_SMP3_1 ADC_SMPR3_SMP3_2 ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_0 ADC_SMPR3_SMP4_1 ADC_SMPR3_SMP4_2 ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_0 ADC_SMPR3_SMP5_1 ADC_SMPR3_SMP5_2 ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_0 ADC_SMPR3_SMP6_1 ADC_SMPR3_SMP6_2 ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_0 ADC_SMPR3_SMP7_1 ADC_SMPR3_SMP7_2 ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_0 ADC_SMPR3_SMP8_1 ADC_SMPR3_SMP8_2 ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_0 ADC_SMPR3_SMP9_1 ADC_SMPR3_SMP9_2 ADC_JOFR1_JOFFSET1 ADC_JOFR2_JOFFSET2 ADC_JOFR3_JOFFSET3 ADC_JOFR4_JOFFSET4 ADC_HTR_HT ADC_LTR_LT ADC_SQR1_L ADC_SQR1_L_0 ADC_SQR1_L_1 ADC_SQR1_L_2 ADC_SQR1_L_3 ADC_SQR1_SQ28 ADC_SQR1_SQ28_0 ADC_SQR1_SQ28_1 ADC_SQR1_SQ28_2 ADC_SQR1_SQ28_3 ADC_SQR1_SQ28_4 ADC_SQR1_SQ27 ADC_SQR1_SQ27_0 ADC_SQR1_SQ27_1 ADC_SQR1_SQ27_2 ADC_SQR1_SQ27_3 ADC_SQR1_SQ27_4 ADC_SQR1_SQ26 ADC_SQR1_SQ26_0 ADC_SQR1_SQ26_1 ADC_SQR1_SQ26_2 ADC_SQR1_SQ26_3 ADC_SQR1_SQ26_4 ADC_SQR1_SQ25 ADC_SQR1_SQ25_0 ADC_SQR1_SQ25_1 ADC_SQR1_SQ25_2 ADC_SQR1_SQ25_3 ADC_SQR1_SQ25_4 ADC_SQR2_SQ19 ADC_SQR2_SQ19_0 ADC_SQR2_SQ19_1 ADC_SQR2_SQ19_2 ADC_SQR2_SQ19_3 ADC_SQR2_SQ19_4 ADC_SQR2_SQ20 ADC_SQR2_SQ20_0 ADC_SQR2_SQ20_1 ADC_SQR2_SQ20_2 ADC_SQR2_SQ20_3 ADC_SQR2_SQ20_4 ADC_SQR2_SQ21 ADC_SQR2_SQ21_0 ADC_SQR2_SQ21_1 ADC_SQR2_SQ21_2 ADC_SQR2_SQ21_3 ADC_SQR2_SQ21_4 ADC_SQR2_SQ22 ADC_SQR2_SQ22_0 ADC_SQR2_SQ22_1 ADC_SQR2_SQ22_2 ADC_SQR2_SQ22_3 ADC_SQR2_SQ22_4 ADC_SQR2_SQ23 ADC_SQR2_SQ23_0 ADC_SQR2_SQ23_1 ADC_SQR2_SQ23_2 ADC_SQR2_SQ23_3 ADC_SQR2_SQ23_4 ADC_SQR2_SQ24 ADC_SQR2_SQ24_0 ADC_SQR2_SQ24_1 ADC_SQR2_SQ24_2 ADC_SQR2_SQ24_3 ADC_SQR2_SQ24_4 ADC_SQR3_SQ13 ADC_SQR3_SQ13_0 ADC_SQR3_SQ13_1 ADC_SQR3_SQ13_2 ADC_SQR3_SQ13_3 ADC_SQR3_SQ13_4 ADC_SQR3_SQ14 ADC_SQR3_SQ14_0 ADC_SQR3_SQ14_1 ADC_SQR3_SQ14_2 ADC_SQR3_SQ14_3 ADC_SQR3_SQ14_4 ADC_SQR3_SQ15 ADC_SQR3_SQ15_0 ADC_SQR3_SQ15_1 ADC_SQR3_SQ15_2 ADC_SQR3_SQ15_3 ADC_SQR3_SQ15_4 ADC_SQR3_SQ16 ADC_SQR3_SQ16_0 ADC_SQR3_SQ16_1 ADC_SQR3_SQ16_2 ADC_SQR3_SQ16_3 ADC_SQR3_SQ16_4 ADC_SQR3_SQ17 ADC_SQR3_SQ17_0 ADC_SQR3_SQ17_1 ADC_SQR3_SQ17_2 ADC_SQR3_SQ17_3 ADC_SQR3_SQ17_4 ADC_SQR3_SQ18 ADC_SQR3_SQ18_0 ADC_SQR3_SQ18_1 ADC_SQR3_SQ18_2 ADC_SQR3_SQ18_3 ADC_SQR3_SQ18_4 ADC_SQR4_SQ7 ADC_SQR4_SQ7_0 ADC_SQR4_SQ7_1 ADC_SQR4_SQ7_2 ADC_SQR4_SQ7_3 ADC_SQR4_SQ7_4 ADC_SQR4_SQ8 ADC_SQR4_SQ8_0 ADC_SQR4_SQ8_1 ADC_SQR4_SQ8_2 ADC_SQR4_SQ8_3 ADC_SQR4_SQ8_4 ADC_SQR4_SQ9 ADC_SQR4_SQ9_0 ADC_SQR4_SQ9_1 ADC_SQR4_SQ9_2 ADC_SQR4_SQ9_3 ADC_SQR4_SQ9_4 ADC_SQR4_SQ10 ADC_SQR4_SQ10_0 ADC_SQR4_SQ10_1 ADC_SQR4_SQ10_2 ADC_SQR4_SQ10_3 ADC_SQR4_SQ10_4 ADC_SQR4_SQ11 ADC_SQR4_SQ11_0 ADC_SQR4_SQ11_1 ADC_SQR4_SQ11_2 ADC_SQR4_SQ11_3 ADC_SQR4_SQ11_4 ADC_SQR4_SQ12 ADC_SQR4_SQ12_0 ADC_SQR4_SQ12_1 ADC_SQR4_SQ12_2 ADC_SQR4_SQ12_3 ADC_SQR4_SQ12_4 ADC_SQR5_SQ1 ADC_SQR5_SQ1_0 ADC_SQR5_SQ1_1 ADC_SQR5_SQ1_2 ADC_SQR5_SQ1_3 ADC_SQR5_SQ1_4 ADC_SQR5_SQ2 ADC_SQR5_SQ2_0 ADC_SQR5_SQ2_1 ADC_SQR5_SQ2_2 ADC_SQR5_SQ2_3 ADC_SQR5_SQ2_4 ADC_SQR5_SQ3 ADC_SQR5_SQ3_0 ADC_SQR5_SQ3_1 ADC_SQR5_SQ3_2 ADC_SQR5_SQ3_3 ADC_SQR5_SQ3_4 ADC_SQR5_SQ4 ADC_SQR5_SQ4_0 ADC_SQR5_SQ4_1 ADC_SQR5_SQ4_2 ADC_SQR5_SQ4_3 ADC_SQR5_SQ4_4 ADC_SQR5_SQ5 ADC_SQR5_SQ5_0 ADC_SQR5_SQ5_1 ADC_SQR5_SQ5_2 ADC_SQR5_SQ5_3 ADC_SQR5_SQ5_4 ADC_SQR5_SQ6 ADC_SQR5_SQ6_0 ADC_SQR5_SQ6_1 ADC_SQR5_SQ6_2 ADC_SQR5_SQ6_3 ADC_SQR5_SQ6_4 ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_0 ADC_JSQR_JSQ1_1 ADC_JSQR_JSQ1_2 ADC_JSQR_JSQ1_3 ADC_JSQR_JSQ1_4 ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_0 ADC_JSQR_JSQ2_1 ADC_JSQR_JSQ2_2 ADC_JSQR_JSQ2_3 ADC_JSQR_JSQ2_4 ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_0 ADC_JSQR_JSQ3_1 ADC_JSQR_JSQ3_2 ADC_JSQR_JSQ3_3 ADC_JSQR_JSQ3_4 ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_0 ADC_JSQR_JSQ4_1 ADC_JSQR_JSQ4_2 ADC_JSQR_JSQ4_3 ADC_JSQR_JSQ4_4 ADC_JSQR_JL ADC_JSQR_JL_0 ADC_JSQR_JL_1 ADC_JDR1_JDATA ADC_JDR2_JDATA ADC_JDR3_JDATA ADC_JDR4_JDATA ADC_DR_DATA ADC_SMPR3_SMP30 ADC_SMPR3_SMP30_0 ADC_SMPR3_SMP30_1 ADC_SMPR3_SMP30_2 ADC_SMPR3_SMP31 ADC_SMPR3_SMP31_0 ADC_SMPR3_SMP31_1 ADC_SMPR3_SMP31_2 ADC_CSR_AWD1 ADC_CSR_EOC1 ADC_CSR_JEOC1 ADC_CSR_JSTRT1 ADC_CSR_STRT1 ADC_CSR_OVR1 ADC_CSR_ADONS1 ADC_CCR_ADCPRE ADC_CCR_ADCPRE_0 ADC_CCR_ADCPRE_1 ADC_CCR_TSVREFE AES_CR_EN AES_CR_DATATYPE AES_CR_DATATYPE_0 AES_CR_DATATYPE_1 AES_CR_MODE AES_CR_MODE_0 AES_CR_MODE_1 AES_CR_CHMOD AES_CR_CHMOD_0 AES_CR_CHMOD_1 AES_CR_CCFC AES_CR_ERRC AES_CR_CCIE AES_CR_ERRIE AES_CR_DMAINEN AES_CR_DMAOUTEN AES_SR_CCF AES_SR_RDERR AES_SR_WRERR AES_DINR AES_DOUTR AES_KEYR0 AES_KEYR1 AES_KEYR2 AES_KEYR3 AES_IVR0 AES_IVR1 AES_IVR2 AES_IVR3 COMP_CSR_10KPU COMP_CSR_400KPU COMP_CSR_10KPD COMP_CSR_400KPD COMP_CSR_CMP1EN COMP_CSR_SW1 COMP_CSR_CMP1OUT COMP_CSR_SPEED COMP_CSR_CMP2OUT COMP_CSR_VREFOUTEN COMP_CSR_WNDWE COMP_CSR_INSEL COMP_CSR_INSEL_0 COMP_CSR_INSEL_1 COMP_CSR_INSEL_2 COMP_CSR_OUTSEL COMP_CSR_OUTSEL_0 COMP_CSR_OUTSEL_1 COMP_CSR_OUTSEL_2 COMP_CSR_FCH3 COMP_CSR_FCH8 COMP_CSR_RCH13 COMP_CSR_CAIE COMP_CSR_CAIF COMP_CSR_TSUSP OPAMP_CSR_OPA1PD OPAMP_CSR_S3SEL1 OPAMP_CSR_S4SEL1 OPAMP_CSR_S5SEL1 OPAMP_CSR_S6SEL1 OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA2PD OPAMP_CSR_S3SEL2 OPAMP_CSR_S4SEL2 OPAMP_CSR_S5SEL2 OPAMP_CSR_S6SEL2 OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA3PD OPAMP_CSR_S3SEL3 OPAMP_CSR_S4SEL3 OPAMP_CSR_S5SEL3 OPAMP_CSR_S6SEL3 OPAMP_CSR_OPA3CAL_L OPAMP_CSR_OPA3CAL_H OPAMP_CSR_OPA3LPM OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL3 OPAMP_CSR_S7SEL2 OPAMP_CSR_AOP_RANGE OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA3CALOUT OPAMP_OTR_AO1_OPT_OFFSET_TRIM OPAMP_OTR_AO2_OPT_OFFSET_TRIM OPAMP_OTR_AO3_OPT_OFFSET_TRIM OPAMP_OTR_OT_USER OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP CRC_DR_DR CRC_IDR_IDR CRC_CR_RESET DAC_CR_EN1 DAC_CR_BOFF1 DAC_CR_TEN1 DAC_CR_TSEL1 DAC_CR_TSEL1_0 DAC_CR_TSEL1_1 DAC_CR_TSEL1_2 DAC_CR_WAVE1 DAC_CR_WAVE1_0 DAC_CR_WAVE1_1 DAC_CR_MAMP1 DAC_CR_MAMP1_0 DAC_CR_MAMP1_1 DAC_CR_MAMP1_2 DAC_CR_MAMP1_3 DAC_CR_DMAEN1 DAC_CR_DMAUDRIE1 DAC_CR_EN2 DAC_CR_BOFF2 DAC_CR_TEN2 DAC_CR_TSEL2 DAC_CR_TSEL2_0 DAC_CR_TSEL2_1 DAC_CR_TSEL2_2 DAC_CR_WAVE2 DAC_CR_WAVE2_0 DAC_CR_WAVE2_1 DAC_CR_MAMP2 DAC_CR_MAMP2_0 DAC_CR_MAMP2_1 DAC_CR_MAMP2_2 DAC_CR_MAMP2_3 DAC_CR_DMAEN2 DAC_CR_DMAUDRIE2 DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG2 DAC_DHR12R1_DACC1DHR DAC_DHR12L1_DACC1DHR DAC_DHR8R1_DACC1DHR DAC_DHR12R2_DACC2DHR DAC_DHR12L2_DACC2DHR DAC_DHR8R2_DACC2DHR DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC2DHR DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC2DHR DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC2DHR DAC_DOR1_DACC1DOR DAC_DOR2_DACC2DOR DAC_SR_DMAUDR1 DAC_SR_DMAUDR2 DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_0 DBGMCU_IDCODE_REV_ID_1 DBGMCU_IDCODE_REV_ID_2 DBGMCU_IDCODE_REV_ID_3 DBGMCU_IDCODE_REV_ID_4 DBGMCU_IDCODE_REV_ID_5 DBGMCU_IDCODE_REV_ID_6 DBGMCU_IDCODE_REV_ID_7 DBGMCU_IDCODE_REV_ID_8 DBGMCU_IDCODE_REV_ID_9 DBGMCU_IDCODE_REV_ID_10 DBGMCU_IDCODE_REV_ID_11 DBGMCU_IDCODE_REV_ID_12 DBGMCU_IDCODE_REV_ID_13 DBGMCU_IDCODE_REV_ID_14 DBGMCU_IDCODE_REV_ID_15 DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STANDBY DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_0 DBGMCU_CR_TRACE_MODE_1 DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP DMA_ISR_GIF1 DMA_ISR_TCIF1 DMA_ISR_HTIF1 DMA_ISR_TEIF1 DMA_ISR_GIF2 DMA_ISR_TCIF2 DMA_ISR_HTIF2 DMA_ISR_TEIF2 DMA_ISR_GIF3 DMA_ISR_TCIF3 DMA_ISR_HTIF3 DMA_ISR_TEIF3 DMA_ISR_GIF4 DMA_ISR_TCIF4 DMA_ISR_HTIF4 DMA_ISR_TEIF4 DMA_ISR_GIF5 DMA_ISR_TCIF5 DMA_ISR_HTIF5 DMA_ISR_TEIF5 DMA_ISR_GIF6 DMA_ISR_TCIF6 DMA_ISR_HTIF6 DMA_ISR_TEIF6 DMA_ISR_GIF7 DMA_ISR_TCIF7 DMA_ISR_HTIF7 DMA_ISR_TEIF7 DMA_IFCR_CGIF1 DMA_IFCR_CTCIF1 DMA_IFCR_CHTIF1 DMA_IFCR_CTEIF1 DMA_IFCR_CGIF2 DMA_IFCR_CTCIF2 DMA_IFCR_CHTIF2 DMA_IFCR_CTEIF2 DMA_IFCR_CGIF3 DMA_IFCR_CTCIF3 DMA_IFCR_CHTIF3 DMA_IFCR_CTEIF3 DMA_IFCR_CGIF4 DMA_IFCR_CTCIF4 DMA_IFCR_CHTIF4 DMA_IFCR_CTEIF4 DMA_IFCR_CGIF5 DMA_IFCR_CTCIF5 DMA_IFCR_CHTIF5 DMA_IFCR_CTEIF5 DMA_IFCR_CGIF6 DMA_IFCR_CTCIF6 DMA_IFCR_CHTIF6 DMA_IFCR_CTEIF6 DMA_IFCR_CGIF7 DMA_IFCR_CTCIF7 DMA_IFCR_CHTIF7 DMA_IFCR_CTEIF7 DMA_CCR1_EN DMA_CCR1_TCIE DMA_CCR1_HTIE DMA_CCR1_TEIE DMA_CCR1_DIR DMA_CCR1_CIRC DMA_CCR1_PINC DMA_CCR1_MINC DMA_CCR1_PSIZE DMA_CCR1_PSIZE_0 DMA_CCR1_PSIZE_1 DMA_CCR1_MSIZE DMA_CCR1_MSIZE_0 DMA_CCR1_MSIZE_1 DMA_CCR1_PL DMA_CCR1_PL_0 DMA_CCR1_PL_1 DMA_CCR1_MEM2MEM DMA_CCR2_EN DMA_CCR2_TCIE DMA_CCR2_HTIE DMA_CCR2_TEIE DMA_CCR2_DIR DMA_CCR2_CIRC DMA_CCR2_PINC DMA_CCR2_MINC DMA_CCR2_PSIZE DMA_CCR2_PSIZE_0 DMA_CCR2_PSIZE_1 DMA_CCR2_MSIZE DMA_CCR2_MSIZE_0 DMA_CCR2_MSIZE_1 DMA_CCR2_PL DMA_CCR2_PL_0 DMA_CCR2_PL_1 DMA_CCR2_MEM2MEM DMA_CCR3_EN DMA_CCR3_TCIE DMA_CCR3_HTIE DMA_CCR3_TEIE DMA_CCR3_DIR DMA_CCR3_CIRC DMA_CCR3_PINC DMA_CCR3_MINC DMA_CCR3_PSIZE DMA_CCR3_PSIZE_0 DMA_CCR3_PSIZE_1 DMA_CCR3_MSIZE DMA_CCR3_MSIZE_0 DMA_CCR3_MSIZE_1 DMA_CCR3_PL DMA_CCR3_PL_0 DMA_CCR3_PL_1 DMA_CCR3_MEM2MEM DMA_CCR4_EN DMA_CCR4_TCIE DMA_CCR4_HTIE DMA_CCR4_TEIE DMA_CCR4_DIR DMA_CCR4_CIRC DMA_CCR4_PINC DMA_CCR4_MINC DMA_CCR4_PSIZE DMA_CCR4_PSIZE_0 DMA_CCR4_PSIZE_1 DMA_CCR4_MSIZE DMA_CCR4_MSIZE_0 DMA_CCR4_MSIZE_1 DMA_CCR4_PL DMA_CCR4_PL_0 DMA_CCR4_PL_1 DMA_CCR4_MEM2MEM DMA_CCR5_EN DMA_CCR5_TCIE DMA_CCR5_HTIE DMA_CCR5_TEIE DMA_CCR5_DIR DMA_CCR5_CIRC DMA_CCR5_PINC DMA_CCR5_MINC DMA_CCR5_PSIZE DMA_CCR5_PSIZE_0 DMA_CCR5_PSIZE_1 DMA_CCR5_MSIZE DMA_CCR5_MSIZE_0 DMA_CCR5_MSIZE_1 DMA_CCR5_PL DMA_CCR5_PL_0 DMA_CCR5_PL_1 DMA_CCR5_MEM2MEM DMA_CCR6_EN DMA_CCR6_TCIE DMA_CCR6_HTIE DMA_CCR6_TEIE DMA_CCR6_DIR DMA_CCR6_CIRC DMA_CCR6_PINC DMA_CCR6_MINC DMA_CCR6_PSIZE DMA_CCR6_PSIZE_0 DMA_CCR6_PSIZE_1 DMA_CCR6_MSIZE DMA_CCR6_MSIZE_0 DMA_CCR6_MSIZE_1 DMA_CCR6_PL DMA_CCR6_PL_0 DMA_CCR6_PL_1 DMA_CCR6_MEM2MEM DMA_CCR7_EN DMA_CCR7_TCIE DMA_CCR7_HTIE DMA_CCR7_TEIE DMA_CCR7_DIR DMA_CCR7_CIRC DMA_CCR7_PINC DMA_CCR7_MINC DMA_CCR7_PSIZE DMA_CCR7_PSIZE_0 DMA_CCR7_PSIZE_1 DMA_CCR7_MSIZE DMA_CCR7_MSIZE_0 DMA_CCR7_MSIZE_1 DMA_CCR7_PL DMA_CCR7_PL_0 DMA_CCR7_PL_1 DMA_CCR7_MEM2MEM DMA_CNDTR1_NDT DMA_CNDTR2_NDT DMA_CNDTR3_NDT DMA_CNDTR4_NDT DMA_CNDTR5_NDT DMA_CNDTR6_NDT DMA_CNDTR7_NDT DMA_CPAR1_PA DMA_CPAR2_PA DMA_CPAR3_PA DMA_CPAR4_PA DMA_CPAR5_PA DMA_CPAR6_PA DMA_CPAR7_PA DMA_CMAR1_MA DMA_CMAR2_MA DMA_CMAR3_MA DMA_CMAR4_MA DMA_CMAR5_MA DMA_CMAR6_MA DMA_CMAR7_MA EXTI_IMR_MR0 EXTI_IMR_MR1 EXTI_IMR_MR2 EXTI_IMR_MR3 EXTI_IMR_MR4 EXTI_IMR_MR5 EXTI_IMR_MR6 EXTI_IMR_MR7 EXTI_IMR_MR8 EXTI_IMR_MR9 EXTI_IMR_MR10 EXTI_IMR_MR11 EXTI_IMR_MR12 EXTI_IMR_MR13 EXTI_IMR_MR14 EXTI_IMR_MR15 EXTI_IMR_MR16 EXTI_IMR_MR17 EXTI_IMR_MR18 EXTI_IMR_MR19 EXTI_IMR_MR20 EXTI_IMR_MR21 EXTI_IMR_MR22 EXTI_IMR_MR23 EXTI_EMR_MR0 EXTI_EMR_MR1 EXTI_EMR_MR2 EXTI_EMR_MR3 EXTI_EMR_MR4 EXTI_EMR_MR5 EXTI_EMR_MR6 EXTI_EMR_MR7 EXTI_EMR_MR8 EXTI_EMR_MR9 EXTI_EMR_MR10 EXTI_EMR_MR11 EXTI_EMR_MR12 EXTI_EMR_MR13 EXTI_EMR_MR14 EXTI_EMR_MR15 EXTI_EMR_MR16 EXTI_EMR_MR17 EXTI_EMR_MR18 EXTI_EMR_MR19 EXTI_EMR_MR20 EXTI_EMR_MR21 EXTI_EMR_MR22 EXTI_EMR_MR23 EXTI_RTSR_TR0 EXTI_RTSR_TR1 EXTI_RTSR_TR2 EXTI_RTSR_TR3 EXTI_RTSR_TR4 EXTI_RTSR_TR5 EXTI_RTSR_TR6 EXTI_RTSR_TR7 EXTI_RTSR_TR8 EXTI_RTSR_TR9 EXTI_RTSR_TR10 EXTI_RTSR_TR11 EXTI_RTSR_TR12 EXTI_RTSR_TR13 EXTI_RTSR_TR14 EXTI_RTSR_TR15 EXTI_RTSR_TR16 EXTI_RTSR_TR17 EXTI_RTSR_TR18 EXTI_RTSR_TR19 EXTI_RTSR_TR20 EXTI_RTSR_TR21 EXTI_RTSR_TR22 EXTI_RTSR_TR23 EXTI_FTSR_TR0 EXTI_FTSR_TR1 EXTI_FTSR_TR2 EXTI_FTSR_TR3 EXTI_FTSR_TR4 EXTI_FTSR_TR5 EXTI_FTSR_TR6 EXTI_FTSR_TR7 EXTI_FTSR_TR8 EXTI_FTSR_TR9 EXTI_FTSR_TR10 EXTI_FTSR_TR11 EXTI_FTSR_TR12 EXTI_FTSR_TR13 EXTI_FTSR_TR14 EXTI_FTSR_TR15 EXTI_FTSR_TR16 EXTI_FTSR_TR17 EXTI_FTSR_TR18 EXTI_FTSR_TR19 EXTI_FTSR_TR20 EXTI_FTSR_TR21 EXTI_FTSR_TR22 EXTI_FTSR_TR23 EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER23 EXTI_PR_PR0 EXTI_PR_PR1 EXTI_PR_PR2 EXTI_PR_PR3 EXTI_PR_PR4 EXTI_PR_PR5 EXTI_PR_PR6 EXTI_PR_PR7 EXTI_PR_PR8 EXTI_PR_PR9 EXTI_PR_PR10 EXTI_PR_PR11 EXTI_PR_PR12 EXTI_PR_PR13 EXTI_PR_PR14 EXTI_PR_PR15 EXTI_PR_PR16 EXTI_PR_PR17 EXTI_PR_PR18 EXTI_PR_PR19 EXTI_PR_PR20 EXTI_PR_PR21 EXTI_PR_PR22 EXTI_PR_PR23 FLASH_ACR_LATENCY FLASH_ACR_PRFTEN FLASH_ACR_ACC64 FLASH_ACR_SLEEP_PD FLASH_ACR_RUN_PD FLASH_PECR_PELOCK FLASH_PECR_PRGLOCK FLASH_PECR_OPTLOCK FLASH_PECR_PROG FLASH_PECR_DATA FLASH_PECR_FTDW FLASH_PECR_ERASE FLASH_PECR_FPRG FLASH_PECR_PARALLBANK FLASH_PECR_EOPIE FLASH_PECR_ERRIE FLASH_PECR_OBL_LAUNCH FLASH_PDKEYR_PDKEYR FLASH_PEKEYR_PEKEYR FLASH_PRGKEYR_PRGKEYR FLASH_OPTKEYR_OPTKEYR FLASH_SR_BSY FLASH_SR_EOP FLASH_SR_ENHV FLASH_SR_READY FLASH_SR_WRPERR FLASH_SR_PGAERR FLASH_SR_SIZERR FLASH_SR_OPTVERR FLASH_SR_OPTVERRUSR FLASH_OBR_RDPRT FLASH_OBR_BOR_LEV FLASH_OBR_USER FLASH_OBR_IWDG_SW FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_BFB2 FLASH_WRPR_WRP FLASH_WRPR1_WRP FLASH_WRPR2_WRP FSMC_BCR1_MBKEN FSMC_BCR1_MUXEN FSMC_BCR1_MTYP FSMC_BCR1_MTYP_0 FSMC_BCR1_MTYP_1 FSMC_BCR1_MWID FSMC_BCR1_MWID_0 FSMC_BCR1_MWID_1 FSMC_BCR1_FACCEN FSMC_BCR1_BURSTEN FSMC_BCR1_WAITPOL FSMC_BCR1_WRAPMOD FSMC_BCR1_WAITCFG FSMC_BCR1_WREN FSMC_BCR1_WAITEN FSMC_BCR1_EXTMOD FSMC_BCR1_ASYNCWAIT FSMC_BCR1_CBURSTRW FSMC_BCR2_MBKEN FSMC_BCR2_MUXEN FSMC_BCR2_MTYP FSMC_BCR2_MTYP_0 FSMC_BCR2_MTYP_1 FSMC_BCR2_MWID FSMC_BCR2_MWID_0 FSMC_BCR2_MWID_1 FSMC_BCR2_FACCEN FSMC_BCR2_BURSTEN FSMC_BCR2_WAITPOL FSMC_BCR2_WRAPMOD FSMC_BCR2_WAITCFG FSMC_BCR2_WREN FSMC_BCR2_WAITEN FSMC_BCR2_EXTMOD FSMC_BCR2_ASYNCWAIT FSMC_BCR2_CBURSTRW FSMC_BCR3_MBKEN FSMC_BCR3_MUXEN FSMC_BCR3_MTYP FSMC_BCR3_MTYP_0 FSMC_BCR3_MTYP_1 FSMC_BCR3_MWID FSMC_BCR3_MWID_0 FSMC_BCR3_MWID_1 FSMC_BCR3_FACCEN FSMC_BCR3_BURSTEN FSMC_BCR3_WAITPOL FSMC_BCR3_WRAPMOD FSMC_BCR3_WAITCFG FSMC_BCR3_WREN FSMC_BCR3_WAITEN FSMC_BCR3_EXTMOD FSMC_BCR3_ASYNCWAIT FSMC_BCR3_CBURSTRW FSMC_BCR4_MBKEN FSMC_BCR4_MUXEN FSMC_BCR4_MTYP FSMC_BCR4_MTYP_0 FSMC_BCR4_MTYP_1 FSMC_BCR4_MWID FSMC_BCR4_MWID_0 FSMC_BCR4_MWID_1 FSMC_BCR4_FACCEN FSMC_BCR4_BURSTEN FSMC_BCR4_WAITPOL FSMC_BCR4_WRAPMOD FSMC_BCR4_WAITCFG FSMC_BCR4_WREN FSMC_BCR4_WAITEN FSMC_BCR4_EXTMOD FSMC_BCR4_ASYNCWAIT FSMC_BCR4_CBURSTRW FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_0 FSMC_BTR1_ADDSET_1 FSMC_BTR1_ADDSET_2 FSMC_BTR1_ADDSET_3 FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_0 FSMC_BTR1_ADDHLD_1 FSMC_BTR1_ADDHLD_2 FSMC_BTR1_ADDHLD_3 FSMC_BTR1_DATAST FSMC_BTR1_DATAST_0 FSMC_BTR1_DATAST_1 FSMC_BTR1_DATAST_2 FSMC_BTR1_DATAST_3 FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_0 FSMC_BTR1_BUSTURN_1 FSMC_BTR1_BUSTURN_2 FSMC_BTR1_BUSTURN_3 FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_0 FSMC_BTR1_CLKDIV_1 FSMC_BTR1_CLKDIV_2 FSMC_BTR1_CLKDIV_3 FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_0 FSMC_BTR1_DATLAT_1 FSMC_BTR1_DATLAT_2 FSMC_BTR1_DATLAT_3 FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_0 FSMC_BTR1_ACCMOD_1 FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_0 FSMC_BTR2_ADDSET_1 FSMC_BTR2_ADDSET_2 FSMC_BTR2_ADDSET_3 FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_0 FSMC_BTR2_ADDHLD_1 FSMC_BTR2_ADDHLD_2 FSMC_BTR2_ADDHLD_3 FSMC_BTR2_DATAST FSMC_BTR2_DATAST_0 FSMC_BTR2_DATAST_1 FSMC_BTR2_DATAST_2 FSMC_BTR2_DATAST_3 FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_0 FSMC_BTR2_BUSTURN_1 FSMC_BTR2_BUSTURN_2 FSMC_BTR2_BUSTURN_3 FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_0 FSMC_BTR2_CLKDIV_1 FSMC_BTR2_CLKDIV_2 FSMC_BTR2_CLKDIV_3 FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_0 FSMC_BTR2_DATLAT_1 FSMC_BTR2_DATLAT_2 FSMC_BTR2_DATLAT_3 FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_0 FSMC_BTR2_ACCMOD_1 FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_0 FSMC_BTR3_ADDSET_1 FSMC_BTR3_ADDSET_2 FSMC_BTR3_ADDSET_3 FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_0 FSMC_BTR3_ADDHLD_1 FSMC_BTR3_ADDHLD_2 FSMC_BTR3_ADDHLD_3 FSMC_BTR3_DATAST FSMC_BTR3_DATAST_0 FSMC_BTR3_DATAST_1 FSMC_BTR3_DATAST_2 FSMC_BTR3_DATAST_3 FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_0 FSMC_BTR3_BUSTURN_1 FSMC_BTR3_BUSTURN_2 FSMC_BTR3_BUSTURN_3 FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_0 FSMC_BTR3_CLKDIV_1 FSMC_BTR3_CLKDIV_2 FSMC_BTR3_CLKDIV_3 FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_0 FSMC_BTR3_DATLAT_1 FSMC_BTR3_DATLAT_2 FSMC_BTR3_DATLAT_3 FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_0 FSMC_BTR3_ACCMOD_1 FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_0 FSMC_BTR4_ADDSET_1 FSMC_BTR4_ADDSET_2 FSMC_BTR4_ADDSET_3 FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_0 FSMC_BTR4_ADDHLD_1 FSMC_BTR4_ADDHLD_2 FSMC_BTR4_ADDHLD_3 FSMC_BTR4_DATAST FSMC_BTR4_DATAST_0 FSMC_BTR4_DATAST_1 FSMC_BTR4_DATAST_2 FSMC_BTR4_DATAST_3 FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_0 FSMC_BTR4_BUSTURN_1 FSMC_BTR4_BUSTURN_2 FSMC_BTR4_BUSTURN_3 FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_0 FSMC_BTR4_CLKDIV_1 FSMC_BTR4_CLKDIV_2 FSMC_BTR4_CLKDIV_3 FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_0 FSMC_BTR4_DATLAT_1 FSMC_BTR4_DATLAT_2 FSMC_BTR4_DATLAT_3 FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_0 FSMC_BTR4_ACCMOD_1 FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_0 FSMC_BWTR1_ADDSET_1 FSMC_BWTR1_ADDSET_2 FSMC_BWTR1_ADDSET_3 FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_0 FSMC_BWTR1_ADDHLD_1 FSMC_BWTR1_ADDHLD_2 FSMC_BWTR1_ADDHLD_3 FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_0 FSMC_BWTR1_DATAST_1 FSMC_BWTR1_DATAST_2 FSMC_BWTR1_DATAST_3 FSMC_BWTR1_CLKDIV FSMC_BWTR1_CLKDIV_0 FSMC_BWTR1_CLKDIV_1 FSMC_BWTR1_CLKDIV_2 FSMC_BWTR1_CLKDIV_3 FSMC_BWTR1_DATLAT FSMC_BWTR1_DATLAT_0 FSMC_BWTR1_DATLAT_1 FSMC_BWTR1_DATLAT_2 FSMC_BWTR1_DATLAT_3 FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_0 FSMC_BWTR1_ACCMOD_1 FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_0 FSMC_BWTR2_ADDSET_1 FSMC_BWTR2_ADDSET_2 FSMC_BWTR2_ADDSET_3 FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_0 FSMC_BWTR2_ADDHLD_1 FSMC_BWTR2_ADDHLD_2 FSMC_BWTR2_ADDHLD_3 FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_0 FSMC_BWTR2_DATAST_1 FSMC_BWTR2_DATAST_2 FSMC_BWTR2_DATAST_3 FSMC_BWTR2_CLKDIV FSMC_BWTR2_CLKDIV_0 FSMC_BWTR2_CLKDIV_1 FSMC_BWTR2_CLKDIV_2 FSMC_BWTR2_CLKDIV_3 FSMC_BWTR2_DATLAT FSMC_BWTR2_DATLAT_0 FSMC_BWTR2_DATLAT_1 FSMC_BWTR2_DATLAT_2 FSMC_BWTR2_DATLAT_3 FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_0 FSMC_BWTR2_ACCMOD_1 FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_0 FSMC_BWTR3_ADDSET_1 FSMC_BWTR3_ADDSET_2 FSMC_BWTR3_ADDSET_3 FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_0 FSMC_BWTR3_ADDHLD_1 FSMC_BWTR3_ADDHLD_2 FSMC_BWTR3_ADDHLD_3 FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_0 FSMC_BWTR3_DATAST_1 FSMC_BWTR3_DATAST_2 FSMC_BWTR3_DATAST_3 FSMC_BWTR3_CLKDIV FSMC_BWTR3_CLKDIV_0 FSMC_BWTR3_CLKDIV_1 FSMC_BWTR3_CLKDIV_2 FSMC_BWTR3_CLKDIV_3 FSMC_BWTR3_DATLAT FSMC_BWTR3_DATLAT_0 FSMC_BWTR3_DATLAT_1 FSMC_BWTR3_DATLAT_2 FSMC_BWTR3_DATLAT_3 FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_0 FSMC_BWTR3_ACCMOD_1 FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_0 FSMC_BWTR4_ADDSET_1 FSMC_BWTR4_ADDSET_2 FSMC_BWTR4_ADDSET_3 FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_0 FSMC_BWTR4_ADDHLD_1 FSMC_BWTR4_ADDHLD_2 FSMC_BWTR4_ADDHLD_3 FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_0 FSMC_BWTR4_DATAST_1 FSMC_BWTR4_DATAST_2 FSMC_BWTR4_DATAST_3 FSMC_BWTR4_CLKDIV FSMC_BWTR4_CLKDIV_0 FSMC_BWTR4_CLKDIV_1 FSMC_BWTR4_CLKDIV_2 FSMC_BWTR4_CLKDIV_3 FSMC_BWTR4_DATLAT FSMC_BWTR4_DATLAT_0 FSMC_BWTR4_DATLAT_1 FSMC_BWTR4_DATLAT_2 FSMC_BWTR4_DATLAT_3 FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_0 FSMC_BWTR4_ACCMOD_1 GPIO_MODER_MODER0 GPIO_MODER_MODER0_0 GPIO_MODER_MODER0_1 GPIO_MODER_MODER1 GPIO_MODER_MODER1_0 GPIO_MODER_MODER1_1 GPIO_MODER_MODER2 GPIO_MODER_MODER2_0 GPIO_MODER_MODER2_1 GPIO_MODER_MODER3 GPIO_MODER_MODER3_0 GPIO_MODER_MODER3_1 GPIO_MODER_MODER4 GPIO_MODER_MODER4_0 GPIO_MODER_MODER4_1 GPIO_MODER_MODER5 GPIO_MODER_MODER5_0 GPIO_MODER_MODER5_1 GPIO_MODER_MODER6 GPIO_MODER_MODER6_0 GPIO_MODER_MODER6_1 GPIO_MODER_MODER7 GPIO_MODER_MODER7_0 GPIO_MODER_MODER7_1 GPIO_MODER_MODER8 GPIO_MODER_MODER8_0 GPIO_MODER_MODER8_1 GPIO_MODER_MODER9 GPIO_MODER_MODER9_0 GPIO_MODER_MODER9_1 GPIO_MODER_MODER10 GPIO_MODER_MODER10_0 GPIO_MODER_MODER10_1 GPIO_MODER_MODER11 GPIO_MODER_MODER11_0 GPIO_MODER_MODER11_1 GPIO_MODER_MODER12 GPIO_MODER_MODER12_0 GPIO_MODER_MODER12_1 GPIO_MODER_MODER13 GPIO_MODER_MODER13_0 GPIO_MODER_MODER13_1 GPIO_MODER_MODER14 GPIO_MODER_MODER14_0 GPIO_MODER_MODER14_1 GPIO_MODER_MODER15 GPIO_MODER_MODER15_0 GPIO_MODER_MODER15_1 GPIO_OTYPER_OT_0 GPIO_OTYPER_OT_1 GPIO_OTYPER_OT_2 GPIO_OTYPER_OT_3 GPIO_OTYPER_OT_4 GPIO_OTYPER_OT_5 GPIO_OTYPER_OT_6 GPIO_OTYPER_OT_7 GPIO_OTYPER_OT_8 GPIO_OTYPER_OT_9 GPIO_OTYPER_OT_10 GPIO_OTYPER_OT_11 GPIO_OTYPER_OT_12 GPIO_OTYPER_OT_13 GPIO_OTYPER_OT_14 GPIO_OTYPER_OT_15 GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDER_OSPEEDR15_1 GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPDR15_1 GPIO_IDR_IDR_0 GPIO_IDR_IDR_1 GPIO_IDR_IDR_2 GPIO_IDR_IDR_3 GPIO_IDR_IDR_4 GPIO_IDR_IDR_5 GPIO_IDR_IDR_6 GPIO_IDR_IDR_7 GPIO_IDR_IDR_8 GPIO_IDR_IDR_9 GPIO_IDR_IDR_10 GPIO_IDR_IDR_11 GPIO_IDR_IDR_12 GPIO_IDR_IDR_13 GPIO_IDR_IDR_14 GPIO_IDR_IDR_15 GPIO_OTYPER_IDR_0 GPIO_OTYPER_IDR_1 GPIO_OTYPER_IDR_2 GPIO_OTYPER_IDR_3 GPIO_OTYPER_IDR_4 GPIO_OTYPER_IDR_5 GPIO_OTYPER_IDR_6 GPIO_OTYPER_IDR_7 GPIO_OTYPER_IDR_8 GPIO_OTYPER_IDR_9 GPIO_OTYPER_IDR_10 GPIO_OTYPER_IDR_11 GPIO_OTYPER_IDR_12 GPIO_OTYPER_IDR_13 GPIO_OTYPER_IDR_14 GPIO_OTYPER_IDR_15 GPIO_ODR_ODR_0 GPIO_ODR_ODR_1 GPIO_ODR_ODR_2 GPIO_ODR_ODR_3 GPIO_ODR_ODR_4 GPIO_ODR_ODR_5 GPIO_ODR_ODR_6 GPIO_ODR_ODR_7 GPIO_ODR_ODR_8 GPIO_ODR_ODR_9 GPIO_ODR_ODR_10 GPIO_ODR_ODR_11 GPIO_ODR_ODR_12 GPIO_ODR_ODR_13 GPIO_ODR_ODR_14 GPIO_ODR_ODR_15 GPIO_OTYPER_ODR_0 GPIO_OTYPER_ODR_1 GPIO_OTYPER_ODR_2 GPIO_OTYPER_ODR_3 GPIO_OTYPER_ODR_4 GPIO_OTYPER_ODR_5 GPIO_OTYPER_ODR_6 GPIO_OTYPER_ODR_7 GPIO_OTYPER_ODR_8 GPIO_OTYPER_ODR_9 GPIO_OTYPER_ODR_10 GPIO_OTYPER_ODR_11 GPIO_OTYPER_ODR_12 GPIO_OTYPER_ODR_13 GPIO_OTYPER_ODR_14 GPIO_OTYPER_ODR_15 GPIO_BSRR_BS_0 GPIO_BSRR_BS_1 GPIO_BSRR_BS_2 GPIO_BSRR_BS_3 GPIO_BSRR_BS_4 GPIO_BSRR_BS_5 GPIO_BSRR_BS_6 GPIO_BSRR_BS_7 GPIO_BSRR_BS_8 GPIO_BSRR_BS_9 GPIO_BSRR_BS_10 GPIO_BSRR_BS_11 GPIO_BSRR_BS_12 GPIO_BSRR_BS_13 GPIO_BSRR_BS_14 GPIO_BSRR_BS_15 GPIO_BSRR_BR_0 GPIO_BSRR_BR_1 GPIO_BSRR_BR_2 GPIO_BSRR_BR_3 GPIO_BSRR_BR_4 GPIO_BSRR_BR_5 GPIO_BSRR_BR_6 GPIO_BSRR_BR_7 GPIO_BSRR_BR_8 GPIO_BSRR_BR_9 GPIO_BSRR_BR_10 GPIO_BSRR_BR_11 GPIO_BSRR_BR_12 GPIO_BSRR_BR_13 GPIO_BSRR_BR_14 GPIO_BSRR_BR_15 GPIO_LCKR_LCK0 GPIO_LCKR_LCK1 GPIO_LCKR_LCK2 GPIO_LCKR_LCK3 GPIO_LCKR_LCK4 GPIO_LCKR_LCK5 GPIO_LCKR_LCK6 GPIO_LCKR_LCK7 GPIO_LCKR_LCK8 GPIO_LCKR_LCK9 GPIO_LCKR_LCK10 GPIO_LCKR_LCK11 GPIO_LCKR_LCK12 GPIO_LCKR_LCK13 GPIO_LCKR_LCK14 GPIO_LCKR_LCK15 GPIO_LCKR_LCKK GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL7 GPIO_AFRH_AFRH8 GPIO_AFRH_AFRH9 GPIO_AFRH_AFRH10 GPIO_AFRH_AFRH11 GPIO_AFRH_AFRH12 GPIO_AFRH_AFRH13 GPIO_AFRH_AFRH14 GPIO_AFRH_AFRH15 I2C_CR1_PE I2C_CR1_SMBUS I2C_CR1_SMBTYPE I2C_CR1_ENARP I2C_CR1_ENPEC I2C_CR1_ENGC I2C_CR1_NOSTRETCH I2C_CR1_START I2C_CR1_STOP I2C_CR1_ACK I2C_CR1_POS I2C_CR1_PEC I2C_CR1_ALERT I2C_CR1_SWRST I2C_CR2_FREQ I2C_CR2_FREQ_0 I2C_CR2_FREQ_1 I2C_CR2_FREQ_2 I2C_CR2_FREQ_3 I2C_CR2_FREQ_4 I2C_CR2_FREQ_5 I2C_CR2_ITERREN I2C_CR2_ITEVTEN I2C_CR2_ITBUFEN I2C_CR2_DMAEN I2C_CR2_LAST I2C_OAR1_ADD1_7 I2C_OAR1_ADD8_9 I2C_OAR1_ADD0 I2C_OAR1_ADD1 I2C_OAR1_ADD2 I2C_OAR1_ADD3 I2C_OAR1_ADD4 I2C_OAR1_ADD5 I2C_OAR1_ADD6 I2C_OAR1_ADD7 I2C_OAR1_ADD8 I2C_OAR1_ADD9 I2C_OAR1_ADDMODE I2C_OAR2_ENDUAL I2C_OAR2_ADD2 I2C_DR_DR I2C_SR1_SB I2C_SR1_ADDR I2C_SR1_BTF I2C_SR1_ADD10 I2C_SR1_STOPF I2C_SR1_RXNE I2C_SR1_TXE I2C_SR1_BERR I2C_SR1_ARLO I2C_SR1_AF I2C_SR1_OVR I2C_SR1_PECERR I2C_SR1_TIMEOUT I2C_SR1_SMBALERT I2C_SR2_MSL I2C_SR2_BUSY I2C_SR2_TRA I2C_SR2_GENCALL I2C_SR2_SMBDEFAULT I2C_SR2_SMBHOST I2C_SR2_DUALF I2C_SR2_PEC I2C_CCR_CCR I2C_CCR_DUTY I2C_CCR_FS I2C_TRISE_TRISE IWDG_KR_KEY IWDG_PR_PR IWDG_PR_PR_0 IWDG_PR_PR_1 IWDG_PR_PR_2 IWDG_RLR_RL IWDG_SR_PVU IWDG_SR_RVU LCD_CR_LCDEN LCD_CR_VSEL LCD_CR_DUTY LCD_CR_DUTY_0 LCD_CR_DUTY_1 LCD_CR_DUTY_2 LCD_CR_BIAS LCD_CR_BIAS_0 LCD_CR_BIAS_1 LCD_CR_MUX_SEG LCD_FCR_HD LCD_FCR_SOFIE LCD_FCR_UDDIE LCD_FCR_PON LCD_FCR_PON_0 LCD_FCR_PON_1 LCD_FCR_PON_2 LCD_FCR_DEAD LCD_FCR_DEAD_0 LCD_FCR_DEAD_1 LCD_FCR_DEAD_2 LCD_FCR_CC LCD_FCR_CC_0 LCD_FCR_CC_1 LCD_FCR_CC_2 LCD_FCR_BLINKF LCD_FCR_BLINKF_0 LCD_FCR_BLINKF_1 LCD_FCR_BLINKF_2 LCD_FCR_BLINK LCD_FCR_BLINK_0 LCD_FCR_BLINK_1 LCD_FCR_DIV LCD_FCR_PS LCD_SR_ENS LCD_SR_SOF LCD_SR_UDR LCD_SR_UDD LCD_SR_RDY LCD_SR_FCRSR LCD_CLR_SOFC LCD_CLR_UDDC LCD_RAM_SEGMENT_DATA PWR_CR_LPSDSR PWR_CR_PDDS PWR_CR_CWUF PWR_CR_CSBF PWR_CR_PVDE PWR_CR_PLS PWR_CR_PLS_0 PWR_CR_PLS_1 PWR_CR_PLS_2 PWR_CR_PLS_LEV0 PWR_CR_PLS_LEV1 PWR_CR_PLS_LEV2 PWR_CR_PLS_LEV3 PWR_CR_PLS_LEV4 PWR_CR_PLS_LEV5 PWR_CR_PLS_LEV6 PWR_CR_PLS_LEV7 PWR_CR_DBP PWR_CR_ULP PWR_CR_FWU PWR_CR_VOS PWR_CR_VOS_0 PWR_CR_VOS_1 PWR_CR_LPRUN PWR_CSR_WUF PWR_CSR_SBF PWR_CSR_PVDO PWR_CSR_VREFINTRDYF PWR_CSR_VOSF PWR_CSR_REGLPF PWR_CSR_EWUP1 PWR_CSR_EWUP2 PWR_CSR_EWUP3 RCC_CR_HSION RCC_CR_HSIRDY RCC_CR_MSION RCC_CR_MSIRDY RCC_CR_HSEON RCC_CR_HSERDY RCC_CR_HSEBYP RCC_CR_PLLON RCC_CR_PLLRDY RCC_CR_CSSON RCC_CR_RTCPRE RCC_CR_RTCPRE_0 RCC_CR_RTCPRE_1 RCC_ICSCR_HSICAL RCC_ICSCR_HSITRIM RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_0 RCC_ICSCR_MSIRANGE_1 RCC_ICSCR_MSIRANGE_2 RCC_ICSCR_MSIRANGE_3 RCC_ICSCR_MSIRANGE_4 RCC_ICSCR_MSIRANGE_5 RCC_ICSCR_MSIRANGE_6 RCC_ICSCR_MSICAL RCC_ICSCR_MSITRIM RCC_CFGR_SW RCC_CFGR_SW_0 RCC_CFGR_SW_1 RCC_CFGR_SW_MSI RCC_CFGR_SW_HSI RCC_CFGR_SW_HSE RCC_CFGR_SW_PLL RCC_CFGR_SWS RCC_CFGR_SWS_0 RCC_CFGR_SWS_1 RCC_CFGR_SWS_MSI RCC_CFGR_SWS_HSI RCC_CFGR_SWS_HSE RCC_CFGR_SWS_PLL RCC_CFGR_HPRE RCC_CFGR_HPRE_0 RCC_CFGR_HPRE_1 RCC_CFGR_HPRE_2 RCC_CFGR_HPRE_3 RCC_CFGR_HPRE_DIV1 RCC_CFGR_HPRE_DIV2 RCC_CFGR_HPRE_DIV4 RCC_CFGR_HPRE_DIV8 RCC_CFGR_HPRE_DIV16 RCC_CFGR_HPRE_DIV64 RCC_CFGR_HPRE_DIV128 RCC_CFGR_HPRE_DIV256 RCC_CFGR_HPRE_DIV512 RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_0 RCC_CFGR_PPRE1_1 RCC_CFGR_PPRE1_2 RCC_CFGR_PPRE1_DIV1 RCC_CFGR_PPRE1_DIV2 RCC_CFGR_PPRE1_DIV4 RCC_CFGR_PPRE1_DIV8 RCC_CFGR_PPRE1_DIV16 RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_0 RCC_CFGR_PPRE2_1 RCC_CFGR_PPRE2_2 RCC_CFGR_PPRE2_DIV1 RCC_CFGR_PPRE2_DIV2 RCC_CFGR_PPRE2_DIV4 RCC_CFGR_PPRE2_DIV8 RCC_CFGR_PPRE2_DIV16 RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSI RCC_CFGR_PLLSRC_HSE RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_0 RCC_CFGR_PLLMUL_1 RCC_CFGR_PLLMUL_2 RCC_CFGR_PLLMUL_3 RCC_CFGR_PLLMUL3 RCC_CFGR_PLLMUL4 RCC_CFGR_PLLMUL6 RCC_CFGR_PLLMUL8 RCC_CFGR_PLLMUL12 RCC_CFGR_PLLMUL16 RCC_CFGR_PLLMUL24 RCC_CFGR_PLLMUL32 RCC_CFGR_PLLMUL48 RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_0 RCC_CFGR_PLLDIV_1 RCC_CFGR_PLLDIV1 RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV4 RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_0 RCC_CFGR_MCOSEL_1 RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCO_HSI RCC_CFGR_MCO_MSI RCC_CFGR_MCO_HSE RCC_CFGR_MCO_PLL RCC_CFGR_MCO_LSI RCC_CFGR_MCO_LSE RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_0 RCC_CFGR_MCOPRE_1 RCC_CFGR_MCOPRE_2 RCC_CFGR_MCO_DIV1 RCC_CFGR_MCO_DIV2 RCC_CFGR_MCO_DIV4 RCC_CFGR_MCO_DIV8 RCC_CFGR_MCO_DIV16 RCC_CIR_LSIRDYF RCC_CIR_LSERDYF RCC_CIR_HSIRDYF RCC_CIR_HSERDYF RCC_CIR_PLLRDYF RCC_CIR_MSIRDYF RCC_CIR_LSECSS RCC_CIR_CSSF RCC_CIR_LSIRDYIE RCC_CIR_LSERDYIE RCC_CIR_HSIRDYIE RCC_CIR_HSERDYIE RCC_CIR_PLLRDYIE RCC_CIR_MSIRDYIE RCC_CIR_LSECSSIE RCC_CIR_LSIRDYC RCC_CIR_LSERDYC RCC_CIR_HSIRDYC RCC_CIR_HSERDYC RCC_CIR_PLLRDYC RCC_CIR_MSIRDYC RCC_CIR_LSECSSC RCC_CIR_CSSC RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_CRCRST RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_AESRST RCC_AHBRSTR_FSMCRST RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_USART1RST RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_LCDRST RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART3RST RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART5RST RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_USBRST RCC_APB1RSTR_PWRRST RCC_APB1RSTR_DACRST RCC_APB1RSTR_COMPRST RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIODEN RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOGEN RCC_AHBENR_CRCEN RCC_AHBENR_FLITFEN RCC_AHBENR_DMA1EN RCC_AHBENR_DMA2EN RCC_AHBENR_AESEN RCC_AHBENR_FSMCEN RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM11EN RCC_APB2ENR_ADC1EN RCC_APB2ENR_SDIOEN RCC_APB2ENR_SPI1EN RCC_APB2ENR_USART1EN RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM7EN RCC_APB1ENR_LCDEN RCC_APB1ENR_WWDGEN RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI3EN RCC_APB1ENR_USART2EN RCC_APB1ENR_USART3EN RCC_APB1ENR_UART4EN RCC_APB1ENR_UART5EN RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C2EN RCC_APB1ENR_USBEN RCC_APB1ENR_PWREN RCC_APB1ENR_DACEN RCC_APB1ENR_COMPEN RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_AESLPEN RCC_AHBLPENR_FSMCLPEN RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_USART1LPEN RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_COMPLPEN RCC_CSR_LSION RCC_CSR_LSIRDY RCC_CSR_LSEON RCC_CSR_LSERDY RCC_CSR_LSEBYP RCC_CSR_LSECSSON RCC_CSR_LSECSSD RCC_CSR_RTCSEL RCC_CSR_RTCSEL_0 RCC_CSR_RTCSEL_1 RCC_CSR_RTCSEL_NOCLOCK RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_HSE RCC_CSR_RTCEN RCC_CSR_RTCRST RCC_CSR_RMVF RCC_CSR_OBLRSTF RCC_CSR_PINRSTF RCC_CSR_PORRSTF RCC_CSR_SFTRSTF RCC_CSR_IWDGRSTF RCC_CSR_WWDGRSTF RCC_CSR_LPWRRSTF RTC_TR_PM RTC_TR_HT RTC_TR_HT_0 RTC_TR_HT_1 RTC_TR_HU RTC_TR_HU_0 RTC_TR_HU_1 RTC_TR_HU_2 RTC_TR_HU_3 RTC_TR_MNT RTC_TR_MNT_0 RTC_TR_MNT_1 RTC_TR_MNT_2 RTC_TR_MNU RTC_TR_MNU_0 RTC_TR_MNU_1 RTC_TR_MNU_2 RTC_TR_MNU_3 RTC_TR_ST RTC_TR_ST_0 RTC_TR_ST_1 RTC_TR_ST_2 RTC_TR_SU RTC_TR_SU_0 RTC_TR_SU_1 RTC_TR_SU_2 RTC_TR_SU_3 RTC_DR_YT RTC_DR_YT_0 RTC_DR_YT_1 RTC_DR_YT_2 RTC_DR_YT_3 RTC_DR_YU RTC_DR_YU_0 RTC_DR_YU_1 RTC_DR_YU_2 RTC_DR_YU_3 RTC_DR_WDU RTC_DR_WDU_0 RTC_DR_WDU_1 RTC_DR_WDU_2 RTC_DR_MT RTC_DR_MU RTC_DR_MU_0 RTC_DR_MU_1 RTC_DR_MU_2 RTC_DR_MU_3 RTC_DR_DT RTC_DR_DT_0 RTC_DR_DT_1 RTC_DR_DU RTC_DR_DU_0 RTC_DR_DU_1 RTC_DR_DU_2 RTC_DR_DU_3 RTC_CR_COE RTC_CR_OSEL RTC_CR_OSEL_0 RTC_CR_OSEL_1 RTC_CR_POL RTC_CR_COSEL RTC_CR_BCK RTC_CR_SUB1H RTC_CR_ADD1H RTC_CR_TSIE RTC_CR_WUTIE RTC_CR_ALRBIE RTC_CR_ALRAIE RTC_CR_TSE RTC_CR_WUTE RTC_CR_ALRBE RTC_CR_ALRAE RTC_CR_DCE RTC_CR_FMT RTC_CR_BYPSHAD RTC_CR_REFCKON RTC_CR_TSEDGE RTC_CR_WUCKSEL RTC_CR_WUCKSEL_0 RTC_CR_WUCKSEL_1 RTC_CR_WUCKSEL_2 RTC_ISR_RECALPF RTC_ISR_TAMP3F RTC_ISR_TAMP2F RTC_ISR_TAMP1F RTC_ISR_TSOVF RTC_ISR_TSF RTC_ISR_WUTF RTC_ISR_ALRBF RTC_ISR_ALRAF RTC_ISR_INIT RTC_ISR_INITF RTC_ISR_RSF RTC_ISR_INITS RTC_ISR_SHPF RTC_ISR_WUTWF RTC_ISR_ALRBWF RTC_ISR_ALRAWF RTC_PRER_PREDIV_A RTC_PRER_PREDIV_S RTC_WUTR_WUT RTC_CALIBR_DCS RTC_CALIBR_DC RTC_ALRMAR_MSK4 RTC_ALRMAR_WDSEL RTC_ALRMAR_DT RTC_ALRMAR_DT_0 RTC_ALRMAR_DT_1 RTC_ALRMAR_DU RTC_ALRMAR_DU_0 RTC_ALRMAR_DU_1 RTC_ALRMAR_DU_2 RTC_ALRMAR_DU_3 RTC_ALRMAR_MSK3 RTC_ALRMAR_PM RTC_ALRMAR_HT RTC_ALRMAR_HT_0 RTC_ALRMAR_HT_1 RTC_ALRMAR_HU RTC_ALRMAR_HU_0 RTC_ALRMAR_HU_1 RTC_ALRMAR_HU_2 RTC_ALRMAR_HU_3 RTC_ALRMAR_MSK2 RTC_ALRMAR_MNT RTC_ALRMAR_MNT_0 RTC_ALRMAR_MNT_1 RTC_ALRMAR_MNT_2 RTC_ALRMAR_MNU RTC_ALRMAR_MNU_0 RTC_ALRMAR_MNU_1 RTC_ALRMAR_MNU_2 RTC_ALRMAR_MNU_3 RTC_ALRMAR_MSK1 RTC_ALRMAR_ST RTC_ALRMAR_ST_0 RTC_ALRMAR_ST_1 RTC_ALRMAR_ST_2 RTC_ALRMAR_SU RTC_ALRMAR_SU_0 RTC_ALRMAR_SU_1 RTC_ALRMAR_SU_2 RTC_ALRMAR_SU_3 RTC_ALRMBR_MSK4 RTC_ALRMBR_WDSEL RTC_ALRMBR_DT RTC_ALRMBR_DT_0 RTC_ALRMBR_DT_1 RTC_ALRMBR_DU RTC_ALRMBR_DU_0 RTC_ALRMBR_DU_1 RTC_ALRMBR_DU_2 RTC_ALRMBR_DU_3 RTC_ALRMBR_MSK3 RTC_ALRMBR_PM RTC_ALRMBR_HT RTC_ALRMBR_HT_0 RTC_ALRMBR_HT_1 RTC_ALRMBR_HU RTC_ALRMBR_HU_0 RTC_ALRMBR_HU_1 RTC_ALRMBR_HU_2 RTC_ALRMBR_HU_3 RTC_ALRMBR_MSK2 RTC_ALRMBR_MNT RTC_ALRMBR_MNT_0 RTC_ALRMBR_MNT_1 RTC_ALRMBR_MNT_2 RTC_ALRMBR_MNU RTC_ALRMBR_MNU_0 RTC_ALRMBR_MNU_1 RTC_ALRMBR_MNU_2 RTC_ALRMBR_MNU_3 RTC_ALRMBR_MSK1 RTC_ALRMBR_ST RTC_ALRMBR_ST_0 RTC_ALRMBR_ST_1 RTC_ALRMBR_ST_2 RTC_ALRMBR_SU RTC_ALRMBR_SU_0 RTC_ALRMBR_SU_1 RTC_ALRMBR_SU_2 RTC_ALRMBR_SU_3 RTC_WPR_KEY RTC_SSR_SS RTC_SHIFTR_SUBFS RTC_SHIFTR_ADD1S RTC_TSTR_PM RTC_TSTR_HT RTC_TSTR_HT_0 RTC_TSTR_HT_1 RTC_TSTR_HU RTC_TSTR_HU_0 RTC_TSTR_HU_1 RTC_TSTR_HU_2 RTC_TSTR_HU_3 RTC_TSTR_MNT RTC_TSTR_MNT_0 RTC_TSTR_MNT_1 RTC_TSTR_MNT_2 RTC_TSTR_MNU RTC_TSTR_MNU_0 RTC_TSTR_MNU_1 RTC_TSTR_MNU_2 RTC_TSTR_MNU_3 RTC_TSTR_ST RTC_TSTR_ST_0 RTC_TSTR_ST_1 RTC_TSTR_ST_2 RTC_TSTR_SU RTC_TSTR_SU_0 RTC_TSTR_SU_1 RTC_TSTR_SU_2 RTC_TSTR_SU_3 RTC_TSDR_WDU RTC_TSDR_WDU_0 RTC_TSDR_WDU_1 RTC_TSDR_WDU_2 RTC_TSDR_MT RTC_TSDR_MU RTC_TSDR_MU_0 RTC_TSDR_MU_1 RTC_TSDR_MU_2 RTC_TSDR_MU_3 RTC_TSDR_DT RTC_TSDR_DT_0 RTC_TSDR_DT_1 RTC_TSDR_DU RTC_TSDR_DU_0 RTC_TSDR_DU_1 RTC_TSDR_DU_2 RTC_TSDR_DU_3 RTC_TSSSR_SS RTC_CALR_CALP RTC_CALR_CALW8 RTC_CALR_CALW16 RTC_CALR_CALM RTC_CALR_CALM_0 RTC_CALR_CALM_1 RTC_CALR_CALM_2 RTC_CALR_CALM_3 RTC_CALR_CALM_4 RTC_CALR_CALM_5 RTC_CALR_CALM_6 RTC_CALR_CALM_7 RTC_CALR_CALM_8 RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_1 RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_1 RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_2 RTC_TAFCR_TAMPTS RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2E RTC_TAFCR_TAMPIE RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1E RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_0 RTC_ALRMASSR_MASKSS_1 RTC_ALRMASSR_MASKSS_2 RTC_ALRMASSR_MASKSS_3 RTC_ALRMASSR_SS RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_0 RTC_ALRMBSSR_MASKSS_1 RTC_ALRMBSSR_MASKSS_2 RTC_ALRMBSSR_MASKSS_3 RTC_ALRMBSSR_SS RTC_BKP0R RTC_BKP1R RTC_BKP2R RTC_BKP3R RTC_BKP4R RTC_BKP5R RTC_BKP6R RTC_BKP7R RTC_BKP8R RTC_BKP9R RTC_BKP10R RTC_BKP11R RTC_BKP12R RTC_BKP13R RTC_BKP14R RTC_BKP15R RTC_BKP16R RTC_BKP17R RTC_BKP18R RTC_BKP19R RTC_BKP20R RTC_BKP21R RTC_BKP22R RTC_BKP23R RTC_BKP24R RTC_BKP25R RTC_BKP26R RTC_BKP27R RTC_BKP28R RTC_BKP29R RTC_BKP30R RTC_BKP31R SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_0 SDIO_POWER_PWRCTRL_1 SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKEN SDIO_CLKCR_PWRSAV SDIO_CLKCR_BYPASS SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_0 SDIO_CLKCR_WIDBUS_1 SDIO_CLKCR_NEGEDGE SDIO_CLKCR_HWFC_EN SDIO_ARG_CMDARG SDIO_CMD_CMDINDEX SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_0 SDIO_CMD_WAITRESP_1 SDIO_CMD_WAITINT SDIO_CMD_WAITPEND SDIO_CMD_CPSMEN SDIO_CMD_SDIOSUSPEND SDIO_CMD_ENCMDCOMPL SDIO_CMD_NIEN SDIO_CMD_CEATACMD SDIO_RESPCMD_RESPCMD SDIO_RESP0_CARDSTATUS0 SDIO_RESP1_CARDSTATUS1 SDIO_RESP2_CARDSTATUS2 SDIO_RESP3_CARDSTATUS3 SDIO_RESP4_CARDSTATUS4 SDIO_DTIMER_DATATIME SDIO_DLEN_DATALENGTH SDIO_DCTRL_DTEN SDIO_DCTRL_DTDIR SDIO_DCTRL_DTMODE SDIO_DCTRL_DMAEN SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_0 SDIO_DCTRL_DBLOCKSIZE_1 SDIO_DCTRL_DBLOCKSIZE_2 SDIO_DCTRL_DBLOCKSIZE_3 SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWMOD SDIO_DCTRL_SDIOEN SDIO_DCOUNT_DATACOUNT SDIO_STA_CCRCFAIL SDIO_STA_DCRCFAIL SDIO_STA_CTIMEOUT SDIO_STA_DTIMEOUT SDIO_STA_TXUNDERR SDIO_STA_RXOVERR SDIO_STA_CMDREND SDIO_STA_CMDSENT SDIO_STA_DATAEND SDIO_STA_STBITERR SDIO_STA_DBCKEND SDIO_STA_CMDACT SDIO_STA_TXACT SDIO_STA_RXACT SDIO_STA_TXFIFOHE SDIO_STA_RXFIFOHF SDIO_STA_TXFIFOF SDIO_STA_RXFIFOF SDIO_STA_TXFIFOE SDIO_STA_RXFIFOE SDIO_STA_TXDAVL SDIO_STA_RXDAVL SDIO_STA_SDIOIT SDIO_STA_CEATAEND SDIO_ICR_CCRCFAILC SDIO_ICR_DCRCFAILC SDIO_ICR_CTIMEOUTC SDIO_ICR_DTIMEOUTC SDIO_ICR_TXUNDERRC SDIO_ICR_RXOVERRC SDIO_ICR_CMDRENDC SDIO_ICR_CMDSENTC SDIO_ICR_DATAENDC SDIO_ICR_STBITERRC SDIO_ICR_DBCKENDC SDIO_ICR_SDIOITC SDIO_ICR_CEATAENDC SDIO_MASK_CCRCFAILIE SDIO_MASK_DCRCFAILIE SDIO_MASK_CTIMEOUTIE SDIO_MASK_DTIMEOUTIE SDIO_MASK_TXUNDERRIE SDIO_MASK_RXOVERRIE SDIO_MASK_CMDRENDIE SDIO_MASK_CMDSENTIE SDIO_MASK_DATAENDIE SDIO_MASK_STBITERRIE SDIO_MASK_DBCKENDIE SDIO_MASK_CMDACTIE SDIO_MASK_TXACTIE SDIO_MASK_RXACTIE SDIO_MASK_TXFIFOHEIE SDIO_MASK_RXFIFOHFIE SDIO_MASK_TXFIFOFIE SDIO_MASK_RXFIFOFIE SDIO_MASK_TXFIFOEIE SDIO_MASK_RXFIFOEIE SDIO_MASK_TXDAVLIE SDIO_MASK_RXDAVLIE SDIO_MASK_SDIOITIE SDIO_MASK_CEATAENDIE SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFO_FIFODATA SPI_CR1_CPHA SPI_CR1_CPOL SPI_CR1_MSTR SPI_CR1_BR SPI_CR1_BR_0 SPI_CR1_BR_1 SPI_CR1_BR_2 SPI_CR1_SPE SPI_CR1_LSBFIRST SPI_CR1_SSI SPI_CR1_SSM SPI_CR1_RXONLY SPI_CR1_DFF SPI_CR1_CRCNEXT SPI_CR1_CRCEN SPI_CR1_BIDIOE SPI_CR1_BIDIMODE SPI_CR2_RXDMAEN SPI_CR2_TXDMAEN SPI_CR2_SSOE SPI_CR2_FRF SPI_CR2_ERRIE SPI_CR2_RXNEIE SPI_CR2_TXEIE SPI_SR_RXNE SPI_SR_TXE SPI_SR_CHSIDE SPI_SR_UDR SPI_SR_CRCERR SPI_SR_MODF SPI_SR_OVR SPI_SR_BSY SPI_DR_DR SPI_CRCPR_CRCPOLY SPI_RXCRCR_RXCRC SPI_TXCRCR_TXCRC SPI_I2SCFGR_CHLEN SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_0 SPI_I2SCFGR_DATLEN_1 SPI_I2SCFGR_CKPOL SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_0 SPI_I2SCFGR_I2SSTD_1 SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_0 SPI_I2SCFGR_I2SCFG_1 SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SMOD SPI_I2SPR_I2SDIV SPI_I2SPR_ODD SPI_I2SPR_MCKOE SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_0 SYSCFG_MEMRMP_MEM_MODE_1 SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_0 SYSCFG_MEMRMP_BOOT_MODE_1 SYSCFG_PMC_USB_PU SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI0_PA SYSCFG_EXTICR1_EXTI0_PB SYSCFG_EXTICR1_EXTI0_PC SYSCFG_EXTICR1_EXTI0_PD SYSCFG_EXTICR1_EXTI0_PE SYSCFG_EXTICR1_EXTI0_PH SYSCFG_EXTICR1_EXTI0_PF SYSCFG_EXTICR1_EXTI0_PG SYSCFG_EXTICR1_EXTI1_PA SYSCFG_EXTICR1_EXTI1_PB SYSCFG_EXTICR1_EXTI1_PC SYSCFG_EXTICR1_EXTI1_PD SYSCFG_EXTICR1_EXTI1_PE SYSCFG_EXTICR1_EXTI1_PH SYSCFG_EXTICR1_EXTI1_PF SYSCFG_EXTICR1_EXTI1_PG SYSCFG_EXTICR1_EXTI2_PA SYSCFG_EXTICR1_EXTI2_PB SYSCFG_EXTICR1_EXTI2_PC SYSCFG_EXTICR1_EXTI2_PD SYSCFG_EXTICR1_EXTI2_PE SYSCFG_EXTICR1_EXTI2_PH SYSCFG_EXTICR1_EXTI2_PF SYSCFG_EXTICR1_EXTI2_PG SYSCFG_EXTICR1_EXTI3_PA SYSCFG_EXTICR1_EXTI3_PB SYSCFG_EXTICR1_EXTI3_PC SYSCFG_EXTICR1_EXTI3_PD SYSCFG_EXTICR1_EXTI3_PE SYSCFG_EXTICR1_EXTI3_PF SYSCFG_EXTICR1_EXTI3_PG SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI4_PA SYSCFG_EXTICR2_EXTI4_PB SYSCFG_EXTICR2_EXTI4_PC SYSCFG_EXTICR2_EXTI4_PD SYSCFG_EXTICR2_EXTI4_PE SYSCFG_EXTICR2_EXTI4_PF SYSCFG_EXTICR2_EXTI4_PG SYSCFG_EXTICR2_EXTI5_PA SYSCFG_EXTICR2_EXTI5_PB SYSCFG_EXTICR2_EXTI5_PC SYSCFG_EXTICR2_EXTI5_PD SYSCFG_EXTICR2_EXTI5_PE SYSCFG_EXTICR2_EXTI5_PF SYSCFG_EXTICR2_EXTI5_PG SYSCFG_EXTICR2_EXTI6_PA SYSCFG_EXTICR2_EXTI6_PB SYSCFG_EXTICR2_EXTI6_PC SYSCFG_EXTICR2_EXTI6_PD SYSCFG_EXTICR2_EXTI6_PE SYSCFG_EXTICR2_EXTI6_PF SYSCFG_EXTICR2_EXTI6_PG SYSCFG_EXTICR2_EXTI7_PA SYSCFG_EXTICR2_EXTI7_PB SYSCFG_EXTICR2_EXTI7_PC SYSCFG_EXTICR2_EXTI7_PD SYSCFG_EXTICR2_EXTI7_PE SYSCFG_EXTICR2_EXTI7_PF SYSCFG_EXTICR2_EXTI7_PG SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI8_PA SYSCFG_EXTICR3_EXTI8_PB SYSCFG_EXTICR3_EXTI8_PC SYSCFG_EXTICR3_EXTI8_PD SYSCFG_EXTICR3_EXTI8_PE SYSCFG_EXTICR3_EXTI8_PF SYSCFG_EXTICR3_EXTI8_PG SYSCFG_EXTICR3_EXTI9_PA SYSCFG_EXTICR3_EXTI9_PB SYSCFG_EXTICR3_EXTI9_PC SYSCFG_EXTICR3_EXTI9_PD SYSCFG_EXTICR3_EXTI9_PE SYSCFG_EXTICR3_EXTI9_PF SYSCFG_EXTICR3_EXTI9_PG SYSCFG_EXTICR3_EXTI10_PA SYSCFG_EXTICR3_EXTI10_PB SYSCFG_EXTICR3_EXTI10_PC SYSCFG_EXTICR3_EXTI10_PD SYSCFG_EXTICR3_EXTI10_PE SYSCFG_EXTICR3_EXTI10_PF SYSCFG_EXTICR3_EXTI10_PG SYSCFG_EXTICR3_EXTI11_PA SYSCFG_EXTICR3_EXTI11_PB SYSCFG_EXTICR3_EXTI11_PC SYSCFG_EXTICR3_EXTI11_PD SYSCFG_EXTICR3_EXTI11_PE SYSCFG_EXTICR3_EXTI11_PF SYSCFG_EXTICR3_EXTI11_PG SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI12_PA SYSCFG_EXTICR4_EXTI12_PB SYSCFG_EXTICR4_EXTI12_PC SYSCFG_EXTICR4_EXTI12_PD SYSCFG_EXTICR4_EXTI12_PE SYSCFG_EXTICR4_EXTI12_PF SYSCFG_EXTICR4_EXTI12_PG SYSCFG_EXTICR4_EXTI13_PA SYSCFG_EXTICR4_EXTI13_PB SYSCFG_EXTICR4_EXTI13_PC SYSCFG_EXTICR4_EXTI13_PD SYSCFG_EXTICR4_EXTI13_PE SYSCFG_EXTICR4_EXTI13_PF SYSCFG_EXTICR4_EXTI13_PG SYSCFG_EXTICR4_EXTI14_PA SYSCFG_EXTICR4_EXTI14_PB SYSCFG_EXTICR4_EXTI14_PC SYSCFG_EXTICR4_EXTI14_PD SYSCFG_EXTICR4_EXTI14_PE SYSCFG_EXTICR4_EXTI14_PF SYSCFG_EXTICR4_EXTI14_PG SYSCFG_EXTICR4_EXTI15_PA SYSCFG_EXTICR4_EXTI15_PB SYSCFG_EXTICR4_EXTI15_PC SYSCFG_EXTICR4_EXTI15_PD SYSCFG_EXTICR4_EXTI15_PE SYSCFG_EXTICR4_EXTI15_PF SYSCFG_EXTICR4_EXTI15_PG RI_ICR_IC1Z RI_ICR_IC1Z_0 RI_ICR_IC1Z_1 RI_ICR_IC1Z_2 RI_ICR_IC1Z_3 RI_ICR_IC2Z RI_ICR_IC2Z_0 RI_ICR_IC2Z_1 RI_ICR_IC2Z_2 RI_ICR_IC2Z_3 RI_ICR_IC3Z RI_ICR_IC3Z_0 RI_ICR_IC3Z_1 RI_ICR_IC3Z_2 RI_ICR_IC3Z_3 RI_ICR_IC4Z RI_ICR_IC4Z_0 RI_ICR_IC4Z_1 RI_ICR_IC4Z_2 RI_ICR_IC4Z_3 RI_ICR_TIM RI_ICR_TIM_0 RI_ICR_TIM_1 RI_ICR_IC1 RI_ICR_IC2 RI_ICR_IC3 RI_ICR_IC4 RI_ASCR1_CH RI_ASCR1_CH_0 RI_ASCR1_CH_1 RI_ASCR1_CH_2 RI_ASCR1_CH_3 RI_ASCR1_CH_4 RI_ASCR1_CH_5 RI_ASCR1_CH_6 RI_ASCR1_CH_7 RI_ASCR1_CH_8 RI_ASCR1_CH_9 RI_ASCR1_CH_10 RI_ASCR1_CH_11 RI_ASCR1_CH_12 RI_ASCR1_CH_13 RI_ASCR1_CH_14 RI_ASCR1_CH_15 RI_ASCR1_CH_31 RI_ASCR1_CH_18 RI_ASCR1_CH_19 RI_ASCR1_CH_20 RI_ASCR1_CH_21 RI_ASCR1_CH_22 RI_ASCR1_CH_23 RI_ASCR1_CH_24 RI_ASCR1_CH_25 RI_ASCR1_VCOMP RI_ASCR1_CH_27 RI_ASCR1_CH_28 RI_ASCR1_CH_29 RI_ASCR1_CH_30 RI_ASCR1_SCM RI_ASCR2_GR10_1 RI_ASCR2_GR10_2 RI_ASCR2_GR10_3 RI_ASCR2_GR10_4 RI_ASCR2_GR6_1 RI_ASCR2_GR6_2 RI_ASCR2_GR5_1 RI_ASCR2_GR5_2 RI_ASCR2_GR5_3 RI_ASCR2_GR4_1 RI_ASCR2_GR4_2 RI_ASCR2_GR4_3 RI_ASCR2_GR4_4 RI_ASCR2_CH0b RI_ASCR2_CH1b RI_ASCR2_CH2b RI_ASCR2_CH3b RI_ASCR2_CH6b RI_ASCR2_CH7b RI_ASCR2_CH8b RI_ASCR2_CH9b RI_ASCR2_CH10b RI_ASCR2_CH11b RI_ASCR2_CH12b RI_ASCR2_GR6_3 RI_ASCR2_GR6_4 RI_ASCR2_GR5_4 RI_HYSCR1_PA RI_HYSCR1_PA_0 RI_HYSCR1_PA_1 RI_HYSCR1_PA_2 RI_HYSCR1_PA_3 RI_HYSCR1_PA_4 RI_HYSCR1_PA_5 RI_HYSCR1_PA_6 RI_HYSCR1_PA_7 RI_HYSCR1_PA_8 RI_HYSCR1_PA_9 RI_HYSCR1_PA_10 RI_HYSCR1_PA_11 RI_HYSCR1_PA_12 RI_HYSCR1_PA_13 RI_HYSCR1_PA_14 RI_HYSCR1_PA_15 RI_HYSCR1_PB RI_HYSCR1_PB_0 RI_HYSCR1_PB_1 RI_HYSCR1_PB_2 RI_HYSCR1_PB_3 RI_HYSCR1_PB_4 RI_HYSCR1_PB_5 RI_HYSCR1_PB_6 RI_HYSCR1_PB_7 RI_HYSCR1_PB_8 RI_HYSCR1_PB_9 RI_HYSCR1_PB_10 RI_HYSCR1_PB_11 RI_HYSCR1_PB_12 RI_HYSCR1_PB_13 RI_HYSCR1_PB_14 RI_HYSCR1_PB_15 RI_HYSCR2_PC RI_HYSCR2_PC_0 RI_HYSCR2_PC_1 RI_HYSCR2_PC_2 RI_HYSCR2_PC_3 RI_HYSCR2_PC_4 RI_HYSCR2_PC_5 RI_HYSCR2_PC_6 RI_HYSCR2_PC_7 RI_HYSCR2_PC_8 RI_HYSCR2_PC_9 RI_HYSCR2_PC_10 RI_HYSCR2_PC_11 RI_HYSCR2_PC_12 RI_HYSCR2_PC_13 RI_HYSCR2_PC_14 RI_HYSCR2_PC_15 RI_HYSCR2_PD RI_HYSCR2_PD_0 RI_HYSCR2_PD_1 RI_HYSCR2_PD_2 RI_HYSCR2_PD_3 RI_HYSCR2_PD_4 RI_HYSCR2_PD_5 RI_HYSCR2_PD_6 RI_HYSCR2_PD_7 RI_HYSCR2_PD_8 RI_HYSCR2_PD_9 RI_HYSCR2_PD_10 RI_HYSCR2_PD_11 RI_HYSCR2_PD_12 RI_HYSCR2_PD_13 RI_HYSCR2_PD_14 RI_HYSCR2_PD_15 RI_HYSCR2_PE RI_HYSCR2_PE_0 RI_HYSCR2_PE_1 RI_HYSCR2_PE_2 RI_HYSCR2_PE_3 RI_HYSCR2_PE_4 RI_HYSCR2_PE_5 RI_HYSCR2_PE_6 RI_HYSCR2_PE_7 RI_HYSCR2_PE_8 RI_HYSCR2_PE_9 RI_HYSCR2_PE_10 RI_HYSCR2_PE_11 RI_HYSCR2_PE_12 RI_HYSCR2_PE_13 RI_HYSCR2_PE_14 RI_HYSCR2_PE_15 RI_HYSCR3_PF RI_HYSCR3_PF_0 RI_HYSCR3_PF_1 RI_HYSCR3_PF_2 RI_HYSCR3_PF_3 RI_HYSCR3_PF_4 RI_HYSCR3_PF_5 RI_HYSCR3_PF_6 RI_HYSCR3_PF_7 RI_HYSCR3_PF_8 RI_HYSCR3_PF_9 RI_HYSCR3_PF_10 RI_HYSCR3_PF_11 RI_HYSCR3_PF_12 RI_HYSCR3_PF_13 RI_HYSCR3_PF_14 RI_HYSCR3_PF_15 RI_HYSCR4_PG RI_HYSCR4_PG_0 RI_HYSCR4_PG_1 RI_HYSCR4_PG_2 RI_HYSCR4_PG_3 RI_HYSCR4_PG_4 RI_HYSCR4_PG_5 RI_HYSCR4_PG_6 RI_HYSCR4_PG_7 RI_HYSCR4_PG_8 RI_HYSCR4_PG_9 RI_HYSCR4_PG_10 RI_HYSCR4_PG_11 RI_HYSCR4_PG_12 RI_HYSCR4_PG_13 RI_HYSCR4_PG_14 RI_HYSCR4_PG_15 TIM_CR1_CEN TIM_CR1_UDIS TIM_CR1_URS TIM_CR1_OPM TIM_CR1_DIR TIM_CR1_CMS TIM_CR1_CMS_0 TIM_CR1_CMS_1 TIM_CR1_ARPE TIM_CR1_CKD TIM_CR1_CKD_0 TIM_CR1_CKD_1 TIM_CR2_CCDS TIM_CR2_MMS TIM_CR2_MMS_0 TIM_CR2_MMS_1 TIM_CR2_MMS_2 TIM_CR2_TI1S TIM_SMCR_SMS TIM_SMCR_SMS_0 TIM_SMCR_SMS_1 TIM_SMCR_SMS_2 TIM_SMCR_OCCS TIM_SMCR_TS TIM_SMCR_TS_0 TIM_SMCR_TS_1 TIM_SMCR_TS_2 TIM_SMCR_MSM TIM_SMCR_ETF TIM_SMCR_ETF_0 TIM_SMCR_ETF_1 TIM_SMCR_ETF_2 TIM_SMCR_ETF_3 TIM_SMCR_ETPS TIM_SMCR_ETPS_0 TIM_SMCR_ETPS_1 TIM_SMCR_ECE TIM_SMCR_ETP TIM_DIER_UIE TIM_DIER_CC1IE TIM_DIER_CC2IE TIM_DIER_CC3IE TIM_DIER_CC4IE TIM_DIER_TIE TIM_DIER_UDE TIM_DIER_CC1DE TIM_DIER_CC2DE TIM_DIER_CC3DE TIM_DIER_CC4DE TIM_DIER_TDE TIM_SR_UIF TIM_SR_CC1IF TIM_SR_CC2IF TIM_SR_CC3IF TIM_SR_CC4IF TIM_SR_TIF TIM_SR_CC1OF TIM_SR_CC2OF TIM_SR_CC3OF TIM_SR_CC4OF TIM_EGR_UG TIM_EGR_CC1G TIM_EGR_CC2G TIM_EGR_CC3G TIM_EGR_CC4G TIM_EGR_TG TIM_CCMR1_CC1S TIM_CCMR1_CC1S_0 TIM_CCMR1_CC1S_1 TIM_CCMR1_OC1FE TIM_CCMR1_OC1PE TIM_CCMR1_OC1M TIM_CCMR1_OC1M_0 TIM_CCMR1_OC1M_1 TIM_CCMR1_OC1M_2 TIM_CCMR1_OC1CE TIM_CCMR1_CC2S TIM_CCMR1_CC2S_0 TIM_CCMR1_CC2S_1 TIM_CCMR1_OC2FE TIM_CCMR1_OC2PE TIM_CCMR1_OC2M TIM_CCMR1_OC2M_0 TIM_CCMR1_OC2M_1 TIM_CCMR1_OC2M_2 TIM_CCMR1_OC2CE TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_0 TIM_CCMR1_IC1PSC_1 TIM_CCMR1_IC1F TIM_CCMR1_IC1F_0 TIM_CCMR1_IC1F_1 TIM_CCMR1_IC1F_2 TIM_CCMR1_IC1F_3 TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_0 TIM_CCMR1_IC2PSC_1 TIM_CCMR1_IC2F TIM_CCMR1_IC2F_0 TIM_CCMR1_IC2F_1 TIM_CCMR1_IC2F_2 TIM_CCMR1_IC2F_3 TIM_CCMR2_CC3S TIM_CCMR2_CC3S_0 TIM_CCMR2_CC3S_1 TIM_CCMR2_OC3FE TIM_CCMR2_OC3PE TIM_CCMR2_OC3M TIM_CCMR2_OC3M_0 TIM_CCMR2_OC3M_1 TIM_CCMR2_OC3M_2 TIM_CCMR2_OC3CE TIM_CCMR2_CC4S TIM_CCMR2_CC4S_0 TIM_CCMR2_CC4S_1 TIM_CCMR2_OC4FE TIM_CCMR2_OC4PE TIM_CCMR2_OC4M TIM_CCMR2_OC4M_0 TIM_CCMR2_OC4M_1 TIM_CCMR2_OC4M_2 TIM_CCMR2_OC4CE TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_0 TIM_CCMR2_IC3PSC_1 TIM_CCMR2_IC3F TIM_CCMR2_IC3F_0 TIM_CCMR2_IC3F_1 TIM_CCMR2_IC3F_2 TIM_CCMR2_IC3F_3 TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_0 TIM_CCMR2_IC4PSC_1 TIM_CCMR2_IC4F TIM_CCMR2_IC4F_0 TIM_CCMR2_IC4F_1 TIM_CCMR2_IC4F_2 TIM_CCMR2_IC4F_3 TIM_CCER_CC1E TIM_CCER_CC1P TIM_CCER_CC1NP TIM_CCER_CC2E TIM_CCER_CC2P TIM_CCER_CC2NP TIM_CCER_CC3E TIM_CCER_CC3P TIM_CCER_CC3NP TIM_CCER_CC4E TIM_CCER_CC4P TIM_CCER_CC4NP TIM_CNT_CNT TIM_PSC_PSC TIM_ARR_ARR TIM_CCR1_CCR1 TIM_CCR2_CCR2 TIM_CCR3_CCR3 TIM_CCR4_CCR4 TIM_DCR_DBA TIM_DCR_DBA_0 TIM_DCR_DBA_1 TIM_DCR_DBA_2 TIM_DCR_DBA_3 TIM_DCR_DBA_4 TIM_DCR_DBL TIM_DCR_DBL_0 TIM_DCR_DBL_1 TIM_DCR_DBL_2 TIM_DCR_DBL_3 TIM_DCR_DBL_4 TIM_DMAR_DMAB TIM_OR_TI1RMP TIM_OR_TI1RMP_0 TIM_OR_TI1RMP_1 USART_SR_PE USART_SR_FE USART_SR_NE USART_SR_ORE USART_SR_IDLE USART_SR_RXNE USART_SR_TC USART_SR_TXE USART_SR_LBD USART_SR_CTS USART_DR_DR USART_BRR_DIV_FRACTION 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WWDG_CFR_W1 WWDG_CFR_W2 WWDG_CFR_W3 WWDG_CFR_W4 WWDG_CFR_W5 WWDG_CFR_W6 WWDG_CFR_WDGTB WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB1 WWDG_CFR_EWI WWDG_SR_EWIF SysTick_CTRL_ENABLE SysTick_CTRL_TICKINT SysTick_CTRL_CLKSOURCE SysTick_CTRL_COUNTFLAG SysTick_LOAD_RELOAD SysTick_VAL_CURRENT SysTick_CALIB_TENMS SysTick_CALIB_SKEW SysTick_CALIB_NOREF NVIC_ISER_SETENA NVIC_ISER_SETENA_0 NVIC_ISER_SETENA_1 NVIC_ISER_SETENA_2 NVIC_ISER_SETENA_3 NVIC_ISER_SETENA_4 NVIC_ISER_SETENA_5 NVIC_ISER_SETENA_6 NVIC_ISER_SETENA_7 NVIC_ISER_SETENA_8 NVIC_ISER_SETENA_9 NVIC_ISER_SETENA_10 NVIC_ISER_SETENA_11 NVIC_ISER_SETENA_12 NVIC_ISER_SETENA_13 NVIC_ISER_SETENA_14 NVIC_ISER_SETENA_15 NVIC_ISER_SETENA_16 NVIC_ISER_SETENA_17 NVIC_ISER_SETENA_18 NVIC_ISER_SETENA_19 NVIC_ISER_SETENA_20 NVIC_ISER_SETENA_21 NVIC_ISER_SETENA_22 NVIC_ISER_SETENA_23 NVIC_ISER_SETENA_24 NVIC_ISER_SETENA_25 NVIC_ISER_SETENA_26 NVIC_ISER_SETENA_27 NVIC_ISER_SETENA_28 NVIC_ISER_SETENA_29 NVIC_ISER_SETENA_30 NVIC_ISER_SETENA_31 NVIC_ICER_CLRENA NVIC_ICER_CLRENA_0 NVIC_ICER_CLRENA_1 NVIC_ICER_CLRENA_2 NVIC_ICER_CLRENA_3 NVIC_ICER_CLRENA_4 NVIC_ICER_CLRENA_5 NVIC_ICER_CLRENA_6 NVIC_ICER_CLRENA_7 NVIC_ICER_CLRENA_8 NVIC_ICER_CLRENA_9 NVIC_ICER_CLRENA_10 NVIC_ICER_CLRENA_11 NVIC_ICER_CLRENA_12 NVIC_ICER_CLRENA_13 NVIC_ICER_CLRENA_14 NVIC_ICER_CLRENA_15 NVIC_ICER_CLRENA_16 NVIC_ICER_CLRENA_17 NVIC_ICER_CLRENA_18 NVIC_ICER_CLRENA_19 NVIC_ICER_CLRENA_20 NVIC_ICER_CLRENA_21 NVIC_ICER_CLRENA_22 NVIC_ICER_CLRENA_23 NVIC_ICER_CLRENA_24 NVIC_ICER_CLRENA_25 NVIC_ICER_CLRENA_26 NVIC_ICER_CLRENA_27 NVIC_ICER_CLRENA_28 NVIC_ICER_CLRENA_29 NVIC_ICER_CLRENA_30 NVIC_ICER_CLRENA_31 NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_0 NVIC_ISPR_SETPEND_1 NVIC_ISPR_SETPEND_2 NVIC_ISPR_SETPEND_3 NVIC_ISPR_SETPEND_4 NVIC_ISPR_SETPEND_5 NVIC_ISPR_SETPEND_6 NVIC_ISPR_SETPEND_7 NVIC_ISPR_SETPEND_8 NVIC_ISPR_SETPEND_9 NVIC_ISPR_SETPEND_10 NVIC_ISPR_SETPEND_11 NVIC_ISPR_SETPEND_12 NVIC_ISPR_SETPEND_13 NVIC_ISPR_SETPEND_14 NVIC_ISPR_SETPEND_15 NVIC_ISPR_SETPEND_16 NVIC_ISPR_SETPEND_17 NVIC_ISPR_SETPEND_18 NVIC_ISPR_SETPEND_19 NVIC_ISPR_SETPEND_20 NVIC_ISPR_SETPEND_21 NVIC_ISPR_SETPEND_22 NVIC_ISPR_SETPEND_23 NVIC_ISPR_SETPEND_24 NVIC_ISPR_SETPEND_25 NVIC_ISPR_SETPEND_26 NVIC_ISPR_SETPEND_27 NVIC_ISPR_SETPEND_28 NVIC_ISPR_SETPEND_29 NVIC_ISPR_SETPEND_30 NVIC_ISPR_SETPEND_31 NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_0 NVIC_ICPR_CLRPEND_1 NVIC_ICPR_CLRPEND_2 NVIC_ICPR_CLRPEND_3 NVIC_ICPR_CLRPEND_4 NVIC_ICPR_CLRPEND_5 NVIC_ICPR_CLRPEND_6 NVIC_ICPR_CLRPEND_7 NVIC_ICPR_CLRPEND_8 NVIC_ICPR_CLRPEND_9 NVIC_ICPR_CLRPEND_10 NVIC_ICPR_CLRPEND_11 NVIC_ICPR_CLRPEND_12 NVIC_ICPR_CLRPEND_13 NVIC_ICPR_CLRPEND_14 NVIC_ICPR_CLRPEND_15 NVIC_ICPR_CLRPEND_16 NVIC_ICPR_CLRPEND_17 NVIC_ICPR_CLRPEND_18 NVIC_ICPR_CLRPEND_19 NVIC_ICPR_CLRPEND_20 NVIC_ICPR_CLRPEND_21 NVIC_ICPR_CLRPEND_22 NVIC_ICPR_CLRPEND_23 NVIC_ICPR_CLRPEND_24 NVIC_ICPR_CLRPEND_25 NVIC_ICPR_CLRPEND_26 NVIC_ICPR_CLRPEND_27 NVIC_ICPR_CLRPEND_28 NVIC_ICPR_CLRPEND_29 NVIC_ICPR_CLRPEND_30 NVIC_ICPR_CLRPEND_31 NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_0 NVIC_IABR_ACTIVE_1 NVIC_IABR_ACTIVE_2 NVIC_IABR_ACTIVE_3 NVIC_IABR_ACTIVE_4 NVIC_IABR_ACTIVE_5 NVIC_IABR_ACTIVE_6 NVIC_IABR_ACTIVE_7 NVIC_IABR_ACTIVE_8 NVIC_IABR_ACTIVE_9 NVIC_IABR_ACTIVE_10 NVIC_IABR_ACTIVE_11 NVIC_IABR_ACTIVE_12 NVIC_IABR_ACTIVE_13 NVIC_IABR_ACTIVE_14 NVIC_IABR_ACTIVE_15 NVIC_IABR_ACTIVE_16 NVIC_IABR_ACTIVE_17 NVIC_IABR_ACTIVE_18 NVIC_IABR_ACTIVE_19 NVIC_IABR_ACTIVE_20 NVIC_IABR_ACTIVE_21 NVIC_IABR_ACTIVE_22 NVIC_IABR_ACTIVE_23 NVIC_IABR_ACTIVE_24 NVIC_IABR_ACTIVE_25 NVIC_IABR_ACTIVE_26 NVIC_IABR_ACTIVE_27 NVIC_IABR_ACTIVE_28 NVIC_IABR_ACTIVE_29 NVIC_IABR_ACTIVE_30 NVIC_IABR_ACTIVE_31 NVIC_IPR0_PRI_0 NVIC_IPR0_PRI_1 NVIC_IPR0_PRI_2 NVIC_IPR0_PRI_3 NVIC_IPR1_PRI_4 NVIC_IPR1_PRI_5 NVIC_IPR1_PRI_6 NVIC_IPR1_PRI_7 NVIC_IPR2_PRI_8 NVIC_IPR2_PRI_9 NVIC_IPR2_PRI_10 NVIC_IPR2_PRI_11 NVIC_IPR3_PRI_12 NVIC_IPR3_PRI_13 NVIC_IPR3_PRI_14 NVIC_IPR3_PRI_15 NVIC_IPR4_PRI_16 NVIC_IPR4_PRI_17 NVIC_IPR4_PRI_18 NVIC_IPR4_PRI_19 NVIC_IPR5_PRI_20 NVIC_IPR5_PRI_21 NVIC_IPR5_PRI_22 NVIC_IPR5_PRI_23 NVIC_IPR6_PRI_24 NVIC_IPR6_PRI_25 NVIC_IPR6_PRI_26 NVIC_IPR6_PRI_27 NVIC_IPR7_PRI_28 NVIC_IPR7_PRI_29 NVIC_IPR7_PRI_30 NVIC_IPR7_PRI_31 SCB_CPUID_REVISION SCB_CPUID_PARTNO SCB_CPUID_Constant SCB_CPUID_VARIANT SCB_CPUID_IMPLEMENTER SCB_ICSR_VECTACTIVE SCB_ICSR_RETTOBASE SCB_ICSR_VECTPENDING SCB_ICSR_ISRPENDING SCB_ICSR_ISRPREEMPT SCB_ICSR_PENDSTCLR SCB_ICSR_PENDSTSET SCB_ICSR_PENDSVCLR SCB_ICSR_PENDSVSET SCB_ICSR_NMIPENDSET SCB_VTOR_TBLOFF SCB_VTOR_TBLBASE SCB_AIRCR_VECTRESET SCB_AIRCR_VECTCLRACTIVE SCB_AIRCR_SYSRESETREQ SCB_AIRCR_PRIGROUP SCB_AIRCR_PRIGROUP_0 SCB_AIRCR_PRIGROUP_1 SCB_AIRCR_PRIGROUP_2 SCB_AIRCR_PRIGROUP0 SCB_AIRCR_PRIGROUP1 SCB_AIRCR_PRIGROUP2 SCB_AIRCR_PRIGROUP3 SCB_AIRCR_PRIGROUP4 SCB_AIRCR_PRIGROUP5 SCB_AIRCR_PRIGROUP6 SCB_AIRCR_PRIGROUP7 SCB_AIRCR_ENDIANESS SCB_AIRCR_VECTKEY SCB_SCR_SLEEPONEXIT SCB_SCR_SLEEPDEEP SCB_SCR_SEVONPEND SCB_CCR_NONBASETHRDENA SCB_CCR_USERSETMPEND SCB_CCR_UNALIGN_TRP SCB_CCR_DIV_0_TRP SCB_CCR_BFHFNMIGN SCB_CCR_STKALIGN SCB_SHPR_PRI_N SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N3 SCB_SHCSR_MEMFAULTACT SCB_SHCSR_BUSFAULTACT SCB_SHCSR_USGFAULTACT SCB_SHCSR_SVCALLACT SCB_SHCSR_MONITORACT SCB_SHCSR_PENDSVACT SCB_SHCSR_SYSTICKACT SCB_SHCSR_USGFAULTPENDED SCB_SHCSR_MEMFAULTPENDED SCB_SHCSR_BUSFAULTPENDED SCB_SHCSR_SVCALLPENDED SCB_SHCSR_MEMFAULTENA SCB_SHCSR_BUSFAULTENA SCB_SHCSR_USGFAULTENA SCB_CFSR_IACCVIOL SCB_CFSR_DACCVIOL SCB_CFSR_MUNSTKERR SCB_CFSR_MSTKERR SCB_CFSR_MMARVALID SCB_CFSR_IBUSERR SCB_CFSR_PRECISERR SCB_CFSR_IMPRECISERR SCB_CFSR_UNSTKERR SCB_CFSR_STKERR SCB_CFSR_BFARVALID SCB_CFSR_UNDEFINSTR SCB_CFSR_INVSTATE SCB_CFSR_INVPC SCB_CFSR_NOCP SCB_CFSR_UNALIGNED SCB_CFSR_DIVBYZERO SCB_HFSR_VECTTBL SCB_HFSR_FORCED SCB_HFSR_DEBUGEVT SCB_DFSR_HALTED SCB_DFSR_BKPT SCB_DFSR_DWTTRAP SCB_DFSR_VCATCH SCB_DFSR_EXTERNAL SCB_MMFAR_ADDRESS SCB_BFAR_ADDRESS SCB_AFSR_IMPDEF SET_BIT CLEAR_BIT READ_BIT CLEAR_REG WRITE_REG READ_REG MODIFY_REG STM32_TIM1 STM32_TIM2 STM32_TIM3 STM32_TIM4 STM32_TIM5 STM32_TIM6 STM32_TIM7 STM32_TIM8 STM32_TIM9 STM32_TIM10 STM32_TIM11 STM32_TIM12 STM32_TIM13 STM32_TIM14 HAL_IMPLEMENTS_COUNTERS PLATFORM_NAME STM32_HSICLK STM32_LSICLK STM32_VOS_MASK STM32_VOS_1P8 STM32_VOS_1P5 STM32_VOS_1P2 STM32_PLS_MASK STM32_PLS_LEV0 STM32_PLS_LEV1 STM32_PLS_LEV2 STM32_PLS_LEV3 STM32_PLS_LEV4 STM32_PLS_LEV5 STM32_PLS_LEV6 STM32_PLS_LEV7 STM32_RTCPRE_MASK STM32_RTCPRE_DIV2 STM32_RTCPRE_DIV4 STM32_RTCPRE_DIV8 STM32_RTCPRE_DIV16 STM32_SW_MSI STM32_SW_HSI STM32_SW_HSE STM32_SW_PLL STM32_HPRE_DIV1 STM32_HPRE_DIV2 STM32_HPRE_DIV4 STM32_HPRE_DIV8 STM32_HPRE_DIV16 STM32_HPRE_DIV64 STM32_HPRE_DIV128 STM32_HPRE_DIV256 STM32_HPRE_DIV512 STM32_PPRE1_DIV1 STM32_PPRE1_DIV2 STM32_PPRE1_DIV4 STM32_PPRE1_DIV8 STM32_PPRE1_DIV16 STM32_PPRE2_DIV1 STM32_PPRE2_DIV2 STM32_PPRE2_DIV4 STM32_PPRE2_DIV8 STM32_PPRE2_DIV16 STM32_PLLSRC_HSI STM32_PLLSRC_HSE STM32_MCOSEL_NOCLOCK STM32_MCOSEL_SYSCLK STM32_MCOSEL_HSI STM32_MCOSEL_MSI STM32_MCOSEL_HSE STM32_MCOSEL_PLL STM32_MCOSEL_LSI STM32_MCOSEL_LSE STM32_MCOPRE_DIV1 STM32_MCOPRE_DIV2 STM32_MCOPRE_DIV4 STM32_MCOPRE_DIV8 STM32_MCOPRE_DIV16 STM32_MSIRANGE_MASK STM32_MSIRANGE_64K STM32_MSIRANGE_128K STM32_MSIRANGE_256K STM32_MSIRANGE_512K STM32_MSIRANGE_1M STM32_MSIRANGE_2M STM32_MSIRANGE_4M STM32_RTCSEL_MASK STM32_RTCSEL_NOCLOCK STM32_RTCSEL_LSE STM32_RTCSEL_LSI STM32_RTCSEL_HSEDIV STM32_HAS_ADC1 STM32_HAS_ADC2 STM32_HAS_ADC3 STM32_HAS_ADC4 STM32_HAS_CAN1 STM32_HAS_CAN2 STM32_CAN_MAX_FILTERS STM32_HAS_DAC STM32_ADVANCED_DMA STM32_HAS_DMA1 STM32_HAS_DMA2 STM32_HAS_ETH STM32_EXTI_NUM_CHANNELS STM32_HAS_GPIOA STM32_HAS_GPIOB STM32_HAS_GPIOC STM32_HAS_GPIOD STM32_HAS_GPIOE STM32_HAS_GPIOF STM32_HAS_GPIOG STM32_HAS_GPIOH STM32_HAS_GPIOI STM32_HAS_I2C1 STM32_I2C1_RX_DMA_MSK STM32_I2C1_RX_DMA_CHN STM32_I2C1_TX_DMA_MSK STM32_I2C1_TX_DMA_CHN STM32_HAS_I2C2 STM32_I2C2_RX_DMA_MSK STM32_I2C2_RX_DMA_CHN STM32_I2C2_TX_DMA_MSK STM32_I2C2_TX_DMA_CHN STM32_HAS_I2C3 STM32_I2C3_RX_DMA_MSK STM32_I2C3_RX_DMA_CHN STM32_I2C3_TX_DMA_MSK STM32_I2C3_TX_DMA_CHN STM32_HAS_RTC STM32_RTC_HAS_SUBSECONDS STM32_RTC_IS_CALENDAR STM32_HAS_SDIO STM32_HAS_SPI1 STM32_SPI1_RX_DMA_MSK STM32_SPI1_RX_DMA_CHN STM32_SPI1_TX_DMA_MSK STM32_SPI1_TX_DMA_CHN STM32_HAS_SPI2 STM32_SPI2_RX_DMA_MSK STM32_SPI2_RX_DMA_CHN STM32_SPI2_TX_DMA_MSK STM32_SPI2_TX_DMA_CHN STM32_HAS_SPI3 STM32_SPI3_RX_DMA_MSK STM32_SPI3_RX_DMA_CHN STM32_SPI3_TX_DMA_MSK STM32_SPI3_TX_DMA_CHN STM32_HAS_TIM1 STM32_HAS_TIM2 STM32_HAS_TIM3 STM32_HAS_TIM4 STM32_HAS_TIM5 STM32_HAS_TIM6 STM32_HAS_TIM7 STM32_HAS_TIM8 STM32_HAS_TIM9 STM32_HAS_TIM10 STM32_HAS_TIM11 STM32_HAS_TIM12 STM32_HAS_TIM13 STM32_HAS_TIM14 STM32_HAS_TIM15 STM32_HAS_TIM16 STM32_HAS_TIM17 STM32_HAS_TIM18 STM32_HAS_TIM19 STM32_HAS_USART1 STM32_USART1_RX_DMA_MSK STM32_USART1_RX_DMA_CHN STM32_USART1_TX_DMA_MSK STM32_USART1_TX_DMA_CHN STM32_HAS_USART2 STM32_USART2_RX_DMA_MSK STM32_USART2_RX_DMA_CHN STM32_USART2_TX_DMA_MSK STM32_USART2_TX_DMA_CHN STM32_HAS_USART3 STM32_USART3_RX_DMA_MSK STM32_USART3_RX_DMA_CHN STM32_USART3_TX_DMA_MSK STM32_USART3_TX_DMA_CHN STM32_HAS_UART4 STM32_UART4_RX_DMA_MSK STM32_UART4_RX_DMA_CHN STM32_UART4_TX_DMA_MSK STM32_UART4_TX_DMA_CHN STM32_HAS_UART5 STM32_UART5_RX_DMA_MSK STM32_UART5_RX_DMA_CHN STM32_UART5_TX_DMA_MSK STM32_UART5_TX_DMA_CHN STM32_HAS_USART6 STM32_USART6_RX_DMA_MSK STM32_USART6_RX_DMA_CHN STM32_USART6_TX_DMA_MSK STM32_USART6_TX_DMA_CHN STM32_HAS_USB STM32_HAS_OTG1 STM32_HAS_OTG2 WWDG_IRQHandler PVD_IRQHandler TAMPER_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Ch1_IRQHandler DMA1_Ch2_IRQHandler DMA1_Ch3_IRQHandler DMA1_Ch4_IRQHandler DMA1_Ch5_IRQHandler DMA1_Ch6_IRQHandler DMA1_Ch7_IRQHandler ADC1_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler DAC_IRQHandler COMP_IRQHandler EXTI9_5_IRQHandler TIM9_IRQHandler TIM10_IRQHandler TIM11_IRQHandler LCD_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler USB_FS_WKUP_IRQHandler TIM6_IRQHandler TIM7_IRQHandler STM32_HSECLK_MAX STM32_SYSCLK_MAX STM32_PLLVCO_MAX STM32_PLLVCO_MIN STM32_PCLK1_MAX STM32_PCLK2_MAX STM32_0WS_THRESHOLD STM32_HSI_AVAILABLE STM32_ACTIVATE_PLL STM32_PLLMUL STM32_PLLDIV STM32_PLLCLKIN STM32_PLLVCO STM32_PLLCLKOUT STM32_MSICLK STM32_SYSCLK STM32_HCLK STM32_PCLK1 STM32_PCLK2 STM_MCODIVCLK STM_MCOCLK STM32_HSEDIVCLK STM_RTCCLK STM32_ADCCLK STM32_USBCLK STM32_TIMCLK1 STM32_TIMCLK2 STM32_FLASHBITS1 STM32_FLASHBITS2 hal_lld_get_counter_value hal_lld_get_counter_frequency stm32_isr.h _STM32_ISR_H_ STM32_TIM2_HANDLER STM32_TIM3_HANDLER STM32_TIM4_HANDLER STM32_TIM2_NUMBER STM32_TIM3_NUMBER STM32_TIM4_NUMBER STM32_USART1_HANDLER STM32_USART2_HANDLER STM32_USART3_HANDLER STM32_USART1_NUMBER STM32_USART2_NUMBER STM32_USART3_NUMBER STM32_USB1_HP_HANDLER STM32_USB1_LP_HANDLER STM32_USB1_HP_NUMBER STM32_USB1_LP_NUMBER stm32_dma.h _STM32_DMA_H_ STM32_DMA_STREAMS STM32_DMA_ISR_MASK STM32_DMA_GETCHANNEL STM32_DMA_IS_VALID_PRIORITY STM32_DMA_STREAM_ID STM32_DMA_STREAM_ID_MSK STM32_DMA_IS_VALID_ID STM32_DMA_STREAM STM32_DMA1_STREAM1 STM32_DMA1_STREAM2 STM32_DMA1_STREAM3 STM32_DMA1_STREAM4 STM32_DMA1_STREAM5 STM32_DMA1_STREAM6 STM32_DMA1_STREAM7 STM32_DMA_CR_EN STM32_DMA_CR_TEIE STM32_DMA_CR_HTIE STM32_DMA_CR_TCIE STM32_DMA_CR_DIR_MASK STM32_DMA_CR_DIR_P2M STM32_DMA_CR_DIR_M2P STM32_DMA_CR_DIR_M2M STM32_DMA_CR_CIRC STM32_DMA_CR_PINC STM32_DMA_CR_MINC STM32_DMA_CR_PSIZE_MASK STM32_DMA_CR_PSIZE_BYTE STM32_DMA_CR_PSIZE_HWORD STM32_DMA_CR_PSIZE_WORD STM32_DMA_CR_MSIZE_MASK STM32_DMA_CR_MSIZE_BYTE STM32_DMA_CR_MSIZE_HWORD STM32_DMA_CR_MSIZE_WORD STM32_DMA_CR_SIZE_MASK STM32_DMA_CR_PL_MASK STM32_DMA_CR_PL STM32_DMA_CR_DMEIE STM32_DMA_CR_CHSEL_MASK STM32_DMA_CR_CHSEL STM32_DMA_ISR_FEIF STM32_DMA_ISR_DMEIF STM32_DMA_ISR_TEIF STM32_DMA_ISR_HTIF STM32_DMA_ISR_TCIF dmaStreamSetPeripheral dmaStreamSetMemory0 dmaStreamSetTransactionSize dmaStreamGetTransactionSize dmaStreamSetMode dmaStreamEnable dmaStreamDisable dmaStreamClearInterrupt dmaStartMemCopy dmaWaitCompletion stm32_rcc.h _STM32_RCC_ rccEnableAPB1 rccDisableAPB1 rccResetAPB1 rccEnableAPB2 rccDisableAPB2 rccResetAPB2 rccEnableAHB rccDisableAHB rccResetAHB rccEnableADC1 rccDisableADC1 rccResetADC1 rccEnableDMA1 rccDisableDMA1 rccResetDMA1 rccEnablePWRInterface rccDisablePWRInterface rccResetPWRInterface rccEnableI2C1 rccDisableI2C1 rccResetI2C1 rccEnableI2C2 rccDisableI2C2 rccResetI2C2 rccEnableSPI1 rccDisableSPI1 rccResetSPI1 rccEnableSPI2 rccDisableSPI2 rccResetSPI2 rccEnableTIM2 rccDisableTIM2 rccResetTIM2 rccEnableTIM3 rccDisableTIM3 rccResetTIM3 rccEnableTIM4 rccDisableTIM4 rccResetTIM4 rccEnableUSART1 rccDisableUSART1 rccResetUSART1 rccEnableUSART2 rccDisableUSART2 rccResetUSART2 rccEnableUSART3 rccDisableUSART3 rccResetUSART3 rccEnableUSB rccDisableUSB rccResetUSB io_channel.h _IO_CHANNEL_H_ _base_channel_methods _base_channel_data chnPutTimeout chnGetTimeout chnWrite chnWriteTimeout chnRead chnReadTimeout CHN_NO_ERROR CHN_CONNECTED CHN_DISCONNECTED CHN_INPUT_AVAILABLE CHN_OUTPUT_EMPTY CHN_TRANSMISSION_END _base_asynchronous_channel_methods _base_asynchronous_channel_data chnGetEventSource chnAddFlagsI io_block.h _IO_BLOCK_H_ _base_block_device_methods _base_block_device_data blkGetDriverState blkIsTransferring blkIsInserted blkIsWriteProtected blkConnect blkDisconnect blkRead blkWrite blkSync blkGetInfo mmcsd.h _MMCSD_H_ tm.h _TM_H_ tmStartMeasurement tmStopMeasurement pal.h _PAL_H_ PAL_MODE_RESET PAL_MODE_UNCONNECTED PAL_MODE_INPUT PAL_MODE_INPUT_PULLUP PAL_MODE_INPUT_PULLDOWN PAL_MODE_INPUT_ANALOG PAL_MODE_OUTPUT_PUSHPULL PAL_MODE_OUTPUT_OPENDRAIN PAL_LOW PAL_HIGH pal_lld.h _PAL_LLD_H_ PAL_STM32_MODE_MASK PAL_STM32_MODE_INPUT PAL_STM32_MODE_OUTPUT PAL_STM32_MODE_ALTERNATE PAL_STM32_MODE_ANALOG PAL_STM32_OTYPE_MASK PAL_STM32_OTYPE_PUSHPULL PAL_STM32_OTYPE_OPENDRAIN PAL_STM32_OSPEED_MASK PAL_STM32_OSPEED_LOWEST PAL_STM32_OSPEED_MID1 PAL_STM32_OSPEED_MID2 PAL_STM32_OSPEED_HIGHEST PAL_STM32_PUDR_MASK PAL_STM32_PUDR_FLOATING PAL_STM32_PUDR_PULLUP PAL_STM32_PUDR_PULLDOWN PAL_STM32_ALTERNATE_MASK PAL_STM32_ALTERNATE PAL_MODE_ALTERNATE PAL_IOPORTS_WIDTH PAL_WHOLE_PORT IOPORT1 IOPORT2 IOPORT3 IOPORT4 IOPORT5 IOPORT8 pal_lld_init pal_lld_readport pal_lld_readlatch pal_lld_writeport pal_lld_setport pal_lld_clearport pal_lld_writegroup pal_lld_setgroupmode pal_lld_writepad PAL_PORT_BIT PAL_GROUP_MASK _IOBUS_DATA IOBUS_DECL palInit palReadPort palReadLatch palWritePort palSetPort palClearPort palTogglePort palReadGroup palWriteGroup palSetGroupMode palReadPad palWritePad palSetPad palClearPad palTogglePad palSetPadMode adc.h _ADC_H_ adc_lld.h _ADC_LLD_H_ ADC_CR2_EXTSEL_SRC ADC_CCR_ADCPRE_DIV1 ADC_CCR_ADCPRE_DIV2 ADC_CCR_ADCPRE_DIV4 ADC_CHANNEL_IN0 ADC_CHANNEL_IN1 ADC_CHANNEL_IN2 ADC_CHANNEL_IN3 ADC_CHANNEL_IN4 ADC_CHANNEL_IN5 ADC_CHANNEL_IN6 ADC_CHANNEL_IN7 ADC_CHANNEL_IN8 ADC_CHANNEL_IN9 ADC_CHANNEL_IN10 ADC_CHANNEL_IN11 ADC_CHANNEL_IN12 ADC_CHANNEL_IN13 ADC_CHANNEL_IN14 ADC_CHANNEL_IN15 ADC_CHANNEL_SENSOR ADC_CHANNEL_VREFINT ADC_CHANNEL_IN18 ADC_CHANNEL_IN19 ADC_CHANNEL_IN20 ADC_CHANNEL_IN21 ADC_CHANNEL_IN22 ADC_CHANNEL_IN23 ADC_CHANNEL_IN24 ADC_CHANNEL_IN25 ADC_SAMPLE_4 ADC_SAMPLE_9 ADC_SAMPLE_16 ADC_SAMPLE_24 ADC_SAMPLE_48 ADC_SAMPLE_96 ADC_SAMPLE_192 ADC_SAMPLE_384 STM32_ADC_ADCPRE STM32_DMA_REQUIRED ADC_SQR1_NUM_CH ADC_SQR5_SQ1_N ADC_SQR5_SQ2_N ADC_SQR5_SQ3_N ADC_SQR5_SQ4_N ADC_SQR5_SQ5_N ADC_SQR5_SQ6_N ADC_SQR4_SQ7_N ADC_SQR4_SQ8_N ADC_SQR4_SQ9_N ADC_SQR4_SQ10_N ADC_SQR4_SQ11_N ADC_SQR4_SQ12_N ADC_SQR3_SQ13_N ADC_SQR3_SQ14_N ADC_SQR3_SQ15_N ADC_SQR3_SQ16_N ADC_SQR3_SQ17_N ADC_SQR3_SQ18_N ADC_SQR2_SQ19_N ADC_SQR2_SQ20_N ADC_SQR2_SQ21_N ADC_SQR2_SQ22_N ADC_SQR2_SQ23_N ADC_SQR2_SQ24_N ADC_SQR1_SQ25_N ADC_SQR1_SQ26_N ADC_SQR1_SQ27_N ADC_SMPR3_SMP_AN0 ADC_SMPR3_SMP_AN1 ADC_SMPR3_SMP_AN2 ADC_SMPR3_SMP_AN3 ADC_SMPR3_SMP_AN4 ADC_SMPR3_SMP_AN5 ADC_SMPR3_SMP_AN6 ADC_SMPR3_SMP_AN7 ADC_SMPR3_SMP_AN8 ADC_SMPR3_SMP_AN9 ADC_SMPR2_SMP_AN10 ADC_SMPR2_SMP_AN11 ADC_SMPR2_SMP_AN12 ADC_SMPR2_SMP_AN13 ADC_SMPR2_SMP_AN14 ADC_SMPR2_SMP_AN15 ADC_SMPR2_SMP_SENSOR ADC_SMPR2_SMP_VREF ADC_SMPR2_SMP_AN18 ADC_SMPR2_SMP_AN19 ADC_SMPR1_SMP_AN20 ADC_SMPR1_SMP_AN21 ADC_SMPR1_SMP_AN22 ADC_SMPR1_SMP_AN23 ADC_SMPR1_SMP_AN24 ADC_SMPR1_SMP_AN25 _adc_reset_i _adc_reset_s _adc_wakeup_isr _adc_timeout_isr _adc_isr_half_code _adc_isr_full_code _adc_isr_error_code can.h _CAN_H_ ext.h _EXT_H_ gpt.h _GPT_H_ i2c.h _I2C_H_ icu.h _ICU_H_ mac.h _MAC_H_ pwm.h _PWM_H_ PWM_OUTPUT_MASK PWM_OUTPUT_DISABLED PWM_OUTPUT_ACTIVE_HIGH PWM_OUTPUT_ACTIVE_LOW pwm_lld.h _PWM_LLD_H_ PWM_CHANNELS PWM_COMPLEMENTARY_OUTPUT_MASK PWM_COMPLEMENTARY_OUTPUT_DISABLED PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW STM32_PWM_USE_ADVANCED STM32_PWM_USE_TIM1 STM32_PWM_USE_TIM5 STM32_PWM_USE_TIM8 STM32_PWM_USE_TIM9 STM32_PWM_TIM1_IRQ_PRIORITY STM32_PWM_TIM5_IRQ_PRIORITY STM32_PWM_TIM8_IRQ_PRIORITY STM32_PWM_TIM9_IRQ_PRIORITY pwm_lld_change_period pwm_lld_is_channel_enabled PWM_FRACTION_TO_WIDTH PWM_DEGREES_TO_WIDTH PWM_PERCENTAGE_TO_WIDTH pwmChangePeriodI pwmEnableChannelI pwmDisableChannelI pwmIsChannelEnabledI rtc.h _RTC_H_ serial.h _SERIAL_H_ SD_PARITY_ERROR SD_FRAMING_ERROR SD_OVERRUN_ERROR SD_NOISE_ERROR SD_BREAK_DETECTED serial_lld.h _SERIAL_LLD_H_ STM32_SERIAL_USE_UART4 STM32_SERIAL_USE_UART5 STM32_SERIAL_USE_USART6 STM32_SERIAL_UART4_PRIORITY STM32_SERIAL_UART5_PRIORITY STM32_SERIAL_USART6_PRIORITY _serial_driver_data USART_CR2_STOP1_BITS USART_CR2_STOP0P5_BITS USART_CR2_STOP2_BITS USART_CR2_STOP1P5_BITS _serial_driver_methods sdPutWouldBlock sdGetWouldBlock sdPut sdPutTimeout sdGet sdGetTimeout sdWrite sdWriteTimeout sdAsynchronousWrite sdRead sdReadTimeout sdAsynchronousRead sdc.h _SDC_H_ spi.h _SPI_H_ spi_lld.h _SPI_LLD_H_ STM32_SPI_USE_SPI3 STM32_SPI_SPI3_IRQ_PRIORITY STM32_SPI_SPI3_DMA_PRIORITY STM32_SPI_SPI1_RX_DMA_STREAM STM32_SPI_SPI1_TX_DMA_STREAM STM32_SPI_SPI2_RX_DMA_STREAM STM32_SPI_SPI2_TX_DMA_STREAM STM32_SPI_SPI3_RX_DMA_STREAM STM32_SPI_SPI3_TX_DMA_STREAM spiSelectI spiUnselectI spiStartIgnoreI spiStartExchangeI spiStartSendI spiStartReceiveI spiPolledExchange _spi_wait_s _spi_wakeup_isr _spi_isr_code uart.h _UART_H_ usb.h _USB_H_ mmc_spi.h _MMC_SPI_H_ serial_usb.h _SERIAL_USB_H_ S2RTT MS2RTT US2RTT RTT2S RTT2MS RTT2US halGetCounterValue halGetCounterFrequency _Ap _VA_LIST struct _VA_LIST _Longlong long long _ULonglong unsigned long long _Wchart unsigned short _Wintt _Ptrdifft int _Sizet unsigned int __Va_list __iar_Atexit void __iar_Atexit(void (*)(void)) void (*)(void) _Wchar _State _Mbstatet struct _Mbstatet _Off _Wstate _Fpost struct _Fpost __iar_dlib_perthread_initialize void __iar_dlib_perthread_initialize(void *) void * __iar_dlib_perthread_allocate void * __iar_dlib_perthread_allocate(void) __iar_dlib_perthread_destroy void __iar_dlib_perthread_destroy(void) __iar_dlib_perthread_deallocate void __iar_dlib_perthread_deallocate(void *) __iar_dlib_perthread_access void * __iar_dlib_perthread_access(void *) __iar_Rmtx __iar_system_Mtxinit void __iar_system_Mtxinit(__iar_Rmtx *) m __iar_Rmtx * __iar_system_Mtxdst void __iar_system_Mtxdst(__iar_Rmtx *) __iar_system_Mtxlock void __iar_system_Mtxlock(__iar_Rmtx *) __iar_system_Mtxunlock void __iar_system_Mtxunlock(__iar_Rmtx *) __iar_file_Mtxinit void __iar_file_Mtxinit(__iar_Rmtx *) __iar_file_Mtxdst void __iar_file_Mtxdst(__iar_Rmtx *) __iar_file_Mtxlock void __iar_file_Mtxlock(__iar_Rmtx *) __iar_file_Mtxunlock void __iar_file_Mtxunlock(__iar_Rmtx *) __iar_clearlocks void __iar_clearlocks(void) _Once_t __iar_Locksyslock_Locale void __iar_Locksyslock_Locale(void) __iar_Locksyslock_Malloc void __iar_Locksyslock_Malloc(void) __iar_Locksyslock_Stream void __iar_Locksyslock_Stream(void) __iar_Locksyslock_Debug void __iar_Locksyslock_Debug(void) __iar_Locksyslock_StaticGuard void __iar_Locksyslock_StaticGuard(void) __iar_Locksyslock void __iar_Locksyslock(unsigned int) __iar_Unlocksyslock_Locale void __iar_Unlocksyslock_Locale(void) __iar_Unlocksyslock_Malloc void __iar_Unlocksyslock_Malloc(void) __iar_Unlocksyslock_Stream void __iar_Unlocksyslock_Stream(void) __iar_Unlocksyslock_Debug void __iar_Unlocksyslock_Debug(void) __iar_Unlocksyslock_StaticGuard void __iar_Unlocksyslock_StaticGuard(void) __iar_Unlocksyslock void __iar_Unlocksyslock(unsigned int) __iar_Initdynamicfilelock void __iar_Initdynamicfilelock(__iar_Rmtx *) __iar_Dstdynamicfilelock void __iar_Dstdynamicfilelock(__iar_Rmtx *) __iar_Lockdynamicfilelock void __iar_Lockdynamicfilelock(__iar_Rmtx *) __iar_Unlockdynamicfilelock void __iar_Unlockdynamicfilelock(__iar_Rmtx *) size_t __data_size_t ptrdiff_t wchar_t int8_t signed char uint8_t unsigned char int16_t short uint16_t int32_t uint32_t int64_t uint64_t int_least8_t uint_least8_t int_least16_t uint_least16_t int_least32_t uint_least32_t int_least64_t uint_least64_t int_fast8_t uint_fast8_t int_fast16_t uint_fast16_t int_fast32_t uint_fast32_t int_fast64_t uint_fast64_t intmax_t uintmax_t intptr_t long uintptr_t unsigned long __data_intptr_t __data_uintptr_t bool_t tmode_t tstate_t trefs_t tslices_t tprio_t msg_t eventid_t eventmask_t flagsmask_t systime_t cnt_t Thread struct Thread p_next p_prev ThreadsQueue struct ThreadsQueue ThreadsList struct ThreadsList regarm_t stkalign_t extctx r0 r1 r2 r3 r12 lr_thd pc xpsr intctx r4 r5 r6 r7 r8 r9 r10 r11 lr context r13 struct intctx port_halt void port_halt(void) _port_init void _port_init(void) _port_irq_epilogue void _port_irq_epilogue(void) _port_switch_from_isr void _port_switch_from_isr(void) _port_exit_from_isr void _port_exit_from_isr(void) _port_switch void _port_switch(Thread *, Thread *) ntp Thread * otp _port_thread_start void _port_thread_start(void) __no_operation void __no_operation(void) __disable_interrupt void __disable_interrupt(void) __enable_interrupt void __enable_interrupt(void) __istate_t __get_interrupt_state __istate_t __get_interrupt_state(void) __set_interrupt_state void __set_interrupt_state(__istate_t) __get_PSR unsigned long __get_PSR(void) __get_IPSR unsigned long __get_IPSR(void) __get_MSP unsigned long __get_MSP(void) __set_MSP void __set_MSP(unsigned long) __get_PSP unsigned long __get_PSP(void) __set_PSP void __set_PSP(unsigned long) __get_PRIMASK unsigned long __get_PRIMASK(void) __set_PRIMASK void __set_PRIMASK(unsigned long) __get_CONTROL unsigned long __get_CONTROL(void) __set_CONTROL void __set_CONTROL(unsigned long) __get_FAULTMASK unsigned long __get_FAULTMASK(void) __set_FAULTMASK void __set_FAULTMASK(unsigned long) __get_BASEPRI unsigned long __get_BASEPRI(void) __set_BASEPRI void __set_BASEPRI(unsigned long) __disable_fiq void __disable_fiq(void) __enable_fiq void __enable_fiq(void) __SWP unsigned long __SWP(unsigned long, unsigned long *) unsigned long * __SWPB unsigned char __SWPB(unsigned char, unsigned char *) unsigned char * __ul __MCR void __MCR(unsigned int, unsigned int, __ul, unsigned int, unsigned int, unsigned int) coproc opcode_1 src CRn CRm opcode_2 __MRC unsigned long __MRC(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) __MCR2 void __MCR2(unsigned int, unsigned int, __ul, unsigned int, unsigned int, unsigned int) __MRC2 unsigned long __MRC2(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) __LDC void __LDC(unsigned int, unsigned int, const __ul *) const __ul * __LDCL void __LDCL(unsigned int, unsigned int, const __ul *) __LDC2 void __LDC2(unsigned int, unsigned int, const __ul *) __LDC2L void __LDC2L(unsigned int, unsigned int, const __ul *) __STC void __STC(unsigned int, unsigned int, __ul *) dst __ul * __STCL void __STCL(unsigned int, unsigned int, __ul *) __STC2 void __STC2(unsigned int, unsigned int, __ul *) __STC2L void __STC2L(unsigned int, unsigned int, __ul *) __LDC_noidx void __LDC_noidx(unsigned int, unsigned int, const __ul *, unsigned int) option __LDCL_noidx void __LDCL_noidx(unsigned int, unsigned int, const __ul *, unsigned int) __LDC2_noidx void __LDC2_noidx(unsigned int, unsigned int, const __ul *, unsigned int) __LDC2L_noidx void __LDC2L_noidx(unsigned int, unsigned int, const __ul *, unsigned int) __STC_noidx void __STC_noidx(unsigned int, unsigned int, __ul *, unsigned int) __STCL_noidx void __STCL_noidx(unsigned int, unsigned int, __ul *, unsigned int) __STC2_noidx void __STC2_noidx(unsigned int, unsigned int, __ul *, unsigned int) __STC2L_noidx void __STC2L_noidx(unsigned int, unsigned int, __ul *, unsigned int) __get_APSR unsigned long __get_APSR(void) __set_APSR void __set_APSR(unsigned long) __get_FPSCR unsigned long __get_FPSCR(void) __set_FPSCR void __set_FPSCR(unsigned long) __CLZ unsigned char __CLZ(unsigned long) __QCFlag int __QCFlag(void) __reset_QC_flag void __reset_QC_flag(void) __SMUL long __SMUL(short, short) __REV unsigned long __REV(unsigned long) __REVSH long __REVSH(short) __REV16 unsigned long __REV16(unsigned long) __RBIT unsigned long __RBIT(unsigned long) __LDREXB unsigned char __LDREXB(unsigned char *) __LDREXH unsigned short __LDREXH(unsigned short *) unsigned short * __LDREX unsigned long __LDREX(unsigned long *) __LDREXD unsigned long long __LDREXD(unsigned long long *) unsigned long long * __STREXB unsigned long __STREXB(unsigned char, unsigned char *) __STREXH unsigned long __STREXH(unsigned short, unsigned short *) __STREX unsigned long __STREX(unsigned long, unsigned long *) __STREXD unsigned long __STREXD(unsigned long long, unsigned long long *) __CLREX void __CLREX(void) __SEV void __SEV(void) __WFE void __WFE(void) __WFI void __WFI(void) __YIELD void __YIELD(void) __PLI void __PLI(const void *) const void * __PLD void __PLD(const void *) __PLDW void __PLDW(const void *) __SSAT unsigned long __SSAT(unsigned long, unsigned int) val sat __USAT unsigned long __USAT(unsigned long, unsigned int) __DMB void __DMB(void) __DSB void __DSB(void) __ISB void __ISB(void) IOREG8 volatile uint8_t IOREG32 volatile uint32_t CSR RVR CVR CBVR CMx_ST struct CMx_ST ISER unused1 ICER unused2 ISPR unused3 ICPR unused4 IABR unused5 IPR unused6 STIR CMx_NVIC struct CMx_NVIC CPUID ICSR VTOR AIRCR SCR CCR SHPR SHCSR CFSR HFSR DFSR MMFAR BFAR AFSR PFR DFR ADR MMFR SAR CPACR CMx_SCB struct CMx_SCB FPCCR FPCAR FPDSCR MVFR0 MVFR1 CMx_FPU struct CMx_FPU DHCSR DCRSR DCRDR DEMCR CMx_SCS struct CMx_SCS CTRL CYCCNT CPICNT EXCCNT SLEEPCNT LSUCNT FOLDCNT PCSR CMx_DWT struct CMx_DWT nvicEnableVector void nvicEnableVector(uint32_t, uint32_t) n prio nvicDisableVector void nvicDisableVector(uint32_t) nvicSetSystemHandlerPriority void nvicSetSystemHandlerPriority(uint32_t, uint32_t) handler chSysInit void chSysInit(void) chSysTimerHandlerI void chSysTimerHandlerI(void) vtfunc_t void (*)(void *) VirtualTimer struct VirtualTimer vt_next vt_prev vt_time vt_func vt_par vt_systime VTList struct VTList vtlist _vt_init void _vt_init(void) chVTSetI void chVTSetI(VirtualTimer *, systime_t, vtfunc_t, void *) vtp VirtualTimer * time vtfunc par chVTResetI void chVTResetI(VirtualTimer *) chTimeIsWithin bool_t chTimeIsWithin(systime_t, systime_t) start end r_queue r_prio r_ctx struct context r_newer r_older r_current ReadyList struct ReadyList rlist _scheduler_init void _scheduler_init(void) chSchReadyI Thread * chSchReadyI(Thread *) tp chSchGoSleepS void chSchGoSleepS(tstate_t) newstate chSchGoSleepTimeoutS msg_t chSchGoSleepTimeoutS(tstate_t, systime_t) chSchWakeupS void chSchWakeupS(Thread *, msg_t) msg chSchRescheduleS void chSchRescheduleS(void) chSchDoRescheduleBehind void chSchDoRescheduleBehind(void) chSchDoRescheduleAhead void chSchDoRescheduleAhead(void) chSchDoReschedule void chSchDoReschedule(void) Semaphore s_queue s_cnt struct Semaphore chSemInit void chSemInit(Semaphore *, cnt_t) sp Semaphore * chSemReset void chSemReset(Semaphore *, cnt_t) chSemResetI void chSemResetI(Semaphore *, cnt_t) chSemWait msg_t chSemWait(Semaphore *) chSemWaitS msg_t chSemWaitS(Semaphore *) chSemWaitTimeout msg_t chSemWaitTimeout(Semaphore *, systime_t) chSemWaitTimeoutS msg_t chSemWaitTimeoutS(Semaphore *, systime_t) chSemSignal void chSemSignal(Semaphore *) chSemSignalI void chSemSignalI(Semaphore *) chSemAddCounterI void chSemAddCounterI(Semaphore *, cnt_t) chSemSignalWait msg_t chSemSignalWait(Semaphore *, Semaphore *) sps spw bs_sem BinarySemaphore struct BinarySemaphore Mutex m_queue m_owner m_next struct Mutex chMtxInit void chMtxInit(Mutex *) mp Mutex * chMtxLock void chMtxLock(Mutex *) chMtxLockS void chMtxLockS(Mutex *) chMtxTryLock bool_t chMtxTryLock(Mutex *) chMtxTryLockS bool_t chMtxTryLockS(Mutex *) chMtxUnlock Mutex * chMtxUnlock(void) chMtxUnlockS Mutex * chMtxUnlockS(void) chMtxUnlockAll void chMtxUnlockAll(void) CondVar c_queue struct CondVar chCondInit void chCondInit(CondVar *) cp CondVar * chCondSignal void chCondSignal(CondVar *) chCondSignalI void chCondSignalI(CondVar *) chCondBroadcast void chCondBroadcast(CondVar *) chCondBroadcastI void chCondBroadcastI(CondVar *) chCondWait msg_t chCondWait(CondVar *) chCondWaitS msg_t chCondWaitS(CondVar *) chCondWaitTimeout msg_t chCondWaitTimeout(CondVar *, systime_t) chCondWaitTimeoutS msg_t chCondWaitTimeoutS(CondVar *, systime_t) EventListener struct EventListener el_next el_listener el_mask el_flags EventSource es_next struct EventSource evhandler_t void (*)(eventid_t) chEvtRegisterMask void chEvtRegisterMask(EventSource *, EventListener *, eventmask_t) esp EventSource * elp EventListener * mask chEvtUnregister void chEvtUnregister(EventSource *, EventListener *) chEvtGetAndClearEvents eventmask_t chEvtGetAndClearEvents(eventmask_t) chEvtAddEvents eventmask_t chEvtAddEvents(eventmask_t) chEvtGetAndClearFlags flagsmask_t chEvtGetAndClearFlags(EventListener *) chEvtGetAndClearFlagsI flagsmask_t chEvtGetAndClearFlagsI(EventListener *) chEvtSignal void chEvtSignal(Thread *, eventmask_t) chEvtSignalI void chEvtSignalI(Thread *, eventmask_t) chEvtBroadcastFlags void chEvtBroadcastFlags(EventSource *, flagsmask_t) flags chEvtBroadcastFlagsI void chEvtBroadcastFlagsI(EventSource *, flagsmask_t) chEvtDispatch void chEvtDispatch(const evhandler_t *, eventmask_t) handlers const evhandler_t * chEvtWaitOne eventmask_t chEvtWaitOne(eventmask_t) chEvtWaitAny eventmask_t chEvtWaitAny(eventmask_t) chEvtWaitAll eventmask_t chEvtWaitAll(eventmask_t) chEvtWaitOneTimeout eventmask_t chEvtWaitOneTimeout(eventmask_t, systime_t) chEvtWaitAnyTimeout eventmask_t chEvtWaitAnyTimeout(eventmask_t, systime_t) chEvtWaitAllTimeout eventmask_t chEvtWaitAllTimeout(eventmask_t, systime_t) chMsgSend msg_t chMsgSend(Thread *, msg_t) chMsgWait Thread * chMsgWait(void) chMsgRelease void chMsgRelease(Thread *, msg_t) mb_buffer mb_top mb_wrptr mb_rdptr mb_fullsem mb_emptysem Mailbox struct Mailbox chMBInit void chMBInit(Mailbox *, msg_t *, cnt_t) mbp Mailbox * buf msg_t * chMBReset void chMBReset(Mailbox *) chMBPost msg_t chMBPost(Mailbox *, msg_t, systime_t) timeout chMBPostS msg_t chMBPostS(Mailbox *, msg_t, systime_t) chMBPostI msg_t chMBPostI(Mailbox *, msg_t) chMBPostAhead msg_t chMBPostAhead(Mailbox *, msg_t, systime_t) chMBPostAheadS msg_t chMBPostAheadS(Mailbox *, msg_t, systime_t) chMBPostAheadI msg_t chMBPostAheadI(Mailbox *, msg_t) chMBFetch msg_t chMBFetch(Mailbox *, msg_t *, systime_t) msgp chMBFetchS msg_t chMBFetchS(Mailbox *, msg_t *, systime_t) chMBFetchI msg_t chMBFetchI(Mailbox *, msg_t *) memgetfunc_t void *(*)(size_t) size _core_init void _core_init(void) chCoreAlloc void * chCoreAlloc(size_t) chCoreAllocI void * chCoreAllocI(size_t) chCoreStatus size_t chCoreStatus(void) memory_heap MemoryHeap struct memory_heap heap_header align next union heap_header heap u h h_provider h_free h_mtx _heap_init void _heap_init(void) chHeapInit void chHeapInit(MemoryHeap *, void *, size_t) heapp MemoryHeap * chHeapAlloc void * chHeapAlloc(MemoryHeap *, size_t) chHeapFree void chHeapFree(void *) p chHeapStatus size_t chHeapStatus(MemoryHeap *, size_t *) sizep size_t * pool_header ph_next struct pool_header mp_next mp_object_size mp_provider MemoryPool struct MemoryPool chPoolInit void chPoolInit(MemoryPool *, size_t, memgetfunc_t) MemoryPool * provider chPoolLoadArray void chPoolLoadArray(MemoryPool *, void *, size_t) chPoolAllocI void * chPoolAllocI(MemoryPool *) chPoolAlloc void * chPoolAlloc(MemoryPool *) chPoolFreeI void chPoolFreeI(MemoryPool *, void *) objp chPoolFree void chPoolFree(MemoryPool *, void *) p_prio p_ctx p_newer p_older p_name p_state p_flags p_refs p_preempt p_time rdymsg exitcode wtobjp ewmask p_u p_waiting p_msgqueue p_msg p_epending p_mtxlist p_realprio p_mpool tfunc_t msg_t (*)(void *) _thread_init Thread * _thread_init(Thread *, tprio_t) chThdCreateI Thread * chThdCreateI(void *, size_t, tprio_t, tfunc_t, void *) wsp pf arg chThdCreateStatic Thread * chThdCreateStatic(void *, size_t, tprio_t, tfunc_t, void *) chThdSetPriority tprio_t chThdSetPriority(tprio_t) newprio chThdResume Thread * chThdResume(Thread *) chThdTerminate void chThdTerminate(Thread *) chThdSleep void chThdSleep(systime_t) chThdSleepUntil void chThdSleepUntil(systime_t) chThdYield void chThdYield(void) chThdExit void chThdExit(msg_t) chThdExitS void chThdExitS(msg_t) chThdWait msg_t chThdWait(Thread *) chThdAddRef Thread * chThdAddRef(Thread *) chThdRelease void chThdRelease(Thread *) chThdCreateFromHeap Thread * chThdCreateFromHeap(MemoryHeap *, size_t, tprio_t, tfunc_t, void *) chThdCreateFromMemoryPool Thread * chThdCreateFromMemoryPool(MemoryPool *, tprio_t, tfunc_t, void *) ch_identifier ch_zero ch_size ch_version ch_ptrsize ch_timesize ch_threadsize cf_off_prio cf_off_ctx cf_off_newer cf_off_older cf_off_name cf_off_stklimit cf_off_state cf_off_flags cf_off_refs cf_off_preempt cf_off_time chdebug_t struct chdebug_t ch_debug chRegFirstThread Thread * chRegFirstThread(void) chRegNextThread Thread * chRegNextThread(Thread *) prio_insert void prio_insert(Thread *, ThreadsQueue *) tqp ThreadsQueue * queue_insert void queue_insert(Thread *, ThreadsQueue *) fifo_remove Thread * fifo_remove(ThreadsQueue *) lifo_remove Thread * lifo_remove(ThreadsQueue *) dequeue Thread * dequeue(Thread *) list_insert void list_insert(Thread *, ThreadsList *) tlp ThreadsList * list_remove Thread * list_remove(ThreadsList *) GenericQueue struct GenericQueue qnotify_t void (*)(GenericQueue *) qp GenericQueue * q_waiting q_counter q_buffer q_top q_wrptr q_rdptr q_notify q_link InputQueue OutputQueue chIQInit void chIQInit(InputQueue *, uint8_t *, size_t, qnotify_t, void *) iqp InputQueue * bp uint8_t * infy link chIQResetI void chIQResetI(InputQueue *) chIQPutI msg_t chIQPutI(InputQueue *, uint8_t) b chIQGetTimeout msg_t chIQGetTimeout(InputQueue *, systime_t) chIQReadTimeout size_t chIQReadTimeout(InputQueue *, uint8_t *, size_t, systime_t) chOQInit void chOQInit(OutputQueue *, uint8_t *, size_t, qnotify_t, void *) oqp OutputQueue * onfy chOQResetI void chOQResetI(OutputQueue *) chOQPutTimeout msg_t chOQPutTimeout(OutputQueue *, uint8_t, systime_t) chOQGetI msg_t chOQGetI(OutputQueue *) chOQWriteTimeout size_t chOQWriteTimeout(OutputQueue *, const uint8_t *, size_t, systime_t) const uint8_t * BaseSequentialStreamVMT write instance read put get vmt struct BaseSequentialStreamVMT BaseSequentialStream struct BaseSequentialStream fileoffset_t BaseFileStreamVMT close geterror getsize getposition lseek offset struct BaseFileStreamVMT BaseFileStream struct BaseFileStream _idle_thread_wa struct extctx _idle_thread void _idle_thread(void *) boardInit void boardInit(void) IRQn NonMaskableInt_IRQn MemoryManagement_IRQn BusFault_IRQn UsageFault_IRQn SVC_IRQn DebugMonitor_IRQn PendSV_IRQn SysTick_IRQn WWDG_IRQn PVD_IRQn TAMPER_STAMP_IRQn RTC_WKUP_IRQn FLASH_IRQn RCC_IRQn EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQn DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn DMA1_Channel4_IRQn DMA1_Channel5_IRQn DMA1_Channel6_IRQn DMA1_Channel7_IRQn ADC1_IRQn USB_HP_IRQn USB_LP_IRQn DAC_IRQn COMP_IRQn EXTI9_5_IRQn LCD_IRQn TIM9_IRQn TIM10_IRQn TIM11_IRQn TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQn I2C1_ER_IRQn I2C2_EV_IRQn I2C2_ER_IRQn SPI1_IRQn SPI2_IRQn USART1_IRQn USART2_IRQn USART3_IRQn EXTI15_10_IRQn RTC_Alarm_IRQn USB_FS_WKUP_IRQn TIM6_IRQn TIM7_IRQn IRQn_Type enum IRQn __get_xPSR uint32_t __get_xPSR(void) __ROR uint32_t __ROR(uint32_t, uint32_t) op1 op2 _reserved0 Q V C Z N w APSR_Type union APSR_Type ISR IPSR_Type union IPSR_Type T IT xPSR_Type union xPSR_Type nPRIV SPSEL FPCA CONTROL_Type union CONTROL_Type RESERVED0 RSERVED1 RESERVED2 RESERVED3 RESERVED4 IP RESERVED5 NVIC_Type struct NVIC_Type SHP ISAR SCB_Type struct SCB_Type ICTR ACTLR SCnSCB_Type struct SCnSCB_Type LOAD VAL CALIB SysTick_Type struct SysTick_Type u8 u16 u32 PORT TER RESERVED1 TPR TCR IWR IRR IMCR LAR LSR PID4 PID5 PID6 PID7 PID0 PID1 PID2 PID3 CID0 CID1 CID2 CID3 ITM_Type struct ITM_Type COMP0 MASK0 FUNCTION0 COMP1 MASK1 FUNCTION1 COMP2 MASK2 FUNCTION2 COMP3 MASK3 FUNCTION3 DWT_Type struct DWT_Type SSPSR CSPSR ACPR SPPR FFSR FFCR FSCR TRIGGER FIFO0 ITATBCTR2 ITATBCTR0 FIFO1 ITCTRL CLAIMSET CLAIMCLR RESERVED7 DEVID DEVTYPE TPI_Type struct TPI_Type TYPE RNR RBAR RASR RBAR_A1 RASR_A1 RBAR_A2 RASR_A2 RBAR_A3 RASR_A3 MPU_Type struct MPU_Type CoreDebug_Type struct CoreDebug_Type NVIC_SetPriorityGrouping void NVIC_SetPriorityGrouping(uint32_t) PriorityGroup reg_value PriorityGroupTmp NVIC_GetPriorityGrouping uint32_t NVIC_GetPriorityGrouping(void) NVIC_EnableIRQ void NVIC_EnableIRQ(IRQn_Type) NVIC_DisableIRQ void NVIC_DisableIRQ(IRQn_Type) NVIC_GetPendingIRQ uint32_t NVIC_GetPendingIRQ(IRQn_Type) NVIC_SetPendingIRQ void NVIC_SetPendingIRQ(IRQn_Type) NVIC_ClearPendingIRQ void NVIC_ClearPendingIRQ(IRQn_Type) NVIC_GetActive uint32_t NVIC_GetActive(IRQn_Type) NVIC_SetPriority void NVIC_SetPriority(IRQn_Type, uint32_t) priority NVIC_GetPriority uint32_t NVIC_GetPriority(IRQn_Type) NVIC_EncodePriority uint32_t NVIC_EncodePriority(uint32_t, uint32_t, uint32_t) PreemptPriority SubPriority PreemptPriorityBits SubPriorityBits NVIC_DecodePriority void NVIC_DecodePriority(uint32_t, uint32_t, uint32_t *, uint32_t *) Priority pPreemptPriority uint32_t * pSubPriority NVIC_SystemReset void NVIC_SystemReset(void) SysTick_Config uint32_t SysTick_Config(uint32_t) ticks ITM_RxBuffer ITM_SendChar uint32_t ITM_SendChar(uint32_t) ch ITM_ReceiveChar int32_t ITM_ReceiveChar(void) ITM_CheckChar int32_t ITM_CheckChar(void) RESET SET FlagStatus enum FlagStatus ITStatus DISABLE ENABLE FunctionalState enum FunctionalState ERROR SUCCESS ErrorStatus enum ErrorStatus SR CR1 CR2 SMPR1 SMPR2 SMPR3 JOFR1 JOFR2 JOFR3 JOFR4 HTR LTR SQR1 SQR2 SQR3 SQR4 SQR5 JSQR JDR1 JDR2 JDR3 JDR4 DR SMPR0 ADC_TypeDef struct ADC_TypeDef ADC_Common_TypeDef struct ADC_Common_TypeDef CR DINR DOUTR KEYR0 KEYR1 KEYR2 KEYR3 IVR0 IVR1 IVR2 IVR3 AES_TypeDef struct AES_TypeDef COMP_TypeDef struct COMP_TypeDef IDR CRC_TypeDef struct CRC_TypeDef SWTRIGR DHR12R1 DHR12L1 DHR8R1 DHR12R2 DHR12L2 DHR8R2 DHR12RD DHR12LD DHR8RD DOR1 DOR2 DAC_TypeDef struct DAC_TypeDef IDCODE APB1FZ APB2FZ DBGMCU_TypeDef struct DBGMCU_TypeDef CNDTR CPAR CMAR DMA_Channel_TypeDef struct DMA_Channel_TypeDef IFCR DMA_TypeDef struct DMA_TypeDef IMR EMR RTSR FTSR SWIER PR EXTI_TypeDef struct EXTI_TypeDef ACR PECR PDKEYR PEKEYR PRGKEYR OPTKEYR OBR WRPR RESERVED WRPR1 WRPR2 FLASH_TypeDef struct FLASH_TypeDef RDP USER WRP01 WRP23 WRP45 WRP67 WRP89 WRP1011 OB_TypeDef struct OB_TypeDef OTR LPOTR OPAMP_TypeDef struct OPAMP_TypeDef BTCR FSMC_Bank1_TypeDef struct FSMC_Bank1_TypeDef BWTR FSMC_Bank1E_TypeDef struct FSMC_Bank1E_TypeDef MEMRMP PMC EXTICR SYSCFG_TypeDef struct SYSCFG_TypeDef OAR1 OAR2 SR1 SR2 RESERVED6 TRISE RESERVED8 I2C_TypeDef struct I2C_TypeDef KR RLR IWDG_TypeDef struct IWDG_TypeDef FCR CLR RAM LCD_TypeDef struct LCD_TypeDef PWR_TypeDef struct PWR_TypeDef ICSCR CFGR CIR AHBRSTR APB2RSTR APB1RSTR AHBENR APB2ENR APB1ENR AHBLPENR APB2LPENR APB1LPENR RCC_TypeDef struct RCC_TypeDef ICR ASCR1 ASCR2 HYSCR1 HYSCR2 HYSCR3 HYSCR4 RI_TypeDef struct RI_TypeDef TR PRER WUTR CALIBR ALRMAR ALRMBR WPR SSR SHIFTR TSTR TSDR TSSSR CALR TAFCR ALRMASSR ALRMBSSR BKP0R BKP1R BKP2R BKP3R BKP4R BKP5R BKP6R BKP7R BKP8R BKP9R BKP10R BKP11R BKP12R BKP13R BKP14R BKP15R BKP16R BKP17R BKP18R BKP19R BKP20R BKP21R BKP22R BKP23R BKP24R BKP25R BKP26R BKP27R BKP28R BKP29R BKP30R BKP31R RTC_TypeDef struct RTC_TypeDef POWER CLKCR ARG CMD RESPCMD RESP1 RESP2 RESP3 RESP4 DTIMER DLEN DCTRL DCOUNT STA MASK FIFOCNT FIFO SDIO_TypeDef struct SDIO_TypeDef CRCPR RXCRCR TXCRCR I2SCFGR I2SPR SPI_TypeDef struct SPI_TypeDef SMCR DIER EGR CCMR1 CCMR2 CCER CNT PSC RESERVED10 ARR RESERVED12 CCR1 CCR2 CCR3 CCR4 RESERVED17 DCR RESERVED18 DMAR RESERVED19 OR RESERVED20 TIM_TypeDef struct TIM_TypeDef BRR CR3 GTPR USART_TypeDef struct USART_TypeDef CFR WWDG_TypeDef struct WWDG_TypeDef _resvd0 _resvd1 _resvd2 _resvd3 _resvd4 _resvd5 _resvd6 _resvd7 _resvd8 _resvd9 RCR _resvd10 BDTR _resvd11 _resvd12 _resvd13 _resvd14 stm32_tim_t struct stm32_tim_t halclock_t halrtcnt_t channel ifcr ishift selfindex vector stm32_dma_stream_t struct stm32_dma_stream_t stm32_dmaisr_t void (*)(void *, uint32_t) _stm32_dma_streams dmaInit void dmaInit(void) dmaStreamAllocate bool_t dmaStreamAllocate(const stm32_dma_stream_t *, uint32_t, stm32_dmaisr_t, void *) dmastp const stm32_dma_stream_t * func param dmaStreamRelease void dmaStreamRelease(const stm32_dma_stream_t *) hal_lld_init void hal_lld_init(void) stm32_clock_init void stm32_clock_init(void) BaseChannelVMT putt gett writet readt struct BaseChannelVMT BaseChannel struct BaseChannel BaseAsynchronousChannelVMT struct BaseAsynchronousChannelVMT event BaseAsynchronousChannel struct BaseAsynchronousChannel BLK_UNINIT BLK_STOP BLK_ACTIVE BLK_CONNECTING BLK_DISCONNECTING BLK_READY BLK_READING BLK_WRITING BLK_SYNCING blkstate_t enum blkstate_t blk_size blk_num BlockDeviceInfo struct BlockDeviceInfo BaseBlockDeviceVMT is_inserted is_protected connect disconnect startblk buffer sync get_info bdip BlockDeviceInfo * struct BaseBlockDeviceVMT state BaseBlockDevice struct BaseBlockDevice TimeMeasurement struct TimeMeasurement tmp TimeMeasurement * stop last worst best tmInit void tmInit(void) tmObjectInit void tmObjectInit(TimeMeasurement *) MODER OTYPER OSPEEDR PUPDR ODR W set clear H BSRR LCKR AFRL AFRH GPIO_TypeDef struct GPIO_TypeDef moder otyper ospeedr pupdr odr afrl afrh stm32_gpio_setup_t struct stm32_gpio_setup_t PAData PBData PCData PDData PEData PHData PALConfig struct PALConfig ioportmask_t iomode_t ioportid_t GPIO_TypeDef * pal_default_config _pal_lld_init void _pal_lld_init(const PALConfig *) config const PALConfig * _pal_lld_setgroupmode void _pal_lld_setgroupmode(ioportid_t, ioportmask_t, iomode_t) port mode portid IOBus struct IOBus palReadBus ioportmask_t palReadBus(IOBus *) bus IOBus * palWriteBus void palWriteBus(IOBus *, ioportmask_t) bits palSetBusMode void palSetBusMode(IOBus *, iomode_t) ADC_UNINIT ADC_STOP ADC_READY ADC_ACTIVE ADC_COMPLETE ADC_ERROR adcstate_t enum adcstate_t adcsample_t adc_channels_num_t ADC_ERR_DMAFAILURE ADC_ERR_OVERFLOW adcerror_t enum adcerror_t ADCDriver struct ADCDriver adccallback_t void (*)(ADCDriver *, adcsample_t *, size_t) adcp ADCDriver * adcsample_t * adcerrorcallback_t void (*)(ADCDriver *, adcerror_t) err circular num_channels end_cb error_cb cr1 cr2 smpr1 smpr2 smpr3 sqr1 sqr2 sqr3 sqr4 sqr5 ADCConversionGroup struct ADCConversionGroup dummy ADCConfig struct ADCConfig samples depth grpp thread mutex adc dmamode ADCD1 adc_lld_init void adc_lld_init(void) adc_lld_start void adc_lld_start(ADCDriver *) adc_lld_stop void adc_lld_stop(ADCDriver *) adc_lld_start_conversion void adc_lld_start_conversion(ADCDriver *) adc_lld_stop_conversion void adc_lld_stop_conversion(ADCDriver *) adcSTM32EnableTSVREFE void adcSTM32EnableTSVREFE(void) adcSTM32DisableTSVREFE void adcSTM32DisableTSVREFE(void) adcInit void adcInit(void) adcObjectInit void adcObjectInit(ADCDriver *) adcStart void adcStart(ADCDriver *, const ADCConfig *) const ADCConfig * adcStop void adcStop(ADCDriver *) adcStartConversion void adcStartConversion(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t) const ADCConversionGroup * adcStartConversionI void adcStartConversionI(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t) adcStopConversion void adcStopConversion(ADCDriver *) adcStopConversionI void adcStopConversionI(ADCDriver *) adcConvert msg_t adcConvert(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t) adcAcquireBus void adcAcquireBus(ADCDriver *) adcReleaseBus void adcReleaseBus(ADCDriver *) PWM_UNINIT PWM_STOP PWM_READY pwmstate_t enum pwmstate_t PWMDriver struct PWMDriver pwmcallback_t void (*)(PWMDriver *) pwmp PWMDriver * pwmmode_t pwmchannel_t pwmcnt_t callback PWMChannelConfig struct PWMChannelConfig frequency period channels PWMConfig struct PWMConfig clock tim PWMD4 pwm_lld_init void pwm_lld_init(void) pwm_lld_start void pwm_lld_start(PWMDriver *) pwm_lld_stop void pwm_lld_stop(PWMDriver *) pwm_lld_enable_channel void pwm_lld_enable_channel(PWMDriver *, pwmchannel_t, pwmcnt_t) width pwm_lld_disable_channel void pwm_lld_disable_channel(PWMDriver *, pwmchannel_t) pwmInit void pwmInit(void) pwmObjectInit void pwmObjectInit(PWMDriver *) pwmStart void pwmStart(PWMDriver *, const PWMConfig *) const PWMConfig * pwmStop void pwmStop(PWMDriver *) pwmChangePeriod void pwmChangePeriod(PWMDriver *, pwmcnt_t) pwmEnableChannel void pwmEnableChannel(PWMDriver *, pwmchannel_t, pwmcnt_t) pwmDisableChannel void pwmDisableChannel(PWMDriver *, pwmchannel_t) SD_UNINIT SD_STOP SD_READY sdstate_t enum sdstate_t SerialDriver struct SerialDriver sc_speed sc_cr1 sc_cr2 sc_cr3 SerialConfig struct SerialConfig SD1 SD2 sd_lld_init void sd_lld_init(void) sd_lld_start void sd_lld_start(SerialDriver *, const SerialConfig *) sdp SerialDriver * const SerialConfig * sd_lld_stop void sd_lld_stop(SerialDriver *) SerialDriverVMT struct SerialDriverVMT iqueue oqueue ib ob usart sdInit void sdInit(void) sdObjectInit void sdObjectInit(SerialDriver *, qnotify_t, qnotify_t) inotify onotify sdStart void sdStart(SerialDriver *, const SerialConfig *) sdStop void sdStop(SerialDriver *) sdIncomingDataI void sdIncomingDataI(SerialDriver *, uint8_t) sdRequestDataI msg_t sdRequestDataI(SerialDriver *) SPI_UNINIT SPI_STOP SPI_READY SPI_ACTIVE SPI_COMPLETE spistate_t enum spistate_t SPIDriver struct SPIDriver spicallback_t void (*)(SPIDriver *) spip SPIDriver * ssport sspad SPIConfig struct SPIConfig spi dmarx dmatx rxdmamode txdmamode SPID2 spi_lld_init void spi_lld_init(void) spi_lld_start void spi_lld_start(SPIDriver *) spi_lld_stop void spi_lld_stop(SPIDriver *) spi_lld_select void spi_lld_select(SPIDriver *) spi_lld_unselect void spi_lld_unselect(SPIDriver *) spi_lld_ignore void spi_lld_ignore(SPIDriver *, size_t) spi_lld_exchange void spi_lld_exchange(SPIDriver *, size_t, const void *, void *) txbuf rxbuf spi_lld_send void spi_lld_send(SPIDriver *, size_t, const void *) spi_lld_receive void spi_lld_receive(SPIDriver *, size_t, void *) spi_lld_polled_exchange uint16_t spi_lld_polled_exchange(SPIDriver *, uint16_t) frame spiInit void spiInit(void) spiObjectInit void spiObjectInit(SPIDriver *) spiStart void spiStart(SPIDriver *, const SPIConfig *) const SPIConfig * spiStop void spiStop(SPIDriver *) spiSelect void spiSelect(SPIDriver *) spiUnselect void spiUnselect(SPIDriver *) spiStartIgnore void spiStartIgnore(SPIDriver *, size_t) spiStartExchange void spiStartExchange(SPIDriver *, size_t, const void *, void *) spiStartSend void spiStartSend(SPIDriver *, size_t, const void *) spiStartReceive void spiStartReceive(SPIDriver *, size_t, void *) spiIgnore void spiIgnore(SPIDriver *, size_t) spiExchange void spiExchange(SPIDriver *, size_t, const void *, void *) spiSend void spiSend(SPIDriver *, size_t, const void *) spiReceive void spiReceive(SPIDriver *, size_t, void *) spiAcquireBus void spiAcquireBus(SPIDriver *) spiReleaseBus void spiReleaseBus(SPIDriver *) halInit void halInit(void) halIsCounterWithin bool_t halIsCounterWithin(halrtcnt_t, halrtcnt_t) halPolledDelay void halPolledDelay(halrtcnt_t) hal_lld_backup_domain_init void hal_lld_backup_domain_init(void) [ %?Wo¢µÇÚï¹ÓëÀÕ줺ØðªÀ×ëµ×ô®Ðì§Äá º Ó ç ÷
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c:macro@_DLIB_ELF_INIT_USE_RELATIVE_ROM_ADDRESSES c:macro@_DLIB_ELF_INIT_REGION_COUNT_TYPE c:macro@_DLIB_ELF_INIT_MODULE_ATTRIBUTES c:macro@_DLIB_ELF_INIT_INTERFACE_VERSION c:macro@_VA_DEFINED c:macro@_SIZE_ON_STACK c:macro@_VA_START c:macro@_VA_END c:macro@_VA_ARG c:macro@_XMATHWRAPPERS_DEF c:macro@_DLIB_SMALL_TARGET_INTERNAL c:macro@_DLIB_FILE_DESCRIPTOR c:macro@_DLIB_STDOUT_USES_STATIC_BUFFER c:macro@_DLIB_FULL_LOCALE_SUPPORT c:macro@_DLIB_FORMATTED_MULTIBYTE c:macro@_DLIB_THROW_HANDLING c:macro@_DLIB_PRINTF_MULTIBYTE c:macro@_DLIB_PRINTF_LONG_LONG c:macro@_DLIB_PRINTF_SPECIFIER_FLOAT c:macro@_DLIB_PRINTF_SPECIFIER_A c:macro@_DLIB_PRINTF_SPECIFIER_N c:macro@_DLIB_PRINTF_QUALIFIERS c:macro@_DLIB_PRINTF_FLAGS c:macro@_DLIB_PRINTF_WIDTH_AND_PRECISION c:macro@_DLIB_PRINTF_SPECIFIER_UNSIGNED c:macro@_DLIB_PRINTF_SPECIFIER_SIGNED c:macro@_DLIB_PRINTF_INT_TYPE_IS_INT c:macro@_DLIB_PRINTF_INT_TYPE_IS_LONG c:macro@_DLIB_PRINTF_CHAR_BY_CHAR c:macro@_DLIB_SCANF_MULTIBYTE c:macro@_DLIB_SCANF_LONG_LONG c:macro@_DLIB_SCANF_WIDTH c:macro@_DLIB_SCANF_QUALIFIERS c:macro@_DLIB_SCANF_SPECIFIER_FLOAT c:macro@_DLIB_SCANF_SPECIFIER_N c:macro@_DLIB_SCANF_SPECIFIER_SCANSET c:macro@_DLIB_SCANF_SPECIFIER_SIGNED c:macro@_DLIB_SCANF_SPECIFIER_UNSIGNED c:macro@_DLIB_SCANF_ASSIGNMENT_SUPPRESSING c:macro@_DLIB_STRFTIME_MULTIBYTE c:macro@_DLIB_QSORT_USE_BUBBLE_SORT c:macro@_DLIB_RAND_USE_SIMPLE c:macro@_DLIB_WIDE_CHARACTERS c:macro@_DLIB_DEBUG_BREAK_FUNCTION_ATTRIBUTE c:macro@_DLIB_DATA_ATTR c:macro@_DLIB_CONST_ATTR c:macro@__INT_SIZE__ c:macro@_DLIB_MBSTATET_USES_UNSIGNED_LONG c:macro@_DLIB_TIME_USES_LONG c:macro@_DLIB_AEABI_DIFUNC_CONTAINS_OFFSETS c:macro@_DLIB_FAST_FMA c:macro@_DLIB_SUPPORT_RTTI c:macro@_DLIB_SMALL_FP_HELPERS c:macro@_DLIB_USE_LONGLONG_IN_DOUBLE_FP_HELPERS c:macro@__SIZE_T_MAX__ c:macro@_DLIB_INCLUDE_DLMALLOC_ALTERNATIVE c:macro@__SIGNED_LONG_LONG_MAX__ c:macro@__SIGNED_LONG_MAX__ c:macro@_DLIB_TIME_ALLOW_64 c:macro@_DLIB_TIME_USES_64_DEFAULT c:macro@_DLIB_ALLOW_LARGE_CONSTANT_TABLES_FOR_MATH c:macro@__HAS_WEAK__ c:macro@__WEAK c:macro@_HAS_PRAGMA_PRINTF_ARGS c:macro@_NO_RETURN c:macro@__FLOAT_SIZE__ c:macro@__DOUBLE_SIZE__ c:macro@_F_FNAME c:macro@_F_FUN c:macro@_F_TYPE c:macro@_F_PTRCAST c:macro@_F_CAST c:macro@__LONG_DOUBLE_SIZE__ c:macro@_LONG_DOUBLE_IS_DOUBLE c:macro@_L_FNAME c:macro@_L_FUN c:macro@_L_TYPE c:macro@_L_PTRCAST c:macro@_L_CAST c:macro@_D_FNAME c:macro@_D_FUN c:macro@_D_TYPE c:macro@_HAS_STRICT_LINKAGE c:macro@_HAS_FIXED_POINT c:macro@_HAS_SECURE c:macro@_SECURE_PARAM c:macro@_HAS_DINKUM_COMPLEX c:macro@_IS_EMBEDDED c:macro@_IS_CPP_LANGUAGE c:macro@_HAS_EXCEPTIONS c:macro@_HAS_NAMESPACE c:macro@_HAS_GENERIC_TEMPLATES c:macro@_STD_BEGIN c:macro@_STD_END c:macro@_STD c:macro@_C_STD_BEGIN c:macro@_C_STD_END c:macro@_CSTD c:macro@_X_STD_BEGIN c:macro@_X_STD_END c:macro@_XSTD c:macro@_C_LIB_DECL c:macro@_END_C_LIB_DECL c:macro@_EXTERN_C c:macro@_END_EXTERN_C c:macro@_EXTERN_CPP c:macro@_END_EXTERN_CPP c:macro@_XENCODING_LIMITS_H c:macro@_EncodingSb_LenMax c:macro@__WCHAR_T_MAX__ c:macro@_EncodingUtf8_LenMax c:macro@_ENCODING_WITH_USED c:macro@_ENCODING_LEN_MAX c:macro@_ENCODING_CUR_MAX c:macro@_FBIAS c:macro@_FOFF c:macro@_FMANTISSA c:macro@__LITTLE_ENDIAN__ c:macro@_F0 c:macro@_DBIAS c:macro@_DOFF c:macro@_LOFF c:macro@_DMANTISSA c:macro@_D0 c:macro@_DLONG c:macro@_LBIAS c:macro@_LMANTISSA c:macro@_L0 c:macro@_C2 c:macro@_MBMAX c:macro@_MAX_EXP_DIG c:macro@_MAX_INT_DIG c:macro@_MAX_SIG_DIG c:macro@__WCHAR_T_TYPE__ c:macro@_WCMIN c:macro@_WIMIN c:macro@_WCMAX c:macro@_WIMAX c:macro@_ILONG c:macro@_NULL c:macro@__PTRDIFF_T_TYPE__ c:macro@__SIZE_T_TYPE__ c:macro@_Restrict c:macro@_FPOSOFF c:macro@_DLIB_THREADS_H c:macro@_DLIB_COMPILER_TLS c:macro@_DLIB_TLS_QUAL c:macro@_DLIB_MULTI_THREAD c:macro@_DLIB_GLOBAL_VARIABLES c:macro@_DLIB_FILE_OP_LOCKS c:macro@_DLIB_THREAD_MACRO_SETUP_DONE c:macro@_DLIB_TLS_MEMORY c:macro@_DLIB_TLS_MEMORY_GLUE c:macro@_DLIB_TLS_REQUIRE_INIT c:macro@_DLIB_TLS_REQUIRE_CSTART_INIT c:macro@_DLIB_TLS_INITIALIZER_MEMORY c:macro@_DLIB_TLS_SEGMENT_DATA c:macro@_DLIB_TLS_SEGMENT_INIT c:macro@__IAR_DLIB_PERTHREAD_SIZE c:macro@__IAR_DLIB_PERTHREAD_INIT_SIZE c:macro@__IAR_DLIB_PERTHREAD_SYMBOL_OFFSET c:macro@_TLS_CONST_DECLARATION c:macro@_TLS_LOCATION_HELPER0 c:macro@_TLS_LOCATION_HELPER1 c:macro@_TLS_LOCATION_HELPER2 c:macro@_TLS_DEFINITION c:macro@_TLS_REFERENCE c:macro@_TLS_REFERENCE_DEF c:macro@_TLS_DATA_DECL c:macro@_TLS_DEFINE_INIT c:macro@_TLS_DEFINE_NO_INIT c:macro@_TLS_DATA_DEF c:macro@_TLS_DATA_DEF_DT c:macro@_TLS_DATA_PTR c:macro@_TLS_ARR_DEF c:macro@_TLS_ARR c:macro@_DLIB_THREAD_LOCK_ONCE_TYPE c:macro@_DLIB_THREAD_LOCK_ONCE_MACRO c:macro@_DLIB_THREAD_LOCK_ONCE_TYPE_INIT c:macro@_Once c:macro@_ONCE_T_INIT c:macro@_MULTI_THREAD c:macro@_GLOBAL_LOCALE c:macro@_FILE_OP_LOCKS c:macro@_COMPILER_TLS c:macro@_TLS_QUAL c:macro@_LOCK_LOCALE c:macro@_LOCK_MALLOC c:macro@_LOCK_STREAM c:macro@_LOCK_DEBUG c:macro@_LOCK_STATIC_GUARD c:macro@_MAX_LOCK c:macro@_Mbstinit c:macro@_MAX c:macro@_MIN c:macro@_YSIZET_H c:macro@_SIZE_T c:macro@_SIZET c:macro@_STD_USING_SIZE_T c:macro@__DATA_PTR_MEM_HELPER1__ c:macro@__DATA_PTR_MEMORY_LIST1__ c:macro@NULL c:macro@offsetof c:macro@_PTRDIFF_T c:macro@_PTRDIFFT c:macro@_STD_USING_PTRDIFF_T c:macro@_WCHART c:macro@_STDINT c:macro@__INT8_T_TYPE__ c:macro@__UINT8_T_TYPE__ c:macro@__INT16_T_TYPE__ c:macro@__UINT16_T_TYPE__ c:macro@__INT32_T_TYPE__ c:macro@__UINT32_T_TYPE__ c:macro@__INT64_T_TYPE__ c:macro@__UINT64_T_TYPE__ c:macro@__INT_LEAST8_T_TYPE__ c:macro@__UINT_LEAST8_T_TYPE__ c:macro@__INT_LEAST16_T_TYPE__ c:macro@__UINT_LEAST16_T_TYPE__ c:macro@__INT_LEAST32_T_TYPE__ c:macro@__UINT_LEAST32_T_TYPE__ c:macro@__INT_LEAST64_T_TYPE__ c:macro@__UINT_LEAST64_T_TYPE__ c:macro@__INT_FAST8_T_TYPE__ c:macro@__UINT_FAST8_T_TYPE__ c:macro@__INT_FAST16_T_TYPE__ c:macro@__UINT_FAST16_T_TYPE__ c:macro@__INT_FAST32_T_TYPE__ c:macro@__UINT_FAST32_T_TYPE__ c:macro@__INT_FAST64_T_TYPE__ c:macro@__UINT_FAST64_T_TYPE__ c:macro@__INTMAX_T_TYPE__ c:macro@__UINTMAX_T_TYPE__ c:macro@__INTPTR_T_TYPE__ c:macro@__UINTPTR_T_TYPE__ c:macro@INT8_MAX c:macro@INT8_MIN c:macro@UINT8_MAX c:macro@INT16_MAX c:macro@INT16_MIN c:macro@UINT16_MAX c:macro@INT32_MAX c:macro@INT32_MIN c:macro@UINT32_MAX c:macro@INT64_MAX c:macro@INT64_MIN c:macro@UINT64_MAX c:macro@INT_LEAST8_MAX c:macro@INT_LEAST8_MIN c:macro@UINT_LEAST8_MAX c:macro@INT_LEAST16_MAX c:macro@INT_LEAST16_MIN c:macro@UINT_LEAST16_MAX c:macro@INT_LEAST32_MAX c:macro@INT_LEAST32_MIN c:macro@UINT_LEAST32_MAX c:macro@INT_LEAST64_MAX c:macro@INT_LEAST64_MIN c:macro@UINT_LEAST64_MAX c:macro@INT_FAST8_MAX c:macro@INT_FAST8_MIN c:macro@UINT_FAST8_MAX c:macro@INT_FAST16_MAX c:macro@INT_FAST16_MIN c:macro@UINT_FAST16_MAX c:macro@INT_FAST32_MAX c:macro@INT_FAST32_MIN c:macro@UINT_FAST32_MAX c:macro@INT_FAST64_MAX c:macro@INT_FAST64_MIN c:macro@UINT_FAST64_MAX c:macro@INTMAX_MAX c:macro@INTMAX_MIN c:macro@UINTMAX_MAX c:macro@SIZE_MAX c:macro@PTRDIFF_MAX c:macro@PTRDIFF_MIN c:macro@INTPTR_MAX c:macro@INTPTR_MIN c:macro@UINTPTR_MAX c:macro@WCHAR_MIN c:macro@WCHAR_MAX c:macro@WINT_MIN c:macro@WINT_MAX c:macro@SIG_ATOMIC_MIN c:macro@SIG_ATOMIC_MAX c:macro@INT8_C c:macro@UINT8_C c:macro@INT16_C c:macro@UINT16_C c:macro@INT32_C c:macro@UINT32_C c:macro@INT64_C c:macro@UINT64_C c:macro@INTMAX_C c:macro@UINTMAX_C c:macro@_STDBOOL c:macro@bool c:macro@true c:macro@false c:macro@__bool_true_false_are_defined c:macro@INLINE c:macro@ROMCONST c:macro@PACK_STRUCT_STRUCT c:macro@PACK_STRUCT_BEGIN c:macro@PACK_STRUCT_END c:macro@_CHLISTS_H_ c:macro@queue_init c:macro@list_init c:macro@isempty c:macro@notempty c:macro@_THREADSQUEUE_DATA c:macro@THREADSQUEUE_DECL c:macro@_CHCORE_H_ c:macro@CORTEX_M0 c:macro@CORTEX_M1 c:macro@CORTEX_M3 c:macro@CORTEX_M4 c:macro@_CMPARAMS_H_ c:macro@CORTEX_MODEL c:macro@CORTEX_HAS_ST c:macro@CORTEX_HAS_MPU c:macro@CORTEX_HAS_FPU c:macro@CORTEX_PRIORITY_BITS c:macro@CORTEX_PRIORITY_LEVELS c:macro@CORTEX_MINIMUM_PRIORITY c:macro@CORTEX_MAXIMUM_PRIORITY c:macro@CORTEX_IS_VALID_PRIORITY c:macro@CORTEX_IS_VALID_KERNEL_PRIORITY c:macro@CORTEX_PRIORITY_MASK c:macro@CH_ARCHITECTURE_ARM c:macro@CH_COMPILER_NAME c:macro@_CHCORE_V7M_H_ c:macro@CORTEX_BASEPRI_DISABLED c:macro@PORT_IDLE_THREAD_STACK_SIZE c:macro@PORT_INT_REQUIRED_STACK c:macro@CORTEX_ENABLE_WFI_IDLE c:macro@CORTEX_PRIORITY_SYSTICK c:macro@CORTEX_USE_FPU c:macro@CORTEX_SIMPLIFIED_PRIORITY c:macro@CORTEX_PRIORITY_SVCALL c:macro@CORTEX_VTOR_INIT c:macro@CORTEX_PRIGROUP_INIT c:macro@CORTEX_MAX_KERNEL_PRIORITY c:macro@CORTEX_BASEPRI_KERNEL c:macro@CORTEX_PRIORITY_PENDSV c:macro@CH_ARCHITECTURE_ARM_v7M c:macro@CH_ARCHITECTURE_NAME c:macro@CH_CORE_VARIANT_NAME c:macro@CH_PORT_INFO c:macro@SETUP_CONTEXT c:macro@STACK_ALIGN c:macro@THD_WA_SIZE c:macro@WORKING_AREA c:macro@PORT_IRQ_PROLOGUE c:macro@PORT_IRQ_EPILOGUE c:macro@PORT_IRQ_HANDLER c:macro@PORT_FAST_IRQ_HANDLER c:macro@port_init c:macro@port_lock c:macro@port_unlock c:macro@port_lock_from_isr c:macro@port_unlock_from_isr c:macro@port_disable c:macro@port_suspend c:macro@port_enable c:macro@port_wait_for_interrupt c:macro@port_switch c:macro@__INTRINSICS_INCLUDED c:macro@__TID__ c:macro@__cpid c:macro@__cpreg c:macro@__cpopc c:macro@__constrange c:macro@__fabs c:macro@__fabsf c:macro@_NVIC_H_ c:macro@HANDLER_MEM_MANAGE c:macro@HANDLER_BUS_FAULT c:macro@HANDLER_USAGE_FAULT c:macro@HANDLER_RESERVED_3 c:macro@HANDLER_RESERVED_4 c:macro@HANDLER_RESERVED_5 c:macro@HANDLER_RESERVED_6 c:macro@HANDLER_SVCALL c:macro@HANDLER_DEBUG_MONITOR c:macro@HANDLER_RESERVED_9 c:macro@HANDLER_PENDSV c:macro@HANDLER_SYSTICK c:macro@NVIC_ITCR c:macro@STBase c:macro@ST_CSR c:macro@ST_RVR c:macro@ST_CVR c:macro@ST_CBVR c:macro@CSR_ENABLE_MASK c:macro@ENABLE_OFF_BITS c:macro@ENABLE_ON_BITS c:macro@CSR_TICKINT_MASK c:macro@TICKINT_DISABLED_BITS c:macro@TICKINT_ENABLED_BITS c:macro@CSR_CLKSOURCE_MASK c:macro@CLKSOURCE_EXT_BITS c:macro@CLKSOURCE_CORE_BITS c:macro@CSR_COUNTFLAG_MASK c:macro@RVR_RELOAD_MASK c:macro@CVR_CURRENT_MASK c:macro@CBVR_TENMS_MASK c:macro@CBVR_SKEW_MASK c:macro@CBVR_NOREF_MASK c:macro@NVICBase c:macro@NVIC_ISER c:macro@NVIC_ICER c:macro@NVIC_ISPR c:macro@NVIC_ICPR c:macro@NVIC_IABR c:macro@NVIC_IPR c:macro@NVIC_STIR c:macro@SCBBase c:macro@SCB_CPUID c:macro@SCB_ICSR c:macro@SCB_VTOR c:macro@SCB_AIRCR c:macro@SCB_SCR c:macro@SCB_CCR c:macro@SCB_SHPR c:macro@SCB_SHCSR c:macro@SCB_CFSR c:macro@SCB_HFSR c:macro@SCB_DFSR c:macro@SCB_MMFAR c:macro@SCB_BFAR c:macro@SCB_AFSR c:macro@SCB_PFR c:macro@SCB_DFR c:macro@SCB_ADR c:macro@SCB_MMFR c:macro@SCB_SAR c:macro@SCB_CPACR c:macro@ICSR_VECTACTIVE_MASK c:macro@ICSR_RETTOBASE c:macro@ICSR_VECTPENDING_MASK c:macro@ICSR_ISRPENDING c:macro@ICSR_ISRPREEMPT c:macro@ICSR_PENDSTCLR c:macro@ICSR_PENDSTSET c:macro@ICSR_PENDSVCLR c:macro@ICSR_PENDSVSET c:macro@ICSR_NMIPENDSET c:macro@AIRCR_VECTKEY c:macro@AIRCR_PRIGROUP_MASK c:macro@AIRCR_PRIGROUP c:macro@FPUBase c:macro@SCB_FPCCR c:macro@SCB_FPCAR c:macro@SCB_FPDSCR c:macro@SCB_MVFR0 c:macro@SCB_MVFR1 c:macro@FPCCR_ASPEN c:macro@FPCCR_LSPEN c:macro@FPCCR_MONRDY c:macro@FPCCR_BFRDY c:macro@FPCCR_MMRDY c:macro@FPCCR_HFRDY c:macro@FPCCR_THREAD c:macro@FPCCR_USER c:macro@FPCCR_LSPACT c:macro@FPDSCR_AHP c:macro@FPDSCR_DN c:macro@FPDSCR_FZ c:macro@FPDSCR_RMODE c:macro@SCSBase c:macro@SCS_DHCSR c:macro@SCS_DCRSR c:macro@SCS_DCRDR c:macro@SCS_DEMCR c:macro@SCS_DEMCR_TRCENA c:macro@DWTBase c:macro@DWT_CTRL c:macro@DWT_CYCCNT c:macro@DWT_CPICNT c:macro@DWT_EXCCNT c:macro@DWT_SLEEPCNT c:macro@DWT_LSUCNT c:macro@DWT_FOLDCNT c:macro@DWT_PCSR c:macro@DWT_CTRL_CYCCNTENA c:macro@PORT_OPTIMIZED_ISPREEMPTIONREQUIRED c:macro@chSchIsPreemptionRequired c:macro@_CHSYS_H_ c:macro@chSysGetIdleThread c:macro@chSysHalt c:macro@chSysSwitch c:macro@chSysDisable c:macro@chSysSuspend c:macro@chSysEnable c:macro@chSysLock c:macro@chSysUnlock c:macro@chSysLockFromIsr c:macro@chSysUnlockFromIsr c:macro@CH_IRQ_PROLOGUE c:macro@CH_IRQ_EPILOGUE c:macro@CH_IRQ_HANDLER c:macro@CH_FAST_IRQ_HANDLER c:macro@_CHVT_H_ c:macro@S2ST c:macro@MS2ST c:macro@US2ST c:macro@chVTDoTickI c:macro@chVTIsArmedI c:macro@chVTSet c:macro@chVTReset c:macro@chTimeNow c:macro@_CHSCHD_H_ c:macro@RDY_OK c:macro@RDY_TIMEOUT c:macro@RDY_RESET c:macro@NOPRIO c:macro@IDLEPRIO c:macro@LOWPRIO c:macro@NORMALPRIO c:macro@HIGHPRIO c:macro@ABSPRIO c:macro@TIME_IMMEDIATE c:macro@TIME_INFINITE c:macro@firstprio c:macro@currp c:macro@setcurrp c:macro@chSchIsRescRequiredI c:macro@chSchCanYieldS c:macro@chSchDoYieldS c:macro@chSchPreemption c:macro@_CHSEM_H_ c:macro@_SEMAPHORE_DATA c:macro@SEMAPHORE_DECL c:macro@chSemFastWaitI c:macro@chSemFastSignalI c:macro@chSemGetCounterI c:macro@_CHBSEM_H_ c:macro@_BSEMAPHORE_DATA c:macro@BSEMAPHORE_DECL c:macro@chBSemInit c:macro@chBSemWait c:macro@chBSemWaitS c:macro@chBSemWaitTimeout c:macro@chBSemWaitTimeoutS c:macro@chBSemReset c:macro@chBSemResetI c:macro@chBSemSignal c:macro@chBSemSignalI c:macro@chBSemGetStateI c:macro@_CHMTX_H_ c:macro@_MUTEX_DATA c:macro@MUTEX_DECL c:macro@chMtxQueueNotEmptyS c:macro@_CHCOND_H_ c:macro@_CONDVAR_DATA c:macro@CONDVAR_DECL c:macro@_CHEVENTS_H_ c:macro@_EVENTSOURCE_DATA c:macro@EVENTSOURCE_DECL c:macro@ALL_EVENTS c:macro@EVENT_MASK c:macro@chEvtRegister c:macro@chEvtInit c:macro@chEvtIsListeningI c:macro@chEvtBroadcast c:macro@chEvtBroadcastI c:macro@_CHMSG_H_ c:macro@chMsgIsPendingI c:macro@chMsgGet c:macro@chMsgReleaseS c:macro@_CHMBOXES_H_ c:macro@chMBSizeI c:macro@chMBGetFreeCountI c:macro@chMBGetUsedCountI c:macro@chMBPeekI c:macro@_MAILBOX_DATA c:macro@MAILBOX_DECL c:macro@_CHMEMCORE_H_ c:macro@MEM_ALIGN_SIZE c:macro@MEM_ALIGN_MASK c:macro@MEM_ALIGN_PREV c:macro@MEM_ALIGN_NEXT c:macro@MEM_IS_ALIGNED c:macro@_CHHEAP_H_ c:macro@_CHMEMPOOLS_H_ c:macro@_MEMORYPOOL_DATA c:macro@MEMORYPOOL_DECL c:macro@chPoolAdd c:macro@chPoolAddI c:macro@_CHTHREADS_H_ c:macro@THD_STATE_READY c:macro@THD_STATE_CURRENT c:macro@THD_STATE_SUSPENDED c:macro@THD_STATE_WTSEM c:macro@THD_STATE_WTMTX c:macro@THD_STATE_WTCOND c:macro@THD_STATE_SLEEPING c:macro@THD_STATE_WTEXIT c:macro@THD_STATE_WTOREVT c:macro@THD_STATE_WTANDEVT c:macro@THD_STATE_SNDMSGQ c:macro@THD_STATE_SNDMSG c:macro@THD_STATE_WTMSG c:macro@THD_STATE_WTQUEUE c:macro@THD_STATE_FINAL c:macro@THD_STATE_NAMES c:macro@THD_MEM_MODE_MASK c:macro@THD_MEM_MODE_STATIC c:macro@THD_MEM_MODE_HEAP c:macro@THD_MEM_MODE_MEMPOOL c:macro@THD_TERMINATE c:macro@chThdSelf c:macro@chThdGetPriority c:macro@chThdGetTicks c:macro@chThdLS c:macro@chThdTerminated c:macro@chThdShouldTerminate c:macro@chThdResumeI c:macro@chThdSleepS c:macro@chThdSleepSeconds c:macro@chThdSleepMilliseconds c:macro@chThdSleepMicroseconds c:macro@_CHDYNAMIC_H_ c:macro@_CHREGISTRY_H_ c:macro@chRegSetThreadName c:macro@chRegGetThreadName c:macro@REG_REMOVE c:macro@REG_INSERT c:macro@_CHINLINE_H_ c:macro@_CHQUEUES_H_ c:macro@Q_OK c:macro@Q_TIMEOUT c:macro@Q_RESET c:macro@Q_EMPTY c:macro@Q_FULL c:macro@chQSizeI c:macro@chQSpaceI c:macro@chQGetLink c:macro@chIQGetFullI c:macro@chIQGetEmptyI c:macro@chIQIsEmptyI c:macro@chIQIsFullI c:macro@chIQGet c:macro@_INPUTQUEUE_DATA c:macro@INPUTQUEUE_DECL c:macro@chOQGetFullI c:macro@chOQGetEmptyI c:macro@chOQIsEmptyI c:macro@chOQIsFullI c:macro@chOQPut c:macro@_OUTPUTQUEUE_DATA c:macro@OUTPUTQUEUE_DECL c:macro@_CHSTREAMS_H_ c:macro@_base_sequential_stream_methods c:macro@_base_sequential_stream_data c:macro@chSequentialStreamWrite c:macro@chSequentialStreamRead c:macro@chSequentialStreamPut c:macro@chSequentialStreamGet c:macro@_CHFILES_H_ c:macro@FILE_OK c:macro@FILE_ERROR c:macro@_base_file_stream_methods c:macro@_base_file_stream_data c:macro@chFileStreamClose c:macro@chFileStreamGetError c:macro@chFileStreamGetSize c:macro@chFileStreamGetPosition c:macro@chFileStreamSeek c:macro@_CHDEBUG_H_ c:macro@CH_DBG_ENABLED c:macro@__QUOTE_THIS c:macro@CH_TRACE_BUFFER_SIZE c:macro@CH_STACK_FILL_VALUE c:macro@CH_THREAD_FILL_VALUE c:macro@dbg_enter_lock c:macro@dbg_leave_lock c:macro@dbg_check_disable c:macro@dbg_check_suspend c:macro@dbg_check_enable c:macro@dbg_check_lock c:macro@dbg_check_unlock c:macro@dbg_check_lock_from_isr c:macro@dbg_check_unlock_from_isr c:macro@dbg_check_enter_isr c:macro@dbg_check_leave_isr c:macro@chDbgCheckClassI c:macro@chDbgCheckClassS c:macro@dbg_trace c:macro@chDbgCheck c:macro@chDbgAssert c:macro@chDbgPanic c:macro@_HAL_H_ c:macro@_BOARD_H_ c:macro@BOARD_ST_STM32L_DISCOVERY c:macro@BOARD_NAME c:macro@STM32_LSECLK c:macro@STM32_HSECLK c:macro@STM32_HSE_BYPASS c:macro@STM32L1XX_MD c:macro@GPIOA_BUTTON c:macro@GPIOA_PIN1 c:macro@GPIOA_PIN2 c:macro@GPIOA_PIN3 c:macro@GPIOA_PIN4 c:macro@GPIOA_PIN5 c:macro@GPIOA_PIN6 c:macro@GPIOA_PIN7 c:macro@GPIOA_PIN8 c:macro@GPIOA_PIN9 c:macro@GPIOA_PIN10 c:macro@GPIOA_PIN11 c:macro@GPIOA_PIN12 c:macro@GPIOA_JTAG_TMS c:macro@GPIOA_JTAG_TCK c:macro@GPIOA_JTAG_TDI c:macro@GPIOB_PIN0 c:macro@GPIOB_PIN1 c:macro@GPIOB_BOOT1 c:macro@GPIOB_JTAG_TDO c:macro@GPIOB_JTAG_TRST c:macro@GPIOB_PIN5 c:macro@GPIOB_LED4 c:macro@GPIOB_LED3 c:macro@GPIOB_PIN8 c:macro@GPIOB_PIN9 c:macro@GPIOB_PIN10 c:macro@GPIOB_PIN11 c:macro@GPIOB_PIN12 c:macro@GPIOB_PIN13 c:macro@GPIOB_PIN14 c:macro@GPIOB_PIN15 c:macro@GPIOC_PIN0 c:macro@GPIOC_PIN1 c:macro@GPIOC_PIN2 c:macro@GPIOC_PIN3 c:macro@GPIOC_PIN4 c:macro@GPIOC_PIN5 c:macro@GPIOC_PIN6 c:macro@GPIOC_PIN7 c:macro@GPIOC_PIN8 c:macro@GPIOC_PIN9 c:macro@GPIOC_PIN10 c:macro@GPIOC_PIN11 c:macro@GPIOC_PIN12 c:macro@GPIOC_PIN13 c:macro@GPIOC_OSC32_IN c:macro@GPIOC_OSC32_OUT c:macro@GPIOD_PIN0 c:macro@GPIOD_PIN1 c:macro@GPIOD_PIN2 c:macro@GPIOD_PIN3 c:macro@GPIOD_PIN4 c:macro@GPIOD_PIN5 c:macro@GPIOD_PIN6 c:macro@GPIOD_PIN7 c:macro@GPIOD_PIN8 c:macro@GPIOD_PIN9 c:macro@GPIOD_PIN10 c:macro@GPIOD_PIN11 c:macro@GPIOD_PIN12 c:macro@GPIOD_PIN13 c:macro@GPIOD_PIN14 c:macro@GPIOD_PIN15 c:macro@GPIOE_PIN0 c:macro@GPIOE_PIN1 c:macro@GPIOE_PIN2 c:macro@GPIOE_PIN3 c:macro@GPIOE_PIN4 c:macro@GPIOE_PIN5 c:macro@GPIOE_PIN6 c:macro@GPIOE_PIN7 c:macro@GPIOE_PIN8 c:macro@GPIOE_PIN9 c:macro@GPIOE_PIN10 c:macro@GPIOE_PIN11 c:macro@GPIOE_PIN12 c:macro@GPIOE_PIN13 c:macro@GPIOE_PIN14 c:macro@GPIOE_PIN15 c:macro@GPIOH_OSC_IN c:macro@GPIOH_OSC_OUT c:macro@GPIOH_PIN2 c:macro@GPIOH_PIN3 c:macro@GPIOH_PIN4 c:macro@GPIOH_PIN5 c:macro@GPIOH_PIN6 c:macro@GPIOH_PIN7 c:macro@GPIOH_PIN8 c:macro@GPIOH_PIN9 c:macro@GPIOH_PIN10 c:macro@GPIOH_PIN11 c:macro@GPIOH_PIN12 c:macro@GPIOH_PIN13 c:macro@GPIOH_PIN14 c:macro@GPIOH_PIN15 c:macro@PIN_MODE_INPUT c:macro@PIN_MODE_OUTPUT c:macro@PIN_MODE_ALTERNATE c:macro@PIN_MODE_ANALOG c:macro@PIN_ODR_LOW c:macro@PIN_ODR_HIGH c:macro@PIN_OTYPE_PUSHPULL c:macro@PIN_OTYPE_OPENDRAIN c:macro@PIN_OSPEED_400K c:macro@PIN_OSPEED_2M c:macro@PIN_OSPEED_10M c:macro@PIN_OSPEED_40M c:macro@PIN_PUPDR_FLOATING c:macro@PIN_PUPDR_PULLUP c:macro@PIN_PUPDR_PULLDOWN c:macro@PIN_AFIO_AF c:macro@VAL_GPIOA_MODER c:macro@VAL_GPIOA_OTYPER c:macro@VAL_GPIOA_OSPEEDR c:macro@VAL_GPIOA_PUPDR c:macro@VAL_GPIOA_ODR c:macro@VAL_GPIOA_AFRL c:macro@VAL_GPIOA_AFRH c:macro@VAL_GPIOB_MODER c:macro@VAL_GPIOB_OTYPER c:macro@VAL_GPIOB_OSPEEDR c:macro@VAL_GPIOB_PUPDR c:macro@VAL_GPIOB_ODR c:macro@VAL_GPIOB_AFRL c:macro@VAL_GPIOB_AFRH c:macro@VAL_GPIOC_MODER c:macro@VAL_GPIOC_OTYPER c:macro@VAL_GPIOC_OSPEEDR c:macro@VAL_GPIOC_PUPDR c:macro@VAL_GPIOC_ODR c:macro@VAL_GPIOC_AFRL c:macro@VAL_GPIOC_AFRH c:macro@VAL_GPIOD_MODER c:macro@VAL_GPIOD_OTYPER c:macro@VAL_GPIOD_OSPEEDR c:macro@VAL_GPIOD_PUPDR c:macro@VAL_GPIOD_ODR c:macro@VAL_GPIOD_AFRL c:macro@VAL_GPIOD_AFRH c:macro@VAL_GPIOE_MODER c:macro@VAL_GPIOE_OTYPER c:macro@VAL_GPIOE_OSPEEDR c:macro@VAL_GPIOE_PUPDR c:macro@VAL_GPIOE_ODR c:macro@VAL_GPIOE_AFRL c:macro@VAL_GPIOE_AFRH c:macro@VAL_GPIOH_MODER c:macro@VAL_GPIOH_OTYPER c:macro@VAL_GPIOH_OSPEEDR c:macro@VAL_GPIOH_PUPDR c:macro@VAL_GPIOH_ODR c:macro@VAL_GPIOH_AFRL c:macro@VAL_GPIOH_AFRH c:macro@_HALCONF_H_ c:macro@STM32L1xx_MCUCONF c:macro@STM32_NO_INIT c:macro@STM32_HSI_ENABLED c:macro@STM32_LSI_ENABLED c:macro@STM32_HSE_ENABLED c:macro@STM32_LSE_ENABLED c:macro@STM32_ADC_CLOCK_ENABLED c:macro@STM32_USB_CLOCK_ENABLED c:macro@STM32_MSIRANGE c:macro@STM32_SW c:macro@STM32_PLLSRC c:macro@STM32_PLLMUL_VALUE c:macro@STM32_PLLDIV_VALUE c:macro@STM32_HPRE c:macro@STM32_PPRE1 c:macro@STM32_PPRE2 c:macro@STM32_MCOSEL c:macro@STM32_MCOPRE c:macro@STM32_RTCSEL c:macro@STM32_RTCPRE c:macro@STM32_VOS c:macro@STM32_PVD_ENABLE c:macro@STM32_PLS c:macro@STM32_ADC_USE_ADC1 c:macro@STM32_ADC_ADC1_DMA_PRIORITY c:macro@STM32_ADC_IRQ_PRIORITY c:macro@STM32_ADC_ADC1_DMA_IRQ_PRIORITY c:macro@STM32_EXT_EXTI0_IRQ_PRIORITY c:macro@STM32_EXT_EXTI1_IRQ_PRIORITY c:macro@STM32_EXT_EXTI2_IRQ_PRIORITY c:macro@STM32_EXT_EXTI3_IRQ_PRIORITY c:macro@STM32_EXT_EXTI4_IRQ_PRIORITY c:macro@STM32_EXT_EXTI5_9_IRQ_PRIORITY c:macro@STM32_EXT_EXTI10_15_IRQ_PRIORITY c:macro@STM32_EXT_EXTI16_IRQ_PRIORITY c:macro@STM32_EXT_EXTI17_IRQ_PRIORITY c:macro@STM32_EXT_EXTI18_IRQ_PRIORITY c:macro@STM32_EXT_EXTI19_IRQ_PRIORITY c:macro@STM32_EXT_EXTI20_IRQ_PRIORITY c:macro@STM32_EXT_EXTI21_22_IRQ_PRIORITY c:macro@STM32_GPT_USE_TIM2 c:macro@STM32_GPT_USE_TIM3 c:macro@STM32_GPT_USE_TIM4 c:macro@STM32_GPT_TIM2_IRQ_PRIORITY c:macro@STM32_GPT_TIM3_IRQ_PRIORITY c:macro@STM32_GPT_TIM4_IRQ_PRIORITY c:macro@STM32_I2C_USE_I2C1 c:macro@STM32_I2C_USE_I2C2 c:macro@STM32_I2C_I2C1_IRQ_PRIORITY c:macro@STM32_I2C_I2C2_IRQ_PRIORITY c:macro@STM32_I2C_I2C1_DMA_PRIORITY c:macro@STM32_I2C_I2C2_DMA_PRIORITY c:macro@STM32_I2C_I2C1_DMA_ERROR_HOOK c:macro@STM32_I2C_I2C2_DMA_ERROR_HOOK c:macro@STM32_ICU_USE_TIM2 c:macro@STM32_ICU_USE_TIM3 c:macro@STM32_ICU_USE_TIM4 c:macro@STM32_ICU_TIM2_IRQ_PRIORITY c:macro@STM32_ICU_TIM3_IRQ_PRIORITY c:macro@STM32_ICU_TIM4_IRQ_PRIORITY c:macro@STM32_PWM_USE_TIM2 c:macro@STM32_PWM_USE_TIM3 c:macro@STM32_PWM_USE_TIM4 c:macro@STM32_PWM_TIM2_IRQ_PRIORITY c:macro@STM32_PWM_TIM3_IRQ_PRIORITY c:macro@STM32_PWM_TIM4_IRQ_PRIORITY c:macro@STM32_SERIAL_USE_USART1 c:macro@STM32_SERIAL_USE_USART2 c:macro@STM32_SERIAL_USE_USART3 c:macro@STM32_SERIAL_USART1_PRIORITY c:macro@STM32_SERIAL_USART2_PRIORITY c:macro@STM32_SERIAL_USART3_PRIORITY c:macro@STM32_SPI_USE_SPI1 c:macro@STM32_SPI_USE_SPI2 c:macro@STM32_SPI_SPI1_DMA_PRIORITY c:macro@STM32_SPI_SPI2_DMA_PRIORITY c:macro@STM32_SPI_SPI1_IRQ_PRIORITY c:macro@STM32_SPI_SPI2_IRQ_PRIORITY c:macro@STM32_SPI_DMA_ERROR_HOOK c:macro@STM32_UART_USE_USART1 c:macro@STM32_UART_USE_USART2 c:macro@STM32_UART_USE_USART3 c:macro@STM32_UART_USART1_IRQ_PRIORITY c:macro@STM32_UART_USART2_IRQ_PRIORITY c:macro@STM32_UART_USART3_IRQ_PRIORITY c:macro@STM32_UART_USART1_DMA_PRIORITY c:macro@STM32_UART_USART2_DMA_PRIORITY c:macro@STM32_UART_USART3_DMA_PRIORITY c:macro@STM32_UART_DMA_ERROR_HOOK c:macro@STM32_USB_USE_USB1 c:macro@STM32_USB_LOW_POWER_ON_SUSPEND c:macro@STM32_USB_USB1_HP_IRQ_PRIORITY c:macro@STM32_USB_USB1_LP_IRQ_PRIORITY c:macro@HAL_USE_TM c:macro@HAL_USE_PAL c:macro@HAL_USE_ADC c:macro@HAL_USE_CAN c:macro@HAL_USE_EXT c:macro@HAL_USE_GPT c:macro@HAL_USE_I2C c:macro@HAL_USE_ICU c:macro@HAL_USE_MAC c:macro@HAL_USE_MMC_SPI c:macro@HAL_USE_PWM c:macro@HAL_USE_RTC c:macro@HAL_USE_SDC c:macro@HAL_USE_SERIAL c:macro@HAL_USE_SERIAL_USB c:macro@HAL_USE_SPI c:macro@HAL_USE_UART c:macro@HAL_USE_USB c:macro@ADC_USE_WAIT c:macro@ADC_USE_MUTUAL_EXCLUSION c:macro@CAN_USE_SLEEP_MODE c:macro@I2C_USE_MUTUAL_EXCLUSION c:macro@MAC_USE_ZERO_COPY c:macro@MAC_USE_EVENTS c:macro@MMC_NICE_WAITING c:macro@SDC_INIT_RETRY c:macro@SDC_MMC_SUPPORT c:macro@SDC_NICE_WAITING c:macro@SERIAL_DEFAULT_BITRATE c:macro@SERIAL_BUFFERS_SIZE c:macro@SPI_USE_WAIT c:macro@SPI_USE_MUTUAL_EXCLUSION c:macro@_HAL_LLD_H_ c:macro@_STM32_H_ c:macro@__STM32L1XX_H c:macro@HSE_VALUE c:macro@HSE_STARTUP_TIMEOUT c:macro@HSI_STARTUP_TIMEOUT c:macro@HSI_VALUE c:macro@LSI_VALUE c:macro@LSE_VALUE c:macro@__STM32L1XX_STDPERIPH_VERSION_MAIN c:macro@__STM32L1XX_STDPERIPH_VERSION_SUB1 c:macro@__STM32L1XX_STDPERIPH_VERSION_SUB2 c:macro@__STM32L1XX_STDPERIPH_VERSION_RC c:macro@__STM32L1XX_STDPERIPH_VERSION c:macro@__CM3_REV c:macro@__MPU_PRESENT c:macro@__NVIC_PRIO_BITS c:macro@__Vendor_SysTickConfig c:macro@__CORE_CM3_H_GENERIC c:macro@__CM3_CMSIS_VERSION_MAIN c:macro@__CM3_CMSIS_VERSION_SUB c:macro@__CM3_CMSIS_VERSION c:macro@__CORTEX_M c:macro@__ASM c:macro@__INLINE c:macro@__STATIC_INLINE c:macro@__FPU_USED c:macro@__CORE_CMINSTR_H c:macro@__CMSIS_IAR_H__ c:macro@__CORE__ c:macro@__ARM6M__ c:macro@__enable_irq c:macro@__disable_irq c:macro@__NOP c:macro@__VER__ c:macro@__BKPT c:macro@__LDREXW c:macro@__STREXW c:macro@__enable_fault_irq c:macro@__disable_fault_irq c:macro@__CORE_CMFUNC_H c:macro@__CORE_CM3_H_DEPENDANT c:macro@__I c:macro@__O c:macro@__IO c:macro@NVIC_STIR_INTID_Pos c:macro@NVIC_STIR_INTID_Msk c:macro@SCB_CPUID_IMPLEMENTER_Pos c:macro@SCB_CPUID_IMPLEMENTER_Msk c:macro@SCB_CPUID_VARIANT_Pos c:macro@SCB_CPUID_VARIANT_Msk c:macro@SCB_CPUID_ARCHITECTURE_Pos c:macro@SCB_CPUID_ARCHITECTURE_Msk c:macro@SCB_CPUID_PARTNO_Pos c:macro@SCB_CPUID_PARTNO_Msk c:macro@SCB_CPUID_REVISION_Pos c:macro@SCB_CPUID_REVISION_Msk c:macro@SCB_ICSR_NMIPENDSET_Pos c:macro@SCB_ICSR_NMIPENDSET_Msk c:macro@SCB_ICSR_PENDSVSET_Pos c:macro@SCB_ICSR_PENDSVSET_Msk c:macro@SCB_ICSR_PENDSVCLR_Pos c:macro@SCB_ICSR_PENDSVCLR_Msk c:macro@SCB_ICSR_PENDSTSET_Pos c:macro@SCB_ICSR_PENDSTSET_Msk c:macro@SCB_ICSR_PENDSTCLR_Pos c:macro@SCB_ICSR_PENDSTCLR_Msk c:macro@SCB_ICSR_ISRPREEMPT_Pos c:macro@SCB_ICSR_ISRPREEMPT_Msk c:macro@SCB_ICSR_ISRPENDING_Pos c:macro@SCB_ICSR_ISRPENDING_Msk c:macro@SCB_ICSR_VECTPENDING_Pos c:macro@SCB_ICSR_VECTPENDING_Msk c:macro@SCB_ICSR_RETTOBASE_Pos c:macro@SCB_ICSR_RETTOBASE_Msk c:macro@SCB_ICSR_VECTACTIVE_Pos c:macro@SCB_ICSR_VECTACTIVE_Msk c:macro@SCB_VTOR_TBLBASE_Pos c:macro@SCB_VTOR_TBLBASE_Msk c:macro@SCB_VTOR_TBLOFF_Pos c:macro@SCB_VTOR_TBLOFF_Msk c:macro@SCB_AIRCR_VECTKEY_Pos c:macro@SCB_AIRCR_VECTKEY_Msk c:macro@SCB_AIRCR_VECTKEYSTAT_Pos c:macro@SCB_AIRCR_VECTKEYSTAT_Msk c:macro@SCB_AIRCR_ENDIANESS_Pos c:macro@SCB_AIRCR_ENDIANESS_Msk c:macro@SCB_AIRCR_PRIGROUP_Pos c:macro@SCB_AIRCR_PRIGROUP_Msk c:macro@SCB_AIRCR_SYSRESETREQ_Pos c:macro@SCB_AIRCR_SYSRESETREQ_Msk c:macro@SCB_AIRCR_VECTCLRACTIVE_Pos c:macro@SCB_AIRCR_VECTCLRACTIVE_Msk c:macro@SCB_AIRCR_VECTRESET_Pos c:macro@SCB_AIRCR_VECTRESET_Msk c:macro@SCB_SCR_SEVONPEND_Pos c:macro@SCB_SCR_SEVONPEND_Msk c:macro@SCB_SCR_SLEEPDEEP_Pos c:macro@SCB_SCR_SLEEPDEEP_Msk c:macro@SCB_SCR_SLEEPONEXIT_Pos c:macro@SCB_SCR_SLEEPONEXIT_Msk c:macro@SCB_CCR_STKALIGN_Pos c:macro@SCB_CCR_STKALIGN_Msk c:macro@SCB_CCR_BFHFNMIGN_Pos c:macro@SCB_CCR_BFHFNMIGN_Msk c:macro@SCB_CCR_DIV_0_TRP_Pos c:macro@SCB_CCR_DIV_0_TRP_Msk c:macro@SCB_CCR_UNALIGN_TRP_Pos c:macro@SCB_CCR_UNALIGN_TRP_Msk c:macro@SCB_CCR_USERSETMPEND_Pos c:macro@SCB_CCR_USERSETMPEND_Msk c:macro@SCB_CCR_NONBASETHRDENA_Pos c:macro@SCB_CCR_NONBASETHRDENA_Msk c:macro@SCB_SHCSR_USGFAULTENA_Pos c:macro@SCB_SHCSR_USGFAULTENA_Msk c:macro@SCB_SHCSR_BUSFAULTENA_Pos c:macro@SCB_SHCSR_BUSFAULTENA_Msk c:macro@SCB_SHCSR_MEMFAULTENA_Pos c:macro@SCB_SHCSR_MEMFAULTENA_Msk c:macro@SCB_SHCSR_SVCALLPENDED_Pos c:macro@SCB_SHCSR_SVCALLPENDED_Msk c:macro@SCB_SHCSR_BUSFAULTPENDED_Pos c:macro@SCB_SHCSR_BUSFAULTPENDED_Msk c:macro@SCB_SHCSR_MEMFAULTPENDED_Pos c:macro@SCB_SHCSR_MEMFAULTPENDED_Msk c:macro@SCB_SHCSR_USGFAULTPENDED_Pos c:macro@SCB_SHCSR_USGFAULTPENDED_Msk c:macro@SCB_SHCSR_SYSTICKACT_Pos c:macro@SCB_SHCSR_SYSTICKACT_Msk c:macro@SCB_SHCSR_PENDSVACT_Pos c:macro@SCB_SHCSR_PENDSVACT_Msk c:macro@SCB_SHCSR_MONITORACT_Pos c:macro@SCB_SHCSR_MONITORACT_Msk c:macro@SCB_SHCSR_SVCALLACT_Pos c:macro@SCB_SHCSR_SVCALLACT_Msk c:macro@SCB_SHCSR_USGFAULTACT_Pos c:macro@SCB_SHCSR_USGFAULTACT_Msk c:macro@SCB_SHCSR_BUSFAULTACT_Pos c:macro@SCB_SHCSR_BUSFAULTACT_Msk c:macro@SCB_SHCSR_MEMFAULTACT_Pos c:macro@SCB_SHCSR_MEMFAULTACT_Msk c:macro@SCB_CFSR_USGFAULTSR_Pos c:macro@SCB_CFSR_USGFAULTSR_Msk c:macro@SCB_CFSR_BUSFAULTSR_Pos c:macro@SCB_CFSR_BUSFAULTSR_Msk c:macro@SCB_CFSR_MEMFAULTSR_Pos c:macro@SCB_CFSR_MEMFAULTSR_Msk c:macro@SCB_HFSR_DEBUGEVT_Pos c:macro@SCB_HFSR_DEBUGEVT_Msk c:macro@SCB_HFSR_FORCED_Pos c:macro@SCB_HFSR_FORCED_Msk c:macro@SCB_HFSR_VECTTBL_Pos c:macro@SCB_HFSR_VECTTBL_Msk c:macro@SCB_DFSR_EXTERNAL_Pos c:macro@SCB_DFSR_EXTERNAL_Msk c:macro@SCB_DFSR_VCATCH_Pos c:macro@SCB_DFSR_VCATCH_Msk c:macro@SCB_DFSR_DWTTRAP_Pos c:macro@SCB_DFSR_DWTTRAP_Msk c:macro@SCB_DFSR_BKPT_Pos c:macro@SCB_DFSR_BKPT_Msk c:macro@SCB_DFSR_HALTED_Pos c:macro@SCB_DFSR_HALTED_Msk c:macro@SCnSCB_ICTR_INTLINESNUM_Pos c:macro@SCnSCB_ICTR_INTLINESNUM_Msk c:macro@SCnSCB_ACTLR_DISFOLD_Pos c:macro@SCnSCB_ACTLR_DISFOLD_Msk c:macro@SCnSCB_ACTLR_DISDEFWBUF_Pos c:macro@SCnSCB_ACTLR_DISDEFWBUF_Msk c:macro@SCnSCB_ACTLR_DISMCYCINT_Pos c:macro@SCnSCB_ACTLR_DISMCYCINT_Msk c:macro@SysTick_CTRL_COUNTFLAG_Pos c:macro@SysTick_CTRL_COUNTFLAG_Msk c:macro@SysTick_CTRL_CLKSOURCE_Pos c:macro@SysTick_CTRL_CLKSOURCE_Msk c:macro@SysTick_CTRL_TICKINT_Pos c:macro@SysTick_CTRL_TICKINT_Msk c:macro@SysTick_CTRL_ENABLE_Pos c:macro@SysTick_CTRL_ENABLE_Msk c:macro@SysTick_LOAD_RELOAD_Pos c:macro@SysTick_LOAD_RELOAD_Msk c:macro@SysTick_VAL_CURRENT_Pos c:macro@SysTick_VAL_CURRENT_Msk c:macro@SysTick_CALIB_NOREF_Pos c:macro@SysTick_CALIB_NOREF_Msk c:macro@SysTick_CALIB_SKEW_Pos c:macro@SysTick_CALIB_SKEW_Msk c:macro@SysTick_CALIB_TENMS_Pos c:macro@SysTick_CALIB_TENMS_Msk c:macro@ITM_TPR_PRIVMASK_Pos c:macro@ITM_TPR_PRIVMASK_Msk c:macro@ITM_TCR_BUSY_Pos c:macro@ITM_TCR_BUSY_Msk c:macro@ITM_TCR_TraceBusID_Pos c:macro@ITM_TCR_TraceBusID_Msk c:macro@ITM_TCR_GTSFREQ_Pos c:macro@ITM_TCR_GTSFREQ_Msk c:macro@ITM_TCR_TSPrescale_Pos c:macro@ITM_TCR_TSPrescale_Msk c:macro@ITM_TCR_SWOENA_Pos c:macro@ITM_TCR_SWOENA_Msk c:macro@ITM_TCR_DWTENA_Pos c:macro@ITM_TCR_DWTENA_Msk c:macro@ITM_TCR_SYNCENA_Pos c:macro@ITM_TCR_SYNCENA_Msk c:macro@ITM_TCR_TSENA_Pos c:macro@ITM_TCR_TSENA_Msk c:macro@ITM_TCR_ITMENA_Pos c:macro@ITM_TCR_ITMENA_Msk c:macro@ITM_IWR_ATVALIDM_Pos c:macro@ITM_IWR_ATVALIDM_Msk c:macro@ITM_IRR_ATREADYM_Pos c:macro@ITM_IRR_ATREADYM_Msk c:macro@ITM_IMCR_INTEGRATION_Pos c:macro@ITM_IMCR_INTEGRATION_Msk c:macro@ITM_LSR_ByteAcc_Pos c:macro@ITM_LSR_ByteAcc_Msk c:macro@ITM_LSR_Access_Pos c:macro@ITM_LSR_Access_Msk c:macro@ITM_LSR_Present_Pos c:macro@ITM_LSR_Present_Msk c:macro@DWT_CTRL_NUMCOMP_Pos c:macro@DWT_CTRL_NUMCOMP_Msk c:macro@DWT_CTRL_NOTRCPKT_Pos c:macro@DWT_CTRL_NOTRCPKT_Msk c:macro@DWT_CTRL_NOEXTTRIG_Pos c:macro@DWT_CTRL_NOEXTTRIG_Msk c:macro@DWT_CTRL_NOCYCCNT_Pos c:macro@DWT_CTRL_NOCYCCNT_Msk c:macro@DWT_CTRL_NOPRFCNT_Pos c:macro@DWT_CTRL_NOPRFCNT_Msk c:macro@DWT_CTRL_CYCEVTENA_Pos c:macro@DWT_CTRL_CYCEVTENA_Msk c:macro@DWT_CTRL_FOLDEVTENA_Pos c:macro@DWT_CTRL_FOLDEVTENA_Msk c:macro@DWT_CTRL_LSUEVTENA_Pos c:macro@DWT_CTRL_LSUEVTENA_Msk c:macro@DWT_CTRL_SLEEPEVTENA_Pos c:macro@DWT_CTRL_SLEEPEVTENA_Msk c:macro@DWT_CTRL_EXCEVTENA_Pos c:macro@DWT_CTRL_EXCEVTENA_Msk c:macro@DWT_CTRL_CPIEVTENA_Pos c:macro@DWT_CTRL_CPIEVTENA_Msk c:macro@DWT_CTRL_EXCTRCENA_Pos c:macro@DWT_CTRL_EXCTRCENA_Msk c:macro@DWT_CTRL_PCSAMPLENA_Pos c:macro@DWT_CTRL_PCSAMPLENA_Msk c:macro@DWT_CTRL_SYNCTAP_Pos c:macro@DWT_CTRL_SYNCTAP_Msk c:macro@DWT_CTRL_CYCTAP_Pos c:macro@DWT_CTRL_CYCTAP_Msk c:macro@DWT_CTRL_POSTINIT_Pos c:macro@DWT_CTRL_POSTINIT_Msk c:macro@DWT_CTRL_POSTPRESET_Pos c:macro@DWT_CTRL_POSTPRESET_Msk c:macro@DWT_CTRL_CYCCNTENA_Pos c:macro@DWT_CTRL_CYCCNTENA_Msk c:macro@DWT_CPICNT_CPICNT_Pos c:macro@DWT_CPICNT_CPICNT_Msk c:macro@DWT_EXCCNT_EXCCNT_Pos c:macro@DWT_EXCCNT_EXCCNT_Msk c:macro@DWT_SLEEPCNT_SLEEPCNT_Pos c:macro@DWT_SLEEPCNT_SLEEPCNT_Msk c:macro@DWT_LSUCNT_LSUCNT_Pos c:macro@DWT_LSUCNT_LSUCNT_Msk c:macro@DWT_FOLDCNT_FOLDCNT_Pos c:macro@DWT_FOLDCNT_FOLDCNT_Msk c:macro@DWT_MASK_MASK_Pos c:macro@DWT_MASK_MASK_Msk c:macro@DWT_FUNCTION_MATCHED_Pos c:macro@DWT_FUNCTION_MATCHED_Msk c:macro@DWT_FUNCTION_DATAVADDR1_Pos c:macro@DWT_FUNCTION_DATAVADDR1_Msk c:macro@DWT_FUNCTION_DATAVADDR0_Pos c:macro@DWT_FUNCTION_DATAVADDR0_Msk c:macro@DWT_FUNCTION_DATAVSIZE_Pos c:macro@DWT_FUNCTION_DATAVSIZE_Msk c:macro@DWT_FUNCTION_LNK1ENA_Pos c:macro@DWT_FUNCTION_LNK1ENA_Msk c:macro@DWT_FUNCTION_DATAVMATCH_Pos c:macro@DWT_FUNCTION_DATAVMATCH_Msk c:macro@DWT_FUNCTION_CYCMATCH_Pos c:macro@DWT_FUNCTION_CYCMATCH_Msk c:macro@DWT_FUNCTION_EMITRANGE_Pos c:macro@DWT_FUNCTION_EMITRANGE_Msk c:macro@DWT_FUNCTION_FUNCTION_Pos c:macro@DWT_FUNCTION_FUNCTION_Msk c:macro@TPI_ACPR_PRESCALER_Pos c:macro@TPI_ACPR_PRESCALER_Msk c:macro@TPI_SPPR_TXMODE_Pos c:macro@TPI_SPPR_TXMODE_Msk c:macro@TPI_FFSR_FtNonStop_Pos c:macro@TPI_FFSR_FtNonStop_Msk c:macro@TPI_FFSR_TCPresent_Pos c:macro@TPI_FFSR_TCPresent_Msk c:macro@TPI_FFSR_FtStopped_Pos c:macro@TPI_FFSR_FtStopped_Msk c:macro@TPI_FFSR_FlInProg_Pos c:macro@TPI_FFSR_FlInProg_Msk c:macro@TPI_FFCR_TrigIn_Pos c:macro@TPI_FFCR_TrigIn_Msk c:macro@TPI_FFCR_EnFCont_Pos c:macro@TPI_FFCR_EnFCont_Msk c:macro@TPI_TRIGGER_TRIGGER_Pos c:macro@TPI_TRIGGER_TRIGGER_Msk c:macro@TPI_FIFO0_ITM_ATVALID_Pos c:macro@TPI_FIFO0_ITM_ATVALID_Msk c:macro@TPI_FIFO0_ITM_bytecount_Pos c:macro@TPI_FIFO0_ITM_bytecount_Msk c:macro@TPI_FIFO0_ETM_ATVALID_Pos c:macro@TPI_FIFO0_ETM_ATVALID_Msk c:macro@TPI_FIFO0_ETM_bytecount_Pos c:macro@TPI_FIFO0_ETM_bytecount_Msk c:macro@TPI_FIFO0_ETM2_Pos c:macro@TPI_FIFO0_ETM2_Msk c:macro@TPI_FIFO0_ETM1_Pos c:macro@TPI_FIFO0_ETM1_Msk c:macro@TPI_FIFO0_ETM0_Pos c:macro@TPI_FIFO0_ETM0_Msk c:macro@TPI_ITATBCTR2_ATREADY_Pos c:macro@TPI_ITATBCTR2_ATREADY_Msk c:macro@TPI_FIFO1_ITM_ATVALID_Pos c:macro@TPI_FIFO1_ITM_ATVALID_Msk c:macro@TPI_FIFO1_ITM_bytecount_Pos c:macro@TPI_FIFO1_ITM_bytecount_Msk c:macro@TPI_FIFO1_ETM_ATVALID_Pos c:macro@TPI_FIFO1_ETM_ATVALID_Msk c:macro@TPI_FIFO1_ETM_bytecount_Pos c:macro@TPI_FIFO1_ETM_bytecount_Msk c:macro@TPI_FIFO1_ITM2_Pos c:macro@TPI_FIFO1_ITM2_Msk c:macro@TPI_FIFO1_ITM1_Pos c:macro@TPI_FIFO1_ITM1_Msk c:macro@TPI_FIFO1_ITM0_Pos c:macro@TPI_FIFO1_ITM0_Msk c:macro@TPI_ITATBCTR0_ATREADY_Pos c:macro@TPI_ITATBCTR0_ATREADY_Msk c:macro@TPI_ITCTRL_Mode_Pos c:macro@TPI_ITCTRL_Mode_Msk c:macro@TPI_DEVID_NRZVALID_Pos c:macro@TPI_DEVID_NRZVALID_Msk c:macro@TPI_DEVID_MANCVALID_Pos c:macro@TPI_DEVID_MANCVALID_Msk c:macro@TPI_DEVID_PTINVALID_Pos c:macro@TPI_DEVID_PTINVALID_Msk c:macro@TPI_DEVID_MinBufSz_Pos c:macro@TPI_DEVID_MinBufSz_Msk c:macro@TPI_DEVID_AsynClkIn_Pos c:macro@TPI_DEVID_AsynClkIn_Msk c:macro@TPI_DEVID_NrTraceInput_Pos c:macro@TPI_DEVID_NrTraceInput_Msk c:macro@TPI_DEVTYPE_SubType_Pos c:macro@TPI_DEVTYPE_SubType_Msk c:macro@TPI_DEVTYPE_MajorType_Pos c:macro@TPI_DEVTYPE_MajorType_Msk c:macro@MPU_TYPE_IREGION_Pos c:macro@MPU_TYPE_IREGION_Msk c:macro@MPU_TYPE_DREGION_Pos c:macro@MPU_TYPE_DREGION_Msk c:macro@MPU_TYPE_SEPARATE_Pos c:macro@MPU_TYPE_SEPARATE_Msk c:macro@MPU_CTRL_PRIVDEFENA_Pos c:macro@MPU_CTRL_PRIVDEFENA_Msk c:macro@MPU_CTRL_HFNMIENA_Pos c:macro@MPU_CTRL_HFNMIENA_Msk c:macro@MPU_CTRL_ENABLE_Pos c:macro@MPU_CTRL_ENABLE_Msk c:macro@MPU_RNR_REGION_Pos c:macro@MPU_RNR_REGION_Msk c:macro@MPU_RBAR_ADDR_Pos c:macro@MPU_RBAR_ADDR_Msk c:macro@MPU_RBAR_VALID_Pos c:macro@MPU_RBAR_VALID_Msk c:macro@MPU_RBAR_REGION_Pos c:macro@MPU_RBAR_REGION_Msk c:macro@MPU_RASR_ATTRS_Pos c:macro@MPU_RASR_ATTRS_Msk c:macro@MPU_RASR_XN_Pos c:macro@MPU_RASR_XN_Msk c:macro@MPU_RASR_AP_Pos c:macro@MPU_RASR_AP_Msk c:macro@MPU_RASR_TEX_Pos c:macro@MPU_RASR_TEX_Msk c:macro@MPU_RASR_S_Pos c:macro@MPU_RASR_S_Msk c:macro@MPU_RASR_C_Pos c:macro@MPU_RASR_C_Msk c:macro@MPU_RASR_B_Pos c:macro@MPU_RASR_B_Msk c:macro@MPU_RASR_SRD_Pos c:macro@MPU_RASR_SRD_Msk c:macro@MPU_RASR_SIZE_Pos c:macro@MPU_RASR_SIZE_Msk c:macro@MPU_RASR_ENABLE_Pos c:macro@MPU_RASR_ENABLE_Msk c:macro@CoreDebug_DHCSR_DBGKEY_Pos c:macro@CoreDebug_DHCSR_DBGKEY_Msk c:macro@CoreDebug_DHCSR_S_RESET_ST_Pos c:macro@CoreDebug_DHCSR_S_RESET_ST_Msk c:macro@CoreDebug_DHCSR_S_RETIRE_ST_Pos c:macro@CoreDebug_DHCSR_S_RETIRE_ST_Msk c:macro@CoreDebug_DHCSR_S_LOCKUP_Pos c:macro@CoreDebug_DHCSR_S_LOCKUP_Msk c:macro@CoreDebug_DHCSR_S_SLEEP_Pos c:macro@CoreDebug_DHCSR_S_SLEEP_Msk c:macro@CoreDebug_DHCSR_S_HALT_Pos c:macro@CoreDebug_DHCSR_S_HALT_Msk c:macro@CoreDebug_DHCSR_S_REGRDY_Pos c:macro@CoreDebug_DHCSR_S_REGRDY_Msk c:macro@CoreDebug_DHCSR_C_SNAPSTALL_Pos c:macro@CoreDebug_DHCSR_C_SNAPSTALL_Msk c:macro@CoreDebug_DHCSR_C_MASKINTS_Pos c:macro@CoreDebug_DHCSR_C_MASKINTS_Msk c:macro@CoreDebug_DHCSR_C_STEP_Pos c:macro@CoreDebug_DHCSR_C_STEP_Msk c:macro@CoreDebug_DHCSR_C_HALT_Pos c:macro@CoreDebug_DHCSR_C_HALT_Msk c:macro@CoreDebug_DHCSR_C_DEBUGEN_Pos c:macro@CoreDebug_DHCSR_C_DEBUGEN_Msk c:macro@CoreDebug_DCRSR_REGWnR_Pos c:macro@CoreDebug_DCRSR_REGWnR_Msk c:macro@CoreDebug_DCRSR_REGSEL_Pos c:macro@CoreDebug_DCRSR_REGSEL_Msk c:macro@CoreDebug_DEMCR_TRCENA_Pos c:macro@CoreDebug_DEMCR_TRCENA_Msk c:macro@CoreDebug_DEMCR_MON_REQ_Pos c:macro@CoreDebug_DEMCR_MON_REQ_Msk c:macro@CoreDebug_DEMCR_MON_STEP_Pos c:macro@CoreDebug_DEMCR_MON_STEP_Msk c:macro@CoreDebug_DEMCR_MON_PEND_Pos c:macro@CoreDebug_DEMCR_MON_PEND_Msk c:macro@CoreDebug_DEMCR_MON_EN_Pos c:macro@CoreDebug_DEMCR_MON_EN_Msk c:macro@CoreDebug_DEMCR_VC_HARDERR_Pos c:macro@CoreDebug_DEMCR_VC_HARDERR_Msk c:macro@CoreDebug_DEMCR_VC_INTERR_Pos c:macro@CoreDebug_DEMCR_VC_INTERR_Msk c:macro@CoreDebug_DEMCR_VC_BUSERR_Pos c:macro@CoreDebug_DEMCR_VC_BUSERR_Msk c:macro@CoreDebug_DEMCR_VC_STATERR_Pos c:macro@CoreDebug_DEMCR_VC_STATERR_Msk c:macro@CoreDebug_DEMCR_VC_CHKERR_Pos c:macro@CoreDebug_DEMCR_VC_CHKERR_Msk c:macro@CoreDebug_DEMCR_VC_NOCPERR_Pos c:macro@CoreDebug_DEMCR_VC_NOCPERR_Msk c:macro@CoreDebug_DEMCR_VC_MMERR_Pos c:macro@CoreDebug_DEMCR_VC_MMERR_Msk c:macro@CoreDebug_DEMCR_VC_CORERESET_Pos c:macro@CoreDebug_DEMCR_VC_CORERESET_Msk c:macro@SCS_BASE c:macro@ITM_BASE c:macro@DWT_BASE c:macro@TPI_BASE c:macro@CoreDebug_BASE c:macro@SysTick_BASE c:macro@NVIC_BASE c:macro@SCB_BASE c:macro@SCnSCB c:macro@SCB c:macro@SysTick c:macro@NVIC c:macro@ITM c:macro@DWT c:macro@TPI c:macro@CoreDebug c:macro@MPU_BASE c:macro@MPU c:macro@ITM_RXBUFFER_EMPTY c:macro@IS_FUNCTIONAL_STATE c:macro@__RAM_FUNC c:macro@FLASH_BASE c:macro@SRAM_BASE c:macro@PERIPH_BASE c:macro@SRAM_BB_BASE c:macro@PERIPH_BB_BASE c:macro@FSMC_R_BASE c:macro@APB1PERIPH_BASE c:macro@APB2PERIPH_BASE c:macro@AHBPERIPH_BASE c:macro@TIM2_BASE c:macro@TIM3_BASE c:macro@TIM4_BASE c:macro@TIM5_BASE c:macro@TIM6_BASE c:macro@TIM7_BASE c:macro@LCD_BASE c:macro@RTC_BASE c:macro@WWDG_BASE c:macro@IWDG_BASE c:macro@SPI2_BASE c:macro@SPI3_BASE c:macro@USART2_BASE c:macro@USART3_BASE c:macro@UART4_BASE c:macro@UART5_BASE c:macro@I2C1_BASE c:macro@I2C2_BASE c:macro@PWR_BASE c:macro@DAC_BASE c:macro@COMP_BASE c:macro@RI_BASE c:macro@OPAMP_BASE c:macro@SYSCFG_BASE c:macro@EXTI_BASE c:macro@TIM9_BASE c:macro@TIM10_BASE c:macro@TIM11_BASE c:macro@ADC1_BASE c:macro@ADC_BASE c:macro@SDIO_BASE c:macro@SPI1_BASE c:macro@USART1_BASE c:macro@GPIOA_BASE c:macro@GPIOB_BASE c:macro@GPIOC_BASE c:macro@GPIOD_BASE c:macro@GPIOE_BASE c:macro@GPIOH_BASE c:macro@GPIOF_BASE c:macro@GPIOG_BASE c:macro@CRC_BASE c:macro@RCC_BASE c:macro@FLASH_R_BASE c:macro@OB_BASE c:macro@DMA1_BASE c:macro@DMA1_Channel1_BASE c:macro@DMA1_Channel2_BASE c:macro@DMA1_Channel3_BASE c:macro@DMA1_Channel4_BASE c:macro@DMA1_Channel5_BASE c:macro@DMA1_Channel6_BASE c:macro@DMA1_Channel7_BASE c:macro@DMA2_BASE c:macro@DMA2_Channel1_BASE c:macro@DMA2_Channel2_BASE c:macro@DMA2_Channel3_BASE c:macro@DMA2_Channel4_BASE c:macro@DMA2_Channel5_BASE c:macro@AES_BASE c:macro@FSMC_Bank1_R_BASE c:macro@FSMC_Bank1E_R_BASE c:macro@DBGMCU_BASE c:macro@TIM2 c:macro@TIM3 c:macro@TIM4 c:macro@TIM5 c:macro@TIM6 c:macro@TIM7 c:macro@LCD c:macro@RTC c:macro@WWDG c:macro@IWDG c:macro@SPI2 c:macro@SPI3 c:macro@USART2 c:macro@USART3 c:macro@UART4 c:macro@UART5 c:macro@I2C1 c:macro@I2C2 c:macro@PWR c:macro@DAC c:macro@COMP c:macro@RI c:macro@OPAMP c:macro@SYSCFG c:macro@EXTI c:macro@ADC1 c:macro@ADC c:macro@SDIO c:macro@TIM9 c:macro@TIM10 c:macro@TIM11 c:macro@SPI1 c:macro@USART1 c:macro@DMA1 c:macro@DMA1_Channel1 c:macro@DMA1_Channel2 c:macro@DMA1_Channel3 c:macro@DMA1_Channel4 c:macro@DMA1_Channel5 c:macro@DMA1_Channel6 c:macro@DMA1_Channel7 c:macro@DMA2 c:macro@DMA2_Channel1 c:macro@DMA2_Channel2 c:macro@DMA2_Channel3 c:macro@DMA2_Channel4 c:macro@DMA2_Channel5 c:macro@RCC c:macro@CRC c:macro@GPIOA c:macro@GPIOB c:macro@GPIOC c:macro@GPIOD c:macro@GPIOE c:macro@GPIOH c:macro@GPIOF c:macro@GPIOG c:macro@FLASH c:macro@OB c:macro@AES c:macro@FSMC_Bank1 c:macro@FSMC_Bank1E c:macro@DBGMCU c:macro@ADC_SR_AWD c:macro@ADC_SR_EOC c:macro@ADC_SR_JEOC c:macro@ADC_SR_JSTRT c:macro@ADC_SR_STRT c:macro@ADC_SR_OVR c:macro@ADC_SR_ADONS c:macro@ADC_SR_RCNR c:macro@ADC_SR_JCNR c:macro@ADC_CR1_AWDCH c:macro@ADC_CR1_AWDCH_0 c:macro@ADC_CR1_AWDCH_1 c:macro@ADC_CR1_AWDCH_2 c:macro@ADC_CR1_AWDCH_3 c:macro@ADC_CR1_AWDCH_4 c:macro@ADC_CR1_EOCIE c:macro@ADC_CR1_AWDIE c:macro@ADC_CR1_JEOCIE c:macro@ADC_CR1_SCAN c:macro@ADC_CR1_AWDSGL c:macro@ADC_CR1_JAUTO c:macro@ADC_CR1_DISCEN c:macro@ADC_CR1_JDISCEN c:macro@ADC_CR1_DISCNUM c:macro@ADC_CR1_DISCNUM_0 c:macro@ADC_CR1_DISCNUM_1 c:macro@ADC_CR1_DISCNUM_2 c:macro@ADC_CR1_PDD c:macro@ADC_CR1_PDI c:macro@ADC_CR1_JAWDEN c:macro@ADC_CR1_AWDEN c:macro@ADC_CR1_RES c:macro@ADC_CR1_RES_0 c:macro@ADC_CR1_RES_1 c:macro@ADC_CR1_OVRIE c:macro@ADC_CR2_ADON c:macro@ADC_CR2_CONT c:macro@ADC_CR2_CFG c:macro@ADC_CR2_DELS c:macro@ADC_CR2_DELS_0 c:macro@ADC_CR2_DELS_1 c:macro@ADC_CR2_DELS_2 c:macro@ADC_CR2_DMA c:macro@ADC_CR2_DDS c:macro@ADC_CR2_EOCS c:macro@ADC_CR2_ALIGN c:macro@ADC_CR2_JEXTSEL c:macro@ADC_CR2_JEXTSEL_0 c:macro@ADC_CR2_JEXTSEL_1 c:macro@ADC_CR2_JEXTSEL_2 c:macro@ADC_CR2_JEXTSEL_3 c:macro@ADC_CR2_JEXTEN c:macro@ADC_CR2_JEXTEN_0 c:macro@ADC_CR2_JEXTEN_1 c:macro@ADC_CR2_JSWSTART c:macro@ADC_CR2_EXTSEL c:macro@ADC_CR2_EXTSEL_0 c:macro@ADC_CR2_EXTSEL_1 c:macro@ADC_CR2_EXTSEL_2 c:macro@ADC_CR2_EXTSEL_3 c:macro@ADC_CR2_EXTEN c:macro@ADC_CR2_EXTEN_0 c:macro@ADC_CR2_EXTEN_1 c:macro@ADC_CR2_SWSTART c:macro@ADC_SMPR1_SMP20 c:macro@ADC_SMPR1_SMP20_0 c:macro@ADC_SMPR1_SMP20_1 c:macro@ADC_SMPR1_SMP20_2 c:macro@ADC_SMPR1_SMP21 c:macro@ADC_SMPR1_SMP21_0 c:macro@ADC_SMPR1_SMP21_1 c:macro@ADC_SMPR1_SMP21_2 c:macro@ADC_SMPR1_SMP22 c:macro@ADC_SMPR1_SMP22_0 c:macro@ADC_SMPR1_SMP22_1 c:macro@ADC_SMPR1_SMP22_2 c:macro@ADC_SMPR1_SMP23 c:macro@ADC_SMPR1_SMP23_0 c:macro@ADC_SMPR1_SMP23_1 c:macro@ADC_SMPR1_SMP23_2 c:macro@ADC_SMPR1_SMP24 c:macro@ADC_SMPR1_SMP24_0 c:macro@ADC_SMPR1_SMP24_1 c:macro@ADC_SMPR1_SMP24_2 c:macro@ADC_SMPR1_SMP25 c:macro@ADC_SMPR1_SMP25_0 c:macro@ADC_SMPR1_SMP25_1 c:macro@ADC_SMPR1_SMP25_2 c:macro@ADC_SMPR1_SMP26 c:macro@ADC_SMPR1_SMP26_0 c:macro@ADC_SMPR1_SMP26_1 c:macro@ADC_SMPR1_SMP26_2 c:macro@ADC_SMPR1_SMP27 c:macro@ADC_SMPR1_SMP27_0 c:macro@ADC_SMPR1_SMP27_1 c:macro@ADC_SMPR1_SMP27_2 c:macro@ADC_SMPR1_SMP28 c:macro@ADC_SMPR1_SMP28_0 c:macro@ADC_SMPR1_SMP28_1 c:macro@ADC_SMPR1_SMP28_2 c:macro@ADC_SMPR1_SMP29 c:macro@ADC_SMPR1_SMP29_0 c:macro@ADC_SMPR1_SMP29_1 c:macro@ADC_SMPR1_SMP29_2 c:macro@ADC_SMPR2_SMP10 c:macro@ADC_SMPR2_SMP10_0 c:macro@ADC_SMPR2_SMP10_1 c:macro@ADC_SMPR2_SMP10_2 c:macro@ADC_SMPR2_SMP11 c:macro@ADC_SMPR2_SMP11_0 c:macro@ADC_SMPR2_SMP11_1 c:macro@ADC_SMPR2_SMP11_2 c:macro@ADC_SMPR2_SMP12 c:macro@ADC_SMPR2_SMP12_0 c:macro@ADC_SMPR2_SMP12_1 c:macro@ADC_SMPR2_SMP12_2 c:macro@ADC_SMPR2_SMP13 c:macro@ADC_SMPR2_SMP13_0 c:macro@ADC_SMPR2_SMP13_1 c:macro@ADC_SMPR2_SMP13_2 c:macro@ADC_SMPR2_SMP14 c:macro@ADC_SMPR2_SMP14_0 c:macro@ADC_SMPR2_SMP14_1 c:macro@ADC_SMPR2_SMP14_2 c:macro@ADC_SMPR2_SMP15 c:macro@ADC_SMPR2_SMP15_0 c:macro@ADC_SMPR2_SMP15_1 c:macro@ADC_SMPR2_SMP15_2 c:macro@ADC_SMPR2_SMP16 c:macro@ADC_SMPR2_SMP16_0 c:macro@ADC_SMPR2_SMP16_1 c:macro@ADC_SMPR2_SMP16_2 c:macro@ADC_SMPR2_SMP17 c:macro@ADC_SMPR2_SMP17_0 c:macro@ADC_SMPR2_SMP17_1 c:macro@ADC_SMPR2_SMP17_2 c:macro@ADC_SMPR2_SMP18 c:macro@ADC_SMPR2_SMP18_0 c:macro@ADC_SMPR2_SMP18_1 c:macro@ADC_SMPR2_SMP18_2 c:macro@ADC_SMPR2_SMP19 c:macro@ADC_SMPR2_SMP19_0 c:macro@ADC_SMPR2_SMP19_1 c:macro@ADC_SMPR2_SMP19_2 c:macro@ADC_SMPR3_SMP0 c:macro@ADC_SMPR3_SMP0_0 c:macro@ADC_SMPR3_SMP0_1 c:macro@ADC_SMPR3_SMP0_2 c:macro@ADC_SMPR3_SMP1 c:macro@ADC_SMPR3_SMP1_0 c:macro@ADC_SMPR3_SMP1_1 c:macro@ADC_SMPR3_SMP1_2 c:macro@ADC_SMPR3_SMP2 c:macro@ADC_SMPR3_SMP2_0 c:macro@ADC_SMPR3_SMP2_1 c:macro@ADC_SMPR3_SMP2_2 c:macro@ADC_SMPR3_SMP3 c:macro@ADC_SMPR3_SMP3_0 c:macro@ADC_SMPR3_SMP3_1 c:macro@ADC_SMPR3_SMP3_2 c:macro@ADC_SMPR3_SMP4 c:macro@ADC_SMPR3_SMP4_0 c:macro@ADC_SMPR3_SMP4_1 c:macro@ADC_SMPR3_SMP4_2 c:macro@ADC_SMPR3_SMP5 c:macro@ADC_SMPR3_SMP5_0 c:macro@ADC_SMPR3_SMP5_1 c:macro@ADC_SMPR3_SMP5_2 c:macro@ADC_SMPR3_SMP6 c:macro@ADC_SMPR3_SMP6_0 c:macro@ADC_SMPR3_SMP6_1 c:macro@ADC_SMPR3_SMP6_2 c:macro@ADC_SMPR3_SMP7 c:macro@ADC_SMPR3_SMP7_0 c:macro@ADC_SMPR3_SMP7_1 c:macro@ADC_SMPR3_SMP7_2 c:macro@ADC_SMPR3_SMP8 c:macro@ADC_SMPR3_SMP8_0 c:macro@ADC_SMPR3_SMP8_1 c:macro@ADC_SMPR3_SMP8_2 c:macro@ADC_SMPR3_SMP9 c:macro@ADC_SMPR3_SMP9_0 c:macro@ADC_SMPR3_SMP9_1 c:macro@ADC_SMPR3_SMP9_2 c:macro@ADC_JOFR1_JOFFSET1 c:macro@ADC_JOFR2_JOFFSET2 c:macro@ADC_JOFR3_JOFFSET3 c:macro@ADC_JOFR4_JOFFSET4 c:macro@ADC_HTR_HT c:macro@ADC_LTR_LT c:macro@ADC_SQR1_L c:macro@ADC_SQR1_L_0 c:macro@ADC_SQR1_L_1 c:macro@ADC_SQR1_L_2 c:macro@ADC_SQR1_L_3 c:macro@ADC_SQR1_SQ28 c:macro@ADC_SQR1_SQ28_0 c:macro@ADC_SQR1_SQ28_1 c:macro@ADC_SQR1_SQ28_2 c:macro@ADC_SQR1_SQ28_3 c:macro@ADC_SQR1_SQ28_4 c:macro@ADC_SQR1_SQ27 c:macro@ADC_SQR1_SQ27_0 c:macro@ADC_SQR1_SQ27_1 c:macro@ADC_SQR1_SQ27_2 c:macro@ADC_SQR1_SQ27_3 c:macro@ADC_SQR1_SQ27_4 c:macro@ADC_SQR1_SQ26 c:macro@ADC_SQR1_SQ26_0 c:macro@ADC_SQR1_SQ26_1 c:macro@ADC_SQR1_SQ26_2 c:macro@ADC_SQR1_SQ26_3 c:macro@ADC_SQR1_SQ26_4 c:macro@ADC_SQR1_SQ25 c:macro@ADC_SQR1_SQ25_0 c:macro@ADC_SQR1_SQ25_1 c:macro@ADC_SQR1_SQ25_2 c:macro@ADC_SQR1_SQ25_3 c:macro@ADC_SQR1_SQ25_4 c:macro@ADC_SQR2_SQ19 c:macro@ADC_SQR2_SQ19_0 c:macro@ADC_SQR2_SQ19_1 c:macro@ADC_SQR2_SQ19_2 c:macro@ADC_SQR2_SQ19_3 c:macro@ADC_SQR2_SQ19_4 c:macro@ADC_SQR2_SQ20 c:macro@ADC_SQR2_SQ20_0 c:macro@ADC_SQR2_SQ20_1 c:macro@ADC_SQR2_SQ20_2 c:macro@ADC_SQR2_SQ20_3 c:macro@ADC_SQR2_SQ20_4 c:macro@ADC_SQR2_SQ21 c:macro@ADC_SQR2_SQ21_0 c:macro@ADC_SQR2_SQ21_1 c:macro@ADC_SQR2_SQ21_2 c:macro@ADC_SQR2_SQ21_3 c:macro@ADC_SQR2_SQ21_4 c:macro@ADC_SQR2_SQ22 c:macro@ADC_SQR2_SQ22_0 c:macro@ADC_SQR2_SQ22_1 c:macro@ADC_SQR2_SQ22_2 c:macro@ADC_SQR2_SQ22_3 c:macro@ADC_SQR2_SQ22_4 c:macro@ADC_SQR2_SQ23 c:macro@ADC_SQR2_SQ23_0 c:macro@ADC_SQR2_SQ23_1 c:macro@ADC_SQR2_SQ23_2 c:macro@ADC_SQR2_SQ23_3 c:macro@ADC_SQR2_SQ23_4 c:macro@ADC_SQR2_SQ24 c:macro@ADC_SQR2_SQ24_0 c:macro@ADC_SQR2_SQ24_1 c:macro@ADC_SQR2_SQ24_2 c:macro@ADC_SQR2_SQ24_3 c:macro@ADC_SQR2_SQ24_4 c:macro@ADC_SQR3_SQ13 c:macro@ADC_SQR3_SQ13_0 c:macro@ADC_SQR3_SQ13_1 c:macro@ADC_SQR3_SQ13_2 c:macro@ADC_SQR3_SQ13_3 c:macro@ADC_SQR3_SQ13_4 c:macro@ADC_SQR3_SQ14 c:macro@ADC_SQR3_SQ14_0 c:macro@ADC_SQR3_SQ14_1 c:macro@ADC_SQR3_SQ14_2 c:macro@ADC_SQR3_SQ14_3 c:macro@ADC_SQR3_SQ14_4 c:macro@ADC_SQR3_SQ15 c:macro@ADC_SQR3_SQ15_0 c:macro@ADC_SQR3_SQ15_1 c:macro@ADC_SQR3_SQ15_2 c:macro@ADC_SQR3_SQ15_3 c:macro@ADC_SQR3_SQ15_4 c:macro@ADC_SQR3_SQ16 c:macro@ADC_SQR3_SQ16_0 c:macro@ADC_SQR3_SQ16_1 c:macro@ADC_SQR3_SQ16_2 c:macro@ADC_SQR3_SQ16_3 c:macro@ADC_SQR3_SQ16_4 c:macro@ADC_SQR3_SQ17 c:macro@ADC_SQR3_SQ17_0 c:macro@ADC_SQR3_SQ17_1 c:macro@ADC_SQR3_SQ17_2 c:macro@ADC_SQR3_SQ17_3 c:macro@ADC_SQR3_SQ17_4 c:macro@ADC_SQR3_SQ18 c:macro@ADC_SQR3_SQ18_0 c:macro@ADC_SQR3_SQ18_1 c:macro@ADC_SQR3_SQ18_2 c:macro@ADC_SQR3_SQ18_3 c:macro@ADC_SQR3_SQ18_4 c:macro@ADC_SQR4_SQ7 c:macro@ADC_SQR4_SQ7_0 c:macro@ADC_SQR4_SQ7_1 c:macro@ADC_SQR4_SQ7_2 c:macro@ADC_SQR4_SQ7_3 c:macro@ADC_SQR4_SQ7_4 c:macro@ADC_SQR4_SQ8 c:macro@ADC_SQR4_SQ8_0 c:macro@ADC_SQR4_SQ8_1 c:macro@ADC_SQR4_SQ8_2 c:macro@ADC_SQR4_SQ8_3 c:macro@ADC_SQR4_SQ8_4 c:macro@ADC_SQR4_SQ9 c:macro@ADC_SQR4_SQ9_0 c:macro@ADC_SQR4_SQ9_1 c:macro@ADC_SQR4_SQ9_2 c:macro@ADC_SQR4_SQ9_3 c:macro@ADC_SQR4_SQ9_4 c:macro@ADC_SQR4_SQ10 c:macro@ADC_SQR4_SQ10_0 c:macro@ADC_SQR4_SQ10_1 c:macro@ADC_SQR4_SQ10_2 c:macro@ADC_SQR4_SQ10_3 c:macro@ADC_SQR4_SQ10_4 c:macro@ADC_SQR4_SQ11 c:macro@ADC_SQR4_SQ11_0 c:macro@ADC_SQR4_SQ11_1 c:macro@ADC_SQR4_SQ11_2 c:macro@ADC_SQR4_SQ11_3 c:macro@ADC_SQR4_SQ11_4 c:macro@ADC_SQR4_SQ12 c:macro@ADC_SQR4_SQ12_0 c:macro@ADC_SQR4_SQ12_1 c:macro@ADC_SQR4_SQ12_2 c:macro@ADC_SQR4_SQ12_3 c:macro@ADC_SQR4_SQ12_4 c:macro@ADC_SQR5_SQ1 c:macro@ADC_SQR5_SQ1_0 c:macro@ADC_SQR5_SQ1_1 c:macro@ADC_SQR5_SQ1_2 c:macro@ADC_SQR5_SQ1_3 c:macro@ADC_SQR5_SQ1_4 c:macro@ADC_SQR5_SQ2 c:macro@ADC_SQR5_SQ2_0 c:macro@ADC_SQR5_SQ2_1 c:macro@ADC_SQR5_SQ2_2 c:macro@ADC_SQR5_SQ2_3 c:macro@ADC_SQR5_SQ2_4 c:macro@ADC_SQR5_SQ3 c:macro@ADC_SQR5_SQ3_0 c:macro@ADC_SQR5_SQ3_1 c:macro@ADC_SQR5_SQ3_2 c:macro@ADC_SQR5_SQ3_3 c:macro@ADC_SQR5_SQ3_4 c:macro@ADC_SQR5_SQ4 c:macro@ADC_SQR5_SQ4_0 c:macro@ADC_SQR5_SQ4_1 c:macro@ADC_SQR5_SQ4_2 c:macro@ADC_SQR5_SQ4_3 c:macro@ADC_SQR5_SQ4_4 c:macro@ADC_SQR5_SQ5 c:macro@ADC_SQR5_SQ5_0 c:macro@ADC_SQR5_SQ5_1 c:macro@ADC_SQR5_SQ5_2 c:macro@ADC_SQR5_SQ5_3 c:macro@ADC_SQR5_SQ5_4 c:macro@ADC_SQR5_SQ6 c:macro@ADC_SQR5_SQ6_0 c:macro@ADC_SQR5_SQ6_1 c:macro@ADC_SQR5_SQ6_2 c:macro@ADC_SQR5_SQ6_3 c:macro@ADC_SQR5_SQ6_4 c:macro@ADC_JSQR_JSQ1 c:macro@ADC_JSQR_JSQ1_0 c:macro@ADC_JSQR_JSQ1_1 c:macro@ADC_JSQR_JSQ1_2 c:macro@ADC_JSQR_JSQ1_3 c:macro@ADC_JSQR_JSQ1_4 c:macro@ADC_JSQR_JSQ2 c:macro@ADC_JSQR_JSQ2_0 c:macro@ADC_JSQR_JSQ2_1 c:macro@ADC_JSQR_JSQ2_2 c:macro@ADC_JSQR_JSQ2_3 c:macro@ADC_JSQR_JSQ2_4 c:macro@ADC_JSQR_JSQ3 c:macro@ADC_JSQR_JSQ3_0 c:macro@ADC_JSQR_JSQ3_1 c:macro@ADC_JSQR_JSQ3_2 c:macro@ADC_JSQR_JSQ3_3 c:macro@ADC_JSQR_JSQ3_4 c:macro@ADC_JSQR_JSQ4 c:macro@ADC_JSQR_JSQ4_0 c:macro@ADC_JSQR_JSQ4_1 c:macro@ADC_JSQR_JSQ4_2 c:macro@ADC_JSQR_JSQ4_3 c:macro@ADC_JSQR_JSQ4_4 c:macro@ADC_JSQR_JL c:macro@ADC_JSQR_JL_0 c:macro@ADC_JSQR_JL_1 c:macro@ADC_JDR1_JDATA c:macro@ADC_JDR2_JDATA c:macro@ADC_JDR3_JDATA c:macro@ADC_JDR4_JDATA c:macro@ADC_DR_DATA c:macro@ADC_SMPR3_SMP30 c:macro@ADC_SMPR3_SMP30_0 c:macro@ADC_SMPR3_SMP30_1 c:macro@ADC_SMPR3_SMP30_2 c:macro@ADC_SMPR3_SMP31 c:macro@ADC_SMPR3_SMP31_0 c:macro@ADC_SMPR3_SMP31_1 c:macro@ADC_SMPR3_SMP31_2 c:macro@ADC_CSR_AWD1 c:macro@ADC_CSR_EOC1 c:macro@ADC_CSR_JEOC1 c:macro@ADC_CSR_JSTRT1 c:macro@ADC_CSR_STRT1 c:macro@ADC_CSR_OVR1 c:macro@ADC_CSR_ADONS1 c:macro@ADC_CCR_ADCPRE c:macro@ADC_CCR_ADCPRE_0 c:macro@ADC_CCR_ADCPRE_1 c:macro@ADC_CCR_TSVREFE c:macro@AES_CR_EN c:macro@AES_CR_DATATYPE c:macro@AES_CR_DATATYPE_0 c:macro@AES_CR_DATATYPE_1 c:macro@AES_CR_MODE c:macro@AES_CR_MODE_0 c:macro@AES_CR_MODE_1 c:macro@AES_CR_CHMOD c:macro@AES_CR_CHMOD_0 c:macro@AES_CR_CHMOD_1 c:macro@AES_CR_CCFC c:macro@AES_CR_ERRC c:macro@AES_CR_CCIE c:macro@AES_CR_ERRIE c:macro@AES_CR_DMAINEN c:macro@AES_CR_DMAOUTEN c:macro@AES_SR_CCF c:macro@AES_SR_RDERR c:macro@AES_SR_WRERR c:macro@AES_DINR c:macro@AES_DOUTR c:macro@AES_KEYR0 c:macro@AES_KEYR1 c:macro@AES_KEYR2 c:macro@AES_KEYR3 c:macro@AES_IVR0 c:macro@AES_IVR1 c:macro@AES_IVR2 c:macro@AES_IVR3 c:macro@COMP_CSR_10KPU c:macro@COMP_CSR_400KPU c:macro@COMP_CSR_10KPD c:macro@COMP_CSR_400KPD c:macro@COMP_CSR_CMP1EN c:macro@COMP_CSR_SW1 c:macro@COMP_CSR_CMP1OUT c:macro@COMP_CSR_SPEED c:macro@COMP_CSR_CMP2OUT c:macro@COMP_CSR_VREFOUTEN c:macro@COMP_CSR_WNDWE c:macro@COMP_CSR_INSEL c:macro@COMP_CSR_INSEL_0 c:macro@COMP_CSR_INSEL_1 c:macro@COMP_CSR_INSEL_2 c:macro@COMP_CSR_OUTSEL c:macro@COMP_CSR_OUTSEL_0 c:macro@COMP_CSR_OUTSEL_1 c:macro@COMP_CSR_OUTSEL_2 c:macro@COMP_CSR_FCH3 c:macro@COMP_CSR_FCH8 c:macro@COMP_CSR_RCH13 c:macro@COMP_CSR_CAIE c:macro@COMP_CSR_CAIF c:macro@COMP_CSR_TSUSP c:macro@OPAMP_CSR_OPA1PD c:macro@OPAMP_CSR_S3SEL1 c:macro@OPAMP_CSR_S4SEL1 c:macro@OPAMP_CSR_S5SEL1 c:macro@OPAMP_CSR_S6SEL1 c:macro@OPAMP_CSR_OPA1CAL_L c:macro@OPAMP_CSR_OPA1CAL_H c:macro@OPAMP_CSR_OPA1LPM c:macro@OPAMP_CSR_OPA2PD c:macro@OPAMP_CSR_S3SEL2 c:macro@OPAMP_CSR_S4SEL2 c:macro@OPAMP_CSR_S5SEL2 c:macro@OPAMP_CSR_S6SEL2 c:macro@OPAMP_CSR_OPA2CAL_L c:macro@OPAMP_CSR_OPA2CAL_H c:macro@OPAMP_CSR_OPA2LPM c:macro@OPAMP_CSR_OPA3PD c:macro@OPAMP_CSR_S3SEL3 c:macro@OPAMP_CSR_S4SEL3 c:macro@OPAMP_CSR_S5SEL3 c:macro@OPAMP_CSR_S6SEL3 c:macro@OPAMP_CSR_OPA3CAL_L c:macro@OPAMP_CSR_OPA3CAL_H c:macro@OPAMP_CSR_OPA3LPM c:macro@OPAMP_CSR_ANAWSEL1 c:macro@OPAMP_CSR_ANAWSEL2 c:macro@OPAMP_CSR_ANAWSEL3 c:macro@OPAMP_CSR_S7SEL2 c:macro@OPAMP_CSR_AOP_RANGE c:macro@OPAMP_CSR_OPA1CALOUT c:macro@OPAMP_CSR_OPA2CALOUT c:macro@OPAMP_CSR_OPA3CALOUT c:macro@OPAMP_OTR_AO1_OPT_OFFSET_TRIM c:macro@OPAMP_OTR_AO2_OPT_OFFSET_TRIM c:macro@OPAMP_OTR_AO3_OPT_OFFSET_TRIM c:macro@OPAMP_OTR_OT_USER c:macro@OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP c:macro@OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP c:macro@OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP c:macro@CRC_DR_DR c:macro@CRC_IDR_IDR c:macro@CRC_CR_RESET c:macro@DAC_CR_EN1 c:macro@DAC_CR_BOFF1 c:macro@DAC_CR_TEN1 c:macro@DAC_CR_TSEL1 c:macro@DAC_CR_TSEL1_0 c:macro@DAC_CR_TSEL1_1 c:macro@DAC_CR_TSEL1_2 c:macro@DAC_CR_WAVE1 c:macro@DAC_CR_WAVE1_0 c:macro@DAC_CR_WAVE1_1 c:macro@DAC_CR_MAMP1 c:macro@DAC_CR_MAMP1_0 c:macro@DAC_CR_MAMP1_1 c:macro@DAC_CR_MAMP1_2 c:macro@DAC_CR_MAMP1_3 c:macro@DAC_CR_DMAEN1 c:macro@DAC_CR_DMAUDRIE1 c:macro@DAC_CR_EN2 c:macro@DAC_CR_BOFF2 c:macro@DAC_CR_TEN2 c:macro@DAC_CR_TSEL2 c:macro@DAC_CR_TSEL2_0 c:macro@DAC_CR_TSEL2_1 c:macro@DAC_CR_TSEL2_2 c:macro@DAC_CR_WAVE2 c:macro@DAC_CR_WAVE2_0 c:macro@DAC_CR_WAVE2_1 c:macro@DAC_CR_MAMP2 c:macro@DAC_CR_MAMP2_0 c:macro@DAC_CR_MAMP2_1 c:macro@DAC_CR_MAMP2_2 c:macro@DAC_CR_MAMP2_3 c:macro@DAC_CR_DMAEN2 c:macro@DAC_CR_DMAUDRIE2 c:macro@DAC_SWTRIGR_SWTRIG1 c:macro@DAC_SWTRIGR_SWTRIG2 c:macro@DAC_DHR12R1_DACC1DHR c:macro@DAC_DHR12L1_DACC1DHR c:macro@DAC_DHR8R1_DACC1DHR c:macro@DAC_DHR12R2_DACC2DHR c:macro@DAC_DHR12L2_DACC2DHR c:macro@DAC_DHR8R2_DACC2DHR c:macro@DAC_DHR12RD_DACC1DHR c:macro@DAC_DHR12RD_DACC2DHR c:macro@DAC_DHR12LD_DACC1DHR c:macro@DAC_DHR12LD_DACC2DHR c:macro@DAC_DHR8RD_DACC1DHR c:macro@DAC_DHR8RD_DACC2DHR c:macro@DAC_DOR1_DACC1DOR c:macro@DAC_DOR2_DACC2DOR c:macro@DAC_SR_DMAUDR1 c:macro@DAC_SR_DMAUDR2 c:macro@DBGMCU_IDCODE_DEV_ID c:macro@DBGMCU_IDCODE_REV_ID c:macro@DBGMCU_IDCODE_REV_ID_0 c:macro@DBGMCU_IDCODE_REV_ID_1 c:macro@DBGMCU_IDCODE_REV_ID_2 c:macro@DBGMCU_IDCODE_REV_ID_3 c:macro@DBGMCU_IDCODE_REV_ID_4 c:macro@DBGMCU_IDCODE_REV_ID_5 c:macro@DBGMCU_IDCODE_REV_ID_6 c:macro@DBGMCU_IDCODE_REV_ID_7 c:macro@DBGMCU_IDCODE_REV_ID_8 c:macro@DBGMCU_IDCODE_REV_ID_9 c:macro@DBGMCU_IDCODE_REV_ID_10 c:macro@DBGMCU_IDCODE_REV_ID_11 c:macro@DBGMCU_IDCODE_REV_ID_12 c:macro@DBGMCU_IDCODE_REV_ID_13 c:macro@DBGMCU_IDCODE_REV_ID_14 c:macro@DBGMCU_IDCODE_REV_ID_15 c:macro@DBGMCU_CR_DBG_SLEEP c:macro@DBGMCU_CR_DBG_STOP c:macro@DBGMCU_CR_DBG_STANDBY c:macro@DBGMCU_CR_TRACE_IOEN c:macro@DBGMCU_CR_TRACE_MODE c:macro@DBGMCU_CR_TRACE_MODE_0 c:macro@DBGMCU_CR_TRACE_MODE_1 c:macro@DBGMCU_APB1_FZ_DBG_TIM2_STOP c:macro@DBGMCU_APB1_FZ_DBG_TIM3_STOP c:macro@DBGMCU_APB1_FZ_DBG_TIM4_STOP c:macro@DBGMCU_APB1_FZ_DBG_TIM5_STOP c:macro@DBGMCU_APB1_FZ_DBG_TIM6_STOP c:macro@DBGMCU_APB1_FZ_DBG_TIM7_STOP c:macro@DBGMCU_APB1_FZ_DBG_RTC_STOP c:macro@DBGMCU_APB1_FZ_DBG_WWDG_STOP c:macro@DBGMCU_APB1_FZ_DBG_IWDG_STOP c:macro@DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT c:macro@DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT c:macro@DBGMCU_APB2_FZ_DBG_TIM9_STOP c:macro@DBGMCU_APB2_FZ_DBG_TIM10_STOP c:macro@DBGMCU_APB2_FZ_DBG_TIM11_STOP c:macro@DMA_ISR_GIF1 c:macro@DMA_ISR_TCIF1 c:macro@DMA_ISR_HTIF1 c:macro@DMA_ISR_TEIF1 c:macro@DMA_ISR_GIF2 c:macro@DMA_ISR_TCIF2 c:macro@DMA_ISR_HTIF2 c:macro@DMA_ISR_TEIF2 c:macro@DMA_ISR_GIF3 c:macro@DMA_ISR_TCIF3 c:macro@DMA_ISR_HTIF3 c:macro@DMA_ISR_TEIF3 c:macro@DMA_ISR_GIF4 c:macro@DMA_ISR_TCIF4 c:macro@DMA_ISR_HTIF4 c:macro@DMA_ISR_TEIF4 c:macro@DMA_ISR_GIF5 c:macro@DMA_ISR_TCIF5 c:macro@DMA_ISR_HTIF5 c:macro@DMA_ISR_TEIF5 c:macro@DMA_ISR_GIF6 c:macro@DMA_ISR_TCIF6 c:macro@DMA_ISR_HTIF6 c:macro@DMA_ISR_TEIF6 c:macro@DMA_ISR_GIF7 c:macro@DMA_ISR_TCIF7 c:macro@DMA_ISR_HTIF7 c:macro@DMA_ISR_TEIF7 c:macro@DMA_IFCR_CGIF1 c:macro@DMA_IFCR_CTCIF1 c:macro@DMA_IFCR_CHTIF1 c:macro@DMA_IFCR_CTEIF1 c:macro@DMA_IFCR_CGIF2 c:macro@DMA_IFCR_CTCIF2 c:macro@DMA_IFCR_CHTIF2 c:macro@DMA_IFCR_CTEIF2 c:macro@DMA_IFCR_CGIF3 c:macro@DMA_IFCR_CTCIF3 c:macro@DMA_IFCR_CHTIF3 c:macro@DMA_IFCR_CTEIF3 c:macro@DMA_IFCR_CGIF4 c:macro@DMA_IFCR_CTCIF4 c:macro@DMA_IFCR_CHTIF4 c:macro@DMA_IFCR_CTEIF4 c:macro@DMA_IFCR_CGIF5 c:macro@DMA_IFCR_CTCIF5 c:macro@DMA_IFCR_CHTIF5 c:macro@DMA_IFCR_CTEIF5 c:macro@DMA_IFCR_CGIF6 c:macro@DMA_IFCR_CTCIF6 c:macro@DMA_IFCR_CHTIF6 c:macro@DMA_IFCR_CTEIF6 c:macro@DMA_IFCR_CGIF7 c:macro@DMA_IFCR_CTCIF7 c:macro@DMA_IFCR_CHTIF7 c:macro@DMA_IFCR_CTEIF7 c:macro@DMA_CCR1_EN c:macro@DMA_CCR1_TCIE c:macro@DMA_CCR1_HTIE c:macro@DMA_CCR1_TEIE c:macro@DMA_CCR1_DIR c:macro@DMA_CCR1_CIRC c:macro@DMA_CCR1_PINC c:macro@DMA_CCR1_MINC c:macro@DMA_CCR1_PSIZE c:macro@DMA_CCR1_PSIZE_0 c:macro@DMA_CCR1_PSIZE_1 c:macro@DMA_CCR1_MSIZE c:macro@DMA_CCR1_MSIZE_0 c:macro@DMA_CCR1_MSIZE_1 c:macro@DMA_CCR1_PL c:macro@DMA_CCR1_PL_0 c:macro@DMA_CCR1_PL_1 c:macro@DMA_CCR1_MEM2MEM c:macro@DMA_CCR2_EN c:macro@DMA_CCR2_TCIE c:macro@DMA_CCR2_HTIE c:macro@DMA_CCR2_TEIE c:macro@DMA_CCR2_DIR c:macro@DMA_CCR2_CIRC c:macro@DMA_CCR2_PINC c:macro@DMA_CCR2_MINC c:macro@DMA_CCR2_PSIZE c:macro@DMA_CCR2_PSIZE_0 c:macro@DMA_CCR2_PSIZE_1 c:macro@DMA_CCR2_MSIZE c:macro@DMA_CCR2_MSIZE_0 c:macro@DMA_CCR2_MSIZE_1 c:macro@DMA_CCR2_PL c:macro@DMA_CCR2_PL_0 c:macro@DMA_CCR2_PL_1 c:macro@DMA_CCR2_MEM2MEM c:macro@DMA_CCR3_EN c:macro@DMA_CCR3_TCIE c:macro@DMA_CCR3_HTIE c:macro@DMA_CCR3_TEIE c:macro@DMA_CCR3_DIR c:macro@DMA_CCR3_CIRC c:macro@DMA_CCR3_PINC c:macro@DMA_CCR3_MINC c:macro@DMA_CCR3_PSIZE c:macro@DMA_CCR3_PSIZE_0 c:macro@DMA_CCR3_PSIZE_1 c:macro@DMA_CCR3_MSIZE c:macro@DMA_CCR3_MSIZE_0 c:macro@DMA_CCR3_MSIZE_1 c:macro@DMA_CCR3_PL c:macro@DMA_CCR3_PL_0 c:macro@DMA_CCR3_PL_1 c:macro@DMA_CCR3_MEM2MEM c:macro@DMA_CCR4_EN c:macro@DMA_CCR4_TCIE c:macro@DMA_CCR4_HTIE c:macro@DMA_CCR4_TEIE c:macro@DMA_CCR4_DIR c:macro@DMA_CCR4_CIRC c:macro@DMA_CCR4_PINC c:macro@DMA_CCR4_MINC c:macro@DMA_CCR4_PSIZE c:macro@DMA_CCR4_PSIZE_0 c:macro@DMA_CCR4_PSIZE_1 c:macro@DMA_CCR4_MSIZE c:macro@DMA_CCR4_MSIZE_0 c:macro@DMA_CCR4_MSIZE_1 c:macro@DMA_CCR4_PL c:macro@DMA_CCR4_PL_0 c:macro@DMA_CCR4_PL_1 c:macro@DMA_CCR4_MEM2MEM c:macro@DMA_CCR5_EN c:macro@DMA_CCR5_TCIE c:macro@DMA_CCR5_HTIE c:macro@DMA_CCR5_TEIE c:macro@DMA_CCR5_DIR c:macro@DMA_CCR5_CIRC c:macro@DMA_CCR5_PINC c:macro@DMA_CCR5_MINC c:macro@DMA_CCR5_PSIZE c:macro@DMA_CCR5_PSIZE_0 c:macro@DMA_CCR5_PSIZE_1 c:macro@DMA_CCR5_MSIZE c:macro@DMA_CCR5_MSIZE_0 c:macro@DMA_CCR5_MSIZE_1 c:macro@DMA_CCR5_PL c:macro@DMA_CCR5_PL_0 c:macro@DMA_CCR5_PL_1 c:macro@DMA_CCR5_MEM2MEM c:macro@DMA_CCR6_EN c:macro@DMA_CCR6_TCIE c:macro@DMA_CCR6_HTIE c:macro@DMA_CCR6_TEIE c:macro@DMA_CCR6_DIR c:macro@DMA_CCR6_CIRC c:macro@DMA_CCR6_PINC c:macro@DMA_CCR6_MINC c:macro@DMA_CCR6_PSIZE c:macro@DMA_CCR6_PSIZE_0 c:macro@DMA_CCR6_PSIZE_1 c:macro@DMA_CCR6_MSIZE c:macro@DMA_CCR6_MSIZE_0 c:macro@DMA_CCR6_MSIZE_1 c:macro@DMA_CCR6_PL c:macro@DMA_CCR6_PL_0 c:macro@DMA_CCR6_PL_1 c:macro@DMA_CCR6_MEM2MEM c:macro@DMA_CCR7_EN c:macro@DMA_CCR7_TCIE c:macro@DMA_CCR7_HTIE c:macro@DMA_CCR7_TEIE c:macro@DMA_CCR7_DIR c:macro@DMA_CCR7_CIRC c:macro@DMA_CCR7_PINC c:macro@DMA_CCR7_MINC c:macro@DMA_CCR7_PSIZE c:macro@DMA_CCR7_PSIZE_0 c:macro@DMA_CCR7_PSIZE_1 c:macro@DMA_CCR7_MSIZE c:macro@DMA_CCR7_MSIZE_0 c:macro@DMA_CCR7_MSIZE_1 c:macro@DMA_CCR7_PL c:macro@DMA_CCR7_PL_0 c:macro@DMA_CCR7_PL_1 c:macro@DMA_CCR7_MEM2MEM c:macro@DMA_CNDTR1_NDT c:macro@DMA_CNDTR2_NDT c:macro@DMA_CNDTR3_NDT c:macro@DMA_CNDTR4_NDT c:macro@DMA_CNDTR5_NDT c:macro@DMA_CNDTR6_NDT c:macro@DMA_CNDTR7_NDT c:macro@DMA_CPAR1_PA c:macro@DMA_CPAR2_PA c:macro@DMA_CPAR3_PA c:macro@DMA_CPAR4_PA c:macro@DMA_CPAR5_PA c:macro@DMA_CPAR6_PA c:macro@DMA_CPAR7_PA c:macro@DMA_CMAR1_MA c:macro@DMA_CMAR2_MA c:macro@DMA_CMAR3_MA c:macro@DMA_CMAR4_MA c:macro@DMA_CMAR5_MA c:macro@DMA_CMAR6_MA c:macro@DMA_CMAR7_MA c:macro@EXTI_IMR_MR0 c:macro@EXTI_IMR_MR1 c:macro@EXTI_IMR_MR2 c:macro@EXTI_IMR_MR3 c:macro@EXTI_IMR_MR4 c:macro@EXTI_IMR_MR5 c:macro@EXTI_IMR_MR6 c:macro@EXTI_IMR_MR7 c:macro@EXTI_IMR_MR8 c:macro@EXTI_IMR_MR9 c:macro@EXTI_IMR_MR10 c:macro@EXTI_IMR_MR11 c:macro@EXTI_IMR_MR12 c:macro@EXTI_IMR_MR13 c:macro@EXTI_IMR_MR14 c:macro@EXTI_IMR_MR15 c:macro@EXTI_IMR_MR16 c:macro@EXTI_IMR_MR17 c:macro@EXTI_IMR_MR18 c:macro@EXTI_IMR_MR19 c:macro@EXTI_IMR_MR20 c:macro@EXTI_IMR_MR21 c:macro@EXTI_IMR_MR22 c:macro@EXTI_IMR_MR23 c:macro@EXTI_EMR_MR0 c:macro@EXTI_EMR_MR1 c:macro@EXTI_EMR_MR2 c:macro@EXTI_EMR_MR3 c:macro@EXTI_EMR_MR4 c:macro@EXTI_EMR_MR5 c:macro@EXTI_EMR_MR6 c:macro@EXTI_EMR_MR7 c:macro@EXTI_EMR_MR8 c:macro@EXTI_EMR_MR9 c:macro@EXTI_EMR_MR10 c:macro@EXTI_EMR_MR11 c:macro@EXTI_EMR_MR12 c:macro@EXTI_EMR_MR13 c:macro@EXTI_EMR_MR14 c:macro@EXTI_EMR_MR15 c:macro@EXTI_EMR_MR16 c:macro@EXTI_EMR_MR17 c:macro@EXTI_EMR_MR18 c:macro@EXTI_EMR_MR19 c:macro@EXTI_EMR_MR20 c:macro@EXTI_EMR_MR21 c:macro@EXTI_EMR_MR22 c:macro@EXTI_EMR_MR23 c:macro@EXTI_RTSR_TR0 c:macro@EXTI_RTSR_TR1 c:macro@EXTI_RTSR_TR2 c:macro@EXTI_RTSR_TR3 c:macro@EXTI_RTSR_TR4 c:macro@EXTI_RTSR_TR5 c:macro@EXTI_RTSR_TR6 c:macro@EXTI_RTSR_TR7 c:macro@EXTI_RTSR_TR8 c:macro@EXTI_RTSR_TR9 c:macro@EXTI_RTSR_TR10 c:macro@EXTI_RTSR_TR11 c:macro@EXTI_RTSR_TR12 c:macro@EXTI_RTSR_TR13 c:macro@EXTI_RTSR_TR14 c:macro@EXTI_RTSR_TR15 c:macro@EXTI_RTSR_TR16 c:macro@EXTI_RTSR_TR17 c:macro@EXTI_RTSR_TR18 c:macro@EXTI_RTSR_TR19 c:macro@EXTI_RTSR_TR20 c:macro@EXTI_RTSR_TR21 c:macro@EXTI_RTSR_TR22 c:macro@EXTI_RTSR_TR23 c:macro@EXTI_FTSR_TR0 c:macro@EXTI_FTSR_TR1 c:macro@EXTI_FTSR_TR2 c:macro@EXTI_FTSR_TR3 c:macro@EXTI_FTSR_TR4 c:macro@EXTI_FTSR_TR5 c:macro@EXTI_FTSR_TR6 c:macro@EXTI_FTSR_TR7 c:macro@EXTI_FTSR_TR8 c:macro@EXTI_FTSR_TR9 c:macro@EXTI_FTSR_TR10 c:macro@EXTI_FTSR_TR11 c:macro@EXTI_FTSR_TR12 c:macro@EXTI_FTSR_TR13 c:macro@EXTI_FTSR_TR14 c:macro@EXTI_FTSR_TR15 c:macro@EXTI_FTSR_TR16 c:macro@EXTI_FTSR_TR17 c:macro@EXTI_FTSR_TR18 c:macro@EXTI_FTSR_TR19 c:macro@EXTI_FTSR_TR20 c:macro@EXTI_FTSR_TR21 c:macro@EXTI_FTSR_TR22 c:macro@EXTI_FTSR_TR23 c:macro@EXTI_SWIER_SWIER0 c:macro@EXTI_SWIER_SWIER1 c:macro@EXTI_SWIER_SWIER2 c:macro@EXTI_SWIER_SWIER3 c:macro@EXTI_SWIER_SWIER4 c:macro@EXTI_SWIER_SWIER5 c:macro@EXTI_SWIER_SWIER6 c:macro@EXTI_SWIER_SWIER7 c:macro@EXTI_SWIER_SWIER8 c:macro@EXTI_SWIER_SWIER9 c:macro@EXTI_SWIER_SWIER10 c:macro@EXTI_SWIER_SWIER11 c:macro@EXTI_SWIER_SWIER12 c:macro@EXTI_SWIER_SWIER13 c:macro@EXTI_SWIER_SWIER14 c:macro@EXTI_SWIER_SWIER15 c:macro@EXTI_SWIER_SWIER16 c:macro@EXTI_SWIER_SWIER17 c:macro@EXTI_SWIER_SWIER18 c:macro@EXTI_SWIER_SWIER19 c:macro@EXTI_SWIER_SWIER20 c:macro@EXTI_SWIER_SWIER21 c:macro@EXTI_SWIER_SWIER22 c:macro@EXTI_SWIER_SWIER23 c:macro@EXTI_PR_PR0 c:macro@EXTI_PR_PR1 c:macro@EXTI_PR_PR2 c:macro@EXTI_PR_PR3 c:macro@EXTI_PR_PR4 c:macro@EXTI_PR_PR5 c:macro@EXTI_PR_PR6 c:macro@EXTI_PR_PR7 c:macro@EXTI_PR_PR8 c:macro@EXTI_PR_PR9 c:macro@EXTI_PR_PR10 c:macro@EXTI_PR_PR11 c:macro@EXTI_PR_PR12 c:macro@EXTI_PR_PR13 c:macro@EXTI_PR_PR14 c:macro@EXTI_PR_PR15 c:macro@EXTI_PR_PR16 c:macro@EXTI_PR_PR17 c:macro@EXTI_PR_PR18 c:macro@EXTI_PR_PR19 c:macro@EXTI_PR_PR20 c:macro@EXTI_PR_PR21 c:macro@EXTI_PR_PR22 c:macro@EXTI_PR_PR23 c:macro@FLASH_ACR_LATENCY c:macro@FLASH_ACR_PRFTEN c:macro@FLASH_ACR_ACC64 c:macro@FLASH_ACR_SLEEP_PD c:macro@FLASH_ACR_RUN_PD c:macro@FLASH_PECR_PELOCK c:macro@FLASH_PECR_PRGLOCK c:macro@FLASH_PECR_OPTLOCK c:macro@FLASH_PECR_PROG c:macro@FLASH_PECR_DATA c:macro@FLASH_PECR_FTDW c:macro@FLASH_PECR_ERASE c:macro@FLASH_PECR_FPRG c:macro@FLASH_PECR_PARALLBANK c:macro@FLASH_PECR_EOPIE c:macro@FLASH_PECR_ERRIE c:macro@FLASH_PECR_OBL_LAUNCH c:macro@FLASH_PDKEYR_PDKEYR c:macro@FLASH_PEKEYR_PEKEYR c:macro@FLASH_PRGKEYR_PRGKEYR c:macro@FLASH_OPTKEYR_OPTKEYR c:macro@FLASH_SR_BSY c:macro@FLASH_SR_EOP c:macro@FLASH_SR_ENHV c:macro@FLASH_SR_READY c:macro@FLASH_SR_WRPERR c:macro@FLASH_SR_PGAERR c:macro@FLASH_SR_SIZERR c:macro@FLASH_SR_OPTVERR c:macro@FLASH_SR_OPTVERRUSR c:macro@FLASH_OBR_RDPRT c:macro@FLASH_OBR_BOR_LEV c:macro@FLASH_OBR_USER c:macro@FLASH_OBR_IWDG_SW c:macro@FLASH_OBR_nRST_STOP c:macro@FLASH_OBR_nRST_STDBY c:macro@FLASH_OBR_nRST_BFB2 c:macro@FLASH_WRPR_WRP c:macro@FLASH_WRPR1_WRP c:macro@FLASH_WRPR2_WRP c:macro@FSMC_BCR1_MBKEN c:macro@FSMC_BCR1_MUXEN c:macro@FSMC_BCR1_MTYP c:macro@FSMC_BCR1_MTYP_0 c:macro@FSMC_BCR1_MTYP_1 c:macro@FSMC_BCR1_MWID c:macro@FSMC_BCR1_MWID_0 c:macro@FSMC_BCR1_MWID_1 c:macro@FSMC_BCR1_FACCEN c:macro@FSMC_BCR1_BURSTEN c:macro@FSMC_BCR1_WAITPOL c:macro@FSMC_BCR1_WRAPMOD c:macro@FSMC_BCR1_WAITCFG c:macro@FSMC_BCR1_WREN c:macro@FSMC_BCR1_WAITEN c:macro@FSMC_BCR1_EXTMOD c:macro@FSMC_BCR1_ASYNCWAIT c:macro@FSMC_BCR1_CBURSTRW c:macro@FSMC_BCR2_MBKEN c:macro@FSMC_BCR2_MUXEN c:macro@FSMC_BCR2_MTYP c:macro@FSMC_BCR2_MTYP_0 c:macro@FSMC_BCR2_MTYP_1 c:macro@FSMC_BCR2_MWID c:macro@FSMC_BCR2_MWID_0 c:macro@FSMC_BCR2_MWID_1 c:macro@FSMC_BCR2_FACCEN c:macro@FSMC_BCR2_BURSTEN c:macro@FSMC_BCR2_WAITPOL c:macro@FSMC_BCR2_WRAPMOD c:macro@FSMC_BCR2_WAITCFG c:macro@FSMC_BCR2_WREN c:macro@FSMC_BCR2_WAITEN c:macro@FSMC_BCR2_EXTMOD c:macro@FSMC_BCR2_ASYNCWAIT c:macro@FSMC_BCR2_CBURSTRW c:macro@FSMC_BCR3_MBKEN c:macro@FSMC_BCR3_MUXEN c:macro@FSMC_BCR3_MTYP c:macro@FSMC_BCR3_MTYP_0 c:macro@FSMC_BCR3_MTYP_1 c:macro@FSMC_BCR3_MWID c:macro@FSMC_BCR3_MWID_0 c:macro@FSMC_BCR3_MWID_1 c:macro@FSMC_BCR3_FACCEN c:macro@FSMC_BCR3_BURSTEN c:macro@FSMC_BCR3_WAITPOL c:macro@FSMC_BCR3_WRAPMOD c:macro@FSMC_BCR3_WAITCFG c:macro@FSMC_BCR3_WREN c:macro@FSMC_BCR3_WAITEN c:macro@FSMC_BCR3_EXTMOD c:macro@FSMC_BCR3_ASYNCWAIT c:macro@FSMC_BCR3_CBURSTRW c:macro@FSMC_BCR4_MBKEN c:macro@FSMC_BCR4_MUXEN c:macro@FSMC_BCR4_MTYP c:macro@FSMC_BCR4_MTYP_0 c:macro@FSMC_BCR4_MTYP_1 c:macro@FSMC_BCR4_MWID c:macro@FSMC_BCR4_MWID_0 c:macro@FSMC_BCR4_MWID_1 c:macro@FSMC_BCR4_FACCEN c:macro@FSMC_BCR4_BURSTEN c:macro@FSMC_BCR4_WAITPOL c:macro@FSMC_BCR4_WRAPMOD c:macro@FSMC_BCR4_WAITCFG c:macro@FSMC_BCR4_WREN c:macro@FSMC_BCR4_WAITEN c:macro@FSMC_BCR4_EXTMOD c:macro@FSMC_BCR4_ASYNCWAIT c:macro@FSMC_BCR4_CBURSTRW c:macro@FSMC_BTR1_ADDSET c:macro@FSMC_BTR1_ADDSET_0 c:macro@FSMC_BTR1_ADDSET_1 c:macro@FSMC_BTR1_ADDSET_2 c:macro@FSMC_BTR1_ADDSET_3 c:macro@FSMC_BTR1_ADDHLD c:macro@FSMC_BTR1_ADDHLD_0 c:macro@FSMC_BTR1_ADDHLD_1 c:macro@FSMC_BTR1_ADDHLD_2 c:macro@FSMC_BTR1_ADDHLD_3 c:macro@FSMC_BTR1_DATAST c:macro@FSMC_BTR1_DATAST_0 c:macro@FSMC_BTR1_DATAST_1 c:macro@FSMC_BTR1_DATAST_2 c:macro@FSMC_BTR1_DATAST_3 c:macro@FSMC_BTR1_BUSTURN c:macro@FSMC_BTR1_BUSTURN_0 c:macro@FSMC_BTR1_BUSTURN_1 c:macro@FSMC_BTR1_BUSTURN_2 c:macro@FSMC_BTR1_BUSTURN_3 c:macro@FSMC_BTR1_CLKDIV c:macro@FSMC_BTR1_CLKDIV_0 c:macro@FSMC_BTR1_CLKDIV_1 c:macro@FSMC_BTR1_CLKDIV_2 c:macro@FSMC_BTR1_CLKDIV_3 c:macro@FSMC_BTR1_DATLAT c:macro@FSMC_BTR1_DATLAT_0 c:macro@FSMC_BTR1_DATLAT_1 c:macro@FSMC_BTR1_DATLAT_2 c:macro@FSMC_BTR1_DATLAT_3 c:macro@FSMC_BTR1_ACCMOD c:macro@FSMC_BTR1_ACCMOD_0 c:macro@FSMC_BTR1_ACCMOD_1 c:macro@FSMC_BTR2_ADDSET c:macro@FSMC_BTR2_ADDSET_0 c:macro@FSMC_BTR2_ADDSET_1 c:macro@FSMC_BTR2_ADDSET_2 c:macro@FSMC_BTR2_ADDSET_3 c:macro@FSMC_BTR2_ADDHLD c:macro@FSMC_BTR2_ADDHLD_0 c:macro@FSMC_BTR2_ADDHLD_1 c:macro@FSMC_BTR2_ADDHLD_2 c:macro@FSMC_BTR2_ADDHLD_3 c:macro@FSMC_BTR2_DATAST c:macro@FSMC_BTR2_DATAST_0 c:macro@FSMC_BTR2_DATAST_1 c:macro@FSMC_BTR2_DATAST_2 c:macro@FSMC_BTR2_DATAST_3 c:macro@FSMC_BTR2_BUSTURN c:macro@FSMC_BTR2_BUSTURN_0 c:macro@FSMC_BTR2_BUSTURN_1 c:macro@FSMC_BTR2_BUSTURN_2 c:macro@FSMC_BTR2_BUSTURN_3 c:macro@FSMC_BTR2_CLKDIV c:macro@FSMC_BTR2_CLKDIV_0 c:macro@FSMC_BTR2_CLKDIV_1 c:macro@FSMC_BTR2_CLKDIV_2 c:macro@FSMC_BTR2_CLKDIV_3 c:macro@FSMC_BTR2_DATLAT c:macro@FSMC_BTR2_DATLAT_0 c:macro@FSMC_BTR2_DATLAT_1 c:macro@FSMC_BTR2_DATLAT_2 c:macro@FSMC_BTR2_DATLAT_3 c:macro@FSMC_BTR2_ACCMOD c:macro@FSMC_BTR2_ACCMOD_0 c:macro@FSMC_BTR2_ACCMOD_1 c:macro@FSMC_BTR3_ADDSET c:macro@FSMC_BTR3_ADDSET_0 c:macro@FSMC_BTR3_ADDSET_1 c:macro@FSMC_BTR3_ADDSET_2 c:macro@FSMC_BTR3_ADDSET_3 c:macro@FSMC_BTR3_ADDHLD c:macro@FSMC_BTR3_ADDHLD_0 c:macro@FSMC_BTR3_ADDHLD_1 c:macro@FSMC_BTR3_ADDHLD_2 c:macro@FSMC_BTR3_ADDHLD_3 c:macro@FSMC_BTR3_DATAST c:macro@FSMC_BTR3_DATAST_0 c:macro@FSMC_BTR3_DATAST_1 c:macro@FSMC_BTR3_DATAST_2 c:macro@FSMC_BTR3_DATAST_3 c:macro@FSMC_BTR3_BUSTURN c:macro@FSMC_BTR3_BUSTURN_0 c:macro@FSMC_BTR3_BUSTURN_1 c:macro@FSMC_BTR3_BUSTURN_2 c:macro@FSMC_BTR3_BUSTURN_3 c:macro@FSMC_BTR3_CLKDIV c:macro@FSMC_BTR3_CLKDIV_0 c:macro@FSMC_BTR3_CLKDIV_1 c:macro@FSMC_BTR3_CLKDIV_2 c:macro@FSMC_BTR3_CLKDIV_3 c:macro@FSMC_BTR3_DATLAT c:macro@FSMC_BTR3_DATLAT_0 c:macro@FSMC_BTR3_DATLAT_1 c:macro@FSMC_BTR3_DATLAT_2 c:macro@FSMC_BTR3_DATLAT_3 c:macro@FSMC_BTR3_ACCMOD c:macro@FSMC_BTR3_ACCMOD_0 c:macro@FSMC_BTR3_ACCMOD_1 c:macro@FSMC_BTR4_ADDSET c:macro@FSMC_BTR4_ADDSET_0 c:macro@FSMC_BTR4_ADDSET_1 c:macro@FSMC_BTR4_ADDSET_2 c:macro@FSMC_BTR4_ADDSET_3 c:macro@FSMC_BTR4_ADDHLD c:macro@FSMC_BTR4_ADDHLD_0 c:macro@FSMC_BTR4_ADDHLD_1 c:macro@FSMC_BTR4_ADDHLD_2 c:macro@FSMC_BTR4_ADDHLD_3 c:macro@FSMC_BTR4_DATAST c:macro@FSMC_BTR4_DATAST_0 c:macro@FSMC_BTR4_DATAST_1 c:macro@FSMC_BTR4_DATAST_2 c:macro@FSMC_BTR4_DATAST_3 c:macro@FSMC_BTR4_BUSTURN c:macro@FSMC_BTR4_BUSTURN_0 c:macro@FSMC_BTR4_BUSTURN_1 c:macro@FSMC_BTR4_BUSTURN_2 c:macro@FSMC_BTR4_BUSTURN_3 c:macro@FSMC_BTR4_CLKDIV c:macro@FSMC_BTR4_CLKDIV_0 c:macro@FSMC_BTR4_CLKDIV_1 c:macro@FSMC_BTR4_CLKDIV_2 c:macro@FSMC_BTR4_CLKDIV_3 c:macro@FSMC_BTR4_DATLAT c:macro@FSMC_BTR4_DATLAT_0 c:macro@FSMC_BTR4_DATLAT_1 c:macro@FSMC_BTR4_DATLAT_2 c:macro@FSMC_BTR4_DATLAT_3 c:macro@FSMC_BTR4_ACCMOD c:macro@FSMC_BTR4_ACCMOD_0 c:macro@FSMC_BTR4_ACCMOD_1 c:macro@FSMC_BWTR1_ADDSET c:macro@FSMC_BWTR1_ADDSET_0 c:macro@FSMC_BWTR1_ADDSET_1 c:macro@FSMC_BWTR1_ADDSET_2 c:macro@FSMC_BWTR1_ADDSET_3 c:macro@FSMC_BWTR1_ADDHLD c:macro@FSMC_BWTR1_ADDHLD_0 c:macro@FSMC_BWTR1_ADDHLD_1 c:macro@FSMC_BWTR1_ADDHLD_2 c:macro@FSMC_BWTR1_ADDHLD_3 c:macro@FSMC_BWTR1_DATAST c:macro@FSMC_BWTR1_DATAST_0 c:macro@FSMC_BWTR1_DATAST_1 c:macro@FSMC_BWTR1_DATAST_2 c:macro@FSMC_BWTR1_DATAST_3 c:macro@FSMC_BWTR1_CLKDIV c:macro@FSMC_BWTR1_CLKDIV_0 c:macro@FSMC_BWTR1_CLKDIV_1 c:macro@FSMC_BWTR1_CLKDIV_2 c:macro@FSMC_BWTR1_CLKDIV_3 c:macro@FSMC_BWTR1_DATLAT c:macro@FSMC_BWTR1_DATLAT_0 c:macro@FSMC_BWTR1_DATLAT_1 c:macro@FSMC_BWTR1_DATLAT_2 c:macro@FSMC_BWTR1_DATLAT_3 c:macro@FSMC_BWTR1_ACCMOD c:macro@FSMC_BWTR1_ACCMOD_0 c:macro@FSMC_BWTR1_ACCMOD_1 c:macro@FSMC_BWTR2_ADDSET c:macro@FSMC_BWTR2_ADDSET_0 c:macro@FSMC_BWTR2_ADDSET_1 c:macro@FSMC_BWTR2_ADDSET_2 c:macro@FSMC_BWTR2_ADDSET_3 c:macro@FSMC_BWTR2_ADDHLD c:macro@FSMC_BWTR2_ADDHLD_0 c:macro@FSMC_BWTR2_ADDHLD_1 c:macro@FSMC_BWTR2_ADDHLD_2 c:macro@FSMC_BWTR2_ADDHLD_3 c:macro@FSMC_BWTR2_DATAST c:macro@FSMC_BWTR2_DATAST_0 c:macro@FSMC_BWTR2_DATAST_1 c:macro@FSMC_BWTR2_DATAST_2 c:macro@FSMC_BWTR2_DATAST_3 c:macro@FSMC_BWTR2_CLKDIV c:macro@FSMC_BWTR2_CLKDIV_0 c:macro@FSMC_BWTR2_CLKDIV_1 c:macro@FSMC_BWTR2_CLKDIV_2 c:macro@FSMC_BWTR2_CLKDIV_3 c:macro@FSMC_BWTR2_DATLAT c:macro@FSMC_BWTR2_DATLAT_0 c:macro@FSMC_BWTR2_DATLAT_1 c:macro@FSMC_BWTR2_DATLAT_2 c:macro@FSMC_BWTR2_DATLAT_3 c:macro@FSMC_BWTR2_ACCMOD c:macro@FSMC_BWTR2_ACCMOD_0 c:macro@FSMC_BWTR2_ACCMOD_1 c:macro@FSMC_BWTR3_ADDSET c:macro@FSMC_BWTR3_ADDSET_0 c:macro@FSMC_BWTR3_ADDSET_1 c:macro@FSMC_BWTR3_ADDSET_2 c:macro@FSMC_BWTR3_ADDSET_3 c:macro@FSMC_BWTR3_ADDHLD c:macro@FSMC_BWTR3_ADDHLD_0 c:macro@FSMC_BWTR3_ADDHLD_1 c:macro@FSMC_BWTR3_ADDHLD_2 c:macro@FSMC_BWTR3_ADDHLD_3 c:macro@FSMC_BWTR3_DATAST c:macro@FSMC_BWTR3_DATAST_0 c:macro@FSMC_BWTR3_DATAST_1 c:macro@FSMC_BWTR3_DATAST_2 c:macro@FSMC_BWTR3_DATAST_3 c:macro@FSMC_BWTR3_CLKDIV c:macro@FSMC_BWTR3_CLKDIV_0 c:macro@FSMC_BWTR3_CLKDIV_1 c:macro@FSMC_BWTR3_CLKDIV_2 c:macro@FSMC_BWTR3_CLKDIV_3 c:macro@FSMC_BWTR3_DATLAT c:macro@FSMC_BWTR3_DATLAT_0 c:macro@FSMC_BWTR3_DATLAT_1 c:macro@FSMC_BWTR3_DATLAT_2 c:macro@FSMC_BWTR3_DATLAT_3 c:macro@FSMC_BWTR3_ACCMOD c:macro@FSMC_BWTR3_ACCMOD_0 c:macro@FSMC_BWTR3_ACCMOD_1 c:macro@FSMC_BWTR4_ADDSET c:macro@FSMC_BWTR4_ADDSET_0 c:macro@FSMC_BWTR4_ADDSET_1 c:macro@FSMC_BWTR4_ADDSET_2 c:macro@FSMC_BWTR4_ADDSET_3 c:macro@FSMC_BWTR4_ADDHLD c:macro@FSMC_BWTR4_ADDHLD_0 c:macro@FSMC_BWTR4_ADDHLD_1 c:macro@FSMC_BWTR4_ADDHLD_2 c:macro@FSMC_BWTR4_ADDHLD_3 c:macro@FSMC_BWTR4_DATAST c:macro@FSMC_BWTR4_DATAST_0 c:macro@FSMC_BWTR4_DATAST_1 c:macro@FSMC_BWTR4_DATAST_2 c:macro@FSMC_BWTR4_DATAST_3 c:macro@FSMC_BWTR4_CLKDIV c:macro@FSMC_BWTR4_CLKDIV_0 c:macro@FSMC_BWTR4_CLKDIV_1 c:macro@FSMC_BWTR4_CLKDIV_2 c:macro@FSMC_BWTR4_CLKDIV_3 c:macro@FSMC_BWTR4_DATLAT c:macro@FSMC_BWTR4_DATLAT_0 c:macro@FSMC_BWTR4_DATLAT_1 c:macro@FSMC_BWTR4_DATLAT_2 c:macro@FSMC_BWTR4_DATLAT_3 c:macro@FSMC_BWTR4_ACCMOD c:macro@FSMC_BWTR4_ACCMOD_0 c:macro@FSMC_BWTR4_ACCMOD_1 c:macro@GPIO_MODER_MODER0 c:macro@GPIO_MODER_MODER0_0 c:macro@GPIO_MODER_MODER0_1 c:macro@GPIO_MODER_MODER1 c:macro@GPIO_MODER_MODER1_0 c:macro@GPIO_MODER_MODER1_1 c:macro@GPIO_MODER_MODER2 c:macro@GPIO_MODER_MODER2_0 c:macro@GPIO_MODER_MODER2_1 c:macro@GPIO_MODER_MODER3 c:macro@GPIO_MODER_MODER3_0 c:macro@GPIO_MODER_MODER3_1 c:macro@GPIO_MODER_MODER4 c:macro@GPIO_MODER_MODER4_0 c:macro@GPIO_MODER_MODER4_1 c:macro@GPIO_MODER_MODER5 c:macro@GPIO_MODER_MODER5_0 c:macro@GPIO_MODER_MODER5_1 c:macro@GPIO_MODER_MODER6 c:macro@GPIO_MODER_MODER6_0 c:macro@GPIO_MODER_MODER6_1 c:macro@GPIO_MODER_MODER7 c:macro@GPIO_MODER_MODER7_0 c:macro@GPIO_MODER_MODER7_1 c:macro@GPIO_MODER_MODER8 c:macro@GPIO_MODER_MODER8_0 c:macro@GPIO_MODER_MODER8_1 c:macro@GPIO_MODER_MODER9 c:macro@GPIO_MODER_MODER9_0 c:macro@GPIO_MODER_MODER9_1 c:macro@GPIO_MODER_MODER10 c:macro@GPIO_MODER_MODER10_0 c:macro@GPIO_MODER_MODER10_1 c:macro@GPIO_MODER_MODER11 c:macro@GPIO_MODER_MODER11_0 c:macro@GPIO_MODER_MODER11_1 c:macro@GPIO_MODER_MODER12 c:macro@GPIO_MODER_MODER12_0 c:macro@GPIO_MODER_MODER12_1 c:macro@GPIO_MODER_MODER13 c:macro@GPIO_MODER_MODER13_0 c:macro@GPIO_MODER_MODER13_1 c:macro@GPIO_MODER_MODER14 c:macro@GPIO_MODER_MODER14_0 c:macro@GPIO_MODER_MODER14_1 c:macro@GPIO_MODER_MODER15 c:macro@GPIO_MODER_MODER15_0 c:macro@GPIO_MODER_MODER15_1 c:macro@GPIO_OTYPER_OT_0 c:macro@GPIO_OTYPER_OT_1 c:macro@GPIO_OTYPER_OT_2 c:macro@GPIO_OTYPER_OT_3 c:macro@GPIO_OTYPER_OT_4 c:macro@GPIO_OTYPER_OT_5 c:macro@GPIO_OTYPER_OT_6 c:macro@GPIO_OTYPER_OT_7 c:macro@GPIO_OTYPER_OT_8 c:macro@GPIO_OTYPER_OT_9 c:macro@GPIO_OTYPER_OT_10 c:macro@GPIO_OTYPER_OT_11 c:macro@GPIO_OTYPER_OT_12 c:macro@GPIO_OTYPER_OT_13 c:macro@GPIO_OTYPER_OT_14 c:macro@GPIO_OTYPER_OT_15 c:macro@GPIO_OSPEEDER_OSPEEDR0 c:macro@GPIO_OSPEEDER_OSPEEDR0_0 c:macro@GPIO_OSPEEDER_OSPEEDR0_1 c:macro@GPIO_OSPEEDER_OSPEEDR1 c:macro@GPIO_OSPEEDER_OSPEEDR1_0 c:macro@GPIO_OSPEEDER_OSPEEDR1_1 c:macro@GPIO_OSPEEDER_OSPEEDR2 c:macro@GPIO_OSPEEDER_OSPEEDR2_0 c:macro@GPIO_OSPEEDER_OSPEEDR2_1 c:macro@GPIO_OSPEEDER_OSPEEDR3 c:macro@GPIO_OSPEEDER_OSPEEDR3_0 c:macro@GPIO_OSPEEDER_OSPEEDR3_1 c:macro@GPIO_OSPEEDER_OSPEEDR4 c:macro@GPIO_OSPEEDER_OSPEEDR4_0 c:macro@GPIO_OSPEEDER_OSPEEDR4_1 c:macro@GPIO_OSPEEDER_OSPEEDR5 c:macro@GPIO_OSPEEDER_OSPEEDR5_0 c:macro@GPIO_OSPEEDER_OSPEEDR5_1 c:macro@GPIO_OSPEEDER_OSPEEDR6 c:macro@GPIO_OSPEEDER_OSPEEDR6_0 c:macro@GPIO_OSPEEDER_OSPEEDR6_1 c:macro@GPIO_OSPEEDER_OSPEEDR7 c:macro@GPIO_OSPEEDER_OSPEEDR7_0 c:macro@GPIO_OSPEEDER_OSPEEDR7_1 c:macro@GPIO_OSPEEDER_OSPEEDR8 c:macro@GPIO_OSPEEDER_OSPEEDR8_0 c:macro@GPIO_OSPEEDER_OSPEEDR8_1 c:macro@GPIO_OSPEEDER_OSPEEDR9 c:macro@GPIO_OSPEEDER_OSPEEDR9_0 c:macro@GPIO_OSPEEDER_OSPEEDR9_1 c:macro@GPIO_OSPEEDER_OSPEEDR10 c:macro@GPIO_OSPEEDER_OSPEEDR10_0 c:macro@GPIO_OSPEEDER_OSPEEDR10_1 c:macro@GPIO_OSPEEDER_OSPEEDR11 c:macro@GPIO_OSPEEDER_OSPEEDR11_0 c:macro@GPIO_OSPEEDER_OSPEEDR11_1 c:macro@GPIO_OSPEEDER_OSPEEDR12 c:macro@GPIO_OSPEEDER_OSPEEDR12_0 c:macro@GPIO_OSPEEDER_OSPEEDR12_1 c:macro@GPIO_OSPEEDER_OSPEEDR13 c:macro@GPIO_OSPEEDER_OSPEEDR13_0 c:macro@GPIO_OSPEEDER_OSPEEDR13_1 c:macro@GPIO_OSPEEDER_OSPEEDR14 c:macro@GPIO_OSPEEDER_OSPEEDR14_0 c:macro@GPIO_OSPEEDER_OSPEEDR14_1 c:macro@GPIO_OSPEEDER_OSPEEDR15 c:macro@GPIO_OSPEEDER_OSPEEDR15_0 c:macro@GPIO_OSPEEDER_OSPEEDR15_1 c:macro@GPIO_PUPDR_PUPDR0 c:macro@GPIO_PUPDR_PUPDR0_0 c:macro@GPIO_PUPDR_PUPDR0_1 c:macro@GPIO_PUPDR_PUPDR1 c:macro@GPIO_PUPDR_PUPDR1_0 c:macro@GPIO_PUPDR_PUPDR1_1 c:macro@GPIO_PUPDR_PUPDR2 c:macro@GPIO_PUPDR_PUPDR2_0 c:macro@GPIO_PUPDR_PUPDR2_1 c:macro@GPIO_PUPDR_PUPDR3 c:macro@GPIO_PUPDR_PUPDR3_0 c:macro@GPIO_PUPDR_PUPDR3_1 c:macro@GPIO_PUPDR_PUPDR4 c:macro@GPIO_PUPDR_PUPDR4_0 c:macro@GPIO_PUPDR_PUPDR4_1 c:macro@GPIO_PUPDR_PUPDR5 c:macro@GPIO_PUPDR_PUPDR5_0 c:macro@GPIO_PUPDR_PUPDR5_1 c:macro@GPIO_PUPDR_PUPDR6 c:macro@GPIO_PUPDR_PUPDR6_0 c:macro@GPIO_PUPDR_PUPDR6_1 c:macro@GPIO_PUPDR_PUPDR7 c:macro@GPIO_PUPDR_PUPDR7_0 c:macro@GPIO_PUPDR_PUPDR7_1 c:macro@GPIO_PUPDR_PUPDR8 c:macro@GPIO_PUPDR_PUPDR8_0 c:macro@GPIO_PUPDR_PUPDR8_1 c:macro@GPIO_PUPDR_PUPDR9 c:macro@GPIO_PUPDR_PUPDR9_0 c:macro@GPIO_PUPDR_PUPDR9_1 c:macro@GPIO_PUPDR_PUPDR10 c:macro@GPIO_PUPDR_PUPDR10_0 c:macro@GPIO_PUPDR_PUPDR10_1 c:macro@GPIO_PUPDR_PUPDR11 c:macro@GPIO_PUPDR_PUPDR11_0 c:macro@GPIO_PUPDR_PUPDR11_1 c:macro@GPIO_PUPDR_PUPDR12 c:macro@GPIO_PUPDR_PUPDR12_0 c:macro@GPIO_PUPDR_PUPDR12_1 c:macro@GPIO_PUPDR_PUPDR13 c:macro@GPIO_PUPDR_PUPDR13_0 c:macro@GPIO_PUPDR_PUPDR13_1 c:macro@GPIO_PUPDR_PUPDR14 c:macro@GPIO_PUPDR_PUPDR14_0 c:macro@GPIO_PUPDR_PUPDR14_1 c:macro@GPIO_PUPDR_PUPDR15 c:macro@GPIO_PUPDR_PUPDR15_0 c:macro@GPIO_PUPDR_PUPDR15_1 c:macro@GPIO_IDR_IDR_0 c:macro@GPIO_IDR_IDR_1 c:macro@GPIO_IDR_IDR_2 c:macro@GPIO_IDR_IDR_3 c:macro@GPIO_IDR_IDR_4 c:macro@GPIO_IDR_IDR_5 c:macro@GPIO_IDR_IDR_6 c:macro@GPIO_IDR_IDR_7 c:macro@GPIO_IDR_IDR_8 c:macro@GPIO_IDR_IDR_9 c:macro@GPIO_IDR_IDR_10 c:macro@GPIO_IDR_IDR_11 c:macro@GPIO_IDR_IDR_12 c:macro@GPIO_IDR_IDR_13 c:macro@GPIO_IDR_IDR_14 c:macro@GPIO_IDR_IDR_15 c:macro@GPIO_OTYPER_IDR_0 c:macro@GPIO_OTYPER_IDR_1 c:macro@GPIO_OTYPER_IDR_2 c:macro@GPIO_OTYPER_IDR_3 c:macro@GPIO_OTYPER_IDR_4 c:macro@GPIO_OTYPER_IDR_5 c:macro@GPIO_OTYPER_IDR_6 c:macro@GPIO_OTYPER_IDR_7 c:macro@GPIO_OTYPER_IDR_8 c:macro@GPIO_OTYPER_IDR_9 c:macro@GPIO_OTYPER_IDR_10 c:macro@GPIO_OTYPER_IDR_11 c:macro@GPIO_OTYPER_IDR_12 c:macro@GPIO_OTYPER_IDR_13 c:macro@GPIO_OTYPER_IDR_14 c:macro@GPIO_OTYPER_IDR_15 c:macro@GPIO_ODR_ODR_0 c:macro@GPIO_ODR_ODR_1 c:macro@GPIO_ODR_ODR_2 c:macro@GPIO_ODR_ODR_3 c:macro@GPIO_ODR_ODR_4 c:macro@GPIO_ODR_ODR_5 c:macro@GPIO_ODR_ODR_6 c:macro@GPIO_ODR_ODR_7 c:macro@GPIO_ODR_ODR_8 c:macro@GPIO_ODR_ODR_9 c:macro@GPIO_ODR_ODR_10 c:macro@GPIO_ODR_ODR_11 c:macro@GPIO_ODR_ODR_12 c:macro@GPIO_ODR_ODR_13 c:macro@GPIO_ODR_ODR_14 c:macro@GPIO_ODR_ODR_15 c:macro@GPIO_OTYPER_ODR_0 c:macro@GPIO_OTYPER_ODR_1 c:macro@GPIO_OTYPER_ODR_2 c:macro@GPIO_OTYPER_ODR_3 c:macro@GPIO_OTYPER_ODR_4 c:macro@GPIO_OTYPER_ODR_5 c:macro@GPIO_OTYPER_ODR_6 c:macro@GPIO_OTYPER_ODR_7 c:macro@GPIO_OTYPER_ODR_8 c:macro@GPIO_OTYPER_ODR_9 c:macro@GPIO_OTYPER_ODR_10 c:macro@GPIO_OTYPER_ODR_11 c:macro@GPIO_OTYPER_ODR_12 c:macro@GPIO_OTYPER_ODR_13 c:macro@GPIO_OTYPER_ODR_14 c:macro@GPIO_OTYPER_ODR_15 c:macro@GPIO_BSRR_BS_0 c:macro@GPIO_BSRR_BS_1 c:macro@GPIO_BSRR_BS_2 c:macro@GPIO_BSRR_BS_3 c:macro@GPIO_BSRR_BS_4 c:macro@GPIO_BSRR_BS_5 c:macro@GPIO_BSRR_BS_6 c:macro@GPIO_BSRR_BS_7 c:macro@GPIO_BSRR_BS_8 c:macro@GPIO_BSRR_BS_9 c:macro@GPIO_BSRR_BS_10 c:macro@GPIO_BSRR_BS_11 c:macro@GPIO_BSRR_BS_12 c:macro@GPIO_BSRR_BS_13 c:macro@GPIO_BSRR_BS_14 c:macro@GPIO_BSRR_BS_15 c:macro@GPIO_BSRR_BR_0 c:macro@GPIO_BSRR_BR_1 c:macro@GPIO_BSRR_BR_2 c:macro@GPIO_BSRR_BR_3 c:macro@GPIO_BSRR_BR_4 c:macro@GPIO_BSRR_BR_5 c:macro@GPIO_BSRR_BR_6 c:macro@GPIO_BSRR_BR_7 c:macro@GPIO_BSRR_BR_8 c:macro@GPIO_BSRR_BR_9 c:macro@GPIO_BSRR_BR_10 c:macro@GPIO_BSRR_BR_11 c:macro@GPIO_BSRR_BR_12 c:macro@GPIO_BSRR_BR_13 c:macro@GPIO_BSRR_BR_14 c:macro@GPIO_BSRR_BR_15 c:macro@GPIO_LCKR_LCK0 c:macro@GPIO_LCKR_LCK1 c:macro@GPIO_LCKR_LCK2 c:macro@GPIO_LCKR_LCK3 c:macro@GPIO_LCKR_LCK4 c:macro@GPIO_LCKR_LCK5 c:macro@GPIO_LCKR_LCK6 c:macro@GPIO_LCKR_LCK7 c:macro@GPIO_LCKR_LCK8 c:macro@GPIO_LCKR_LCK9 c:macro@GPIO_LCKR_LCK10 c:macro@GPIO_LCKR_LCK11 c:macro@GPIO_LCKR_LCK12 c:macro@GPIO_LCKR_LCK13 c:macro@GPIO_LCKR_LCK14 c:macro@GPIO_LCKR_LCK15 c:macro@GPIO_LCKR_LCKK c:macro@GPIO_AFRL_AFRL0 c:macro@GPIO_AFRL_AFRL1 c:macro@GPIO_AFRL_AFRL2 c:macro@GPIO_AFRL_AFRL3 c:macro@GPIO_AFRL_AFRL4 c:macro@GPIO_AFRL_AFRL5 c:macro@GPIO_AFRL_AFRL6 c:macro@GPIO_AFRL_AFRL7 c:macro@GPIO_AFRH_AFRH8 c:macro@GPIO_AFRH_AFRH9 c:macro@GPIO_AFRH_AFRH10 c:macro@GPIO_AFRH_AFRH11 c:macro@GPIO_AFRH_AFRH12 c:macro@GPIO_AFRH_AFRH13 c:macro@GPIO_AFRH_AFRH14 c:macro@GPIO_AFRH_AFRH15 c:macro@I2C_CR1_PE c:macro@I2C_CR1_SMBUS c:macro@I2C_CR1_SMBTYPE c:macro@I2C_CR1_ENARP c:macro@I2C_CR1_ENPEC c:macro@I2C_CR1_ENGC c:macro@I2C_CR1_NOSTRETCH c:macro@I2C_CR1_START c:macro@I2C_CR1_STOP c:macro@I2C_CR1_ACK c:macro@I2C_CR1_POS c:macro@I2C_CR1_PEC c:macro@I2C_CR1_ALERT c:macro@I2C_CR1_SWRST c:macro@I2C_CR2_FREQ c:macro@I2C_CR2_FREQ_0 c:macro@I2C_CR2_FREQ_1 c:macro@I2C_CR2_FREQ_2 c:macro@I2C_CR2_FREQ_3 c:macro@I2C_CR2_FREQ_4 c:macro@I2C_CR2_FREQ_5 c:macro@I2C_CR2_ITERREN c:macro@I2C_CR2_ITEVTEN c:macro@I2C_CR2_ITBUFEN c:macro@I2C_CR2_DMAEN c:macro@I2C_CR2_LAST c:macro@I2C_OAR1_ADD1_7 c:macro@I2C_OAR1_ADD8_9 c:macro@I2C_OAR1_ADD0 c:macro@I2C_OAR1_ADD1 c:macro@I2C_OAR1_ADD2 c:macro@I2C_OAR1_ADD3 c:macro@I2C_OAR1_ADD4 c:macro@I2C_OAR1_ADD5 c:macro@I2C_OAR1_ADD6 c:macro@I2C_OAR1_ADD7 c:macro@I2C_OAR1_ADD8 c:macro@I2C_OAR1_ADD9 c:macro@I2C_OAR1_ADDMODE c:macro@I2C_OAR2_ENDUAL c:macro@I2C_OAR2_ADD2 c:macro@I2C_DR_DR c:macro@I2C_SR1_SB c:macro@I2C_SR1_ADDR c:macro@I2C_SR1_BTF c:macro@I2C_SR1_ADD10 c:macro@I2C_SR1_STOPF c:macro@I2C_SR1_RXNE c:macro@I2C_SR1_TXE c:macro@I2C_SR1_BERR c:macro@I2C_SR1_ARLO c:macro@I2C_SR1_AF c:macro@I2C_SR1_OVR c:macro@I2C_SR1_PECERR c:macro@I2C_SR1_TIMEOUT c:macro@I2C_SR1_SMBALERT c:macro@I2C_SR2_MSL c:macro@I2C_SR2_BUSY c:macro@I2C_SR2_TRA c:macro@I2C_SR2_GENCALL c:macro@I2C_SR2_SMBDEFAULT c:macro@I2C_SR2_SMBHOST c:macro@I2C_SR2_DUALF c:macro@I2C_SR2_PEC c:macro@I2C_CCR_CCR c:macro@I2C_CCR_DUTY c:macro@I2C_CCR_FS c:macro@I2C_TRISE_TRISE c:macro@IWDG_KR_KEY c:macro@IWDG_PR_PR c:macro@IWDG_PR_PR_0 c:macro@IWDG_PR_PR_1 c:macro@IWDG_PR_PR_2 c:macro@IWDG_RLR_RL c:macro@IWDG_SR_PVU c:macro@IWDG_SR_RVU c:macro@LCD_CR_LCDEN c:macro@LCD_CR_VSEL c:macro@LCD_CR_DUTY c:macro@LCD_CR_DUTY_0 c:macro@LCD_CR_DUTY_1 c:macro@LCD_CR_DUTY_2 c:macro@LCD_CR_BIAS c:macro@LCD_CR_BIAS_0 c:macro@LCD_CR_BIAS_1 c:macro@LCD_CR_MUX_SEG c:macro@LCD_FCR_HD c:macro@LCD_FCR_SOFIE c:macro@LCD_FCR_UDDIE c:macro@LCD_FCR_PON c:macro@LCD_FCR_PON_0 c:macro@LCD_FCR_PON_1 c:macro@LCD_FCR_PON_2 c:macro@LCD_FCR_DEAD c:macro@LCD_FCR_DEAD_0 c:macro@LCD_FCR_DEAD_1 c:macro@LCD_FCR_DEAD_2 c:macro@LCD_FCR_CC c:macro@LCD_FCR_CC_0 c:macro@LCD_FCR_CC_1 c:macro@LCD_FCR_CC_2 c:macro@LCD_FCR_BLINKF c:macro@LCD_FCR_BLINKF_0 c:macro@LCD_FCR_BLINKF_1 c:macro@LCD_FCR_BLINKF_2 c:macro@LCD_FCR_BLINK c:macro@LCD_FCR_BLINK_0 c:macro@LCD_FCR_BLINK_1 c:macro@LCD_FCR_DIV c:macro@LCD_FCR_PS c:macro@LCD_SR_ENS c:macro@LCD_SR_SOF c:macro@LCD_SR_UDR c:macro@LCD_SR_UDD c:macro@LCD_SR_RDY c:macro@LCD_SR_FCRSR c:macro@LCD_CLR_SOFC c:macro@LCD_CLR_UDDC c:macro@LCD_RAM_SEGMENT_DATA c:macro@PWR_CR_LPSDSR c:macro@PWR_CR_PDDS c:macro@PWR_CR_CWUF c:macro@PWR_CR_CSBF c:macro@PWR_CR_PVDE c:macro@PWR_CR_PLS c:macro@PWR_CR_PLS_0 c:macro@PWR_CR_PLS_1 c:macro@PWR_CR_PLS_2 c:macro@PWR_CR_PLS_LEV0 c:macro@PWR_CR_PLS_LEV1 c:macro@PWR_CR_PLS_LEV2 c:macro@PWR_CR_PLS_LEV3 c:macro@PWR_CR_PLS_LEV4 c:macro@PWR_CR_PLS_LEV5 c:macro@PWR_CR_PLS_LEV6 c:macro@PWR_CR_PLS_LEV7 c:macro@PWR_CR_DBP c:macro@PWR_CR_ULP c:macro@PWR_CR_FWU c:macro@PWR_CR_VOS c:macro@PWR_CR_VOS_0 c:macro@PWR_CR_VOS_1 c:macro@PWR_CR_LPRUN c:macro@PWR_CSR_WUF c:macro@PWR_CSR_SBF c:macro@PWR_CSR_PVDO c:macro@PWR_CSR_VREFINTRDYF c:macro@PWR_CSR_VOSF c:macro@PWR_CSR_REGLPF c:macro@PWR_CSR_EWUP1 c:macro@PWR_CSR_EWUP2 c:macro@PWR_CSR_EWUP3 c:macro@RCC_CR_HSION c:macro@RCC_CR_HSIRDY c:macro@RCC_CR_MSION c:macro@RCC_CR_MSIRDY c:macro@RCC_CR_HSEON c:macro@RCC_CR_HSERDY c:macro@RCC_CR_HSEBYP c:macro@RCC_CR_PLLON c:macro@RCC_CR_PLLRDY c:macro@RCC_CR_CSSON c:macro@RCC_CR_RTCPRE c:macro@RCC_CR_RTCPRE_0 c:macro@RCC_CR_RTCPRE_1 c:macro@RCC_ICSCR_HSICAL c:macro@RCC_ICSCR_HSITRIM c:macro@RCC_ICSCR_MSIRANGE c:macro@RCC_ICSCR_MSIRANGE_0 c:macro@RCC_ICSCR_MSIRANGE_1 c:macro@RCC_ICSCR_MSIRANGE_2 c:macro@RCC_ICSCR_MSIRANGE_3 c:macro@RCC_ICSCR_MSIRANGE_4 c:macro@RCC_ICSCR_MSIRANGE_5 c:macro@RCC_ICSCR_MSIRANGE_6 c:macro@RCC_ICSCR_MSICAL c:macro@RCC_ICSCR_MSITRIM c:macro@RCC_CFGR_SW c:macro@RCC_CFGR_SW_0 c:macro@RCC_CFGR_SW_1 c:macro@RCC_CFGR_SW_MSI c:macro@RCC_CFGR_SW_HSI c:macro@RCC_CFGR_SW_HSE c:macro@RCC_CFGR_SW_PLL c:macro@RCC_CFGR_SWS c:macro@RCC_CFGR_SWS_0 c:macro@RCC_CFGR_SWS_1 c:macro@RCC_CFGR_SWS_MSI c:macro@RCC_CFGR_SWS_HSI c:macro@RCC_CFGR_SWS_HSE c:macro@RCC_CFGR_SWS_PLL c:macro@RCC_CFGR_HPRE c:macro@RCC_CFGR_HPRE_0 c:macro@RCC_CFGR_HPRE_1 c:macro@RCC_CFGR_HPRE_2 c:macro@RCC_CFGR_HPRE_3 c:macro@RCC_CFGR_HPRE_DIV1 c:macro@RCC_CFGR_HPRE_DIV2 c:macro@RCC_CFGR_HPRE_DIV4 c:macro@RCC_CFGR_HPRE_DIV8 c:macro@RCC_CFGR_HPRE_DIV16 c:macro@RCC_CFGR_HPRE_DIV64 c:macro@RCC_CFGR_HPRE_DIV128 c:macro@RCC_CFGR_HPRE_DIV256 c:macro@RCC_CFGR_HPRE_DIV512 c:macro@RCC_CFGR_PPRE1 c:macro@RCC_CFGR_PPRE1_0 c:macro@RCC_CFGR_PPRE1_1 c:macro@RCC_CFGR_PPRE1_2 c:macro@RCC_CFGR_PPRE1_DIV1 c:macro@RCC_CFGR_PPRE1_DIV2 c:macro@RCC_CFGR_PPRE1_DIV4 c:macro@RCC_CFGR_PPRE1_DIV8 c:macro@RCC_CFGR_PPRE1_DIV16 c:macro@RCC_CFGR_PPRE2 c:macro@RCC_CFGR_PPRE2_0 c:macro@RCC_CFGR_PPRE2_1 c:macro@RCC_CFGR_PPRE2_2 c:macro@RCC_CFGR_PPRE2_DIV1 c:macro@RCC_CFGR_PPRE2_DIV2 c:macro@RCC_CFGR_PPRE2_DIV4 c:macro@RCC_CFGR_PPRE2_DIV8 c:macro@RCC_CFGR_PPRE2_DIV16 c:macro@RCC_CFGR_PLLSRC c:macro@RCC_CFGR_PLLSRC_HSI c:macro@RCC_CFGR_PLLSRC_HSE c:macro@RCC_CFGR_PLLMUL c:macro@RCC_CFGR_PLLMUL_0 c:macro@RCC_CFGR_PLLMUL_1 c:macro@RCC_CFGR_PLLMUL_2 c:macro@RCC_CFGR_PLLMUL_3 c:macro@RCC_CFGR_PLLMUL3 c:macro@RCC_CFGR_PLLMUL4 c:macro@RCC_CFGR_PLLMUL6 c:macro@RCC_CFGR_PLLMUL8 c:macro@RCC_CFGR_PLLMUL12 c:macro@RCC_CFGR_PLLMUL16 c:macro@RCC_CFGR_PLLMUL24 c:macro@RCC_CFGR_PLLMUL32 c:macro@RCC_CFGR_PLLMUL48 c:macro@RCC_CFGR_PLLDIV c:macro@RCC_CFGR_PLLDIV_0 c:macro@RCC_CFGR_PLLDIV_1 c:macro@RCC_CFGR_PLLDIV1 c:macro@RCC_CFGR_PLLDIV2 c:macro@RCC_CFGR_PLLDIV3 c:macro@RCC_CFGR_PLLDIV4 c:macro@RCC_CFGR_MCOSEL c:macro@RCC_CFGR_MCOSEL_0 c:macro@RCC_CFGR_MCOSEL_1 c:macro@RCC_CFGR_MCOSEL_2 c:macro@RCC_CFGR_MCO_NOCLOCK c:macro@RCC_CFGR_MCO_SYSCLK c:macro@RCC_CFGR_MCO_HSI c:macro@RCC_CFGR_MCO_MSI c:macro@RCC_CFGR_MCO_HSE c:macro@RCC_CFGR_MCO_PLL c:macro@RCC_CFGR_MCO_LSI c:macro@RCC_CFGR_MCO_LSE c:macro@RCC_CFGR_MCOPRE c:macro@RCC_CFGR_MCOPRE_0 c:macro@RCC_CFGR_MCOPRE_1 c:macro@RCC_CFGR_MCOPRE_2 c:macro@RCC_CFGR_MCO_DIV1 c:macro@RCC_CFGR_MCO_DIV2 c:macro@RCC_CFGR_MCO_DIV4 c:macro@RCC_CFGR_MCO_DIV8 c:macro@RCC_CFGR_MCO_DIV16 c:macro@RCC_CIR_LSIRDYF c:macro@RCC_CIR_LSERDYF c:macro@RCC_CIR_HSIRDYF c:macro@RCC_CIR_HSERDYF c:macro@RCC_CIR_PLLRDYF c:macro@RCC_CIR_MSIRDYF c:macro@RCC_CIR_LSECSS c:macro@RCC_CIR_CSSF c:macro@RCC_CIR_LSIRDYIE c:macro@RCC_CIR_LSERDYIE c:macro@RCC_CIR_HSIRDYIE c:macro@RCC_CIR_HSERDYIE c:macro@RCC_CIR_PLLRDYIE c:macro@RCC_CIR_MSIRDYIE c:macro@RCC_CIR_LSECSSIE c:macro@RCC_CIR_LSIRDYC c:macro@RCC_CIR_LSERDYC c:macro@RCC_CIR_HSIRDYC c:macro@RCC_CIR_HSERDYC c:macro@RCC_CIR_PLLRDYC c:macro@RCC_CIR_MSIRDYC c:macro@RCC_CIR_LSECSSC c:macro@RCC_CIR_CSSC c:macro@RCC_AHBRSTR_GPIOARST c:macro@RCC_AHBRSTR_GPIOBRST c:macro@RCC_AHBRSTR_GPIOCRST c:macro@RCC_AHBRSTR_GPIODRST c:macro@RCC_AHBRSTR_GPIOERST c:macro@RCC_AHBRSTR_GPIOHRST c:macro@RCC_AHBRSTR_GPIOFRST c:macro@RCC_AHBRSTR_GPIOGRST c:macro@RCC_AHBRSTR_CRCRST c:macro@RCC_AHBRSTR_FLITFRST c:macro@RCC_AHBRSTR_DMA1RST c:macro@RCC_AHBRSTR_DMA2RST c:macro@RCC_AHBRSTR_AESRST c:macro@RCC_AHBRSTR_FSMCRST c:macro@RCC_APB2RSTR_SYSCFGRST c:macro@RCC_APB2RSTR_TIM9RST c:macro@RCC_APB2RSTR_TIM10RST c:macro@RCC_APB2RSTR_TIM11RST c:macro@RCC_APB2RSTR_ADC1RST c:macro@RCC_APB2RSTR_SDIORST c:macro@RCC_APB2RSTR_SPI1RST c:macro@RCC_APB2RSTR_USART1RST c:macro@RCC_APB1RSTR_TIM2RST c:macro@RCC_APB1RSTR_TIM3RST c:macro@RCC_APB1RSTR_TIM4RST c:macro@RCC_APB1RSTR_TIM5RST c:macro@RCC_APB1RSTR_TIM6RST c:macro@RCC_APB1RSTR_TIM7RST c:macro@RCC_APB1RSTR_LCDRST c:macro@RCC_APB1RSTR_WWDGRST c:macro@RCC_APB1RSTR_SPI2RST c:macro@RCC_APB1RSTR_SPI3RST c:macro@RCC_APB1RSTR_USART2RST c:macro@RCC_APB1RSTR_USART3RST c:macro@RCC_APB1RSTR_UART4RST c:macro@RCC_APB1RSTR_UART5RST c:macro@RCC_APB1RSTR_I2C1RST c:macro@RCC_APB1RSTR_I2C2RST c:macro@RCC_APB1RSTR_USBRST c:macro@RCC_APB1RSTR_PWRRST c:macro@RCC_APB1RSTR_DACRST c:macro@RCC_APB1RSTR_COMPRST c:macro@RCC_AHBENR_GPIOAEN c:macro@RCC_AHBENR_GPIOBEN c:macro@RCC_AHBENR_GPIOCEN c:macro@RCC_AHBENR_GPIODEN c:macro@RCC_AHBENR_GPIOEEN c:macro@RCC_AHBENR_GPIOHEN c:macro@RCC_AHBENR_GPIOFEN c:macro@RCC_AHBENR_GPIOGEN c:macro@RCC_AHBENR_CRCEN c:macro@RCC_AHBENR_FLITFEN c:macro@RCC_AHBENR_DMA1EN c:macro@RCC_AHBENR_DMA2EN c:macro@RCC_AHBENR_AESEN c:macro@RCC_AHBENR_FSMCEN c:macro@RCC_APB2ENR_SYSCFGEN c:macro@RCC_APB2ENR_TIM9EN c:macro@RCC_APB2ENR_TIM10EN c:macro@RCC_APB2ENR_TIM11EN c:macro@RCC_APB2ENR_ADC1EN c:macro@RCC_APB2ENR_SDIOEN c:macro@RCC_APB2ENR_SPI1EN c:macro@RCC_APB2ENR_USART1EN c:macro@RCC_APB1ENR_TIM2EN c:macro@RCC_APB1ENR_TIM3EN c:macro@RCC_APB1ENR_TIM4EN c:macro@RCC_APB1ENR_TIM5EN c:macro@RCC_APB1ENR_TIM6EN c:macro@RCC_APB1ENR_TIM7EN c:macro@RCC_APB1ENR_LCDEN c:macro@RCC_APB1ENR_WWDGEN c:macro@RCC_APB1ENR_SPI2EN c:macro@RCC_APB1ENR_SPI3EN c:macro@RCC_APB1ENR_USART2EN c:macro@RCC_APB1ENR_USART3EN c:macro@RCC_APB1ENR_UART4EN c:macro@RCC_APB1ENR_UART5EN c:macro@RCC_APB1ENR_I2C1EN c:macro@RCC_APB1ENR_I2C2EN c:macro@RCC_APB1ENR_USBEN c:macro@RCC_APB1ENR_PWREN c:macro@RCC_APB1ENR_DACEN c:macro@RCC_APB1ENR_COMPEN c:macro@RCC_AHBLPENR_GPIOALPEN c:macro@RCC_AHBLPENR_GPIOBLPEN c:macro@RCC_AHBLPENR_GPIOCLPEN c:macro@RCC_AHBLPENR_GPIODLPEN c:macro@RCC_AHBLPENR_GPIOELPEN c:macro@RCC_AHBLPENR_GPIOHLPEN c:macro@RCC_AHBLPENR_GPIOFLPEN c:macro@RCC_AHBLPENR_GPIOGLPEN c:macro@RCC_AHBLPENR_CRCLPEN c:macro@RCC_AHBLPENR_FLITFLPEN c:macro@RCC_AHBLPENR_SRAMLPEN c:macro@RCC_AHBLPENR_DMA1LPEN c:macro@RCC_AHBLPENR_DMA2LPEN c:macro@RCC_AHBLPENR_AESLPEN c:macro@RCC_AHBLPENR_FSMCLPEN c:macro@RCC_APB2LPENR_SYSCFGLPEN c:macro@RCC_APB2LPENR_TIM9LPEN c:macro@RCC_APB2LPENR_TIM10LPEN c:macro@RCC_APB2LPENR_TIM11LPEN c:macro@RCC_APB2LPENR_ADC1LPEN c:macro@RCC_APB2LPENR_SDIOLPEN c:macro@RCC_APB2LPENR_SPI1LPEN c:macro@RCC_APB2LPENR_USART1LPEN c:macro@RCC_APB1LPENR_TIM2LPEN c:macro@RCC_APB1LPENR_TIM3LPEN c:macro@RCC_APB1LPENR_TIM4LPEN c:macro@RCC_APB1LPENR_TIM5LPEN c:macro@RCC_APB1LPENR_TIM6LPEN c:macro@RCC_APB1LPENR_TIM7LPEN c:macro@RCC_APB1LPENR_LCDLPEN c:macro@RCC_APB1LPENR_WWDGLPEN c:macro@RCC_APB1LPENR_SPI2LPEN c:macro@RCC_APB1LPENR_SPI3LPEN c:macro@RCC_APB1LPENR_USART2LPEN c:macro@RCC_APB1LPENR_USART3LPEN c:macro@RCC_APB1LPENR_UART4LPEN c:macro@RCC_APB1LPENR_UART5LPEN c:macro@RCC_APB1LPENR_I2C1LPEN c:macro@RCC_APB1LPENR_I2C2LPEN c:macro@RCC_APB1LPENR_USBLPEN c:macro@RCC_APB1LPENR_PWRLPEN c:macro@RCC_APB1LPENR_DACLPEN c:macro@RCC_APB1LPENR_COMPLPEN c:macro@RCC_CSR_LSION c:macro@RCC_CSR_LSIRDY c:macro@RCC_CSR_LSEON c:macro@RCC_CSR_LSERDY c:macro@RCC_CSR_LSEBYP c:macro@RCC_CSR_LSECSSON c:macro@RCC_CSR_LSECSSD c:macro@RCC_CSR_RTCSEL c:macro@RCC_CSR_RTCSEL_0 c:macro@RCC_CSR_RTCSEL_1 c:macro@RCC_CSR_RTCSEL_NOCLOCK c:macro@RCC_CSR_RTCSEL_LSE c:macro@RCC_CSR_RTCSEL_LSI c:macro@RCC_CSR_RTCSEL_HSE c:macro@RCC_CSR_RTCEN c:macro@RCC_CSR_RTCRST c:macro@RCC_CSR_RMVF c:macro@RCC_CSR_OBLRSTF c:macro@RCC_CSR_PINRSTF c:macro@RCC_CSR_PORRSTF c:macro@RCC_CSR_SFTRSTF c:macro@RCC_CSR_IWDGRSTF c:macro@RCC_CSR_WWDGRSTF c:macro@RCC_CSR_LPWRRSTF c:macro@RTC_TR_PM c:macro@RTC_TR_HT c:macro@RTC_TR_HT_0 c:macro@RTC_TR_HT_1 c:macro@RTC_TR_HU c:macro@RTC_TR_HU_0 c:macro@RTC_TR_HU_1 c:macro@RTC_TR_HU_2 c:macro@RTC_TR_HU_3 c:macro@RTC_TR_MNT c:macro@RTC_TR_MNT_0 c:macro@RTC_TR_MNT_1 c:macro@RTC_TR_MNT_2 c:macro@RTC_TR_MNU c:macro@RTC_TR_MNU_0 c:macro@RTC_TR_MNU_1 c:macro@RTC_TR_MNU_2 c:macro@RTC_TR_MNU_3 c:macro@RTC_TR_ST c:macro@RTC_TR_ST_0 c:macro@RTC_TR_ST_1 c:macro@RTC_TR_ST_2 c:macro@RTC_TR_SU c:macro@RTC_TR_SU_0 c:macro@RTC_TR_SU_1 c:macro@RTC_TR_SU_2 c:macro@RTC_TR_SU_3 c:macro@RTC_DR_YT c:macro@RTC_DR_YT_0 c:macro@RTC_DR_YT_1 c:macro@RTC_DR_YT_2 c:macro@RTC_DR_YT_3 c:macro@RTC_DR_YU c:macro@RTC_DR_YU_0 c:macro@RTC_DR_YU_1 c:macro@RTC_DR_YU_2 c:macro@RTC_DR_YU_3 c:macro@RTC_DR_WDU c:macro@RTC_DR_WDU_0 c:macro@RTC_DR_WDU_1 c:macro@RTC_DR_WDU_2 c:macro@RTC_DR_MT c:macro@RTC_DR_MU c:macro@RTC_DR_MU_0 c:macro@RTC_DR_MU_1 c:macro@RTC_DR_MU_2 c:macro@RTC_DR_MU_3 c:macro@RTC_DR_DT c:macro@RTC_DR_DT_0 c:macro@RTC_DR_DT_1 c:macro@RTC_DR_DU c:macro@RTC_DR_DU_0 c:macro@RTC_DR_DU_1 c:macro@RTC_DR_DU_2 c:macro@RTC_DR_DU_3 c:macro@RTC_CR_COE c:macro@RTC_CR_OSEL c:macro@RTC_CR_OSEL_0 c:macro@RTC_CR_OSEL_1 c:macro@RTC_CR_POL c:macro@RTC_CR_COSEL c:macro@RTC_CR_BCK c:macro@RTC_CR_SUB1H c:macro@RTC_CR_ADD1H c:macro@RTC_CR_TSIE c:macro@RTC_CR_WUTIE c:macro@RTC_CR_ALRBIE c:macro@RTC_CR_ALRAIE c:macro@RTC_CR_TSE c:macro@RTC_CR_WUTE c:macro@RTC_CR_ALRBE c:macro@RTC_CR_ALRAE c:macro@RTC_CR_DCE c:macro@RTC_CR_FMT c:macro@RTC_CR_BYPSHAD c:macro@RTC_CR_REFCKON c:macro@RTC_CR_TSEDGE c:macro@RTC_CR_WUCKSEL c:macro@RTC_CR_WUCKSEL_0 c:macro@RTC_CR_WUCKSEL_1 c:macro@RTC_CR_WUCKSEL_2 c:macro@RTC_ISR_RECALPF c:macro@RTC_ISR_TAMP3F c:macro@RTC_ISR_TAMP2F c:macro@RTC_ISR_TAMP1F c:macro@RTC_ISR_TSOVF c:macro@RTC_ISR_TSF c:macro@RTC_ISR_WUTF c:macro@RTC_ISR_ALRBF c:macro@RTC_ISR_ALRAF c:macro@RTC_ISR_INIT c:macro@RTC_ISR_INITF c:macro@RTC_ISR_RSF c:macro@RTC_ISR_INITS c:macro@RTC_ISR_SHPF c:macro@RTC_ISR_WUTWF c:macro@RTC_ISR_ALRBWF c:macro@RTC_ISR_ALRAWF c:macro@RTC_PRER_PREDIV_A c:macro@RTC_PRER_PREDIV_S c:macro@RTC_WUTR_WUT c:macro@RTC_CALIBR_DCS c:macro@RTC_CALIBR_DC c:macro@RTC_ALRMAR_MSK4 c:macro@RTC_ALRMAR_WDSEL c:macro@RTC_ALRMAR_DT c:macro@RTC_ALRMAR_DT_0 c:macro@RTC_ALRMAR_DT_1 c:macro@RTC_ALRMAR_DU c:macro@RTC_ALRMAR_DU_0 c:macro@RTC_ALRMAR_DU_1 c:macro@RTC_ALRMAR_DU_2 c:macro@RTC_ALRMAR_DU_3 c:macro@RTC_ALRMAR_MSK3 c:macro@RTC_ALRMAR_PM c:macro@RTC_ALRMAR_HT c:macro@RTC_ALRMAR_HT_0 c:macro@RTC_ALRMAR_HT_1 c:macro@RTC_ALRMAR_HU c:macro@RTC_ALRMAR_HU_0 c:macro@RTC_ALRMAR_HU_1 c:macro@RTC_ALRMAR_HU_2 c:macro@RTC_ALRMAR_HU_3 c:macro@RTC_ALRMAR_MSK2 c:macro@RTC_ALRMAR_MNT c:macro@RTC_ALRMAR_MNT_0 c:macro@RTC_ALRMAR_MNT_1 c:macro@RTC_ALRMAR_MNT_2 c:macro@RTC_ALRMAR_MNU c:macro@RTC_ALRMAR_MNU_0 c:macro@RTC_ALRMAR_MNU_1 c:macro@RTC_ALRMAR_MNU_2 c:macro@RTC_ALRMAR_MNU_3 c:macro@RTC_ALRMAR_MSK1 c:macro@RTC_ALRMAR_ST c:macro@RTC_ALRMAR_ST_0 c:macro@RTC_ALRMAR_ST_1 c:macro@RTC_ALRMAR_ST_2 c:macro@RTC_ALRMAR_SU c:macro@RTC_ALRMAR_SU_0 c:macro@RTC_ALRMAR_SU_1 c:macro@RTC_ALRMAR_SU_2 c:macro@RTC_ALRMAR_SU_3 c:macro@RTC_ALRMBR_MSK4 c:macro@RTC_ALRMBR_WDSEL c:macro@RTC_ALRMBR_DT c:macro@RTC_ALRMBR_DT_0 c:macro@RTC_ALRMBR_DT_1 c:macro@RTC_ALRMBR_DU c:macro@RTC_ALRMBR_DU_0 c:macro@RTC_ALRMBR_DU_1 c:macro@RTC_ALRMBR_DU_2 c:macro@RTC_ALRMBR_DU_3 c:macro@RTC_ALRMBR_MSK3 c:macro@RTC_ALRMBR_PM c:macro@RTC_ALRMBR_HT c:macro@RTC_ALRMBR_HT_0 c:macro@RTC_ALRMBR_HT_1 c:macro@RTC_ALRMBR_HU c:macro@RTC_ALRMBR_HU_0 c:macro@RTC_ALRMBR_HU_1 c:macro@RTC_ALRMBR_HU_2 c:macro@RTC_ALRMBR_HU_3 c:macro@RTC_ALRMBR_MSK2 c:macro@RTC_ALRMBR_MNT c:macro@RTC_ALRMBR_MNT_0 c:macro@RTC_ALRMBR_MNT_1 c:macro@RTC_ALRMBR_MNT_2 c:macro@RTC_ALRMBR_MNU c:macro@RTC_ALRMBR_MNU_0 c:macro@RTC_ALRMBR_MNU_1 c:macro@RTC_ALRMBR_MNU_2 c:macro@RTC_ALRMBR_MNU_3 c:macro@RTC_ALRMBR_MSK1 c:macro@RTC_ALRMBR_ST c:macro@RTC_ALRMBR_ST_0 c:macro@RTC_ALRMBR_ST_1 c:macro@RTC_ALRMBR_ST_2 c:macro@RTC_ALRMBR_SU c:macro@RTC_ALRMBR_SU_0 c:macro@RTC_ALRMBR_SU_1 c:macro@RTC_ALRMBR_SU_2 c:macro@RTC_ALRMBR_SU_3 c:macro@RTC_WPR_KEY c:macro@RTC_SSR_SS c:macro@RTC_SHIFTR_SUBFS c:macro@RTC_SHIFTR_ADD1S c:macro@RTC_TSTR_PM c:macro@RTC_TSTR_HT c:macro@RTC_TSTR_HT_0 c:macro@RTC_TSTR_HT_1 c:macro@RTC_TSTR_HU c:macro@RTC_TSTR_HU_0 c:macro@RTC_TSTR_HU_1 c:macro@RTC_TSTR_HU_2 c:macro@RTC_TSTR_HU_3 c:macro@RTC_TSTR_MNT c:macro@RTC_TSTR_MNT_0 c:macro@RTC_TSTR_MNT_1 c:macro@RTC_TSTR_MNT_2 c:macro@RTC_TSTR_MNU c:macro@RTC_TSTR_MNU_0 c:macro@RTC_TSTR_MNU_1 c:macro@RTC_TSTR_MNU_2 c:macro@RTC_TSTR_MNU_3 c:macro@RTC_TSTR_ST c:macro@RTC_TSTR_ST_0 c:macro@RTC_TSTR_ST_1 c:macro@RTC_TSTR_ST_2 c:macro@RTC_TSTR_SU c:macro@RTC_TSTR_SU_0 c:macro@RTC_TSTR_SU_1 c:macro@RTC_TSTR_SU_2 c:macro@RTC_TSTR_SU_3 c:macro@RTC_TSDR_WDU c:macro@RTC_TSDR_WDU_0 c:macro@RTC_TSDR_WDU_1 c:macro@RTC_TSDR_WDU_2 c:macro@RTC_TSDR_MT c:macro@RTC_TSDR_MU c:macro@RTC_TSDR_MU_0 c:macro@RTC_TSDR_MU_1 c:macro@RTC_TSDR_MU_2 c:macro@RTC_TSDR_MU_3 c:macro@RTC_TSDR_DT c:macro@RTC_TSDR_DT_0 c:macro@RTC_TSDR_DT_1 c:macro@RTC_TSDR_DU c:macro@RTC_TSDR_DU_0 c:macro@RTC_TSDR_DU_1 c:macro@RTC_TSDR_DU_2 c:macro@RTC_TSDR_DU_3 c:macro@RTC_TSSSR_SS c:macro@RTC_CALR_CALP c:macro@RTC_CALR_CALW8 c:macro@RTC_CALR_CALW16 c:macro@RTC_CALR_CALM c:macro@RTC_CALR_CALM_0 c:macro@RTC_CALR_CALM_1 c:macro@RTC_CALR_CALM_2 c:macro@RTC_CALR_CALM_3 c:macro@RTC_CALR_CALM_4 c:macro@RTC_CALR_CALM_5 c:macro@RTC_CALR_CALM_6 c:macro@RTC_CALR_CALM_7 c:macro@RTC_CALR_CALM_8 c:macro@RTC_TAFCR_ALARMOUTTYPE c:macro@RTC_TAFCR_TAMPPUDIS c:macro@RTC_TAFCR_TAMPPRCH c:macro@RTC_TAFCR_TAMPPRCH_0 c:macro@RTC_TAFCR_TAMPPRCH_1 c:macro@RTC_TAFCR_TAMPFLT c:macro@RTC_TAFCR_TAMPFLT_0 c:macro@RTC_TAFCR_TAMPFLT_1 c:macro@RTC_TAFCR_TAMPFREQ c:macro@RTC_TAFCR_TAMPFREQ_0 c:macro@RTC_TAFCR_TAMPFREQ_1 c:macro@RTC_TAFCR_TAMPFREQ_2 c:macro@RTC_TAFCR_TAMPTS c:macro@RTC_TAFCR_TAMP3TRG c:macro@RTC_TAFCR_TAMP3E c:macro@RTC_TAFCR_TAMP2TRG c:macro@RTC_TAFCR_TAMP2E c:macro@RTC_TAFCR_TAMPIE c:macro@RTC_TAFCR_TAMP1TRG c:macro@RTC_TAFCR_TAMP1E c:macro@RTC_ALRMASSR_MASKSS c:macro@RTC_ALRMASSR_MASKSS_0 c:macro@RTC_ALRMASSR_MASKSS_1 c:macro@RTC_ALRMASSR_MASKSS_2 c:macro@RTC_ALRMASSR_MASKSS_3 c:macro@RTC_ALRMASSR_SS c:macro@RTC_ALRMBSSR_MASKSS c:macro@RTC_ALRMBSSR_MASKSS_0 c:macro@RTC_ALRMBSSR_MASKSS_1 c:macro@RTC_ALRMBSSR_MASKSS_2 c:macro@RTC_ALRMBSSR_MASKSS_3 c:macro@RTC_ALRMBSSR_SS c:macro@RTC_BKP0R c:macro@RTC_BKP1R c:macro@RTC_BKP2R c:macro@RTC_BKP3R c:macro@RTC_BKP4R c:macro@RTC_BKP5R c:macro@RTC_BKP6R c:macro@RTC_BKP7R c:macro@RTC_BKP8R c:macro@RTC_BKP9R c:macro@RTC_BKP10R c:macro@RTC_BKP11R c:macro@RTC_BKP12R c:macro@RTC_BKP13R c:macro@RTC_BKP14R c:macro@RTC_BKP15R c:macro@RTC_BKP16R c:macro@RTC_BKP17R c:macro@RTC_BKP18R c:macro@RTC_BKP19R c:macro@RTC_BKP20R c:macro@RTC_BKP21R c:macro@RTC_BKP22R c:macro@RTC_BKP23R c:macro@RTC_BKP24R c:macro@RTC_BKP25R c:macro@RTC_BKP26R c:macro@RTC_BKP27R c:macro@RTC_BKP28R c:macro@RTC_BKP29R c:macro@RTC_BKP30R c:macro@RTC_BKP31R c:macro@SDIO_POWER_PWRCTRL c:macro@SDIO_POWER_PWRCTRL_0 c:macro@SDIO_POWER_PWRCTRL_1 c:macro@SDIO_CLKCR_CLKDIV c:macro@SDIO_CLKCR_CLKEN c:macro@SDIO_CLKCR_PWRSAV c:macro@SDIO_CLKCR_BYPASS c:macro@SDIO_CLKCR_WIDBUS c:macro@SDIO_CLKCR_WIDBUS_0 c:macro@SDIO_CLKCR_WIDBUS_1 c:macro@SDIO_CLKCR_NEGEDGE c:macro@SDIO_CLKCR_HWFC_EN c:macro@SDIO_ARG_CMDARG c:macro@SDIO_CMD_CMDINDEX c:macro@SDIO_CMD_WAITRESP c:macro@SDIO_CMD_WAITRESP_0 c:macro@SDIO_CMD_WAITRESP_1 c:macro@SDIO_CMD_WAITINT c:macro@SDIO_CMD_WAITPEND c:macro@SDIO_CMD_CPSMEN c:macro@SDIO_CMD_SDIOSUSPEND c:macro@SDIO_CMD_ENCMDCOMPL c:macro@SDIO_CMD_NIEN c:macro@SDIO_CMD_CEATACMD c:macro@SDIO_RESPCMD_RESPCMD c:macro@SDIO_RESP0_CARDSTATUS0 c:macro@SDIO_RESP1_CARDSTATUS1 c:macro@SDIO_RESP2_CARDSTATUS2 c:macro@SDIO_RESP3_CARDSTATUS3 c:macro@SDIO_RESP4_CARDSTATUS4 c:macro@SDIO_DTIMER_DATATIME c:macro@SDIO_DLEN_DATALENGTH c:macro@SDIO_DCTRL_DTEN c:macro@SDIO_DCTRL_DTDIR c:macro@SDIO_DCTRL_DTMODE c:macro@SDIO_DCTRL_DMAEN c:macro@SDIO_DCTRL_DBLOCKSIZE c:macro@SDIO_DCTRL_DBLOCKSIZE_0 c:macro@SDIO_DCTRL_DBLOCKSIZE_1 c:macro@SDIO_DCTRL_DBLOCKSIZE_2 c:macro@SDIO_DCTRL_DBLOCKSIZE_3 c:macro@SDIO_DCTRL_RWSTART c:macro@SDIO_DCTRL_RWSTOP c:macro@SDIO_DCTRL_RWMOD c:macro@SDIO_DCTRL_SDIOEN c:macro@SDIO_DCOUNT_DATACOUNT c:macro@SDIO_STA_CCRCFAIL c:macro@SDIO_STA_DCRCFAIL c:macro@SDIO_STA_CTIMEOUT c:macro@SDIO_STA_DTIMEOUT c:macro@SDIO_STA_TXUNDERR c:macro@SDIO_STA_RXOVERR c:macro@SDIO_STA_CMDREND c:macro@SDIO_STA_CMDSENT c:macro@SDIO_STA_DATAEND c:macro@SDIO_STA_STBITERR c:macro@SDIO_STA_DBCKEND c:macro@SDIO_STA_CMDACT c:macro@SDIO_STA_TXACT c:macro@SDIO_STA_RXACT c:macro@SDIO_STA_TXFIFOHE c:macro@SDIO_STA_RXFIFOHF c:macro@SDIO_STA_TXFIFOF c:macro@SDIO_STA_RXFIFOF c:macro@SDIO_STA_TXFIFOE c:macro@SDIO_STA_RXFIFOE c:macro@SDIO_STA_TXDAVL c:macro@SDIO_STA_RXDAVL c:macro@SDIO_STA_SDIOIT c:macro@SDIO_STA_CEATAEND c:macro@SDIO_ICR_CCRCFAILC c:macro@SDIO_ICR_DCRCFAILC c:macro@SDIO_ICR_CTIMEOUTC c:macro@SDIO_ICR_DTIMEOUTC c:macro@SDIO_ICR_TXUNDERRC c:macro@SDIO_ICR_RXOVERRC c:macro@SDIO_ICR_CMDRENDC c:macro@SDIO_ICR_CMDSENTC c:macro@SDIO_ICR_DATAENDC c:macro@SDIO_ICR_STBITERRC c:macro@SDIO_ICR_DBCKENDC c:macro@SDIO_ICR_SDIOITC c:macro@SDIO_ICR_CEATAENDC c:macro@SDIO_MASK_CCRCFAILIE c:macro@SDIO_MASK_DCRCFAILIE c:macro@SDIO_MASK_CTIMEOUTIE c:macro@SDIO_MASK_DTIMEOUTIE c:macro@SDIO_MASK_TXUNDERRIE c:macro@SDIO_MASK_RXOVERRIE c:macro@SDIO_MASK_CMDRENDIE c:macro@SDIO_MASK_CMDSENTIE c:macro@SDIO_MASK_DATAENDIE c:macro@SDIO_MASK_STBITERRIE c:macro@SDIO_MASK_DBCKENDIE c:macro@SDIO_MASK_CMDACTIE c:macro@SDIO_MASK_TXACTIE c:macro@SDIO_MASK_RXACTIE c:macro@SDIO_MASK_TXFIFOHEIE c:macro@SDIO_MASK_RXFIFOHFIE c:macro@SDIO_MASK_TXFIFOFIE c:macro@SDIO_MASK_RXFIFOFIE c:macro@SDIO_MASK_TXFIFOEIE c:macro@SDIO_MASK_RXFIFOEIE c:macro@SDIO_MASK_TXDAVLIE c:macro@SDIO_MASK_RXDAVLIE c:macro@SDIO_MASK_SDIOITIE c:macro@SDIO_MASK_CEATAENDIE c:macro@SDIO_FIFOCNT_FIFOCOUNT c:macro@SDIO_FIFO_FIFODATA c:macro@SPI_CR1_CPHA c:macro@SPI_CR1_CPOL c:macro@SPI_CR1_MSTR c:macro@SPI_CR1_BR c:macro@SPI_CR1_BR_0 c:macro@SPI_CR1_BR_1 c:macro@SPI_CR1_BR_2 c:macro@SPI_CR1_SPE c:macro@SPI_CR1_LSBFIRST c:macro@SPI_CR1_SSI c:macro@SPI_CR1_SSM c:macro@SPI_CR1_RXONLY c:macro@SPI_CR1_DFF c:macro@SPI_CR1_CRCNEXT c:macro@SPI_CR1_CRCEN c:macro@SPI_CR1_BIDIOE c:macro@SPI_CR1_BIDIMODE c:macro@SPI_CR2_RXDMAEN c:macro@SPI_CR2_TXDMAEN c:macro@SPI_CR2_SSOE c:macro@SPI_CR2_FRF c:macro@SPI_CR2_ERRIE c:macro@SPI_CR2_RXNEIE c:macro@SPI_CR2_TXEIE c:macro@SPI_SR_RXNE c:macro@SPI_SR_TXE c:macro@SPI_SR_CHSIDE c:macro@SPI_SR_UDR c:macro@SPI_SR_CRCERR c:macro@SPI_SR_MODF c:macro@SPI_SR_OVR c:macro@SPI_SR_BSY c:macro@SPI_DR_DR c:macro@SPI_CRCPR_CRCPOLY c:macro@SPI_RXCRCR_RXCRC c:macro@SPI_TXCRCR_TXCRC c:macro@SPI_I2SCFGR_CHLEN c:macro@SPI_I2SCFGR_DATLEN c:macro@SPI_I2SCFGR_DATLEN_0 c:macro@SPI_I2SCFGR_DATLEN_1 c:macro@SPI_I2SCFGR_CKPOL c:macro@SPI_I2SCFGR_I2SSTD c:macro@SPI_I2SCFGR_I2SSTD_0 c:macro@SPI_I2SCFGR_I2SSTD_1 c:macro@SPI_I2SCFGR_PCMSYNC c:macro@SPI_I2SCFGR_I2SCFG c:macro@SPI_I2SCFGR_I2SCFG_0 c:macro@SPI_I2SCFGR_I2SCFG_1 c:macro@SPI_I2SCFGR_I2SE c:macro@SPI_I2SCFGR_I2SMOD c:macro@SPI_I2SPR_I2SDIV c:macro@SPI_I2SPR_ODD c:macro@SPI_I2SPR_MCKOE c:macro@SYSCFG_MEMRMP_MEM_MODE c:macro@SYSCFG_MEMRMP_MEM_MODE_0 c:macro@SYSCFG_MEMRMP_MEM_MODE_1 c:macro@SYSCFG_MEMRMP_BOOT_MODE c:macro@SYSCFG_MEMRMP_BOOT_MODE_0 c:macro@SYSCFG_MEMRMP_BOOT_MODE_1 c:macro@SYSCFG_PMC_USB_PU c:macro@SYSCFG_EXTICR1_EXTI0 c:macro@SYSCFG_EXTICR1_EXTI1 c:macro@SYSCFG_EXTICR1_EXTI2 c:macro@SYSCFG_EXTICR1_EXTI3 c:macro@SYSCFG_EXTICR1_EXTI0_PA c:macro@SYSCFG_EXTICR1_EXTI0_PB c:macro@SYSCFG_EXTICR1_EXTI0_PC c:macro@SYSCFG_EXTICR1_EXTI0_PD c:macro@SYSCFG_EXTICR1_EXTI0_PE c:macro@SYSCFG_EXTICR1_EXTI0_PH c:macro@SYSCFG_EXTICR1_EXTI0_PF c:macro@SYSCFG_EXTICR1_EXTI0_PG c:macro@SYSCFG_EXTICR1_EXTI1_PA c:macro@SYSCFG_EXTICR1_EXTI1_PB c:macro@SYSCFG_EXTICR1_EXTI1_PC c:macro@SYSCFG_EXTICR1_EXTI1_PD c:macro@SYSCFG_EXTICR1_EXTI1_PE c:macro@SYSCFG_EXTICR1_EXTI1_PH c:macro@SYSCFG_EXTICR1_EXTI1_PF c:macro@SYSCFG_EXTICR1_EXTI1_PG c:macro@SYSCFG_EXTICR1_EXTI2_PA c:macro@SYSCFG_EXTICR1_EXTI2_PB c:macro@SYSCFG_EXTICR1_EXTI2_PC c:macro@SYSCFG_EXTICR1_EXTI2_PD c:macro@SYSCFG_EXTICR1_EXTI2_PE c:macro@SYSCFG_EXTICR1_EXTI2_PH c:macro@SYSCFG_EXTICR1_EXTI2_PF c:macro@SYSCFG_EXTICR1_EXTI2_PG c:macro@SYSCFG_EXTICR1_EXTI3_PA c:macro@SYSCFG_EXTICR1_EXTI3_PB c:macro@SYSCFG_EXTICR1_EXTI3_PC c:macro@SYSCFG_EXTICR1_EXTI3_PD c:macro@SYSCFG_EXTICR1_EXTI3_PE c:macro@SYSCFG_EXTICR1_EXTI3_PF c:macro@SYSCFG_EXTICR1_EXTI3_PG c:macro@SYSCFG_EXTICR2_EXTI4 c:macro@SYSCFG_EXTICR2_EXTI5 c:macro@SYSCFG_EXTICR2_EXTI6 c:macro@SYSCFG_EXTICR2_EXTI7 c:macro@SYSCFG_EXTICR2_EXTI4_PA c:macro@SYSCFG_EXTICR2_EXTI4_PB c:macro@SYSCFG_EXTICR2_EXTI4_PC c:macro@SYSCFG_EXTICR2_EXTI4_PD c:macro@SYSCFG_EXTICR2_EXTI4_PE c:macro@SYSCFG_EXTICR2_EXTI4_PF c:macro@SYSCFG_EXTICR2_EXTI4_PG c:macro@SYSCFG_EXTICR2_EXTI5_PA c:macro@SYSCFG_EXTICR2_EXTI5_PB c:macro@SYSCFG_EXTICR2_EXTI5_PC c:macro@SYSCFG_EXTICR2_EXTI5_PD c:macro@SYSCFG_EXTICR2_EXTI5_PE c:macro@SYSCFG_EXTICR2_EXTI5_PF c:macro@SYSCFG_EXTICR2_EXTI5_PG c:macro@SYSCFG_EXTICR2_EXTI6_PA c:macro@SYSCFG_EXTICR2_EXTI6_PB c:macro@SYSCFG_EXTICR2_EXTI6_PC c:macro@SYSCFG_EXTICR2_EXTI6_PD c:macro@SYSCFG_EXTICR2_EXTI6_PE c:macro@SYSCFG_EXTICR2_EXTI6_PF c:macro@SYSCFG_EXTICR2_EXTI6_PG c:macro@SYSCFG_EXTICR2_EXTI7_PA c:macro@SYSCFG_EXTICR2_EXTI7_PB c:macro@SYSCFG_EXTICR2_EXTI7_PC c:macro@SYSCFG_EXTICR2_EXTI7_PD c:macro@SYSCFG_EXTICR2_EXTI7_PE c:macro@SYSCFG_EXTICR2_EXTI7_PF c:macro@SYSCFG_EXTICR2_EXTI7_PG c:macro@SYSCFG_EXTICR3_EXTI8 c:macro@SYSCFG_EXTICR3_EXTI9 c:macro@SYSCFG_EXTICR3_EXTI10 c:macro@SYSCFG_EXTICR3_EXTI11 c:macro@SYSCFG_EXTICR3_EXTI8_PA c:macro@SYSCFG_EXTICR3_EXTI8_PB c:macro@SYSCFG_EXTICR3_EXTI8_PC c:macro@SYSCFG_EXTICR3_EXTI8_PD c:macro@SYSCFG_EXTICR3_EXTI8_PE c:macro@SYSCFG_EXTICR3_EXTI8_PF c:macro@SYSCFG_EXTICR3_EXTI8_PG c:macro@SYSCFG_EXTICR3_EXTI9_PA c:macro@SYSCFG_EXTICR3_EXTI9_PB c:macro@SYSCFG_EXTICR3_EXTI9_PC c:macro@SYSCFG_EXTICR3_EXTI9_PD c:macro@SYSCFG_EXTICR3_EXTI9_PE c:macro@SYSCFG_EXTICR3_EXTI9_PF c:macro@SYSCFG_EXTICR3_EXTI9_PG c:macro@SYSCFG_EXTICR3_EXTI10_PA c:macro@SYSCFG_EXTICR3_EXTI10_PB c:macro@SYSCFG_EXTICR3_EXTI10_PC c:macro@SYSCFG_EXTICR3_EXTI10_PD c:macro@SYSCFG_EXTICR3_EXTI10_PE c:macro@SYSCFG_EXTICR3_EXTI10_PF c:macro@SYSCFG_EXTICR3_EXTI10_PG c:macro@SYSCFG_EXTICR3_EXTI11_PA c:macro@SYSCFG_EXTICR3_EXTI11_PB c:macro@SYSCFG_EXTICR3_EXTI11_PC c:macro@SYSCFG_EXTICR3_EXTI11_PD c:macro@SYSCFG_EXTICR3_EXTI11_PE c:macro@SYSCFG_EXTICR3_EXTI11_PF c:macro@SYSCFG_EXTICR3_EXTI11_PG c:macro@SYSCFG_EXTICR4_EXTI12 c:macro@SYSCFG_EXTICR4_EXTI13 c:macro@SYSCFG_EXTICR4_EXTI14 c:macro@SYSCFG_EXTICR4_EXTI15 c:macro@SYSCFG_EXTICR4_EXTI12_PA c:macro@SYSCFG_EXTICR4_EXTI12_PB c:macro@SYSCFG_EXTICR4_EXTI12_PC c:macro@SYSCFG_EXTICR4_EXTI12_PD c:macro@SYSCFG_EXTICR4_EXTI12_PE c:macro@SYSCFG_EXTICR4_EXTI12_PF c:macro@SYSCFG_EXTICR4_EXTI12_PG c:macro@SYSCFG_EXTICR4_EXTI13_PA c:macro@SYSCFG_EXTICR4_EXTI13_PB c:macro@SYSCFG_EXTICR4_EXTI13_PC c:macro@SYSCFG_EXTICR4_EXTI13_PD c:macro@SYSCFG_EXTICR4_EXTI13_PE c:macro@SYSCFG_EXTICR4_EXTI13_PF c:macro@SYSCFG_EXTICR4_EXTI13_PG c:macro@SYSCFG_EXTICR4_EXTI14_PA c:macro@SYSCFG_EXTICR4_EXTI14_PB c:macro@SYSCFG_EXTICR4_EXTI14_PC c:macro@SYSCFG_EXTICR4_EXTI14_PD c:macro@SYSCFG_EXTICR4_EXTI14_PE c:macro@SYSCFG_EXTICR4_EXTI14_PF c:macro@SYSCFG_EXTICR4_EXTI14_PG c:macro@SYSCFG_EXTICR4_EXTI15_PA c:macro@SYSCFG_EXTICR4_EXTI15_PB c:macro@SYSCFG_EXTICR4_EXTI15_PC c:macro@SYSCFG_EXTICR4_EXTI15_PD c:macro@SYSCFG_EXTICR4_EXTI15_PE c:macro@SYSCFG_EXTICR4_EXTI15_PF c:macro@SYSCFG_EXTICR4_EXTI15_PG c:macro@RI_ICR_IC1Z c:macro@RI_ICR_IC1Z_0 c:macro@RI_ICR_IC1Z_1 c:macro@RI_ICR_IC1Z_2 c:macro@RI_ICR_IC1Z_3 c:macro@RI_ICR_IC2Z c:macro@RI_ICR_IC2Z_0 c:macro@RI_ICR_IC2Z_1 c:macro@RI_ICR_IC2Z_2 c:macro@RI_ICR_IC2Z_3 c:macro@RI_ICR_IC3Z c:macro@RI_ICR_IC3Z_0 c:macro@RI_ICR_IC3Z_1 c:macro@RI_ICR_IC3Z_2 c:macro@RI_ICR_IC3Z_3 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c:macro@RI_HYSCR1_PB c:macro@RI_HYSCR1_PB_0 c:macro@RI_HYSCR1_PB_1 c:macro@RI_HYSCR1_PB_2 c:macro@RI_HYSCR1_PB_3 c:macro@RI_HYSCR1_PB_4 c:macro@RI_HYSCR1_PB_5 c:macro@RI_HYSCR1_PB_6 c:macro@RI_HYSCR1_PB_7 c:macro@RI_HYSCR1_PB_8 c:macro@RI_HYSCR1_PB_9 c:macro@RI_HYSCR1_PB_10 c:macro@RI_HYSCR1_PB_11 c:macro@RI_HYSCR1_PB_12 c:macro@RI_HYSCR1_PB_13 c:macro@RI_HYSCR1_PB_14 c:macro@RI_HYSCR1_PB_15 c:macro@RI_HYSCR2_PC c:macro@RI_HYSCR2_PC_0 c:macro@RI_HYSCR2_PC_1 c:macro@RI_HYSCR2_PC_2 c:macro@RI_HYSCR2_PC_3 c:macro@RI_HYSCR2_PC_4 c:macro@RI_HYSCR2_PC_5 c:macro@RI_HYSCR2_PC_6 c:macro@RI_HYSCR2_PC_7 c:macro@RI_HYSCR2_PC_8 c:macro@RI_HYSCR2_PC_9 c:macro@RI_HYSCR2_PC_10 c:macro@RI_HYSCR2_PC_11 c:macro@RI_HYSCR2_PC_12 c:macro@RI_HYSCR2_PC_13 c:macro@RI_HYSCR2_PC_14 c:macro@RI_HYSCR2_PC_15 c:macro@RI_HYSCR2_PD c:macro@RI_HYSCR2_PD_0 c:macro@RI_HYSCR2_PD_1 c:macro@RI_HYSCR2_PD_2 c:macro@RI_HYSCR2_PD_3 c:macro@RI_HYSCR2_PD_4 c:macro@RI_HYSCR2_PD_5 c:macro@RI_HYSCR2_PD_6 c:macro@RI_HYSCR2_PD_7 c:macro@RI_HYSCR2_PD_8 c:macro@RI_HYSCR2_PD_9 c:macro@RI_HYSCR2_PD_10 c:macro@RI_HYSCR2_PD_11 c:macro@RI_HYSCR2_PD_12 c:macro@RI_HYSCR2_PD_13 c:macro@RI_HYSCR2_PD_14 c:macro@RI_HYSCR2_PD_15 c:macro@RI_HYSCR2_PE c:macro@RI_HYSCR2_PE_0 c:macro@RI_HYSCR2_PE_1 c:macro@RI_HYSCR2_PE_2 c:macro@RI_HYSCR2_PE_3 c:macro@RI_HYSCR2_PE_4 c:macro@RI_HYSCR2_PE_5 c:macro@RI_HYSCR2_PE_6 c:macro@RI_HYSCR2_PE_7 c:macro@RI_HYSCR2_PE_8 c:macro@RI_HYSCR2_PE_9 c:macro@RI_HYSCR2_PE_10 c:macro@RI_HYSCR2_PE_11 c:macro@RI_HYSCR2_PE_12 c:macro@RI_HYSCR2_PE_13 c:macro@RI_HYSCR2_PE_14 c:macro@RI_HYSCR2_PE_15 c:macro@RI_HYSCR3_PF c:macro@RI_HYSCR3_PF_0 c:macro@RI_HYSCR3_PF_1 c:macro@RI_HYSCR3_PF_2 c:macro@RI_HYSCR3_PF_3 c:macro@RI_HYSCR3_PF_4 c:macro@RI_HYSCR3_PF_5 c:macro@RI_HYSCR3_PF_6 c:macro@RI_HYSCR3_PF_7 c:macro@RI_HYSCR3_PF_8 c:macro@RI_HYSCR3_PF_9 c:macro@RI_HYSCR3_PF_10 c:macro@RI_HYSCR3_PF_11 c:macro@RI_HYSCR3_PF_12 c:macro@RI_HYSCR3_PF_13 c:macro@RI_HYSCR3_PF_14 c:macro@RI_HYSCR3_PF_15 c:macro@RI_HYSCR4_PG c:macro@RI_HYSCR4_PG_0 c:macro@RI_HYSCR4_PG_1 c:macro@RI_HYSCR4_PG_2 c:macro@RI_HYSCR4_PG_3 c:macro@RI_HYSCR4_PG_4 c:macro@RI_HYSCR4_PG_5 c:macro@RI_HYSCR4_PG_6 c:macro@RI_HYSCR4_PG_7 c:macro@RI_HYSCR4_PG_8 c:macro@RI_HYSCR4_PG_9 c:macro@RI_HYSCR4_PG_10 c:macro@RI_HYSCR4_PG_11 c:macro@RI_HYSCR4_PG_12 c:macro@RI_HYSCR4_PG_13 c:macro@RI_HYSCR4_PG_14 c:macro@RI_HYSCR4_PG_15 c:macro@TIM_CR1_CEN c:macro@TIM_CR1_UDIS c:macro@TIM_CR1_URS c:macro@TIM_CR1_OPM c:macro@TIM_CR1_DIR c:macro@TIM_CR1_CMS c:macro@TIM_CR1_CMS_0 c:macro@TIM_CR1_CMS_1 c:macro@TIM_CR1_ARPE c:macro@TIM_CR1_CKD c:macro@TIM_CR1_CKD_0 c:macro@TIM_CR1_CKD_1 c:macro@TIM_CR2_CCDS c:macro@TIM_CR2_MMS c:macro@TIM_CR2_MMS_0 c:macro@TIM_CR2_MMS_1 c:macro@TIM_CR2_MMS_2 c:macro@TIM_CR2_TI1S c:macro@TIM_SMCR_SMS c:macro@TIM_SMCR_SMS_0 c:macro@TIM_SMCR_SMS_1 c:macro@TIM_SMCR_SMS_2 c:macro@TIM_SMCR_OCCS c:macro@TIM_SMCR_TS c:macro@TIM_SMCR_TS_0 c:macro@TIM_SMCR_TS_1 c:macro@TIM_SMCR_TS_2 c:macro@TIM_SMCR_MSM c:macro@TIM_SMCR_ETF c:macro@TIM_SMCR_ETF_0 c:macro@TIM_SMCR_ETF_1 c:macro@TIM_SMCR_ETF_2 c:macro@TIM_SMCR_ETF_3 c:macro@TIM_SMCR_ETPS c:macro@TIM_SMCR_ETPS_0 c:macro@TIM_SMCR_ETPS_1 c:macro@TIM_SMCR_ECE c:macro@TIM_SMCR_ETP c:macro@TIM_DIER_UIE c:macro@TIM_DIER_CC1IE c:macro@TIM_DIER_CC2IE c:macro@TIM_DIER_CC3IE c:macro@TIM_DIER_CC4IE c:macro@TIM_DIER_TIE c:macro@TIM_DIER_UDE c:macro@TIM_DIER_CC1DE c:macro@TIM_DIER_CC2DE c:macro@TIM_DIER_CC3DE c:macro@TIM_DIER_CC4DE c:macro@TIM_DIER_TDE c:macro@TIM_SR_UIF c:macro@TIM_SR_CC1IF c:macro@TIM_SR_CC2IF c:macro@TIM_SR_CC3IF c:macro@TIM_SR_CC4IF c:macro@TIM_SR_TIF c:macro@TIM_SR_CC1OF c:macro@TIM_SR_CC2OF c:macro@TIM_SR_CC3OF c:macro@TIM_SR_CC4OF c:macro@TIM_EGR_UG c:macro@TIM_EGR_CC1G c:macro@TIM_EGR_CC2G c:macro@TIM_EGR_CC3G c:macro@TIM_EGR_CC4G c:macro@TIM_EGR_TG c:macro@TIM_CCMR1_CC1S c:macro@TIM_CCMR1_CC1S_0 c:macro@TIM_CCMR1_CC1S_1 c:macro@TIM_CCMR1_OC1FE c:macro@TIM_CCMR1_OC1PE c:macro@TIM_CCMR1_OC1M c:macro@TIM_CCMR1_OC1M_0 c:macro@TIM_CCMR1_OC1M_1 c:macro@TIM_CCMR1_OC1M_2 c:macro@TIM_CCMR1_OC1CE c:macro@TIM_CCMR1_CC2S c:macro@TIM_CCMR1_CC2S_0 c:macro@TIM_CCMR1_CC2S_1 c:macro@TIM_CCMR1_OC2FE c:macro@TIM_CCMR1_OC2PE c:macro@TIM_CCMR1_OC2M c:macro@TIM_CCMR1_OC2M_0 c:macro@TIM_CCMR1_OC2M_1 c:macro@TIM_CCMR1_OC2M_2 c:macro@TIM_CCMR1_OC2CE c:macro@TIM_CCMR1_IC1PSC c:macro@TIM_CCMR1_IC1PSC_0 c:macro@TIM_CCMR1_IC1PSC_1 c:macro@TIM_CCMR1_IC1F c:macro@TIM_CCMR1_IC1F_0 c:macro@TIM_CCMR1_IC1F_1 c:macro@TIM_CCMR1_IC1F_2 c:macro@TIM_CCMR1_IC1F_3 c:macro@TIM_CCMR1_IC2PSC c:macro@TIM_CCMR1_IC2PSC_0 c:macro@TIM_CCMR1_IC2PSC_1 c:macro@TIM_CCMR1_IC2F c:macro@TIM_CCMR1_IC2F_0 c:macro@TIM_CCMR1_IC2F_1 c:macro@TIM_CCMR1_IC2F_2 c:macro@TIM_CCMR1_IC2F_3 c:macro@TIM_CCMR2_CC3S c:macro@TIM_CCMR2_CC3S_0 c:macro@TIM_CCMR2_CC3S_1 c:macro@TIM_CCMR2_OC3FE c:macro@TIM_CCMR2_OC3PE c:macro@TIM_CCMR2_OC3M c:macro@TIM_CCMR2_OC3M_0 c:macro@TIM_CCMR2_OC3M_1 c:macro@TIM_CCMR2_OC3M_2 c:macro@TIM_CCMR2_OC3CE c:macro@TIM_CCMR2_CC4S c:macro@TIM_CCMR2_CC4S_0 c:macro@TIM_CCMR2_CC4S_1 c:macro@TIM_CCMR2_OC4FE c:macro@TIM_CCMR2_OC4PE c:macro@TIM_CCMR2_OC4M c:macro@TIM_CCMR2_OC4M_0 c:macro@TIM_CCMR2_OC4M_1 c:macro@TIM_CCMR2_OC4M_2 c:macro@TIM_CCMR2_OC4CE c:macro@TIM_CCMR2_IC3PSC c:macro@TIM_CCMR2_IC3PSC_0 c:macro@TIM_CCMR2_IC3PSC_1 c:macro@TIM_CCMR2_IC3F c:macro@TIM_CCMR2_IC3F_0 c:macro@TIM_CCMR2_IC3F_1 c:macro@TIM_CCMR2_IC3F_2 c:macro@TIM_CCMR2_IC3F_3 c:macro@TIM_CCMR2_IC4PSC c:macro@TIM_CCMR2_IC4PSC_0 c:macro@TIM_CCMR2_IC4PSC_1 c:macro@TIM_CCMR2_IC4F c:macro@TIM_CCMR2_IC4F_0 c:macro@TIM_CCMR2_IC4F_1 c:macro@TIM_CCMR2_IC4F_2 c:macro@TIM_CCMR2_IC4F_3 c:macro@TIM_CCER_CC1E c:macro@TIM_CCER_CC1P c:macro@TIM_CCER_CC1NP c:macro@TIM_CCER_CC2E c:macro@TIM_CCER_CC2P c:macro@TIM_CCER_CC2NP c:macro@TIM_CCER_CC3E c:macro@TIM_CCER_CC3P c:macro@TIM_CCER_CC3NP c:macro@TIM_CCER_CC4E c:macro@TIM_CCER_CC4P c:macro@TIM_CCER_CC4NP c:macro@TIM_CNT_CNT c:macro@TIM_PSC_PSC c:macro@TIM_ARR_ARR c:macro@TIM_CCR1_CCR1 c:macro@TIM_CCR2_CCR2 c:macro@TIM_CCR3_CCR3 c:macro@TIM_CCR4_CCR4 c:macro@TIM_DCR_DBA c:macro@TIM_DCR_DBA_0 c:macro@TIM_DCR_DBA_1 c:macro@TIM_DCR_DBA_2 c:macro@TIM_DCR_DBA_3 c:macro@TIM_DCR_DBA_4 c:macro@TIM_DCR_DBL c:macro@TIM_DCR_DBL_0 c:macro@TIM_DCR_DBL_1 c:macro@TIM_DCR_DBL_2 c:macro@TIM_DCR_DBL_3 c:macro@TIM_DCR_DBL_4 c:macro@TIM_DMAR_DMAB c:macro@TIM_OR_TI1RMP c:macro@TIM_OR_TI1RMP_0 c:macro@TIM_OR_TI1RMP_1 c:macro@USART_SR_PE c:macro@USART_SR_FE c:macro@USART_SR_NE c:macro@USART_SR_ORE c:macro@USART_SR_IDLE c:macro@USART_SR_RXNE c:macro@USART_SR_TC c:macro@USART_SR_TXE c:macro@USART_SR_LBD c:macro@USART_SR_CTS c:macro@USART_DR_DR c:macro@USART_BRR_DIV_FRACTION c:macro@USART_BRR_DIV_MANTISSA c:macro@USART_CR1_SBK c:macro@USART_CR1_RWU c:macro@USART_CR1_RE c:macro@USART_CR1_TE c:macro@USART_CR1_IDLEIE c:macro@USART_CR1_RXNEIE c:macro@USART_CR1_TCIE c:macro@USART_CR1_TXEIE c:macro@USART_CR1_PEIE c:macro@USART_CR1_PS c:macro@USART_CR1_PCE c:macro@USART_CR1_WAKE c:macro@USART_CR1_M c:macro@USART_CR1_UE c:macro@USART_CR1_OVER8 c:macro@USART_CR2_ADD c:macro@USART_CR2_LBDL c:macro@USART_CR2_LBDIE c:macro@USART_CR2_LBCL c:macro@USART_CR2_CPHA c:macro@USART_CR2_CPOL c:macro@USART_CR2_CLKEN c:macro@USART_CR2_STOP c:macro@USART_CR2_STOP_0 c:macro@USART_CR2_STOP_1 c:macro@USART_CR2_LINEN c:macro@USART_CR3_EIE c:macro@USART_CR3_IREN c:macro@USART_CR3_IRLP c:macro@USART_CR3_HDSEL c:macro@USART_CR3_NACK c:macro@USART_CR3_SCEN c:macro@USART_CR3_DMAR c:macro@USART_CR3_DMAT c:macro@USART_CR3_RTSE c:macro@USART_CR3_CTSE c:macro@USART_CR3_CTSIE c:macro@USART_CR3_ONEBIT c:macro@USART_GTPR_PSC c:macro@USART_GTPR_PSC_0 c:macro@USART_GTPR_PSC_1 c:macro@USART_GTPR_PSC_2 c:macro@USART_GTPR_PSC_3 c:macro@USART_GTPR_PSC_4 c:macro@USART_GTPR_PSC_5 c:macro@USART_GTPR_PSC_6 c:macro@USART_GTPR_PSC_7 c:macro@USART_GTPR_GT c:macro@USB_EP0R_EA c:macro@USB_EP0R_STAT_TX c:macro@USB_EP0R_STAT_TX_0 c:macro@USB_EP0R_STAT_TX_1 c:macro@USB_EP0R_DTOG_TX c:macro@USB_EP0R_CTR_TX c:macro@USB_EP0R_EP_KIND c:macro@USB_EP0R_EP_TYPE c:macro@USB_EP0R_EP_TYPE_0 c:macro@USB_EP0R_EP_TYPE_1 c:macro@USB_EP0R_SETUP c:macro@USB_EP0R_STAT_RX c:macro@USB_EP0R_STAT_RX_0 c:macro@USB_EP0R_STAT_RX_1 c:macro@USB_EP0R_DTOG_RX c:macro@USB_EP0R_CTR_RX c:macro@USB_EP1R_EA c:macro@USB_EP1R_STAT_TX c:macro@USB_EP1R_STAT_TX_0 c:macro@USB_EP1R_STAT_TX_1 c:macro@USB_EP1R_DTOG_TX c:macro@USB_EP1R_CTR_TX c:macro@USB_EP1R_EP_KIND c:macro@USB_EP1R_EP_TYPE c:macro@USB_EP1R_EP_TYPE_0 c:macro@USB_EP1R_EP_TYPE_1 c:macro@USB_EP1R_SETUP c:macro@USB_EP1R_STAT_RX c:macro@USB_EP1R_STAT_RX_0 c:macro@USB_EP1R_STAT_RX_1 c:macro@USB_EP1R_DTOG_RX c:macro@USB_EP1R_CTR_RX c:macro@USB_EP2R_EA c:macro@USB_EP2R_STAT_TX c:macro@USB_EP2R_STAT_TX_0 c:macro@USB_EP2R_STAT_TX_1 c:macro@USB_EP2R_DTOG_TX c:macro@USB_EP2R_CTR_TX c:macro@USB_EP2R_EP_KIND c:macro@USB_EP2R_EP_TYPE c:macro@USB_EP2R_EP_TYPE_0 c:macro@USB_EP2R_EP_TYPE_1 c:macro@USB_EP2R_SETUP c:macro@USB_EP2R_STAT_RX c:macro@USB_EP2R_STAT_RX_0 c:macro@USB_EP2R_STAT_RX_1 c:macro@USB_EP2R_DTOG_RX c:macro@USB_EP2R_CTR_RX c:macro@USB_EP3R_EA c:macro@USB_EP3R_STAT_TX c:macro@USB_EP3R_STAT_TX_0 c:macro@USB_EP3R_STAT_TX_1 c:macro@USB_EP3R_DTOG_TX c:macro@USB_EP3R_CTR_TX c:macro@USB_EP3R_EP_KIND c:macro@USB_EP3R_EP_TYPE c:macro@USB_EP3R_EP_TYPE_0 c:macro@USB_EP3R_EP_TYPE_1 c:macro@USB_EP3R_SETUP c:macro@USB_EP3R_STAT_RX c:macro@USB_EP3R_STAT_RX_0 c:macro@USB_EP3R_STAT_RX_1 c:macro@USB_EP3R_DTOG_RX c:macro@USB_EP3R_CTR_RX c:macro@USB_EP4R_EA c:macro@USB_EP4R_STAT_TX c:macro@USB_EP4R_STAT_TX_0 c:macro@USB_EP4R_STAT_TX_1 c:macro@USB_EP4R_DTOG_TX c:macro@USB_EP4R_CTR_TX c:macro@USB_EP4R_EP_KIND c:macro@USB_EP4R_EP_TYPE c:macro@USB_EP4R_EP_TYPE_0 c:macro@USB_EP4R_EP_TYPE_1 c:macro@USB_EP4R_SETUP c:macro@USB_EP4R_STAT_RX c:macro@USB_EP4R_STAT_RX_0 c:macro@USB_EP4R_STAT_RX_1 c:macro@USB_EP4R_DTOG_RX c:macro@USB_EP4R_CTR_RX c:macro@USB_EP5R_EA c:macro@USB_EP5R_STAT_TX c:macro@USB_EP5R_STAT_TX_0 c:macro@USB_EP5R_STAT_TX_1 c:macro@USB_EP5R_DTOG_TX c:macro@USB_EP5R_CTR_TX c:macro@USB_EP5R_EP_KIND c:macro@USB_EP5R_EP_TYPE c:macro@USB_EP5R_EP_TYPE_0 c:macro@USB_EP5R_EP_TYPE_1 c:macro@USB_EP5R_SETUP c:macro@USB_EP5R_STAT_RX c:macro@USB_EP5R_STAT_RX_0 c:macro@USB_EP5R_STAT_RX_1 c:macro@USB_EP5R_DTOG_RX c:macro@USB_EP5R_CTR_RX c:macro@USB_EP6R_EA c:macro@USB_EP6R_STAT_TX c:macro@USB_EP6R_STAT_TX_0 c:macro@USB_EP6R_STAT_TX_1 c:macro@USB_EP6R_DTOG_TX c:macro@USB_EP6R_CTR_TX c:macro@USB_EP6R_EP_KIND c:macro@USB_EP6R_EP_TYPE c:macro@USB_EP6R_EP_TYPE_0 c:macro@USB_EP6R_EP_TYPE_1 c:macro@USB_EP6R_SETUP c:macro@USB_EP6R_STAT_RX c:macro@USB_EP6R_STAT_RX_0 c:macro@USB_EP6R_STAT_RX_1 c:macro@USB_EP6R_DTOG_RX c:macro@USB_EP6R_CTR_RX c:macro@USB_EP7R_EA c:macro@USB_EP7R_STAT_TX c:macro@USB_EP7R_STAT_TX_0 c:macro@USB_EP7R_STAT_TX_1 c:macro@USB_EP7R_DTOG_TX c:macro@USB_EP7R_CTR_TX c:macro@USB_EP7R_EP_KIND c:macro@USB_EP7R_EP_TYPE c:macro@USB_EP7R_EP_TYPE_0 c:macro@USB_EP7R_EP_TYPE_1 c:macro@USB_EP7R_SETUP c:macro@USB_EP7R_STAT_RX c:macro@USB_EP7R_STAT_RX_0 c:macro@USB_EP7R_STAT_RX_1 c:macro@USB_EP7R_DTOG_RX c:macro@USB_EP7R_CTR_RX c:macro@USB_CNTR_FRES c:macro@USB_CNTR_PDWN c:macro@USB_CNTR_LP_MODE c:macro@USB_CNTR_FSUSP c:macro@USB_CNTR_RESUME c:macro@USB_CNTR_ESOFM c:macro@USB_CNTR_SOFM c:macro@USB_CNTR_RESETM c:macro@USB_CNTR_SUSPM c:macro@USB_CNTR_WKUPM c:macro@USB_CNTR_ERRM c:macro@USB_CNTR_PMAOVRM c:macro@USB_CNTR_CTRM c:macro@USB_ISTR_EP_ID c:macro@USB_ISTR_DIR c:macro@USB_ISTR_ESOF c:macro@USB_ISTR_SOF c:macro@USB_ISTR_RESET c:macro@USB_ISTR_SUSP c:macro@USB_ISTR_WKUP c:macro@USB_ISTR_ERR c:macro@USB_ISTR_PMAOVR c:macro@USB_ISTR_CTR c:macro@USB_FNR_FN c:macro@USB_FNR_LSOF c:macro@USB_FNR_LCK c:macro@USB_FNR_RXDM c:macro@USB_FNR_RXDP c:macro@USB_DADDR_ADD c:macro@USB_DADDR_ADD0 c:macro@USB_DADDR_ADD1 c:macro@USB_DADDR_ADD2 c:macro@USB_DADDR_ADD3 c:macro@USB_DADDR_ADD4 c:macro@USB_DADDR_ADD5 c:macro@USB_DADDR_ADD6 c:macro@USB_DADDR_EF c:macro@USB_BTABLE_BTABLE c:macro@USB_ADDR0_TX_ADDR0_TX c:macro@USB_ADDR1_TX_ADDR1_TX c:macro@USB_ADDR2_TX_ADDR2_TX c:macro@USB_ADDR3_TX_ADDR3_TX c:macro@USB_ADDR4_TX_ADDR4_TX c:macro@USB_ADDR5_TX_ADDR5_TX c:macro@USB_ADDR6_TX_ADDR6_TX c:macro@USB_ADDR7_TX_ADDR7_TX c:macro@USB_COUNT0_TX_COUNT0_TX c:macro@USB_COUNT1_TX_COUNT1_TX c:macro@USB_COUNT2_TX_COUNT2_TX c:macro@USB_COUNT3_TX_COUNT3_TX c:macro@USB_COUNT4_TX_COUNT4_TX c:macro@USB_COUNT5_TX_COUNT5_TX c:macro@USB_COUNT6_TX_COUNT6_TX c:macro@USB_COUNT7_TX_COUNT7_TX c:macro@USB_COUNT0_TX_0_COUNT0_TX_0 c:macro@USB_COUNT0_TX_1_COUNT0_TX_1 c:macro@USB_COUNT1_TX_0_COUNT1_TX_0 c:macro@USB_COUNT1_TX_1_COUNT1_TX_1 c:macro@USB_COUNT2_TX_0_COUNT2_TX_0 c:macro@USB_COUNT2_TX_1_COUNT2_TX_1 c:macro@USB_COUNT3_TX_0_COUNT3_TX_0 c:macro@USB_COUNT3_TX_1_COUNT3_TX_1 c:macro@USB_COUNT4_TX_0_COUNT4_TX_0 c:macro@USB_COUNT4_TX_1_COUNT4_TX_1 c:macro@USB_COUNT5_TX_0_COUNT5_TX_0 c:macro@USB_COUNT5_TX_1_COUNT5_TX_1 c:macro@USB_COUNT6_TX_0_COUNT6_TX_0 c:macro@USB_COUNT6_TX_1_COUNT6_TX_1 c:macro@USB_COUNT7_TX_0_COUNT7_TX_0 c:macro@USB_COUNT7_TX_1_COUNT7_TX_1 c:macro@USB_ADDR0_RX_ADDR0_RX c:macro@USB_ADDR1_RX_ADDR1_RX c:macro@USB_ADDR2_RX_ADDR2_RX c:macro@USB_ADDR3_RX_ADDR3_RX c:macro@USB_ADDR4_RX_ADDR4_RX c:macro@USB_ADDR5_RX_ADDR5_RX c:macro@USB_ADDR6_RX_ADDR6_RX c:macro@USB_ADDR7_RX_ADDR7_RX c:macro@USB_COUNT0_RX_COUNT0_RX c:macro@USB_COUNT0_RX_NUM_BLOCK c:macro@USB_COUNT0_RX_NUM_BLOCK_0 c:macro@USB_COUNT0_RX_NUM_BLOCK_1 c:macro@USB_COUNT0_RX_NUM_BLOCK_2 c:macro@USB_COUNT0_RX_NUM_BLOCK_3 c:macro@USB_COUNT0_RX_NUM_BLOCK_4 c:macro@USB_COUNT0_RX_BLSIZE c:macro@USB_COUNT1_RX_COUNT1_RX c:macro@USB_COUNT1_RX_NUM_BLOCK c:macro@USB_COUNT1_RX_NUM_BLOCK_0 c:macro@USB_COUNT1_RX_NUM_BLOCK_1 c:macro@USB_COUNT1_RX_NUM_BLOCK_2 c:macro@USB_COUNT1_RX_NUM_BLOCK_3 c:macro@USB_COUNT1_RX_NUM_BLOCK_4 c:macro@USB_COUNT1_RX_BLSIZE c:macro@USB_COUNT2_RX_COUNT2_RX c:macro@USB_COUNT2_RX_NUM_BLOCK c:macro@USB_COUNT2_RX_NUM_BLOCK_0 c:macro@USB_COUNT2_RX_NUM_BLOCK_1 c:macro@USB_COUNT2_RX_NUM_BLOCK_2 c:macro@USB_COUNT2_RX_NUM_BLOCK_3 c:macro@USB_COUNT2_RX_NUM_BLOCK_4 c:macro@USB_COUNT2_RX_BLSIZE c:macro@USB_COUNT3_RX_COUNT3_RX c:macro@USB_COUNT3_RX_NUM_BLOCK c:macro@USB_COUNT3_RX_NUM_BLOCK_0 c:macro@USB_COUNT3_RX_NUM_BLOCK_1 c:macro@USB_COUNT3_RX_NUM_BLOCK_2 c:macro@USB_COUNT3_RX_NUM_BLOCK_3 c:macro@USB_COUNT3_RX_NUM_BLOCK_4 c:macro@USB_COUNT3_RX_BLSIZE c:macro@USB_COUNT4_RX_COUNT4_RX c:macro@USB_COUNT4_RX_NUM_BLOCK c:macro@USB_COUNT4_RX_NUM_BLOCK_0 c:macro@USB_COUNT4_RX_NUM_BLOCK_1 c:macro@USB_COUNT4_RX_NUM_BLOCK_2 c:macro@USB_COUNT4_RX_NUM_BLOCK_3 c:macro@USB_COUNT4_RX_NUM_BLOCK_4 c:macro@USB_COUNT4_RX_BLSIZE c:macro@USB_COUNT5_RX_COUNT5_RX c:macro@USB_COUNT5_RX_NUM_BLOCK c:macro@USB_COUNT5_RX_NUM_BLOCK_0 c:macro@USB_COUNT5_RX_NUM_BLOCK_1 c:macro@USB_COUNT5_RX_NUM_BLOCK_2 c:macro@USB_COUNT5_RX_NUM_BLOCK_3 c:macro@USB_COUNT5_RX_NUM_BLOCK_4 c:macro@USB_COUNT5_RX_BLSIZE c:macro@USB_COUNT6_RX_COUNT6_RX c:macro@USB_COUNT6_RX_NUM_BLOCK c:macro@USB_COUNT6_RX_NUM_BLOCK_0 c:macro@USB_COUNT6_RX_NUM_BLOCK_1 c:macro@USB_COUNT6_RX_NUM_BLOCK_2 c:macro@USB_COUNT6_RX_NUM_BLOCK_3 c:macro@USB_COUNT6_RX_NUM_BLOCK_4 c:macro@USB_COUNT6_RX_BLSIZE c:macro@USB_COUNT7_RX_COUNT7_RX c:macro@USB_COUNT7_RX_NUM_BLOCK c:macro@USB_COUNT7_RX_NUM_BLOCK_0 c:macro@USB_COUNT7_RX_NUM_BLOCK_1 c:macro@USB_COUNT7_RX_NUM_BLOCK_2 c:macro@USB_COUNT7_RX_NUM_BLOCK_3 c:macro@USB_COUNT7_RX_NUM_BLOCK_4 c:macro@USB_COUNT7_RX_BLSIZE c:macro@USB_COUNT0_RX_0_COUNT0_RX_0 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT0_RX_0_BLSIZE_0 c:macro@USB_COUNT0_RX_1_COUNT0_RX_1 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT0_RX_1_BLSIZE_1 c:macro@USB_COUNT1_RX_0_COUNT1_RX_0 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT1_RX_0_BLSIZE_0 c:macro@USB_COUNT1_RX_1_COUNT1_RX_1 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT1_RX_1_BLSIZE_1 c:macro@USB_COUNT2_RX_0_COUNT2_RX_0 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT2_RX_0_BLSIZE_0 c:macro@USB_COUNT2_RX_1_COUNT2_RX_1 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT2_RX_1_BLSIZE_1 c:macro@USB_COUNT3_RX_0_COUNT3_RX_0 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT3_RX_0_BLSIZE_0 c:macro@USB_COUNT3_RX_1_COUNT3_RX_1 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT3_RX_1_BLSIZE_1 c:macro@USB_COUNT4_RX_0_COUNT4_RX_0 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT4_RX_0_BLSIZE_0 c:macro@USB_COUNT4_RX_1_COUNT4_RX_1 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT4_RX_1_BLSIZE_1 c:macro@USB_COUNT5_RX_0_COUNT5_RX_0 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT5_RX_0_BLSIZE_0 c:macro@USB_COUNT5_RX_1_COUNT5_RX_1 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT5_RX_1_BLSIZE_1 c:macro@USB_COUNT6_RX_0_COUNT6_RX_0 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT6_RX_0_BLSIZE_0 c:macro@USB_COUNT6_RX_1_COUNT6_RX_1 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT6_RX_1_BLSIZE_1 c:macro@USB_COUNT7_RX_0_COUNT7_RX_0 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_0 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_1 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_2 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_3 c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_4 c:macro@USB_COUNT7_RX_0_BLSIZE_0 c:macro@USB_COUNT7_RX_1_COUNT7_RX_1 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_0 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_1 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_2 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_3 c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_4 c:macro@USB_COUNT7_RX_1_BLSIZE_1 c:macro@WWDG_CR_T c:macro@WWDG_CR_T0 c:macro@WWDG_CR_T1 c:macro@WWDG_CR_T2 c:macro@WWDG_CR_T3 c:macro@WWDG_CR_T4 c:macro@WWDG_CR_T5 c:macro@WWDG_CR_T6 c:macro@WWDG_CR_WDGA c:macro@WWDG_CFR_W c:macro@WWDG_CFR_W0 c:macro@WWDG_CFR_W1 c:macro@WWDG_CFR_W2 c:macro@WWDG_CFR_W3 c:macro@WWDG_CFR_W4 c:macro@WWDG_CFR_W5 c:macro@WWDG_CFR_W6 c:macro@WWDG_CFR_WDGTB c:macro@WWDG_CFR_WDGTB0 c:macro@WWDG_CFR_WDGTB1 c:macro@WWDG_CFR_EWI c:macro@WWDG_SR_EWIF c:macro@SysTick_CTRL_ENABLE c:macro@SysTick_CTRL_TICKINT c:macro@SysTick_CTRL_CLKSOURCE c:macro@SysTick_CTRL_COUNTFLAG c:macro@SysTick_LOAD_RELOAD c:macro@SysTick_VAL_CURRENT c:macro@SysTick_CALIB_TENMS c:macro@SysTick_CALIB_SKEW c:macro@SysTick_CALIB_NOREF c:macro@NVIC_ISER_SETENA c:macro@NVIC_ISER_SETENA_0 c:macro@NVIC_ISER_SETENA_1 c:macro@NVIC_ISER_SETENA_2 c:macro@NVIC_ISER_SETENA_3 c:macro@NVIC_ISER_SETENA_4 c:macro@NVIC_ISER_SETENA_5 c:macro@NVIC_ISER_SETENA_6 c:macro@NVIC_ISER_SETENA_7 c:macro@NVIC_ISER_SETENA_8 c:macro@NVIC_ISER_SETENA_9 c:macro@NVIC_ISER_SETENA_10 c:macro@NVIC_ISER_SETENA_11 c:macro@NVIC_ISER_SETENA_12 c:macro@NVIC_ISER_SETENA_13 c:macro@NVIC_ISER_SETENA_14 c:macro@NVIC_ISER_SETENA_15 c:macro@NVIC_ISER_SETENA_16 c:macro@NVIC_ISER_SETENA_17 c:macro@NVIC_ISER_SETENA_18 c:macro@NVIC_ISER_SETENA_19 c:macro@NVIC_ISER_SETENA_20 c:macro@NVIC_ISER_SETENA_21 c:macro@NVIC_ISER_SETENA_22 c:macro@NVIC_ISER_SETENA_23 c:macro@NVIC_ISER_SETENA_24 c:macro@NVIC_ISER_SETENA_25 c:macro@NVIC_ISER_SETENA_26 c:macro@NVIC_ISER_SETENA_27 c:macro@NVIC_ISER_SETENA_28 c:macro@NVIC_ISER_SETENA_29 c:macro@NVIC_ISER_SETENA_30 c:macro@NVIC_ISER_SETENA_31 c:macro@NVIC_ICER_CLRENA c:macro@NVIC_ICER_CLRENA_0 c:macro@NVIC_ICER_CLRENA_1 c:macro@NVIC_ICER_CLRENA_2 c:macro@NVIC_ICER_CLRENA_3 c:macro@NVIC_ICER_CLRENA_4 c:macro@NVIC_ICER_CLRENA_5 c:macro@NVIC_ICER_CLRENA_6 c:macro@NVIC_ICER_CLRENA_7 c:macro@NVIC_ICER_CLRENA_8 c:macro@NVIC_ICER_CLRENA_9 c:macro@NVIC_ICER_CLRENA_10 c:macro@NVIC_ICER_CLRENA_11 c:macro@NVIC_ICER_CLRENA_12 c:macro@NVIC_ICER_CLRENA_13 c:macro@NVIC_ICER_CLRENA_14 c:macro@NVIC_ICER_CLRENA_15 c:macro@NVIC_ICER_CLRENA_16 c:macro@NVIC_ICER_CLRENA_17 c:macro@NVIC_ICER_CLRENA_18 c:macro@NVIC_ICER_CLRENA_19 c:macro@NVIC_ICER_CLRENA_20 c:macro@NVIC_ICER_CLRENA_21 c:macro@NVIC_ICER_CLRENA_22 c:macro@NVIC_ICER_CLRENA_23 c:macro@NVIC_ICER_CLRENA_24 c:macro@NVIC_ICER_CLRENA_25 c:macro@NVIC_ICER_CLRENA_26 c:macro@NVIC_ICER_CLRENA_27 c:macro@NVIC_ICER_CLRENA_28 c:macro@NVIC_ICER_CLRENA_29 c:macro@NVIC_ICER_CLRENA_30 c:macro@NVIC_ICER_CLRENA_31 c:macro@NVIC_ISPR_SETPEND c:macro@NVIC_ISPR_SETPEND_0 c:macro@NVIC_ISPR_SETPEND_1 c:macro@NVIC_ISPR_SETPEND_2 c:macro@NVIC_ISPR_SETPEND_3 c:macro@NVIC_ISPR_SETPEND_4 c:macro@NVIC_ISPR_SETPEND_5 c:macro@NVIC_ISPR_SETPEND_6 c:macro@NVIC_ISPR_SETPEND_7 c:macro@NVIC_ISPR_SETPEND_8 c:macro@NVIC_ISPR_SETPEND_9 c:macro@NVIC_ISPR_SETPEND_10 c:macro@NVIC_ISPR_SETPEND_11 c:macro@NVIC_ISPR_SETPEND_12 c:macro@NVIC_ISPR_SETPEND_13 c:macro@NVIC_ISPR_SETPEND_14 c:macro@NVIC_ISPR_SETPEND_15 c:macro@NVIC_ISPR_SETPEND_16 c:macro@NVIC_ISPR_SETPEND_17 c:macro@NVIC_ISPR_SETPEND_18 c:macro@NVIC_ISPR_SETPEND_19 c:macro@NVIC_ISPR_SETPEND_20 c:macro@NVIC_ISPR_SETPEND_21 c:macro@NVIC_ISPR_SETPEND_22 c:macro@NVIC_ISPR_SETPEND_23 c:macro@NVIC_ISPR_SETPEND_24 c:macro@NVIC_ISPR_SETPEND_25 c:macro@NVIC_ISPR_SETPEND_26 c:macro@NVIC_ISPR_SETPEND_27 c:macro@NVIC_ISPR_SETPEND_28 c:macro@NVIC_ISPR_SETPEND_29 c:macro@NVIC_ISPR_SETPEND_30 c:macro@NVIC_ISPR_SETPEND_31 c:macro@NVIC_ICPR_CLRPEND c:macro@NVIC_ICPR_CLRPEND_0 c:macro@NVIC_ICPR_CLRPEND_1 c:macro@NVIC_ICPR_CLRPEND_2 c:macro@NVIC_ICPR_CLRPEND_3 c:macro@NVIC_ICPR_CLRPEND_4 c:macro@NVIC_ICPR_CLRPEND_5 c:macro@NVIC_ICPR_CLRPEND_6 c:macro@NVIC_ICPR_CLRPEND_7 c:macro@NVIC_ICPR_CLRPEND_8 c:macro@NVIC_ICPR_CLRPEND_9 c:macro@NVIC_ICPR_CLRPEND_10 c:macro@NVIC_ICPR_CLRPEND_11 c:macro@NVIC_ICPR_CLRPEND_12 c:macro@NVIC_ICPR_CLRPEND_13 c:macro@NVIC_ICPR_CLRPEND_14 c:macro@NVIC_ICPR_CLRPEND_15 c:macro@NVIC_ICPR_CLRPEND_16 c:macro@NVIC_ICPR_CLRPEND_17 c:macro@NVIC_ICPR_CLRPEND_18 c:macro@NVIC_ICPR_CLRPEND_19 c:macro@NVIC_ICPR_CLRPEND_20 c:macro@NVIC_ICPR_CLRPEND_21 c:macro@NVIC_ICPR_CLRPEND_22 c:macro@NVIC_ICPR_CLRPEND_23 c:macro@NVIC_ICPR_CLRPEND_24 c:macro@NVIC_ICPR_CLRPEND_25 c:macro@NVIC_ICPR_CLRPEND_26 c:macro@NVIC_ICPR_CLRPEND_27 c:macro@NVIC_ICPR_CLRPEND_28 c:macro@NVIC_ICPR_CLRPEND_29 c:macro@NVIC_ICPR_CLRPEND_30 c:macro@NVIC_ICPR_CLRPEND_31 c:macro@NVIC_IABR_ACTIVE c:macro@NVIC_IABR_ACTIVE_0 c:macro@NVIC_IABR_ACTIVE_1 c:macro@NVIC_IABR_ACTIVE_2 c:macro@NVIC_IABR_ACTIVE_3 c:macro@NVIC_IABR_ACTIVE_4 c:macro@NVIC_IABR_ACTIVE_5 c:macro@NVIC_IABR_ACTIVE_6 c:macro@NVIC_IABR_ACTIVE_7 c:macro@NVIC_IABR_ACTIVE_8 c:macro@NVIC_IABR_ACTIVE_9 c:macro@NVIC_IABR_ACTIVE_10 c:macro@NVIC_IABR_ACTIVE_11 c:macro@NVIC_IABR_ACTIVE_12 c:macro@NVIC_IABR_ACTIVE_13 c:macro@NVIC_IABR_ACTIVE_14 c:macro@NVIC_IABR_ACTIVE_15 c:macro@NVIC_IABR_ACTIVE_16 c:macro@NVIC_IABR_ACTIVE_17 c:macro@NVIC_IABR_ACTIVE_18 c:macro@NVIC_IABR_ACTIVE_19 c:macro@NVIC_IABR_ACTIVE_20 c:macro@NVIC_IABR_ACTIVE_21 c:macro@NVIC_IABR_ACTIVE_22 c:macro@NVIC_IABR_ACTIVE_23 c:macro@NVIC_IABR_ACTIVE_24 c:macro@NVIC_IABR_ACTIVE_25 c:macro@NVIC_IABR_ACTIVE_26 c:macro@NVIC_IABR_ACTIVE_27 c:macro@NVIC_IABR_ACTIVE_28 c:macro@NVIC_IABR_ACTIVE_29 c:macro@NVIC_IABR_ACTIVE_30 c:macro@NVIC_IABR_ACTIVE_31 c:macro@NVIC_IPR0_PRI_0 c:macro@NVIC_IPR0_PRI_1 c:macro@NVIC_IPR0_PRI_2 c:macro@NVIC_IPR0_PRI_3 c:macro@NVIC_IPR1_PRI_4 c:macro@NVIC_IPR1_PRI_5 c:macro@NVIC_IPR1_PRI_6 c:macro@NVIC_IPR1_PRI_7 c:macro@NVIC_IPR2_PRI_8 c:macro@NVIC_IPR2_PRI_9 c:macro@NVIC_IPR2_PRI_10 c:macro@NVIC_IPR2_PRI_11 c:macro@NVIC_IPR3_PRI_12 c:macro@NVIC_IPR3_PRI_13 c:macro@NVIC_IPR3_PRI_14 c:macro@NVIC_IPR3_PRI_15 c:macro@NVIC_IPR4_PRI_16 c:macro@NVIC_IPR4_PRI_17 c:macro@NVIC_IPR4_PRI_18 c:macro@NVIC_IPR4_PRI_19 c:macro@NVIC_IPR5_PRI_20 c:macro@NVIC_IPR5_PRI_21 c:macro@NVIC_IPR5_PRI_22 c:macro@NVIC_IPR5_PRI_23 c:macro@NVIC_IPR6_PRI_24 c:macro@NVIC_IPR6_PRI_25 c:macro@NVIC_IPR6_PRI_26 c:macro@NVIC_IPR6_PRI_27 c:macro@NVIC_IPR7_PRI_28 c:macro@NVIC_IPR7_PRI_29 c:macro@NVIC_IPR7_PRI_30 c:macro@NVIC_IPR7_PRI_31 c:macro@SCB_CPUID_REVISION c:macro@SCB_CPUID_PARTNO c:macro@SCB_CPUID_Constant c:macro@SCB_CPUID_VARIANT c:macro@SCB_CPUID_IMPLEMENTER c:macro@SCB_ICSR_VECTACTIVE c:macro@SCB_ICSR_RETTOBASE c:macro@SCB_ICSR_VECTPENDING c:macro@SCB_ICSR_ISRPENDING c:macro@SCB_ICSR_ISRPREEMPT c:macro@SCB_ICSR_PENDSTCLR c:macro@SCB_ICSR_PENDSTSET c:macro@SCB_ICSR_PENDSVCLR c:macro@SCB_ICSR_PENDSVSET c:macro@SCB_ICSR_NMIPENDSET c:macro@SCB_VTOR_TBLOFF c:macro@SCB_VTOR_TBLBASE c:macro@SCB_AIRCR_VECTRESET c:macro@SCB_AIRCR_VECTCLRACTIVE c:macro@SCB_AIRCR_SYSRESETREQ c:macro@SCB_AIRCR_PRIGROUP c:macro@SCB_AIRCR_PRIGROUP_0 c:macro@SCB_AIRCR_PRIGROUP_1 c:macro@SCB_AIRCR_PRIGROUP_2 c:macro@SCB_AIRCR_PRIGROUP0 c:macro@SCB_AIRCR_PRIGROUP1 c:macro@SCB_AIRCR_PRIGROUP2 c:macro@SCB_AIRCR_PRIGROUP3 c:macro@SCB_AIRCR_PRIGROUP4 c:macro@SCB_AIRCR_PRIGROUP5 c:macro@SCB_AIRCR_PRIGROUP6 c:macro@SCB_AIRCR_PRIGROUP7 c:macro@SCB_AIRCR_ENDIANESS c:macro@SCB_AIRCR_VECTKEY c:macro@SCB_SCR_SLEEPONEXIT c:macro@SCB_SCR_SLEEPDEEP c:macro@SCB_SCR_SEVONPEND c:macro@SCB_CCR_NONBASETHRDENA c:macro@SCB_CCR_USERSETMPEND c:macro@SCB_CCR_UNALIGN_TRP c:macro@SCB_CCR_DIV_0_TRP c:macro@SCB_CCR_BFHFNMIGN c:macro@SCB_CCR_STKALIGN c:macro@SCB_SHPR_PRI_N c:macro@SCB_SHPR_PRI_N1 c:macro@SCB_SHPR_PRI_N2 c:macro@SCB_SHPR_PRI_N3 c:macro@SCB_SHCSR_MEMFAULTACT c:macro@SCB_SHCSR_BUSFAULTACT c:macro@SCB_SHCSR_USGFAULTACT c:macro@SCB_SHCSR_SVCALLACT c:macro@SCB_SHCSR_MONITORACT c:macro@SCB_SHCSR_PENDSVACT c:macro@SCB_SHCSR_SYSTICKACT c:macro@SCB_SHCSR_USGFAULTPENDED c:macro@SCB_SHCSR_MEMFAULTPENDED c:macro@SCB_SHCSR_BUSFAULTPENDED c:macro@SCB_SHCSR_SVCALLPENDED c:macro@SCB_SHCSR_MEMFAULTENA c:macro@SCB_SHCSR_BUSFAULTENA c:macro@SCB_SHCSR_USGFAULTENA c:macro@SCB_CFSR_IACCVIOL c:macro@SCB_CFSR_DACCVIOL c:macro@SCB_CFSR_MUNSTKERR c:macro@SCB_CFSR_MSTKERR c:macro@SCB_CFSR_MMARVALID c:macro@SCB_CFSR_IBUSERR c:macro@SCB_CFSR_PRECISERR c:macro@SCB_CFSR_IMPRECISERR c:macro@SCB_CFSR_UNSTKERR c:macro@SCB_CFSR_STKERR c:macro@SCB_CFSR_BFARVALID c:macro@SCB_CFSR_UNDEFINSTR c:macro@SCB_CFSR_INVSTATE c:macro@SCB_CFSR_INVPC c:macro@SCB_CFSR_NOCP c:macro@SCB_CFSR_UNALIGNED c:macro@SCB_CFSR_DIVBYZERO c:macro@SCB_HFSR_VECTTBL c:macro@SCB_HFSR_FORCED c:macro@SCB_HFSR_DEBUGEVT c:macro@SCB_DFSR_HALTED c:macro@SCB_DFSR_BKPT c:macro@SCB_DFSR_DWTTRAP c:macro@SCB_DFSR_VCATCH c:macro@SCB_DFSR_EXTERNAL c:macro@SCB_MMFAR_ADDRESS c:macro@SCB_BFAR_ADDRESS c:macro@SCB_AFSR_IMPDEF c:macro@SET_BIT c:macro@CLEAR_BIT c:macro@READ_BIT c:macro@CLEAR_REG c:macro@WRITE_REG c:macro@READ_REG c:macro@MODIFY_REG c:macro@STM32_TIM1 c:macro@STM32_TIM2 c:macro@STM32_TIM3 c:macro@STM32_TIM4 c:macro@STM32_TIM5 c:macro@STM32_TIM6 c:macro@STM32_TIM7 c:macro@STM32_TIM8 c:macro@STM32_TIM9 c:macro@STM32_TIM10 c:macro@STM32_TIM11 c:macro@STM32_TIM12 c:macro@STM32_TIM13 c:macro@STM32_TIM14 c:macro@HAL_IMPLEMENTS_COUNTERS c:macro@PLATFORM_NAME c:macro@STM32_HSICLK c:macro@STM32_LSICLK c:macro@STM32_VOS_MASK c:macro@STM32_VOS_1P8 c:macro@STM32_VOS_1P5 c:macro@STM32_VOS_1P2 c:macro@STM32_PLS_MASK c:macro@STM32_PLS_LEV0 c:macro@STM32_PLS_LEV1 c:macro@STM32_PLS_LEV2 c:macro@STM32_PLS_LEV3 c:macro@STM32_PLS_LEV4 c:macro@STM32_PLS_LEV5 c:macro@STM32_PLS_LEV6 c:macro@STM32_PLS_LEV7 c:macro@STM32_RTCPRE_MASK c:macro@STM32_RTCPRE_DIV2 c:macro@STM32_RTCPRE_DIV4 c:macro@STM32_RTCPRE_DIV8 c:macro@STM32_RTCPRE_DIV16 c:macro@STM32_SW_MSI c:macro@STM32_SW_HSI c:macro@STM32_SW_HSE c:macro@STM32_SW_PLL c:macro@STM32_HPRE_DIV1 c:macro@STM32_HPRE_DIV2 c:macro@STM32_HPRE_DIV4 c:macro@STM32_HPRE_DIV8 c:macro@STM32_HPRE_DIV16 c:macro@STM32_HPRE_DIV64 c:macro@STM32_HPRE_DIV128 c:macro@STM32_HPRE_DIV256 c:macro@STM32_HPRE_DIV512 c:macro@STM32_PPRE1_DIV1 c:macro@STM32_PPRE1_DIV2 c:macro@STM32_PPRE1_DIV4 c:macro@STM32_PPRE1_DIV8 c:macro@STM32_PPRE1_DIV16 c:macro@STM32_PPRE2_DIV1 c:macro@STM32_PPRE2_DIV2 c:macro@STM32_PPRE2_DIV4 c:macro@STM32_PPRE2_DIV8 c:macro@STM32_PPRE2_DIV16 c:macro@STM32_PLLSRC_HSI c:macro@STM32_PLLSRC_HSE c:macro@STM32_MCOSEL_NOCLOCK c:macro@STM32_MCOSEL_SYSCLK c:macro@STM32_MCOSEL_HSI c:macro@STM32_MCOSEL_MSI c:macro@STM32_MCOSEL_HSE c:macro@STM32_MCOSEL_PLL c:macro@STM32_MCOSEL_LSI c:macro@STM32_MCOSEL_LSE c:macro@STM32_MCOPRE_DIV1 c:macro@STM32_MCOPRE_DIV2 c:macro@STM32_MCOPRE_DIV4 c:macro@STM32_MCOPRE_DIV8 c:macro@STM32_MCOPRE_DIV16 c:macro@STM32_MSIRANGE_MASK c:macro@STM32_MSIRANGE_64K c:macro@STM32_MSIRANGE_128K c:macro@STM32_MSIRANGE_256K c:macro@STM32_MSIRANGE_512K c:macro@STM32_MSIRANGE_1M c:macro@STM32_MSIRANGE_2M c:macro@STM32_MSIRANGE_4M c:macro@STM32_RTCSEL_MASK c:macro@STM32_RTCSEL_NOCLOCK c:macro@STM32_RTCSEL_LSE c:macro@STM32_RTCSEL_LSI c:macro@STM32_RTCSEL_HSEDIV c:macro@STM32_HAS_ADC1 c:macro@STM32_HAS_ADC2 c:macro@STM32_HAS_ADC3 c:macro@STM32_HAS_ADC4 c:macro@STM32_HAS_CAN1 c:macro@STM32_HAS_CAN2 c:macro@STM32_CAN_MAX_FILTERS c:macro@STM32_HAS_DAC c:macro@STM32_ADVANCED_DMA c:macro@STM32_HAS_DMA1 c:macro@STM32_HAS_DMA2 c:macro@STM32_HAS_ETH c:macro@STM32_EXTI_NUM_CHANNELS c:macro@STM32_HAS_GPIOA c:macro@STM32_HAS_GPIOB c:macro@STM32_HAS_GPIOC c:macro@STM32_HAS_GPIOD c:macro@STM32_HAS_GPIOE c:macro@STM32_HAS_GPIOF c:macro@STM32_HAS_GPIOG c:macro@STM32_HAS_GPIOH c:macro@STM32_HAS_GPIOI c:macro@STM32_HAS_I2C1 c:macro@STM32_I2C1_RX_DMA_MSK c:macro@STM32_I2C1_RX_DMA_CHN c:macro@STM32_I2C1_TX_DMA_MSK c:macro@STM32_I2C1_TX_DMA_CHN c:macro@STM32_HAS_I2C2 c:macro@STM32_I2C2_RX_DMA_MSK c:macro@STM32_I2C2_RX_DMA_CHN c:macro@STM32_I2C2_TX_DMA_MSK c:macro@STM32_I2C2_TX_DMA_CHN c:macro@STM32_HAS_I2C3 c:macro@STM32_I2C3_RX_DMA_MSK c:macro@STM32_I2C3_RX_DMA_CHN c:macro@STM32_I2C3_TX_DMA_MSK c:macro@STM32_I2C3_TX_DMA_CHN c:macro@STM32_HAS_RTC c:macro@STM32_RTC_HAS_SUBSECONDS c:macro@STM32_RTC_IS_CALENDAR c:macro@STM32_HAS_SDIO c:macro@STM32_HAS_SPI1 c:macro@STM32_SPI1_RX_DMA_MSK c:macro@STM32_SPI1_RX_DMA_CHN c:macro@STM32_SPI1_TX_DMA_MSK c:macro@STM32_SPI1_TX_DMA_CHN c:macro@STM32_HAS_SPI2 c:macro@STM32_SPI2_RX_DMA_MSK c:macro@STM32_SPI2_RX_DMA_CHN c:macro@STM32_SPI2_TX_DMA_MSK c:macro@STM32_SPI2_TX_DMA_CHN c:macro@STM32_HAS_SPI3 c:macro@STM32_SPI3_RX_DMA_MSK c:macro@STM32_SPI3_RX_DMA_CHN c:macro@STM32_SPI3_TX_DMA_MSK c:macro@STM32_SPI3_TX_DMA_CHN c:macro@STM32_HAS_TIM1 c:macro@STM32_HAS_TIM2 c:macro@STM32_HAS_TIM3 c:macro@STM32_HAS_TIM4 c:macro@STM32_HAS_TIM5 c:macro@STM32_HAS_TIM6 c:macro@STM32_HAS_TIM7 c:macro@STM32_HAS_TIM8 c:macro@STM32_HAS_TIM9 c:macro@STM32_HAS_TIM10 c:macro@STM32_HAS_TIM11 c:macro@STM32_HAS_TIM12 c:macro@STM32_HAS_TIM13 c:macro@STM32_HAS_TIM14 c:macro@STM32_HAS_TIM15 c:macro@STM32_HAS_TIM16 c:macro@STM32_HAS_TIM17 c:macro@STM32_HAS_TIM18 c:macro@STM32_HAS_TIM19 c:macro@STM32_HAS_USART1 c:macro@STM32_USART1_RX_DMA_MSK c:macro@STM32_USART1_RX_DMA_CHN c:macro@STM32_USART1_TX_DMA_MSK c:macro@STM32_USART1_TX_DMA_CHN c:macro@STM32_HAS_USART2 c:macro@STM32_USART2_RX_DMA_MSK c:macro@STM32_USART2_RX_DMA_CHN c:macro@STM32_USART2_TX_DMA_MSK c:macro@STM32_USART2_TX_DMA_CHN c:macro@STM32_HAS_USART3 c:macro@STM32_USART3_RX_DMA_MSK c:macro@STM32_USART3_RX_DMA_CHN c:macro@STM32_USART3_TX_DMA_MSK c:macro@STM32_USART3_TX_DMA_CHN c:macro@STM32_HAS_UART4 c:macro@STM32_UART4_RX_DMA_MSK c:macro@STM32_UART4_RX_DMA_CHN c:macro@STM32_UART4_TX_DMA_MSK c:macro@STM32_UART4_TX_DMA_CHN c:macro@STM32_HAS_UART5 c:macro@STM32_UART5_RX_DMA_MSK c:macro@STM32_UART5_RX_DMA_CHN c:macro@STM32_UART5_TX_DMA_MSK c:macro@STM32_UART5_TX_DMA_CHN c:macro@STM32_HAS_USART6 c:macro@STM32_USART6_RX_DMA_MSK c:macro@STM32_USART6_RX_DMA_CHN c:macro@STM32_USART6_TX_DMA_MSK c:macro@STM32_USART6_TX_DMA_CHN c:macro@STM32_HAS_USB c:macro@STM32_HAS_OTG1 c:macro@STM32_HAS_OTG2 c:macro@WWDG_IRQHandler c:macro@PVD_IRQHandler c:macro@TAMPER_STAMP_IRQHandler c:macro@RTC_WKUP_IRQHandler c:macro@FLASH_IRQHandler c:macro@RCC_IRQHandler c:macro@EXTI0_IRQHandler c:macro@EXTI1_IRQHandler c:macro@EXTI2_IRQHandler c:macro@EXTI3_IRQHandler c:macro@EXTI4_IRQHandler c:macro@DMA1_Ch1_IRQHandler c:macro@DMA1_Ch2_IRQHandler c:macro@DMA1_Ch3_IRQHandler c:macro@DMA1_Ch4_IRQHandler c:macro@DMA1_Ch5_IRQHandler c:macro@DMA1_Ch6_IRQHandler c:macro@DMA1_Ch7_IRQHandler c:macro@ADC1_IRQHandler c:macro@USB_HP_IRQHandler c:macro@USB_LP_IRQHandler c:macro@DAC_IRQHandler c:macro@COMP_IRQHandler c:macro@EXTI9_5_IRQHandler c:macro@TIM9_IRQHandler c:macro@TIM10_IRQHandler c:macro@TIM11_IRQHandler c:macro@LCD_IRQHandler c:macro@TIM2_IRQHandler c:macro@TIM3_IRQHandler c:macro@TIM4_IRQHandler c:macro@I2C1_EV_IRQHandler c:macro@I2C1_ER_IRQHandler c:macro@I2C2_EV_IRQHandler c:macro@I2C2_ER_IRQHandler c:macro@SPI1_IRQHandler c:macro@SPI2_IRQHandler c:macro@USART1_IRQHandler c:macro@USART2_IRQHandler c:macro@USART3_IRQHandler c:macro@EXTI15_10_IRQHandler c:macro@RTC_Alarm_IRQHandler c:macro@USB_FS_WKUP_IRQHandler c:macro@TIM6_IRQHandler c:macro@TIM7_IRQHandler c:macro@STM32_HSECLK_MAX c:macro@STM32_SYSCLK_MAX c:macro@STM32_PLLVCO_MAX c:macro@STM32_PLLVCO_MIN c:macro@STM32_PCLK1_MAX c:macro@STM32_PCLK2_MAX c:macro@STM32_0WS_THRESHOLD c:macro@STM32_HSI_AVAILABLE c:macro@STM32_ACTIVATE_PLL c:macro@STM32_PLLMUL c:macro@STM32_PLLDIV c:macro@STM32_PLLCLKIN c:macro@STM32_PLLVCO c:macro@STM32_PLLCLKOUT c:macro@STM32_MSICLK c:macro@STM32_SYSCLK c:macro@STM32_HCLK c:macro@STM32_PCLK1 c:macro@STM32_PCLK2 c:macro@STM_MCODIVCLK c:macro@STM_MCOCLK c:macro@STM32_HSEDIVCLK c:macro@STM_RTCCLK c:macro@STM32_ADCCLK c:macro@STM32_USBCLK c:macro@STM32_TIMCLK1 c:macro@STM32_TIMCLK2 c:macro@STM32_FLASHBITS1 c:macro@STM32_FLASHBITS2 c:macro@hal_lld_get_counter_value c:macro@hal_lld_get_counter_frequency c:macro@_STM32_ISR_H_ c:macro@STM32_TIM2_HANDLER c:macro@STM32_TIM3_HANDLER c:macro@STM32_TIM4_HANDLER c:macro@STM32_TIM2_NUMBER c:macro@STM32_TIM3_NUMBER c:macro@STM32_TIM4_NUMBER c:macro@STM32_USART1_HANDLER c:macro@STM32_USART2_HANDLER c:macro@STM32_USART3_HANDLER c:macro@STM32_USART1_NUMBER c:macro@STM32_USART2_NUMBER c:macro@STM32_USART3_NUMBER c:macro@STM32_USB1_HP_HANDLER c:macro@STM32_USB1_LP_HANDLER c:macro@STM32_USB1_HP_NUMBER c:macro@STM32_USB1_LP_NUMBER c:macro@_STM32_DMA_H_ c:macro@STM32_DMA_STREAMS c:macro@STM32_DMA_ISR_MASK c:macro@STM32_DMA_GETCHANNEL c:macro@STM32_DMA_IS_VALID_PRIORITY c:macro@STM32_DMA_STREAM_ID c:macro@STM32_DMA_STREAM_ID_MSK c:macro@STM32_DMA_IS_VALID_ID c:macro@STM32_DMA_STREAM c:macro@STM32_DMA1_STREAM1 c:macro@STM32_DMA1_STREAM2 c:macro@STM32_DMA1_STREAM3 c:macro@STM32_DMA1_STREAM4 c:macro@STM32_DMA1_STREAM5 c:macro@STM32_DMA1_STREAM6 c:macro@STM32_DMA1_STREAM7 c:macro@STM32_DMA_CR_EN c:macro@STM32_DMA_CR_TEIE c:macro@STM32_DMA_CR_HTIE c:macro@STM32_DMA_CR_TCIE c:macro@STM32_DMA_CR_DIR_MASK c:macro@STM32_DMA_CR_DIR_P2M c:macro@STM32_DMA_CR_DIR_M2P c:macro@STM32_DMA_CR_DIR_M2M c:macro@STM32_DMA_CR_CIRC c:macro@STM32_DMA_CR_PINC c:macro@STM32_DMA_CR_MINC c:macro@STM32_DMA_CR_PSIZE_MASK c:macro@STM32_DMA_CR_PSIZE_BYTE c:macro@STM32_DMA_CR_PSIZE_HWORD c:macro@STM32_DMA_CR_PSIZE_WORD c:macro@STM32_DMA_CR_MSIZE_MASK c:macro@STM32_DMA_CR_MSIZE_BYTE c:macro@STM32_DMA_CR_MSIZE_HWORD c:macro@STM32_DMA_CR_MSIZE_WORD c:macro@STM32_DMA_CR_SIZE_MASK c:macro@STM32_DMA_CR_PL_MASK c:macro@STM32_DMA_CR_PL c:macro@STM32_DMA_CR_DMEIE c:macro@STM32_DMA_CR_CHSEL_MASK c:macro@STM32_DMA_CR_CHSEL c:macro@STM32_DMA_ISR_FEIF c:macro@STM32_DMA_ISR_DMEIF c:macro@STM32_DMA_ISR_TEIF c:macro@STM32_DMA_ISR_HTIF c:macro@STM32_DMA_ISR_TCIF c:macro@dmaStreamSetPeripheral c:macro@dmaStreamSetMemory0 c:macro@dmaStreamSetTransactionSize c:macro@dmaStreamGetTransactionSize c:macro@dmaStreamSetMode c:macro@dmaStreamEnable c:macro@dmaStreamDisable c:macro@dmaStreamClearInterrupt c:macro@dmaStartMemCopy c:macro@dmaWaitCompletion c:macro@_STM32_RCC_ c:macro@rccEnableAPB1 c:macro@rccDisableAPB1 c:macro@rccResetAPB1 c:macro@rccEnableAPB2 c:macro@rccDisableAPB2 c:macro@rccResetAPB2 c:macro@rccEnableAHB c:macro@rccDisableAHB c:macro@rccResetAHB c:macro@rccEnableADC1 c:macro@rccDisableADC1 c:macro@rccResetADC1 c:macro@rccEnableDMA1 c:macro@rccDisableDMA1 c:macro@rccResetDMA1 c:macro@rccEnablePWRInterface c:macro@rccDisablePWRInterface c:macro@rccResetPWRInterface c:macro@rccEnableI2C1 c:macro@rccDisableI2C1 c:macro@rccResetI2C1 c:macro@rccEnableI2C2 c:macro@rccDisableI2C2 c:macro@rccResetI2C2 c:macro@rccEnableSPI1 c:macro@rccDisableSPI1 c:macro@rccResetSPI1 c:macro@rccEnableSPI2 c:macro@rccDisableSPI2 c:macro@rccResetSPI2 c:macro@rccEnableTIM2 c:macro@rccDisableTIM2 c:macro@rccResetTIM2 c:macro@rccEnableTIM3 c:macro@rccDisableTIM3 c:macro@rccResetTIM3 c:macro@rccEnableTIM4 c:macro@rccDisableTIM4 c:macro@rccResetTIM4 c:macro@rccEnableUSART1 c:macro@rccDisableUSART1 c:macro@rccResetUSART1 c:macro@rccEnableUSART2 c:macro@rccDisableUSART2 c:macro@rccResetUSART2 c:macro@rccEnableUSART3 c:macro@rccDisableUSART3 c:macro@rccResetUSART3 c:macro@rccEnableUSB c:macro@rccDisableUSB c:macro@rccResetUSB c:macro@_IO_CHANNEL_H_ c:macro@_base_channel_methods c:macro@_base_channel_data c:macro@chnPutTimeout c:macro@chnGetTimeout c:macro@chnWrite c:macro@chnWriteTimeout c:macro@chnRead c:macro@chnReadTimeout c:macro@CHN_NO_ERROR c:macro@CHN_CONNECTED c:macro@CHN_DISCONNECTED c:macro@CHN_INPUT_AVAILABLE c:macro@CHN_OUTPUT_EMPTY c:macro@CHN_TRANSMISSION_END c:macro@_base_asynchronous_channel_methods c:macro@_base_asynchronous_channel_data c:macro@chnGetEventSource c:macro@chnAddFlagsI c:macro@_IO_BLOCK_H_ c:macro@_base_block_device_methods c:macro@_base_block_device_data c:macro@blkGetDriverState c:macro@blkIsTransferring c:macro@blkIsInserted c:macro@blkIsWriteProtected c:macro@blkConnect c:macro@blkDisconnect c:macro@blkRead c:macro@blkWrite c:macro@blkSync c:macro@blkGetInfo c:macro@_MMCSD_H_ c:macro@_TM_H_ c:macro@tmStartMeasurement c:macro@tmStopMeasurement c:macro@_PAL_H_ c:macro@PAL_MODE_RESET c:macro@PAL_MODE_UNCONNECTED c:macro@PAL_MODE_INPUT c:macro@PAL_MODE_INPUT_PULLUP c:macro@PAL_MODE_INPUT_PULLDOWN c:macro@PAL_MODE_INPUT_ANALOG c:macro@PAL_MODE_OUTPUT_PUSHPULL c:macro@PAL_MODE_OUTPUT_OPENDRAIN c:macro@PAL_LOW c:macro@PAL_HIGH c:macro@_PAL_LLD_H_ c:macro@PAL_STM32_MODE_MASK c:macro@PAL_STM32_MODE_INPUT c:macro@PAL_STM32_MODE_OUTPUT c:macro@PAL_STM32_MODE_ALTERNATE c:macro@PAL_STM32_MODE_ANALOG c:macro@PAL_STM32_OTYPE_MASK c:macro@PAL_STM32_OTYPE_PUSHPULL c:macro@PAL_STM32_OTYPE_OPENDRAIN c:macro@PAL_STM32_OSPEED_MASK c:macro@PAL_STM32_OSPEED_LOWEST c:macro@PAL_STM32_OSPEED_MID1 c:macro@PAL_STM32_OSPEED_MID2 c:macro@PAL_STM32_OSPEED_HIGHEST c:macro@PAL_STM32_PUDR_MASK c:macro@PAL_STM32_PUDR_FLOATING c:macro@PAL_STM32_PUDR_PULLUP c:macro@PAL_STM32_PUDR_PULLDOWN c:macro@PAL_STM32_ALTERNATE_MASK c:macro@PAL_STM32_ALTERNATE c:macro@PAL_MODE_ALTERNATE c:macro@PAL_IOPORTS_WIDTH c:macro@PAL_WHOLE_PORT c:macro@IOPORT1 c:macro@IOPORT2 c:macro@IOPORT3 c:macro@IOPORT4 c:macro@IOPORT5 c:macro@IOPORT8 c:macro@pal_lld_init c:macro@pal_lld_readport c:macro@pal_lld_readlatch c:macro@pal_lld_writeport c:macro@pal_lld_setport c:macro@pal_lld_clearport c:macro@pal_lld_writegroup c:macro@pal_lld_setgroupmode c:macro@pal_lld_writepad c:macro@PAL_PORT_BIT c:macro@PAL_GROUP_MASK c:macro@_IOBUS_DATA c:macro@IOBUS_DECL c:macro@palInit c:macro@palReadPort c:macro@palReadLatch c:macro@palWritePort c:macro@palSetPort c:macro@palClearPort c:macro@palTogglePort c:macro@palReadGroup c:macro@palWriteGroup c:macro@palSetGroupMode c:macro@palReadPad c:macro@palWritePad c:macro@palSetPad c:macro@palClearPad c:macro@palTogglePad c:macro@palSetPadMode c:macro@_ADC_H_ c:macro@_ADC_LLD_H_ c:macro@ADC_CR2_EXTSEL_SRC c:macro@ADC_CCR_ADCPRE_DIV1 c:macro@ADC_CCR_ADCPRE_DIV2 c:macro@ADC_CCR_ADCPRE_DIV4 c:macro@ADC_CHANNEL_IN0 c:macro@ADC_CHANNEL_IN1 c:macro@ADC_CHANNEL_IN2 c:macro@ADC_CHANNEL_IN3 c:macro@ADC_CHANNEL_IN4 c:macro@ADC_CHANNEL_IN5 c:macro@ADC_CHANNEL_IN6 c:macro@ADC_CHANNEL_IN7 c:macro@ADC_CHANNEL_IN8 c:macro@ADC_CHANNEL_IN9 c:macro@ADC_CHANNEL_IN10 c:macro@ADC_CHANNEL_IN11 c:macro@ADC_CHANNEL_IN12 c:macro@ADC_CHANNEL_IN13 c:macro@ADC_CHANNEL_IN14 c:macro@ADC_CHANNEL_IN15 c:macro@ADC_CHANNEL_SENSOR c:macro@ADC_CHANNEL_VREFINT c:macro@ADC_CHANNEL_IN18 c:macro@ADC_CHANNEL_IN19 c:macro@ADC_CHANNEL_IN20 c:macro@ADC_CHANNEL_IN21 c:macro@ADC_CHANNEL_IN22 c:macro@ADC_CHANNEL_IN23 c:macro@ADC_CHANNEL_IN24 c:macro@ADC_CHANNEL_IN25 c:macro@ADC_SAMPLE_4 c:macro@ADC_SAMPLE_9 c:macro@ADC_SAMPLE_16 c:macro@ADC_SAMPLE_24 c:macro@ADC_SAMPLE_48 c:macro@ADC_SAMPLE_96 c:macro@ADC_SAMPLE_192 c:macro@ADC_SAMPLE_384 c:macro@STM32_ADC_ADCPRE c:macro@STM32_DMA_REQUIRED c:macro@ADC_SQR1_NUM_CH c:macro@ADC_SQR5_SQ1_N c:macro@ADC_SQR5_SQ2_N c:macro@ADC_SQR5_SQ3_N c:macro@ADC_SQR5_SQ4_N c:macro@ADC_SQR5_SQ5_N c:macro@ADC_SQR5_SQ6_N c:macro@ADC_SQR4_SQ7_N c:macro@ADC_SQR4_SQ8_N c:macro@ADC_SQR4_SQ9_N c:macro@ADC_SQR4_SQ10_N c:macro@ADC_SQR4_SQ11_N c:macro@ADC_SQR4_SQ12_N c:macro@ADC_SQR3_SQ13_N c:macro@ADC_SQR3_SQ14_N c:macro@ADC_SQR3_SQ15_N c:macro@ADC_SQR3_SQ16_N c:macro@ADC_SQR3_SQ17_N c:macro@ADC_SQR3_SQ18_N c:macro@ADC_SQR2_SQ19_N c:macro@ADC_SQR2_SQ20_N c:macro@ADC_SQR2_SQ21_N c:macro@ADC_SQR2_SQ22_N c:macro@ADC_SQR2_SQ23_N c:macro@ADC_SQR2_SQ24_N c:macro@ADC_SQR1_SQ25_N c:macro@ADC_SQR1_SQ26_N c:macro@ADC_SQR1_SQ27_N c:macro@ADC_SMPR3_SMP_AN0 c:macro@ADC_SMPR3_SMP_AN1 c:macro@ADC_SMPR3_SMP_AN2 c:macro@ADC_SMPR3_SMP_AN3 c:macro@ADC_SMPR3_SMP_AN4 c:macro@ADC_SMPR3_SMP_AN5 c:macro@ADC_SMPR3_SMP_AN6 c:macro@ADC_SMPR3_SMP_AN7 c:macro@ADC_SMPR3_SMP_AN8 c:macro@ADC_SMPR3_SMP_AN9 c:macro@ADC_SMPR2_SMP_AN10 c:macro@ADC_SMPR2_SMP_AN11 c:macro@ADC_SMPR2_SMP_AN12 c:macro@ADC_SMPR2_SMP_AN13 c:macro@ADC_SMPR2_SMP_AN14 c:macro@ADC_SMPR2_SMP_AN15 c:macro@ADC_SMPR2_SMP_SENSOR c:macro@ADC_SMPR2_SMP_VREF c:macro@ADC_SMPR2_SMP_AN18 c:macro@ADC_SMPR2_SMP_AN19 c:macro@ADC_SMPR1_SMP_AN20 c:macro@ADC_SMPR1_SMP_AN21 c:macro@ADC_SMPR1_SMP_AN22 c:macro@ADC_SMPR1_SMP_AN23 c:macro@ADC_SMPR1_SMP_AN24 c:macro@ADC_SMPR1_SMP_AN25 c:macro@_adc_reset_i c:macro@_adc_reset_s c:macro@_adc_wakeup_isr c:macro@_adc_timeout_isr c:macro@_adc_isr_half_code c:macro@_adc_isr_full_code c:macro@_adc_isr_error_code c:macro@_CAN_H_ c:macro@_EXT_H_ c:macro@_GPT_H_ c:macro@_I2C_H_ c:macro@_ICU_H_ c:macro@_MAC_H_ c:macro@_PWM_H_ c:macro@PWM_OUTPUT_MASK c:macro@PWM_OUTPUT_DISABLED c:macro@PWM_OUTPUT_ACTIVE_HIGH c:macro@PWM_OUTPUT_ACTIVE_LOW c:macro@_PWM_LLD_H_ c:macro@PWM_CHANNELS c:macro@PWM_COMPLEMENTARY_OUTPUT_MASK c:macro@PWM_COMPLEMENTARY_OUTPUT_DISABLED c:macro@PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH c:macro@PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW c:macro@STM32_PWM_USE_ADVANCED c:macro@STM32_PWM_USE_TIM1 c:macro@STM32_PWM_USE_TIM5 c:macro@STM32_PWM_USE_TIM8 c:macro@STM32_PWM_USE_TIM9 c:macro@STM32_PWM_TIM1_IRQ_PRIORITY c:macro@STM32_PWM_TIM5_IRQ_PRIORITY c:macro@STM32_PWM_TIM8_IRQ_PRIORITY c:macro@STM32_PWM_TIM9_IRQ_PRIORITY c:macro@pwm_lld_change_period c:macro@pwm_lld_is_channel_enabled c:macro@PWM_FRACTION_TO_WIDTH c:macro@PWM_DEGREES_TO_WIDTH c:macro@PWM_PERCENTAGE_TO_WIDTH c:macro@pwmChangePeriodI c:macro@pwmEnableChannelI c:macro@pwmDisableChannelI c:macro@pwmIsChannelEnabledI c:macro@_RTC_H_ c:macro@_SERIAL_H_ c:macro@SD_PARITY_ERROR c:macro@SD_FRAMING_ERROR c:macro@SD_OVERRUN_ERROR c:macro@SD_NOISE_ERROR c:macro@SD_BREAK_DETECTED c:macro@_SERIAL_LLD_H_ c:macro@STM32_SERIAL_USE_UART4 c:macro@STM32_SERIAL_USE_UART5 c:macro@STM32_SERIAL_USE_USART6 c:macro@STM32_SERIAL_UART4_PRIORITY c:macro@STM32_SERIAL_UART5_PRIORITY c:macro@STM32_SERIAL_USART6_PRIORITY c:macro@_serial_driver_data c:macro@USART_CR2_STOP1_BITS c:macro@USART_CR2_STOP0P5_BITS c:macro@USART_CR2_STOP2_BITS c:macro@USART_CR2_STOP1P5_BITS c:macro@_serial_driver_methods c:macro@sdPutWouldBlock c:macro@sdGetWouldBlock c:macro@sdPut c:macro@sdPutTimeout c:macro@sdGet c:macro@sdGetTimeout c:macro@sdWrite c:macro@sdWriteTimeout c:macro@sdAsynchronousWrite c:macro@sdRead c:macro@sdReadTimeout c:macro@sdAsynchronousRead c:macro@_SDC_H_ c:macro@_SPI_H_ c:macro@_SPI_LLD_H_ c:macro@STM32_SPI_USE_SPI3 c:macro@STM32_SPI_SPI3_IRQ_PRIORITY c:macro@STM32_SPI_SPI3_DMA_PRIORITY c:macro@STM32_SPI_SPI1_RX_DMA_STREAM c:macro@STM32_SPI_SPI1_TX_DMA_STREAM c:macro@STM32_SPI_SPI2_RX_DMA_STREAM c:macro@STM32_SPI_SPI2_TX_DMA_STREAM c:macro@STM32_SPI_SPI3_RX_DMA_STREAM c:macro@STM32_SPI_SPI3_TX_DMA_STREAM c:macro@spiSelectI c:macro@spiUnselectI c:macro@spiStartIgnoreI c:macro@spiStartExchangeI c:macro@spiStartSendI c:macro@spiStartReceiveI c:macro@spiPolledExchange c:macro@_spi_wait_s c:macro@_spi_wakeup_isr c:macro@_spi_isr_code c:macro@_UART_H_ c:macro@_USB_H_ c:macro@_MMC_SPI_H_ c:macro@_SERIAL_USB_H_ c:macro@S2RTT c:macro@MS2RTT c:macro@US2RTT c:macro@RTT2S c:macro@RTT2MS c:macro@RTT2US c:macro@halGetCounterValue c:macro@halGetCounterFrequency c:@SA@_VA_LIST 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c:spi.h@12525@F@spiSend@txbuf c:@F@spiReceive c:spi.h@12564@F@spiReceive@spip c:spi.h@12581@F@spiReceive@n c:spi.h@12591@F@spiReceive@rxbuf c:@F@spiAcquireBus c:spi.h@12684@F@spiAcquireBus@spip c:@F@spiReleaseBus c:spi.h@12724@F@spiReleaseBus@spip c:@F@halInit c:@F@halIsCounterWithin c:hal.h@6252@F@halIsCounterWithin@start c:hal.h@6270@F@halIsCounterWithin@end c:@F@halPolledDelay c:hal.h@6310@F@halPolledDelay@ticks c:hal_lld.c@1885@F@hal_lld_backup_domain_init S >L|ÂùÀÍî»Ù ç¯ä Ü
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µèÕÁø¯çÓ¿ô¢Þ¥ìªâ¢ë¸ÎÎÃö¦ Ó Â ð ® Ü ¸ æ  ð ª!Ø!"Î"ü"ª#ê#$Ç$ù$®%D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\hal_lld.c <invalid loc> D:\GIT repositáø\ChibiOS\os\kernel\include\ch.h D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\chconf.h D:\GIT repositáø\ChibiOS\os\ports\IAR\ARMCMx\chtypes.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\stddef.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\ycheck.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\yvals.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\DLib_Defaults.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\INC\c\DLib_Config_Normal.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\DLib_Product.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\xencoding_limits.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\DLib_Threads.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\ysizet.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\stdint.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\stdbool.h D:\GIT repositáø\ChibiOS\os\kernel\include\chlists.h D:\GIT repositáø\ChibiOS\os\ports\IAR\ARMCMx\chcore.h D:\GIT repositáø\ChibiOS\os\ports\IAR\ARMCMx\STM32L1xx\cmparams.h D:\GIT repositáø\ChibiOS\os\ports\IAR\ARMCMx\chcore_v7m.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\intrinsics.h D:\GIT repositáø\ChibiOS\os\ports\common\ARMCMx\nvic.h D:\GIT repositáø\ChibiOS\os\kernel\include\chsys.h D:\GIT repositáø\ChibiOS\os\kernel\include\chvt.h D:\GIT repositáø\ChibiOS\os\kernel\include\chschd.h D:\GIT repositáø\ChibiOS\os\kernel\include\chsem.h D:\GIT repositáø\ChibiOS\os\kernel\include\chbsem.h D:\GIT repositáø\ChibiOS\os\kernel\include\chmtx.h D:\GIT repositáø\ChibiOS\os\kernel\include\chcond.h D:\GIT repositáø\ChibiOS\os\kernel\include\chevents.h D:\GIT repositáø\ChibiOS\os\kernel\include\chmsg.h D:\GIT repositáø\ChibiOS\os\kernel\include\chmboxes.h D:\GIT repositáø\ChibiOS\os\kernel\include\chmemcore.h D:\GIT repositáø\ChibiOS\os\kernel\include\chheap.h D:\GIT repositáø\ChibiOS\os\kernel\include\chmempools.h D:\GIT repositáø\ChibiOS\os\kernel\include\chthreads.h D:\GIT repositáø\ChibiOS\os\kernel\include\chdynamic.h D:\GIT repositáø\ChibiOS\os\kernel\include\chregistry.h D:\GIT repositáø\ChibiOS\os\kernel\include\chinline.h D:\GIT repositáø\ChibiOS\os\kernel\include\chqueues.h D:\GIT repositáø\ChibiOS\os\kernel\include\chstreams.h D:\GIT repositáø\ChibiOS\os\kernel\include\chfiles.h D:\GIT repositáø\ChibiOS\os\kernel\include\chdebug.h D:\GIT repositáø\ChibiOS\os\hal\include\hal.h D:\GIT repositáø\ChibiOS\boards\ST_STM32L_DISCOVERY\board.h D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\halconf.h D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\mcuconf.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\hal_lld.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32\stm32.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\stm32l1xx.h D:\GIT repositáø\ChibiOS\os\ports\common\ARMCMx\CMSIS\include\core_cm3.h D:\GIT repositáø\ChibiOS\os\ports\common\ARMCMx\CMSIS\include\core_cmInstr.h C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\inc\c\cmsis_iar.h D:\GIT repositáø\ChibiOS\os\ports\common\ARMCMx\CMSIS\include\core_cmFunc.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\stm32_isr.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\stm32_dma.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\stm32_rcc.h D:\GIT repositáø\ChibiOS\os\hal\include\io_channel.h D:\GIT repositáø\ChibiOS\os\hal\include\io_block.h D:\GIT repositáø\ChibiOS\os\hal\include\mmcsd.h D:\GIT repositáø\ChibiOS\os\hal\include\tm.h D:\GIT repositáø\ChibiOS\os\hal\include\pal.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32\GPIOv2\pal_lld.h D:\GIT repositáø\ChibiOS\os\hal\include\adc.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32L1xx\adc_lld.h D:\GIT repositáø\ChibiOS\os\hal\include\can.h D:\GIT repositáø\ChibiOS\os\hal\include\ext.h D:\GIT repositáø\ChibiOS\os\hal\include\gpt.h D:\GIT repositáø\ChibiOS\os\hal\include\i2c.h D:\GIT repositáø\ChibiOS\os\hal\include\icu.h D:\GIT repositáø\ChibiOS\os\hal\include\mac.h D:\GIT repositáø\ChibiOS\os\hal\include\pwm.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32\pwm_lld.h D:\GIT repositáø\ChibiOS\os\hal\include\rtc.h D:\GIT repositáø\ChibiOS\os\hal\include\serial.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32\USARTv1\serial_lld.h D:\GIT repositáø\ChibiOS\os\hal\include\sdc.h D:\GIT repositáø\ChibiOS\os\hal\include\spi.h D:\GIT repositáø\ChibiOS\os\hal\platforms\STM32\SPIv1\spi_lld.h D:\GIT repositáø\ChibiOS\os\hal\include\uart.h D:\GIT repositáø\ChibiOS\os\hal\include\usb.h D:\GIT repositáø\ChibiOS\os\hal\include\mmc_spi.h D:\GIT repositáø\ChibiOS\os\hal\include\serial_usb.h