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..\..\..\os\hal\include\gpt.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¼ T
·GPT_UNINIT GPT_STOP GPT_READY GPT_CONTINUOUS GPT_ONESHOT Pgptstate_t ê ;PGPTDriver Û @Oä%d "I"\Pgptcallback_t hG ¬
..\..\..\os\hal\platforms\STM32\gpt_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil $ Ä
Pgptfreq_t l ëPgptcnt_t \ ð*Å frequency ö # callback l # PGPTConfig )GPTDriver state 7 # config ¡# clock l # tim ¥# E""¿ `
..\..\..\os\hal\include\pwm.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil PWM_UNINIT PWM_STOP PWM_READY Ppwmstate_t ê RPPWMDriver x WOÃ%C "(";Ppwmcallback_t G^ @
..\..\..\os\hal\platforms\STM32\pwm_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¤ | Ppwmmode_t l Ppwmchannel_t M £Ppwmcnt_t \ ¨*× mode ö # callback # PPWMChannelConfig 4¹*Î0 frequency l # period !# callback #°W channels §# cr2 \ #, PPWMConfig pâ)´PWMDriver state J # config 8# period !# clock l # tim <# Î"4"¿ `
..\..\..\os\hal\include\pwm.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil G PWM_UNINIT PWM_STOP PWM_READY Ppwmstate_t ê RPPWMDriver
WOÃ%C "(";Ppwmcallback_t G^ \
..\..\..\os\hal\platforms\STM32\pwm_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil (" ðG Ppwmmode_t l Ppwmchannel_t M £Ppwmcnt_t \ ¨*× mode ö # callback ' # PPWMChannelConfig 4¹*Î0 frequency l # period !# callback ' #°W channels §# cr2 \ #, PPWMConfig pâ)´PWMDriver state ò # config 8# period !# clock l # tim <# Î"4"¿ qPWMD3 qPWMD4
..\..\..\os\hal\include\gpt.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil $ @H ·GPT_UNINIT GPT_STOP GPT_READY GPT_CONTINUOUS GPT_ONESHOT Pgptstate_t ê ;PGPTDriver {
@Oä%d "I"\Pgptcallback_t hG ¸
..\..\..\os\hal\platforms\STM32\gpt_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil l$ °H Pgptfreq_t l ëPgptcnt_t \ ð*Å frequency ö # callback # PGPTConfig )GPTDriver state × # config ¡# clock l # tim ¥# E""¿ qGPTD2 é ô
..\..\..\os\hal\platforms\STM32\stm32.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 0, \J *ÓT CR1 Ó# _resvd0 \ # CR2 Ó# _resvd1 \ # SMCR Ó# _resvd2 \ #
DIER Ó# _resvd3 \ # SR Ó# _resvd4 \ # EGR Ó# _resvd5 \ # CCMR1 Ó# _resvd6 \ # CCMR2 Ó# _resvd7 \ # CCER Ó# _resvd8 \ #" CNT Ù#$ PSC Ó#( _resvd9 \ #* ARR Ù#, RCR Ó#0 _resvd10 \ #2ÒÙ CCR I#4 BDTR Ó#D _resvd11 \ #F DCR Ó#H _resvd12 \ #J DMAR Ó#L _resvd13 \ #N OR Ó#P _resvd14 \ #R t\ tl Pstm32_tim_t ô È
..\..\..\os\kernel\include\chthreads.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ä) DL uvoid char "ó )ÜThread H p_next # p_prev # p_prio ª # p_ctx Ö # p_newer # p_older # p_name `# p_state t # p_flags c # p_refs # p_preempt # p_time d# p_u #$ p_waiting A #( p_msgqueue #, p_msg » #4 p_epending Ý #8 p_mtxlist j#< p_realprio ª #@ p_mpool #D ù "\t "Ò Ný» % "pPtfunc_t }ÞSÊ rdymsg » exitcode » wtobjp ewmask Ý <
..\..\..\os\kernel\include\chmtx.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 2 ¼M )ªMutex m_queue # m_owner # m_next *# "ï PMutex ï ,
..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil °6 LN uvoid "÷ Pregarm_t ý ÞPstkalign_t | æ)extctx r0 # r1 # r2 # r3 # r12 # lr_thd # pc # xpsr # )òintctx $ r4 # r5 # r6 # r7 # r8 # r9 # r10 # r11 # lr # )context r13
# " `
..\..\..\os\kernel\include\chlists.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil > N PThread Ý #*¢ p_next "# p_prev "# "ñ PThreadsQueue _*Í p_next "# PThreadsList :i Ð
..\..\..\os\ports\RVCT\ARMCMx\chtypes.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ø? èN _Bool Pbool_t ô $Ptmode_t M %Ptstate_t M &Ptrefs_t M 'Ptslices_t M (Ptprio_t l )Pmsg_t / *Peventid_t / +Peventmask_t l ,Pflagsmask_t l -Psystime_t l .Pcnt_t / / ì C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdint.h ARM C/C++ Compiler, 5.03 [Build 24] @ O signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t r& Pint16_t ' Pint32_t ( Pint64_t ) Puint8_t , Puint16_t ¯ - Puint32_t Á . Puint64_t Ñ / Pint_least8_t r5 Pint_least16_t 6 Pint_least32_t 7 Pint_least64_t 8 Puint_least8_t ; Puint_least16_t ¯ < Puint_least32_t Á = Puint_least64_t Ñ > Pint_fast8_t C Pint_fast16_t D Pint_fast32_t E Pint_fast64_t F Puint_fast8_t Á I Puint_fast16_t Á J Puint_fast32_t Á K Puint_fast64_t Ñ L Pintptr_t O Puintptr_t Á P Pintmax_t S Puintmax_t Ñ T È C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stddef.h ARM C/C++ Compiler, 5.03 [Build 24] (H èO int unsigned int unsigned short Pptrdiff_t r#Psize_t y'Pwchar_t 4 8%
..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil . ÜJ º
IRQn NonMaskableInt_IRQn rMemoryManagement_IRQn tBusFault_IRQn uUsageFault_IRQn vSVCall_IRQn {DebugMonitor_IRQn |PendSV_IRQn ~SysTick_IRQn WWDG_IRQn PVD_IRQn TAMPER_IRQn RTC_IRQn FLASH_IRQn RCC_IRQn EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQn
DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn
DMA1_Channel4_IRQn DMA1_Channel5_IRQn DMA1_Channel6_IRQn DMA1_Channel7_IRQn ADC1_2_IRQn USB_HP_CAN1_TX_IRQn USB_LP_CAN1_RX0_IRQn CAN1_RX1_IRQn CAN1_SCE_IRQn EXTI9_5_IRQn TIM1_BRK_IRQn TIM1_UP_IRQn TIM1_TRG_COM_IRQn TIM1_CC_IRQn TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQn I2C1_ER_IRQn I2C2_EV_IRQn !I2C2_ER_IRQn "SPI1_IRQn #SPI2_IRQn $USART1_IRQn %USART2_IRQn &USART3_IRQn 'EXTI15_10_IRQn (RTC_Alarm_IRQn )USB_FS_WKUP_IRQn *TIM8_BRK_IRQn +TIM8_UP_IRQn ,TIM8_TRG_COM_IRQn -TIM8_CC_IRQn .ADC3_IRQn /FSMC_IRQn 0SDIO_IRQn 1TIM5_IRQn 2SPI3_IRQn 3UART4_IRQn 4UART5_IRQn 5TIM6_IRQn 6TIM7_IRQn 7DMA2_Channel1_IRQn 8DMA2_Channel2_IRQn 9DMA2_Channel3_IRQn :DMA2_Channel4_5_IRQn ; PIRQn_Type ü æPs32 / öPs16 ÷Ps8 ø/ Psc32 uú Psc16 û Psc8 üt/ Pvs32 þt Pvs16 Àÿt Pvs8 ÓtuPvsc32 åtPvsc16 ÷tPvsc8 Pu32 l Pu16 \ Pu8 M l Puc32 C\ Puc16 VM Puc8 itl Pvu32 {t\ Pvu16 tM Pvu8 ¡tCPvuc32 ³tVPvuc16 ÅtiPvuc8 ×ý
RESET SET PFlagStatus è(PITStatus è4»DISABLE ENABLE PFunctionalState !/ìERROR SUCCESS PErrorStatus S,*óP SR {# CR1 {# CR2 {# SMPR1 {# SMPR2 {# JOFR1 {# JOFR2 {# JOFR3 {# JOFR4 {# HTR {#$ LTR {#( SQR1 {#, SQR2 {#0 SQR3 {#4 JSQR {#8 JDR1 {#< JDR2 {#@ JDR3 {#D JDR4 {#H DR {#L PADC_TypeDef Ã*Õ À RESERVED0 l # DR1 # RESERVED1 \ # DR2 # RESERVED2 \ #
DR3 # RESERVED3 \ # DR4 # RESERVED4 \ # DR5 # RESERVED5 \ # DR6 # RESERVED6 \ # DR7 # RESERVED7 \ # DR8 # RESERVED8 \ #" DR9 #$ RESERVED9 \ #& DR10 #( RESERVED10 \ #* RTCCR #, RESERVED11 \ #. CR #0 RESERVED12 \ #2 CSR #4¢\ RESERVED13
#6 DR11 #@ RESERVED14 \ #B DR12 #D RESERVED15 \ #F DR13 #H RESERVED16 \ #J DR14 #L RESERVED17 \ #N DR15 #P RESERVED18 \ #R DR16 #T RESERVED19 \ #V DR17 #X RESERVED20 \ #Z DR18 #\ RESERVED21 \ #^ DR19 #` RESERVED22 \ #b DR20 #d RESERVED23 \ #f DR21 #h RESERVED24 \ #j DR22 #l RESERVED25 \ #n DR23 #p RESERVED26 \ #r DR24 #t RESERVED27 \ #v DR25 #x RESERVED28 \ #z DR26 #| RESERVED29 \ #~ DR27 # RESERVED30 \ # DR28 # RESERVED31 \ # DR29 # RESERVED32 \ # DR30 # RESERVED33 \ # DR31 # RESERVED34 \ # DR32 # RESERVED35 \ # DR33 # RESERVED36 \ # DR34 # RESERVED37 \ # DR35 # RESERVED38 \ #¢ DR36 #¤ RESERVED39 \ #¦ DR37 #¨ RESERVED40 \ #ª DR38 #¬ RESERVED41 \ #® DR39 #° RESERVED42 \ #² DR40 #´ RESERVED43 \ #¶ DR41 #¸ RESERVED44 \ #º DR42 #¼ RESERVED45 \ #¾ PBKP_TypeDef ¦* TIR {# TDTR {# TDLR {# TDHR {# PCAN_TxMailBox_TypeDef i²*ï RIR {# RDTR {# RDLR {# RDHR {# PCAN_FIFOMailBox_TypeDef »¾*ª FR1 {# FR2 {# PCAN_FilterRegister_TypeDef È*Û!° MCR {# MSR {# TSR {# RF0R {# RF1R {# IER {# ESR {# BTR {# · l W RESERVED0 ¬# Ñ sTxMailBox È#í ï sFIFOMailBox ä#° l RESERVED1 #Ð FMR {# FM1R {# RESERVED2 l # FS1R {# RESERVED3 l # FFA1R {# RESERVED4 l # FA1R {#§!l RESERVED5 # Â!*
sFilterRegister ¹#À PCAN_TypeDef Mê*Ã" CFGR {# OAR {# PRES {# ESR {# CSR {# TXD {# RXD {# PCEC_TypeDef ïø*¡# DR {# IDR ¡# RESERVED0 M # RESERVED1 \ # CR {# PCRC_TypeDef W
*ï$4 CR {# SWTRIGR {# DHR12R1 {# DHR12L1 {# DHR8R1 {# DHR12R2 {# DHR12L2 {# DHR8R2 {# DHR12RD {# DHR12LD {#$ DHR8RD {#( DOR1 {#, DOR2 {#0 PDAC_TypeDef µ* % IDCODE {# CR {# PDBGMCU_TypeDef §*ì% CCR {# CNDTR {# CPAR {# CMAR {# PDMA_Channel_TypeDef ·³*¤& ISR {# IFCR {# PDMA_TypeDef ¹*/Ø MACCR {# MACFFR {# MACHTHR {# MACHTLR {# MACMIIAR {# MACMIIDR {# MACFCR {# MACVLANTR {# À'l RESERVED0 µ# MACRWUFFR {#( MACPMTCSR {#,þ'l RESERVED1 ó#0 MACSR {#8 MACIMR {#< MACA0HR {#@ MACA0LR {#D MACA1HR {#H MACA1LR {#L MACA2HR {#P MACA2LR {#T MACA3HR {#X MACA3LR {#\)l ' RESERVED2 ¢#` MMCCR {# MMCRIR {# MMCTIR {# MMCRIMR {# MMCTIMR {#*l
RESERVED3
# MMCTGFSCCR {#Ì MMCTGFMSCCR {#ÐÙ*l RESERVED4 N#Ô MMCTGFCR {#è+l RESERVED5 |#ì MMCRFCECR {# MMCRFAECR {#È+l RESERVED6 ½# MMCRGUFCR {#Äø+l Í RESERVED7 ì#È PTPTSCR {# PTPSSIR {# PTPTSHR {# PTPTSLR {# PTPTSHUR {# PTPTSLUR {# PTPTSAR {# PTPTTHR {# PTPTTLR {# ¨-l ¶ RESERVED8 #¤ DMABMR {# DMATPDR {# DMARPDR {# DMARDLAR {# DMATDLAR {# DMASR {# DMAOMR {# DMAIER {# DMAMFBOCR {# Ô.l RESERVED9 I#¤ DMACHTDR {#È DMACHRDR {#Ì DMACHTBAR {#Ð DMACHRBAR {#Ô PETH_TypeDef 8*0 IMR {# EMR {# RTSR {# FTSR {# SWIER {# PR {# PEXTI_TypeDef Á*1$ ACR {# KEYR {# OPTKEYR {# SR {# CR {# AR {# RESERVED {# OBR {# WRPR {# PFLASH_TypeDef §*2 RDP # USER # Data0 # Data1 # WRP0 # WRP1 #
WRP2 # WRP3 # POB_TypeDef ¦·*¹2 ¬2{ BTCR ## PFSMC_Bank1_TypeDef À*î2 á2{ BWTR X# PFSMC_Bank1E_TypeDef TÉ*à3 PCR2 {# SR2 {# PMEM2 {# PATT2 {# RESERVED0 l # ECCR2 {# PFSMC_Bank2_TypeDef ×*Ñ4 PCR3 {# SR3 {# PMEM3 {# PATT3 {# RESERVED0 l # ECCR3 {# PFSMC_Bank3_TypeDef ûå*®5 PCR4 {# SR4 {# PMEM4 {# PATT4 {# PIO4 {# PFSMC_Bank4_TypeDef lò*6 CRL {# CRH {# IDR {# ODR {# BSRR {# BRR {# LCKR {# PGPIO_TypeDef É*7 EVCR {# MAPR {#×6{ EXTICR N# RESERVED0 l # MAPR2 {# PAFIO_TypeDef 2*±9$ CR1 # RESERVED0 \ # CR2 # RESERVED1 \ # OAR1 # RESERVED2 \ #
OAR2 # RESERVED3 \ # DR # RESERVED4 \ # SR1 # RESERVED5 \ # SR2 # RESERVED6 \ # CCR # RESERVED7 \ # TRISE # RESERVED8 \ #" PI2C_TypeDef §*ó9 KR {# PR {# RLR {# SR {# PIWDG_TypeDef Å ³*¢: CR {# CSR {# PPWR_TypeDef ½*¿;( CR {# CFGR {# CIR {# APB2RSTR {# APB1RSTR {# AHBENR {# APB2ENR {# APB1ENR {# BDCR {# CSR {#$ PRCC_TypeDef 6 Ù*>( CRH # RESERVED0 \ # CRL # RESERVED1 \ # PRLH # RESERVED2 \ #
PRLL # RESERVED3 \ # DIVH # RESERVED4 \ # DIVL # RESERVED5 \ # CNTH # RESERVED6 \ # CNTL # RESERVED7 \ # ALRH # RESERVED8 \ #" ALRL #$ RESERVED9 \ #& PRTC_TypeDef Ó õ*Ä@ POWER {# CLKCR {# ARG {# CMD {# RESPCMD ³# RESP1 ³# RESP2 ³# RESP3 ³# RESP4 ³# DTIMER {#$ DLEN {#( DCTRL {#, DCOUNT ³#0 STA ³#4 ICR {#8 MASK {#<ú?l RESERVED0 ï #@ FIFOCNT ³#H¥@l RESERVED1 #L FIFO {# PSDIO_TypeDef *øB$ CR1 # RESERVED0 \ # CR2 # RESERVED1 \ # SR # RESERVED2 \ #
DR # RESERVED3 \ # CRCPR # RESERVED4 \ # RXCRCR # RESERVED5 \ # TXCRCR # RESERVED6 \ # I2SCFGR # RESERVED7 \ # I2SPR # RESERVED8 \ #" PSPI_TypeDef Y « *ÿGP CR1 # RESERVED0 \ # CR2 # RESERVED1 \ # SMCR # RESERVED2 \ #
DIER # RESERVED3 \ # SR # RESERVED4 \ # EGR # RESERVED5 \ # CCMR1 # RESERVED6 \ # CCMR2 # RESERVED7 \ # CCER # RESERVED8 \ #" CNT #$ RESERVED9 \ #& PSC #( RESERVED10 \ #* ARR #, RESERVED11 \ #. RCR #0 RESERVED12 \ #2 CCR1 #4 RESERVED13 \ #6 CCR2 #8 RESERVED14 \ #: CCR3 #< RESERVED15 \ #> CCR4 #@ RESERVED16 \ #B BDTR #D RESERVED17 \ #F DCR #H RESERVED18 \ #J DMAR #L RESERVED19 \ #N PTIM_TypeDef !Û *éI SR # RESERVED0 \ # DR # RESERVED1 \ # BRR # RESERVED2 \ #
CR1 # RESERVED3 \ # CR2 # RESERVED4 \ # CR3 # RESERVED5 \ # GTPR # RESERVED6 \ # PUSART_TypeDef $ñ *£J CR {# CFR {# SR {# PWWDG_TypeDef ÿ$ü ì
..\..\..\os\kernel\include\chqueues.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil <$ øK uvoid "ò PGenericQueue W0 Pqnotify_t S3PInputQueue ü {POutputQueue ü îOÏ%O "ü "G)èGenericQueue $ q_waiting # q_counter Ç # q_buffer è# q_top è# q_wrptr è# q_rdptr è# q_notify # q_link ø # "M ¸
..\..\..\os\kernel\include\chevents.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 0 pM PEventListener % )áEventListener el_next a# el_listener # el_mask Ý # el_flags ò # "ò )
EventSource es_next a# PEventSource e>O¢%Ê "Pevhandler_t ¢C <
..\..\..\os\hal\include\serial.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil è ¤F uvoid "í M "÷ "M )SerialDriver x vmt # event F # state Î# iqueue ED # oqueue WD #0êM ib _#TÿM ob t#d usart #t ó""ÑB ÎSD_UNINIT SD_STOP SD_READY Psdstate_t ¥aPSerialDriver f )¾SerialDriverVMT NÇ %ó %ý %Ç " write # NÆÇ %ó %%Ç "/ read F#Né» %ó %M "V put i#N
» %ó "x get
# N» %ó %M % " putt #Nл %ó % "½ gett Ð#NýÇ %ó %ý %Ç % "à writet ý#N¬Ç %ó %%Ç % " readt ,# $
..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil $* I Phalclock_t l ÉPhalrtcnt_t l Î
..\..\..\os\kernel\include\chmemcore.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil |/ $M uvoid "ó Nù %Ç "ý Pmemgetfunc_t
% t
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¨ $G *È sc_speed l # sc_cr1 \ # sc_cr2 \ # sc_cr3 \ # PSerialConfig éqSD1 ¯H qSD2 ¯H x
..\keil/GPS_dekoduj.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¼ $ *è-ñM UTC_time æ # Status_GPS M # M Latitude #»M
Longitude 0#×M Altitude L## PNMEA_GPGGA â
..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil
à" *© odr l # crl l # crh l # Pstm32_gpio_setup_t ý ?*ªT PAData )# PBData )# PCData )# PDData )#$ PEData )#0 PFData )#< PGData )#H PPALConfig C]Pioportmask_t l mPiomode_t l r"9 Pioportid_t ãzªqpal_default_config û \
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil *È sc_speed l # sc_cr1 \ # sc_cr2 \ # sc_cr3 \ # PSerialConfig é ì
..\..\..\os\kernel\include\chstreams.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil <" ¬K uvoid "ó M "ý "M * vmt !# A" PBaseSequentialStream
N)ëBaseSequentialStreamVMT NôÇ %ù %%Ç "] write t# NÇ %ù %%Ç "
read #N¿» %ù %M "¬ put ¿#NÛ» %ù "Î get Û# t
..\..\..\os\hal\include\tm.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¼) XI PTimeMeasurement > )ñTimeMeasurement O%q " start # Oµ%q "- stop 5# last K # worst K # best K # "é
..\..\..\os\kernel\include\chregistry.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil X t. char Pchdebug_t
:*ô ch_identifier # ch_zero M # ch_size M # ch_version \ # ch_ptrsize M # ch_timesize M # ch_threadsize M #
cf_off_prio M # cf_off_ctx M # cf_off_newer M #
cf_off_older M # cf_off_name M # cf_off_stklimit M # cf_off_state M # cf_off_flags M # cf_off_refs M # cf_off_preempt M # cf_off_time M # l
..\..\..\os\kernel\include\chmempools.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil \. L )pool_header ph_next # "ô *Ù mp_next # mp_object_size Ç # mp_provider FL # PMemoryPool 3
..\..\..\os\kernel\include\chheap.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil h/ ÜL PMemoryHeap `- S"= next heap "ð *½ u # size Ç # Ràheap_header align ö h ! )¢memory_heap h_provider FL # h_free =# h_mtx Ò # ü
..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil L& I *© odr l # crl l # crh l # Pstm32_gpio_setup_t ý ?*ªT PAData )# PBData )# PCData )# PDData )#$ PEData )#0 PFData )#< PGData )#H PPALConfig C]Pioportmask_t l mPiomode_t l r"9 Pioportid_t ãz à
GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\kola\Ing\Automatický vypoutìè meteobalónù\Programování\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil "M p
GPS_dekoduj.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil *à-éM UTC_time Þ # Status_GPS M #M Latitude
#³M
Longitude (#ÏM Altitude D## PNMEA_GPGGA Ú Ì
..\main.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil , ô uvoid char int "Ö "Ü 9 dekodujPrikaz $ï prikaz Ybasepri l P¹Ybasepri l P ÍYbasepri l P áYbasepri l P ïM R \zp_neplatny d qGPGGA_informace <O ¥M æ ¤M ¶ö % Áö % Ìö u
..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ø ü 91
hal_lld_backup_domain_init
..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil è ¨
unsigned int "KQ M L
..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¬ 9Ügpt_lld_stop_timer $d gptp 9Ë
gpt_lld_serve_interrupt $d gptp
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ° ´R "¯H ""ÑB 9Ä\
usart_init $sdp $
config \u 9àz
usart_deinit $u 9³
set_error $sdp $\ sr \sts ò Ybasepri l P²Ybasepri l P 9
serve_interrupt $sdp \u \cr1 \ \sr \ \dr \ Ybasepri l PYbasepri l P ®Ybasepri l P ÂYbasepri l P ö\b » áYbasepri l P õYbasepri l P Ybasepri l P Ybasepri l P ,
..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil H 9«q
pwm_lld_serve_interrupt $w pwmp \sr \
..\..\..\os\various\chprintf.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ä char long unsigned int int "ë "ñS ë " 8Ê$long_to_string_with_divisor $p $ó num $û radix $ó divisor a__result \i \q \l ó \ll ó \i__1 \i__1__3 \q__4 \p__5 \i__1__2 8Eltoa $p $ó num $û radix a__result ¤ C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdarg.h ARM C/C++ Compiler, 5.03 [Build 24] ¼ uvoid "rPva_list ',)¤__va_list __ap x#
..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ü 9
utmObjectInit $-V tmp
..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ì uvoid "é M "ó "M "¯H ¤M " 8
..\..\..\os\hal\src\hal.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ü 8¸§halIsCounterWithin U $ K start $ K end a__result U \now K t
..\..\..\os\hal\src\gpt.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil
ø 9¦gptStartContinuousI $ gptp $.
interval 9ÓÈgptStartOneShotI $ gptp $.
interval 9öègptStopTimerI $ gptp ä
..\..\..\os\kernel\include\chvt.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 8# uvoid "î "ÜPvtfunc_t ø NPVirtualTimer S )þVirtualTimer vt_next ~# vt_prev ~# vt_time # vt_func ü # vt_par ô # " *È vt_next ~# vt_prev ~# vt_time # vt_systime È# t PVTList sOä%ô T
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ô % < "prio_insert $ tp $ tqp \cp " <Ì-queue_insert $ tp $ tqp ;4fifo_remove $ tqp a__result \tp ;À;lifo_remove $ tqp a__result \tp ;îBdequeue $ tp a__result "A ;®Olist_remove $îtlp a__result \tp 9ÔIlist_insert $ tp $îtlp ø
..\..\..\os\kernel\src\chthreads.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil è l$ uvoid "ï ". "Ý 8ÄE _thread_init $ tp $ª prio a__result 8¨ chThdCreateI $õ wsp $Ç size $ª prio $Y pf $õ arg a__result \tp 9øçchThdExitS $» msg \tp \tlp__1 ù \tp__2 ÿ \list_remove__3 ÿ ð
..\..\..\os\kernel\include\chvt.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil T3 N uvoid "î "éPvtfunc_t ø NPVirtualTimer S )þVirtualTimer vt_next ~# vt_prev ~# vt_time # vt_func ü # vt_par ô # " *È vt_next ~# vt_prev ~# vt_time # vt_systime È# t PVTList sqvtlist ÎOñ%ô
..\..\..\os\kernel\src\chsys.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ( uvoid "ë ö T
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil $ à) < "prio_insert $ tp $ tqp \cp " <Ì-queue_insert $ tp $ tqp ;;lifo_remove $ tqp a__result \tp <«Ilist_insert $ tp $«tlp "A ;ëOlist_remove $«tlp a__result \tp 8¦4fifo_remove $ tqp a__result \tp 8ÕBdequeue $ tp a__result À
..\..\..\os\kernel\src\chschd.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil T) uvoid "ì 8²J chSchReadyI $ tp a__result \cp 9âlchSchGoSleepS $t newstate \otp 9ÂchSchDoRescheduleAhead \otp \cp 9©chSchDoRescheduleBehind \otp l
..\..\..\os\kernel\include\chschd.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil < ,* *Ú r_queue # r_prio ª # r_ctx Ö # r_newer # r_older # r_current # PReadyList ð d ô
..\..\..\os\kernel\src\chregistry.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\kola\Ing\Automatický vypoutìè meteobalónù\Programování\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil . 0W T
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil à P7 < "prio_insert $ tp $ tqp \cp " ;à;lifo_remove $ tqp a__result \tp ;Bdequeue $ tp a__result <³Ilist_insert $ tp $³tlp "A ;óOlist_remove $³tlp a__result \tp 9-queue_insert $ tp $ tqp 8Õ4fifo_remove $ tqp a__result \tp X
..\..\..\os\kernel\src\chqueues.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ° À. uvoid "î "õ "Ý "WD M "
8Ì?qwait » $sD qp $ time a__result » "ED "M d
..\..\..\os\kernel\src\chmtx.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ¼ `3 "Ò "õ "Ý 9¯rchMtxLockS $ë mp \ctp ®\tp 8ããchMtxTryLockS U $ë mp a__result U T
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil È ì3 " <-queue_insert $ tp $ò tqp ;Ø;lifo_remove $ò tqp a__result \tp <ýIlist_insert $ tp $}tlp "A ;½Olist_remove $}tlp a__result \tp 9ì"prio_insert $ tp $ò tqp \cp 8§4fifo_remove $ò tqp a__result \tp 8ÖBdequeue $ tp a__result °
..\..\..\os\kernel\src\chmempools.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ø 7 uvoid "ð 9ªchPoolFreeI $ªmp $ö objp \php äY 9ó¤chPoolFree $ªmp $ö objp Ybasepri l PòYbasepri l P 8ªbchPoolAllocI ö $ªmp a__result ö \objp ö ")Z
..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil X9 uvoid "ï 8±ichCoreAllocI õ $Ç size a__result õ \p õ "M ÁM qImage$$RW_IRAM1$$ZI$$Limit 7ìM qImage$$RW_IRAM2$$Base b
..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil : uvoid "ì "}[ "Ç d
..\..\..\os\kernel\src\chevents.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ´ < "F ºF "ô 9©ôchEvtSignalI $ tp $Ý mask 9æ±chEvtBroadcastFlagsI $î esp $ò flags \elp uF
..\..\..\os\kernel\src\chdynamic.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil À ¸@ uvoid "ï ")Z X
..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ì PC " 9×_port_irq_epilogue Ybasepri l PÂ\ctxp ÷ Ypsp l P ÖYbasepri l P
..\..\..\boards\MLAB_STM32F10xRxT01A\board.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ø F ] ` GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ô. È/ ð ?â
dekoduj_zpravu_GPS ô. È/ hNMEA_retezec ¾^ hNMEA_delka M Yi M Yj M Yk M Yl M Ypocet_carek M ð GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil pGPGGA_informace (`
´ ..\main.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil x$ . uvoid char int "Ú "à ?ÇU
gpt2cb x$ $ 4 $ gptp Ybasepri l Æ$ $ Ybasepri l >pThread1 » $ ¾$ $ï arg ]__result » P >êThread_odpal » ¾$ æ' $ï arg ]__result » PYstav M Yodpal_povolen M Yodpal_pomocna M Ypocet_opakovani \ Yperioda_casovace \ xYbasepri l éÜ$ æ' Ymsg » èÜ$ æ' Ybasepri l > ÛThread_GPS » æ' Ê+ ß $ï arg ]__result » P´M ó YinBuffer ¨¨{Yzacatek_retezce ó Ykonec_retezce ó Ypocet_znaku M M c YNMEA_zprava I/a Ê+ b, nFa dQa ÕÞ+ 4, aa dda N ì4, J, ua dxa ¼ è+ b, a ea ô+ , a b«a ü >¶ Ámain è b, . \ ]__result è PÔM Yznaky Éëà
Yprikaz âYpocet_znaku M Ybasepri l ·ö- . Ybasepri l Fµ /a B- ò- ¡nFa dQa Êìt- Æ- aa eda D- Ø- ua dxa ~- ò- a da Z ´ - ª- a b«a ¨ x ..\main.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ptp_odpal puvitaci_zprava Õa Ygpt2cfg Á
2 YUSART2_config áa 2 YwaThread1 ça ø YwaThread_odpal òa ( YwaThread_GPS ýa X X ..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil # Z$ È ?²chal_lld_init # î# h F±c â# ì# y ?Østm32_clock_init î# Z$ T ä ..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil `" d# D unsigned int ?ÁM_pal_lld_init `" ä" ¨ hconfig 9d ?ã_pal_lld_setgroupmode ä" d# | hport 9Q $ Q mask hmode !Q ?d Ycfgtab x2 \mh l \ml l \crh l \crl l Ycfg l Yi x ..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil <! R" I>e <! L! d nZe ?å½VectorB0 L! z! 8 Fäfe P! r! Áne Fã>e `! l! fZe ?gpt_lld_init z! ! $ ?Áàgpt_lld_start ! Ú! hgptp d Ypsc \ ?ïîgpt_lld_stop Ú! " ä hgptp d ?´Ègpt_lld_start_timer " ." Ð hgptp d hinterval ?úîgpt_lld_polled_delay ." R" ¼ hgptp d hinterval ..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil pGPTD2 I è ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ! ä ?«Ê
notify1 X $sD qp ?ÑÒ
notify2 , D $sD qp ?ïVectorD4 , < ?VectorD8 < L ì ?®øsd_lld_init L p Ì ?£sd_lld_start p à ¬ hsdp f hconfig ¥f F¯f ® Þ ÔfÂf fÊf bÕf ?Õàsd_lld_stop à hsdp f FÔÜf è ò ãnñf IKg ! x ndg blg brg b|g b
g dg \§ g d¡g ô ¾ ¨ ²g dµg Õ¨ ¸ Æg dÉg ¸ ì Úg bÝg ¤¸ Þ åg dèg ¤ Þ â ùg düg Ê ²ì ø h dh Ø Éø
! "h d%h ä Føf 4 t ¤n g ng b g d&g p t 6g d9g Ü 4 ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ydefault_config f l2 pSD1 ¯H ø pSD2 ¯H p À ..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil D ú Ì ?¸ÚVectorB4 D ¤ F·2i H ÞnRi d]i ?öíVectorB8 ¤ ô Fõ2i ¨ ü ñnRi d]i d ?Üpwm_lld_init " Ô ?Þpwm_lld_start " T ´ hpwmp w Ypsc l Yccer \ ?Úpwm_lld_stop T hpwmp w ?ø pwm_lld_enable_channel Ø hpwmp w hchannel ¢ hwidth ¹ ÷º Ö Ydier l ?À¾pwm_lld_disable_channel Ø ú l hpwmp w hchannel ¢ ..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil pPWMD3 \ Ð pPWMD4 \ ä è ..\..\..\os\various\chprintf.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil < ô char int long ï ""ï ?çlchprintf < L hchp j hfmt
tVYap ëk \p Ys \c ï Yfiller ï \i ÷ \precision ÷ \width ÷ Yis_long U Yleft_align U \l þ ¼ï Ytmpbuf ³@FØ6k ö ^ ÍfFk fLk fTk e^k F×j ö ^ Gf·j n½j nÅj fÏj eÛj déj æbïj æbõj æbûj æek e k ek e k e)k Fæ6k l Ì éfFk fLk fTk e^k Fåj l Ì Gf·j n½j nÅj fÏj eÛj déj Übïj Übõj Übûj Üek e k ek e k e)k ..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 8 ?>
tm_start htmp -V ?ÃJ
tm_stop > ø htmp -V Ynow K IÝýl > R ä nm ?atmInit R ¬ Ytm ¥U `Fýl Z l hfm ü ..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ymeasurement_offset K ì ..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil ü uvoid "í >Ã7write Ç ü l hip ó hbp n hn Ç ]__result Ç P >=read Ç X hip ó hbp n hn Ç ]__result Ç P >ÎCput » D hip ó hb M ]__result » P >
Hget » $ 0 hip ó ]__result » P >ÕMputt » $ * hip ó hb M htimeout ]__result » P >Rgett » * 0 hip ó htimeout ]__result » P >õWwritet Ç 0 6 ô hip ó hbp n hn Ç htime ]__result Ç P >Í\readt Ç 6 < à hip ó hbp n hn Ç htime ]__result Ç P ?èqsdInit < @ Ì ?³
sdObjectInit @ x ¬ hsdp #n hinotify 4D honotify 4D ?sdStart x hsdp #n hconfig /n Ybasepri l Ybasepri l ?ä®sdStop Ä l hsdp #n Ybasepri l ã¼ Â Ybasepri l ? ÎsdIncomingDataI Ä ò @ hsdp #n hb M >í èsdRequestDataI » ò hsdp #n ^__result » PYb » ð ..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Yvmt gH L2 4 ..\..\..\os\hal\src\pwm.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil p ü ¸ ?=pwmInit p t ( ?´IpwmObjectInit t ~ hpwmp ?\pwmStart ~ ô hpwmp hconfig x
Ybasepri l Ybasepri l ?çqpwmStop ¼ Ô hpwmp Ybasepri l æ´ º Ybasepri l ?ÐpwmChangePeriod ¼ Ô À hpwmp hperiod a Ybasepri l ÏÌ Ò Ybasepri l ?È¥pwmEnableChannel Ô è hpwmp hchannel J hwidth a Ybasepri l Çà æ Ybasepri l ?´ÁpwmDisableChannel è ü hpwmp hchannel J Ybasepri l ³ô ú Ybasepri l ° ..\..\..\os\hal\src\hal.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil f < ?=halInit $ f I¶ o $ F R n?o nKo cUo beo ?¯ºhalPolledDelay F f < hticks K Ystart K Ytimeout K F® o L d ½n?o nKo eUo beo L x ..\..\..\os\hal\src\gpt.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil , þ ! ?=gptInit , 0 Ô ?´IgptObjectInit 0 : À hgptp ?WgptStart : X hgptp hconfig Å
Ybasepri l P V Ybasepri l ?çkgptStop X t hgptp Ybasepri l æl r Ybasepri l ?ÔgptChangeInterval t l hgptp hinterval .
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Ybasepri l ᢠ¨ Ybasepri l FZp ¢ nwp np I¢p ª ² $ n¬p n·p ?¹gptStartOneShot ² Ê hgptp hinterval .
Ybasepri l Â È Ybasepri l F¬p º  ¼n¬p n·p IÇÇp Ê Ò ð nÞp ?¹ÚgptStopTimer Ò ê Ð hgptp Ybasepri l â è Ybasepri l F¸Çp Ú â ÝnÞp ?ùgptPolledDelay ê þ ° hgptp hinterval .
ô ..\..\..\os\kernel\src\chvt.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil & # uvoid "î ?+_vt_init ª & ?éEchVTSetI ª â hvtp jr htime hvtfunc èq hpar ô Yp jr ?cchVTResetI â þ hvtp jr >óchTimeIsWithin U & è hstart hend ___result U : Ytime ô ..\..\..\os\kernel\src\chvt.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil pvtlist ºr À ..\..\..\os\kernel\src\chthreads.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil 0 L% uvoid "ó I¥1v 0 h ¸
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}f£ eª b¸ t ..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil P ° ì9 uvoid "ó ?;_core_init P d P IÄÅ d ~ < fÝ bè Pbö >ÙTchCoreAlloc ù ~ ¦ ( hsize Ç ^__result ù P&Yp ù Ybasepri l ´ ¤ Ybasepri l FØÅ XfÝ eè bö 4 >}chCoreStatus Ç ¦ ° ^__result Ç P ..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ynextmem ý Yendmem ý ..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil F ; uvoid "ð ?D_heap_init ó ?ä\chHeapInit & ß hheapp ][ hbuf ö hsize Ç Yhp N >Î}chHeapAlloc ö & ¦ ¿ hheapp ][ $Ç size ___result ö Yqp N \hp N Yfp N ?»chHeapFree ¦ hp ö Yqp N Yhp N Yheapp ][ >óchHeapStatus Ç F d hheapp ][ hsizep T ^__result Ç P4Yqp N Yn Ç Ysz Ç ü ..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil Ydefault_heap 0[ x p ..\..\..\os\kernel\src\chevents.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil È ü = ?äNchEvtRegisterMask È æ ö hesp J help uF hmask Ý Ybasepri l ãÞ â Ybasepri l ?ÑhchEvtUnregister æ â hesp J help uF Yp uF Ybasepri l Ð Ybasepri l >Ô
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Yctp Ybasepri l ¹Ú æ Ybasepri l P Ôæ ø Ybasepri l ïò ú Ybasepri l , ..\..\..\os\kernel\src\chdynamic.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil à È $A uvoid "ó >é- chThdAddRef à ô ¸ htp ^__result PYbasepri l èì ò Ybasepri l ?ÊCchThdRelease ô J ¤ htp Yrefs Ybasepri l É J Ybasepri l >{ chThdCreateFromHeap J hheapp ][ hsize Ç hprio ª hpf Y harg ù ___result ê Ywsp ù Ytp Ybasepri l ÿ~ Ybasepri l >®¬ chThdCreateFromMemoryPool È d hmp ½ hprio ª hpf Y harg ù ___result Ì Ywsp ù Ytp Ybasepri l ¾ Æ Ybasepri l Ô ..\..\..\os\ports\common\ARMCMx\nvic.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil @ Ö 0B unsigned int ?É'nvicEnableVector @ 0 hn l hprio l Ysh ÷ ?5nvicDisableVector ´ hn l Ysh ÷ ?ÔCnvicSetSystemHandlerPriority ´ Ö hhandler l hprio l Ysh ÷ ¤ ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\STM32L1xx\\vectors.s ARM Assembler, 5.03 [Build 24] C:\Users\Jichy\kola\Ing\Automatický vypoutìè meteobalónù\Programování\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil < > äB _unhandled_exception < > @ ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Jichy\Âkola\Ing\Automatický vypouÂtìè meteobalónù\ProgramovánÃ\Pozemni stanice\Testing\trunk\demos\Autovypoustec STM32F10x\keil D $ ôC IÆÅ D ¼ eá ¯\ ñ dô dý ÅR Z
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MAX_DELKA_PRIKAZU 10 GPS_BUFFER 500 PWM_PERIODA_NORMAL 20000 !PWM_SIRKA_NORMAL PWM_PERIODA_NORMAL/2 $POCET_VENTIL (5*8) %POCET_LIS (1*8) &POCET_ZATAVENI (2*8) 'POCET_STRECHA (5*8) (CEKANI_NA_STRECHU (10*8) )CEKANI_NA_LIS (10*8) ,CTI_STRECHU palReadPad(STRECHA_SENS_PORT, STRECHA_SENS_STATE) -CTI_LIS palReadPad(LIS_SENS_PORT, LIS_SENS_STATE) _GPS_DEKODUJ_H_ #APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) _GPT_H_ I\gptChangeIntervalI(gptp,interval) { gpt_lld_change_interval(gptp, interval); } _GPT_LLD_H_ ]STM32_GPT_USE_TIM6 FALSE fSTM32_GPT_USE_TIM7 FALSE xSTM32_GPT_USE_TIM9 FALSE STM32_GPT_USE_TIM11 FALSE STM32_GPT_USE_TIM12 FALSE STM32_GPT_USE_TIM14 FALSE ½STM32_GPT_TIM6_IRQ_PRIORITY 7 ÄSTM32_GPT_TIM7_IRQ_PRIORITY 7 ÒSTM32_GPT_TIM9_IRQ_PRIORITY 7 ÙSTM32_GPT_TIM11_IRQ_PRIORITY 7 àSTM32_GPT_TIM12_IRQ_PRIORITY 7 çSTM32_GPT_TIM14_IRQ_PRIORITY 7 °gpt_lld_change_interval(gptp,interval) ((gptp)->tim->ARR = (uint16_t)((interval) - 1)) _SERIAL_LLD_H_ î_serial_driver_data _base_asynchronous_channel_data sdstate_t state; InputQueue iqueue; OutputQueue oqueue; uint8_t ib[SERIAL_BUFFERS_SIZE]; uint8_t ob[SERIAL_BUFFERS_SIZE]; USART_TypeDef *usart;
USART_CR2_STOP1_BITS (0 << 12) USART_CR2_STOP0P5_BITS (1 << 12) USART_CR2_STOP2_BITS (2 << 12) USART_CR2_STOP1P5_BITS (3 << 12) _PWM_H_ -PWM_OUTPUT_MASK 0x0F 2PWM_OUTPUT_DISABLED 0x00 7PWM_OUTPUT_ACTIVE_HIGH 0x01 <PWM_OUTPUT_ACTIVE_LOW 0x02 `xPWM_FRACTION_TO_WIDTH(pwmp,denominator,numerator) ((uint16_t)((((uint32_t)(pwmp)->period) * (uint32_t)(numerator)) / (uint32_t)(denominator))) PWM_DEGREES_TO_WIDTH(pwmp,degrees) PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) PWM_PERCENTAGE_TO_WIDTH(pwmp,percentage) PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) °pwmChangePeriodI(pwmp,value) { (pwmp)->period = (value); pwm_lld_change_period(pwmp, value); } ÃpwmEnableChannelI(pwmp,channel,width) pwm_lld_enable_channel(pwmp, channel, width) ÔpwmDisableChannelI(pwmp,channel) pwm_lld_disable_channel(pwmp, channel) àpwmIsChannelEnabledI(pwmp,channel) pwm_lld_is_channel_enabled(pwmp, channel) _PWM_LLD_H_ %PWM_CHANNELS 4 +PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 1PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 :PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 CPWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 STM32_PWM_USE_TIM9 FALSE ÅSTM32_PWM_TIM9_IRQ_PRIORITY 7 pwm_lld_change_period(pwmp,period) ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) ¢pwm_lld_is_channel_enabled(pwmp,channel) (((pwmp)->tim->CCR[channel] != 0) || (((pwmp)->tim->DIER & (2 << channel)) != 0)) !MAX_FILLER 11 "FLOAT_PRECISION 100000 __stdarg_h
__ARMCLIB_VERSION 5030024 __STDARG_DECLS __CLIBNS __CLIBNS 1va_start(ap,parmN) __va_start(ap, parmN) ?va_arg(ap,type) __va_arg(ap, type) S__va_copy(dest,src) ((void)((dest) = (src))) Yva_copy(dest,src) ((void)((dest) = (src))) cva_end(ap) __va_end(ap) _PAL_LLD_H_ )PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 .PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 bPAL_IOPORTS_WIDTH 16 hPAL_WHOLE_PORT ((ioportmask_t)0xFFFF) IOPORT1 GPIOA IOPORT2 GPIOB IOPORT3 GPIOC IOPORT4 GPIOD ¢IOPORT5 GPIOE ©IOPORT6 GPIOF °IOPORT7 GPIOG ½pal_lld_init(config) _pal_lld_init(config) Ëpal_lld_readport(port) ((port)->IDR) Ùpal_lld_readlatch(port) ((port)->ODR) èpal_lld_writeport(port,bits) ((port)->ODR = (bits)) ÷pal_lld_setport(port,bits) ((port)->BSRR = (bits)) pal_lld_clearport(port,bits) ((port)->BRR = (bits)) pal_lld_writegroup(port,mask,offset,bits) ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | (((bits) & (mask)) << (offset))) «pal_lld_setgroupmode(port,mask,offset,mode) _pal_lld_setgroupmode(port, mask << offset, mode) »pal_lld_writepad(port,pad,bit) pal_lld_writegroup(port, 1, pad, bit) _CHVT_H_ .S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) :MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) GUS2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) chVTDoTickI() { vtlist.vt_systime++; if (&vtlist != (VTList *)vtlist.vt_next) { VirtualTimer *vtp; --vtlist.vt_next->vt_time; while (!(vtp = vtlist.vt_next)->vt_time) { vtfunc_t fn = vtp->vt_func; vtp->vt_func = (vtfunc_t)NULL; vtp->vt_next->vt_prev = (void *)&vtlist; (&vtlist)->vt_next = vtp->vt_next; chSysUnlockFromIsr(); fn(vtp->vt_par); chSysLockFromIsr(); } } } chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) ®chVTSet(vtp,time,vtfunc,par) { chSysLock(); chVTSetI(vtp, time, vtfunc, par); chSysUnlock(); } ¼chVTReset(vtp) { chSysLock(); if (chVTIsArmedI(vtp)) chVTResetI(vtp); chSysUnlock(); } ÎchTimeNow() (vtlist.vt_systime) 9 _CHINLINE_H_ $ " _CHINLINE_H_ _CHSCHD_H_ $RDY_OK 0 %RDY_TIMEOUT -1 'RDY_RESET -2 /NOPRIO 0 0IDLEPRIO 1 1LOWPRIO 2 2NORMALPRIO 64 3HIGHPRIO 127 4ABSPRIO 255 ATIME_IMMEDIATE ((systime_t)0) GTIME_INFINITE ((systime_t)-1) Ofirstprio(rlp) ((rlp)->p_next->p_prio) scurrp rlist.r_current ~setcurrp(tp) (currp = (tp)) ³chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) ¾chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) ÉchSchDoYieldS() { if (chSchCanYieldS()) chSchDoRescheduleBehind(); } ×chSchPreemption() { tprio_t p1 = firstprio(&rlist.r_queue); tprio_t p2 = currp->p_prio; if (currp->p_preempt) { if (p1 > p2) chSchDoRescheduleAhead(); } else { if (p1 >= p2) chSchDoRescheduleBehind(); } } 15_offsetof(st,m) ((size_t)((char *)&((st *)0)->m - (char *)0)) _CHREGISTRY_H_ IchRegSetThreadName(p) (currp->p_name = (p)) UchRegGetThreadName(tp) ((tp)->p_name) cREG_REMOVE(tp) { (tp)->p_older->p_newer = (tp)->p_newer; (tp)->p_newer->p_older = (tp)->p_older; } nREG_INSERT(tp) { (tp)->p_newer = (Thread *)&rlist; (tp)->p_older = rlist.r_older; (tp)->p_older->p_newer = rlist.r_older = (tp); } , D _CHINLINE_H_ _CHINLINE_H_ ' / )3H_LOCK(h) chMtxLock(&(h)->h_mtx) 4H_UNLOCK(h) chMtxUnlock() °LIMIT(p) (union heap_header *)((uint8_t *)(p) + sizeof(union heap_header) + (p)->h.size) = _SERIAL_H_ *SD_PARITY_ERROR 32 +SD_FRAMING_ERROR 64 ,SD_OVERRUN_ERROR 128 -SD_NOISE_ERROR 256 .SD_BREAK_DETECTED 512 hm_serial_driver_methods _base_asynchronous_channel_methods sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue) ¦sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue) ²sdPut(sdp,b) chOQPut(&(sdp)->oqueue, b) ¾sdPutTimeout(sdp,b,t) chOQPutTimeout(&(sdp)->oqueue, b, t) ÊsdGet(sdp) chIQGet(&(sdp)->iqueue) ÖsdGetTimeout(sdp,t) chIQGetTimeout(&(sdp)->iqueue, t) âsdWrite(sdp,b,n) chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) ðsdWriteTimeout(sdp,b,n,t) chOQWriteTimeout(&(sdp)->oqueue, b, n, t) ýsdAsynchronousWrite(sdp,b,n) chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) sdRead(sdp,b,n) chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) sdReadTimeout(sdp,b,n,t) chIQReadTimeout(&(sdp)->iqueue, b, n, t) ¥sdAsynchronousRead(sdp,b,n) chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) _SERIAL_LLD_H_ î_serial_driver_data _base_asynchronous_channel_data sdstate_t state; InputQueue iqueue; OutputQueue oqueue; uint8_t ib[SERIAL_BUFFERS_SIZE]; uint8_t ob[SERIAL_BUFFERS_SIZE]; USART_TypeDef *usart;
USART_CR2_STOP1_BITS (0 << 12) USART_CR2_STOP0P5_BITS (1 << 12) USART_CR2_STOP2_BITS (2 << 12) USART_CR2_STOP1P5_BITS (3 << 12) _PWM_H_ -PWM_OUTPUT_MASK 0x0F 2PWM_OUTPUT_DISABLED 0x00 7PWM_OUTPUT_ACTIVE_HIGH 0x01 <PWM_OUTPUT_ACTIVE_LOW 0x02 `xPWM_FRACTION_TO_WIDTH(pwmp,denominator,numerator) ((uint16_t)((((uint32_t)(pwmp)->period) * (uint32_t)(numerator)) / (uint32_t)(denominator))) PWM_DEGREES_TO_WIDTH(pwmp,degrees) PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) PWM_PERCENTAGE_TO_WIDTH(pwmp,percentage) PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) °pwmChangePeriodI(pwmp,value) { (pwmp)->period = (value); pwm_lld_change_period(pwmp, value); } ÃpwmEnableChannelI(pwmp,channel,width) pwm_lld_enable_channel(pwmp, channel, width) ÔpwmDisableChannelI(pwmp,channel) pwm_lld_disable_channel(pwmp, channel) àpwmIsChannelEnabledI(pwmp,channel) pwm_lld_is_channel_enabled(pwmp, channel) _PWM_LLD_H_ %PWM_CHANNELS 4 +PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 1PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 :PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 CPWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 STM32_PWM_USE_TIM9 FALSE ÅSTM32_PWM_TIM9_IRQ_PRIORITY 7 pwm_lld_change_period(pwmp,period) ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) ¢pwm_lld_is_channel_enabled(pwmp,channel) (((pwmp)->tim->CCR[channel] != 0) || (((pwmp)->tim->DIER & (2 << channel)) != 0)) _GPT_H_ I\gptChangeIntervalI(gptp,interval) { gpt_lld_change_interval(gptp, interval); } _GPT_LLD_H_ ]STM32_GPT_USE_TIM6 FALSE fSTM32_GPT_USE_TIM7 FALSE xSTM32_GPT_USE_TIM9 FALSE STM32_GPT_USE_TIM11 FALSE STM32_GPT_USE_TIM12 FALSE STM32_GPT_USE_TIM14 FALSE ½STM32_GPT_TIM6_IRQ_PRIORITY 7 ÄSTM32_GPT_TIM7_IRQ_PRIORITY 7 ÒSTM32_GPT_TIM9_IRQ_PRIORITY 7 ÙSTM32_GPT_TIM11_IRQ_PRIORITY 7 àSTM32_GPT_TIM12_IRQ_PRIORITY 7 çSTM32_GPT_TIM14_IRQ_PRIORITY 7 °gpt_lld_change_interval(gptp,interval) ((gptp)->tim->ARR = (uint16_t)((interval) - 1)) _PAL_LLD_H_ )PAL_MODE_STM32_ALTERNATE_PUSHPULL 16 .PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 bPAL_IOPORTS_WIDTH 16 hPAL_WHOLE_PORT ((ioportmask_t)0xFFFF) IOPORT1 GPIOA IOPORT2 GPIOB IOPORT3 GPIOC IOPORT4 GPIOD ¢IOPORT5 GPIOE ©IOPORT6 GPIOF °IOPORT7 GPIOG ½pal_lld_init(config) _pal_lld_init(config) Ëpal_lld_readport(port) ((port)->IDR) Ùpal_lld_readlatch(port) ((port)->ODR) èpal_lld_writeport(port,bits) ((port)->ODR = (bits)) ÷pal_lld_setport(port,bits) ((port)->BSRR = (bits)) pal_lld_clearport(port,bits) ((port)->BRR = (bits)) pal_lld_writegroup(port,mask,offset,bits) ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | (((bits) & (mask)) << (offset))) «pal_lld_setgroupmode(port,mask,offset,mode) _pal_lld_setgroupmode(port, mask << offset, mode) »pal_lld_writepad(port,pad,bit) pal_lld_writegroup(port, 1, pad, bit) _TM_H_ XtmStartMeasurement(tmp) (tmp)->start(tmp) ctmStopMeasurement(tmp) (tmp)->stop(tmp) )_HAL_LLD_H_ +4HAL_IMPLEMENTS_COUNTERS TRUE :STM32_HSICLK 8000000 ;STM32_LSICLK 40000 BSTM32_PLS_MASK (7 << 5) CSTM32_PLS_LEV0 (0 << 5) DSTM32_PLS_LEV1 (1 << 5) ESTM32_PLS_LEV2 (2 << 5) FSTM32_PLS_LEV3 (3 << 5) GSTM32_PLS_LEV4 (4 << 5) HSTM32_PLS_LEV5 (5 << 5) ISTM32_PLS_LEV6 (6 << 5) JSTM32_PLS_LEV7 (7 << 5) VSTM32_HAS_RTC TRUE WSTM32_RTC_HAS_SUBSECONDS TRUE XSTM32_RTC_IS_CALENDAR FALSE ¨Þhal_lld_get_counter_value() DWT_CYCCNT éhal_lld_get_counter_frequency() STM32_HCLK ðñò +_STM32_H_ 5STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) 3__STM32F10x_H yHSE_VALUE ((uint32_t)8000000) HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) HSI_VALUE ((uint32_t)8000000) __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) __STM32F10X_STDPERIPH_VERSION_RC (0x00) __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24) |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16) |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8) |(__STM32F10X_STDPERIPH_VERSION_RC)) __MPU_PRESENT 0 ¢__NVIC_PRIO_BITS 4 £__Vendor_SysTickConfig 0 ìïIS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT HSE_Value HSE_VALUE HSI_Value HSI_VALUE
FLASH_BASE ((uint32_t)0x08000000)
SRAM_BASE ((uint32_t)0x20000000)
PERIPH_BASE ((uint32_t)0x40000000)
SRAM_BB_BASE ((uint32_t)0x22000000)
PERIPH_BB_BASE ((uint32_t)0x42000000)
FSMC_R_BASE ((uint32_t)0xA0000000)
APB1PERIPH_BASE PERIPH_BASE
APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
TIM2_BASE (APB1PERIPH_BASE + 0x0000)
TIM3_BASE (APB1PERIPH_BASE + 0x0400)
TIM4_BASE (APB1PERIPH_BASE + 0x0800)
TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
TIM6_BASE (APB1PERIPH_BASE + 0x1000)
TIM7_BASE (APB1PERIPH_BASE + 0x1400)
TIM12_BASE (APB1PERIPH_BASE + 0x1800)
TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
TIM14_BASE (APB1PERIPH_BASE + 0x2000)
RTC_BASE (APB1PERIPH_BASE + 0x2800)
WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
IWDG_BASE (APB1PERIPH_BASE + 0x3000) ¡
SPI2_BASE (APB1PERIPH_BASE + 0x3800) ¢
SPI3_BASE (APB1PERIPH_BASE + 0x3C00) £
USART2_BASE (APB1PERIPH_BASE + 0x4400) ¤
USART3_BASE (APB1PERIPH_BASE + 0x4800) ¥
UART4_BASE (APB1PERIPH_BASE + 0x4C00) ¦
UART5_BASE (APB1PERIPH_BASE + 0x5000) §
I2C1_BASE (APB1PERIPH_BASE + 0x5400) ¨
I2C2_BASE (APB1PERIPH_BASE + 0x5800) ©
CAN1_BASE (APB1PERIPH_BASE + 0x6400) ª
CAN2_BASE (APB1PERIPH_BASE + 0x6800) «
BKP_BASE (APB1PERIPH_BASE + 0x6C00) ¬
PWR_BASE (APB1PERIPH_BASE + 0x7000)
DAC_BASE (APB1PERIPH_BASE + 0x7400) ®
CEC_BASE (APB1PERIPH_BASE + 0x7800) °
AFIO_BASE (APB2PERIPH_BASE + 0x0000) ±
EXTI_BASE (APB2PERIPH_BASE + 0x0400) ²
GPIOA_BASE (APB2PERIPH_BASE + 0x0800) ³
GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) ´
GPIOC_BASE (APB2PERIPH_BASE + 0x1000) µ
GPIOD_BASE (APB2PERIPH_BASE + 0x1400) ¶
GPIOE_BASE (APB2PERIPH_BASE + 0x1800) ·
GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) ¸
GPIOG_BASE (APB2PERIPH_BASE + 0x2000) ¹
ADC1_BASE (APB2PERIPH_BASE + 0x2400) º
ADC2_BASE (APB2PERIPH_BASE + 0x2800) »
TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ¼
SPI1_BASE (APB2PERIPH_BASE + 0x3000) ½
TIM8_BASE (APB2PERIPH_BASE + 0x3400) ¾
USART1_BASE (APB2PERIPH_BASE + 0x3800) ¿
ADC3_BASE (APB2PERIPH_BASE + 0x3C00) À
TIM15_BASE (APB2PERIPH_BASE + 0x4000) Á
TIM16_BASE (APB2PERIPH_BASE + 0x4400) Â
TIM17_BASE (APB2PERIPH_BASE + 0x4800) Ã
TIM9_BASE (APB2PERIPH_BASE + 0x4C00) Ä
TIM10_BASE (APB2PERIPH_BASE + 0x5000) Å
TIM11_BASE (APB2PERIPH_BASE + 0x5400) Ç
SDIO_BASE (PERIPH_BASE + 0x18000) É
DMA1_BASE (AHBPERIPH_BASE + 0x0000) Ê
DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) Ë
DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) Ì
DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) Í
DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) Î
DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) Ï
DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) Ð
DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) Ñ
DMA2_BASE (AHBPERIPH_BASE + 0x0400) Ò
DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) Ó
DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) Ô
DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) Õ
DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) Ö
DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ×
RCC_BASE (AHBPERIPH_BASE + 0x1000) Ø
CRC_BASE (AHBPERIPH_BASE + 0x3000) Ú
FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) Û
OB_BASE ((uint32_t)0x1FFFF800) Ý
ETH_BASE (AHBPERIPH_BASE + 0x8000) Þ
ETH_MAC_BASE (ETH_BASE) ß
ETH_MMC_BASE (ETH_BASE + 0x0100) à
ETH_PTP_BASE (ETH_BASE + 0x0700) á
ETH_DMA_BASE (ETH_BASE + 0x1000) ã
FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) ä
FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) å
FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) æ
FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) ç
FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) é
DBGMCU_BASE ((uint32_t)0xE0042000) ó
TIM2 ((TIM_TypeDef *) TIM2_BASE) ô
TIM3 ((TIM_TypeDef *) TIM3_BASE) õ
TIM4 ((TIM_TypeDef *) TIM4_BASE) ö
TIM5 ((TIM_TypeDef *) TIM5_BASE) ÷
TIM6 ((TIM_TypeDef *) TIM6_BASE) ø
TIM7 ((TIM_TypeDef *) TIM7_BASE) ù
TIM12 ((TIM_TypeDef *) TIM12_BASE) ú
TIM13 ((TIM_TypeDef *) TIM13_BASE) û
TIM14 ((TIM_TypeDef *) TIM14_BASE) ü
RTC ((RTC_TypeDef *) RTC_BASE) ý
WWDG ((WWDG_TypeDef *) WWDG_BASE) þ
IWDG ((IWDG_TypeDef *) IWDG_BASE) ÿ
SPI2 ((SPI_TypeDef *) SPI2_BASE) SPI3 ((SPI_TypeDef *) SPI3_BASE) USART2 ((USART_TypeDef *) USART2_BASE) USART3 ((USART_TypeDef *) USART3_BASE) UART4 ((USART_TypeDef *) UART4_BASE) UART5 ((USART_TypeDef *) UART5_BASE)
I2C1 ((I2C_TypeDef *) I2C1_BASE) I2C2 ((I2C_TypeDef *) I2C2_BASE) CAN1 ((CAN_TypeDef *) CAN1_BASE) CAN2 ((CAN_TypeDef *) CAN2_BASE) BKP ((BKP_TypeDef *) BKP_BASE) PWR ((PWR_TypeDef *) PWR_BASE) DAC ((DAC_TypeDef *) DAC_BASE) CEC ((CEC_TypeDef *) CEC_BASE) AFIO ((AFIO_TypeDef *) AFIO_BASE) EXTI ((EXTI_TypeDef *) EXTI_BASE) GPIOA ((GPIO_TypeDef *) GPIOA_BASE) GPIOB ((GPIO_TypeDef *) GPIOB_BASE) GPIOC ((GPIO_TypeDef *) GPIOC_BASE) GPIOD ((GPIO_TypeDef *) GPIOD_BASE) GPIOE ((GPIO_TypeDef *) GPIOE_BASE) GPIOF ((GPIO_TypeDef *) GPIOF_BASE) GPIOG ((GPIO_TypeDef *) GPIOG_BASE) ADC1 ((ADC_TypeDef *) ADC1_BASE) ADC2 ((ADC_TypeDef *) ADC2_BASE) TIM1 ((TIM_TypeDef *) TIM1_BASE) SPI1 ((SPI_TypeDef *) SPI1_BASE) TIM8 ((TIM_TypeDef *) TIM8_BASE) USART1 ((USART_TypeDef *) USART1_BASE) ADC3 ((ADC_TypeDef *) ADC3_BASE) TIM15 ((TIM_TypeDef *) TIM15_BASE) TIM16 ((TIM_TypeDef *) TIM16_BASE) TIM17 ((TIM_TypeDef *) TIM17_BASE) TIM9 ((TIM_TypeDef *) TIM9_BASE) ¡ TIM10 ((TIM_TypeDef *) TIM10_BASE) ¢ TIM11 ((TIM_TypeDef *) TIM11_BASE) £ SDIO ((SDIO_TypeDef *) SDIO_BASE) ¤ DMA1 ((DMA_TypeDef *) DMA1_BASE) ¥ DMA2 ((DMA_TypeDef *) DMA2_BASE) ¦ DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) § DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) ¨ DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) © DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) ª DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) « DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) ¬ DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) ® DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) ¯ DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) ° DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) ± DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) ² RCC ((RCC_TypeDef *) RCC_BASE) ³ CRC ((CRC_TypeDef *) CRC_BASE) ´ FLASH ((FLASH_TypeDef *) FLASH_R_BASE) µ OB ((OB_TypeDef *) OB_BASE) ¶ ETH ((ETH_TypeDef *) ETH_BASE) · FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) ¸ FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) ¹ FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) º FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) » FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) ¼ DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) Õ CRC_DR_DR ((uint32_t)0xFFFFFFFF) Ù CRC_IDR_IDR ((uint8_t)0xFF) Ý CRC_CR_RESET ((uint8_t)0x01) æ PWR_CR_LPDS ((uint16_t)0x0001) ç PWR_CR_PDDS ((uint16_t)0x0002) è PWR_CR_CWUF ((uint16_t)0x0004) é PWR_CR_CSBF ((uint16_t)0x0008) ê PWR_CR_PVDE ((uint16_t)0x0010) ì PWR_CR_PLS ((uint16_t)0x00E0) í PWR_CR_PLS_0 ((uint16_t)0x0020) î PWR_CR_PLS_1 ((uint16_t)0x0040) ï PWR_CR_PLS_2 ((uint16_t)0x0080) ò PWR_CR_PLS_2V2 ((uint16_t)0x0000) ó PWR_CR_PLS_2V3 ((uint16_t)0x0020) ô PWR_CR_PLS_2V4 ((uint16_t)0x0040) õ PWR_CR_PLS_2V5 ((uint16_t)0x0060) ö PWR_CR_PLS_2V6 ((uint16_t)0x0080) ÷ PWR_CR_PLS_2V7 ((uint16_t)0x00A0) ø PWR_CR_PLS_2V8 ((uint16_t)0x00C0) ù PWR_CR_PLS_2V9 ((uint16_t)0x00E0) û PWR_CR_DBP ((uint16_t)0x0100) ÿ PWR_CSR_WUF ((uint16_t)0x0001) PWR_CSR_SBF ((uint16_t)0x0002) PWR_CSR_PVDO ((uint16_t)0x0004) PWR_CSR_EWUP ((uint16_t)0x0100) BKP_DR1_D ((uint16_t)0xFFFF) BKP_DR2_D ((uint16_t)0xFFFF) BKP_DR3_D ((uint16_t)0xFFFF) BKP_DR4_D ((uint16_t)0xFFFF) BKP_DR5_D ((uint16_t)0xFFFF) BKP_DR6_D ((uint16_t)0xFFFF) BKP_DR7_D ((uint16_t)0xFFFF) BKP_DR8_D ((uint16_t)0xFFFF) £ BKP_DR9_D ((uint16_t)0xFFFF) ¦ BKP_DR10_D ((uint16_t)0xFFFF) © BKP_DR11_D ((uint16_t)0xFFFF) ¬ BKP_DR12_D ((uint16_t)0xFFFF) ¯ BKP_DR13_D ((uint16_t)0xFFFF) ² BKP_DR14_D ((uint16_t)0xFFFF) µ BKP_DR15_D ((uint16_t)0xFFFF) ¸ BKP_DR16_D ((uint16_t)0xFFFF) » BKP_DR17_D ((uint16_t)0xFFFF) ¾ BKP_DR18_D ((uint16_t)0xFFFF) Á BKP_DR19_D ((uint16_t)0xFFFF) Ä BKP_DR20_D ((uint16_t)0xFFFF) Ç BKP_DR21_D ((uint16_t)0xFFFF) Ê BKP_DR22_D ((uint16_t)0xFFFF) Í BKP_DR23_D ((uint16_t)0xFFFF) Ð BKP_DR24_D ((uint16_t)0xFFFF) Ó BKP_DR25_D ((uint16_t)0xFFFF) Ö BKP_DR26_D ((uint16_t)0xFFFF) Ù BKP_DR27_D ((uint16_t)0xFFFF) Ü BKP_DR28_D ((uint16_t)0xFFFF) ß BKP_DR29_D ((uint16_t)0xFFFF) â BKP_DR30_D ((uint16_t)0xFFFF) å BKP_DR31_D ((uint16_t)0xFFFF) è BKP_DR32_D ((uint16_t)0xFFFF) ë BKP_DR33_D ((uint16_t)0xFFFF) î BKP_DR34_D ((uint16_t)0xFFFF) ñ BKP_DR35_D ((uint16_t)0xFFFF) ô BKP_DR36_D ((uint16_t)0xFFFF) ÷ BKP_DR37_D ((uint16_t)0xFFFF) ú BKP_DR38_D ((uint16_t)0xFFFF) ý BKP_DR39_D ((uint16_t)0xFFFF)
BKP_DR40_D ((uint16_t)0xFFFF)
BKP_DR41_D ((uint16_t)0xFFFF)
BKP_DR42_D ((uint16_t)0xFFFF)
BKP_RTCCR_CAL ((uint16_t)0x007F)
BKP_RTCCR_CCO ((uint16_t)0x0080)
BKP_RTCCR_ASOE ((uint16_t)0x0100)
BKP_RTCCR_ASOS ((uint16_t)0x0200)
BKP_CR_TPE ((uint8_t)0x01)
BKP_CR_TPAL ((uint8_t)0x02)
BKP_CSR_CTE ((uint16_t)0x0001)
BKP_CSR_CTI ((uint16_t)0x0002)
BKP_CSR_TPIE ((uint16_t)0x0004)
BKP_CSR_TEF ((uint16_t)0x0100)
BKP_CSR_TIF ((uint16_t)0x0200)
RCC_CR_HSION ((uint32_t)0x00000001) ¡
RCC_CR_HSIRDY ((uint32_t)0x00000002) ¢
RCC_CR_HSITRIM ((uint32_t)0x000000F8) £
RCC_CR_HSICAL ((uint32_t)0x0000FF00) ¤
RCC_CR_HSEON ((uint32_t)0x00010000) ¥
RCC_CR_HSERDY ((uint32_t)0x00020000) ¦
RCC_CR_HSEBYP ((uint32_t)0x00040000) §
RCC_CR_CSSON ((uint32_t)0x00080000) ¨
RCC_CR_PLLON ((uint32_t)0x01000000) ©
RCC_CR_PLLRDY ((uint32_t)0x02000000) ´
RCC_CFGR_SW ((uint32_t)0x00000003) µ
RCC_CFGR_SW_0 ((uint32_t)0x00000001) ¶
RCC_CFGR_SW_1 ((uint32_t)0x00000002) ¸
RCC_CFGR_SW_HSI ((uint32_t)0x00000000) ¹
RCC_CFGR_SW_HSE ((uint32_t)0x00000001) º
RCC_CFGR_SW_PLL ((uint32_t)0x00000002) ½
RCC_CFGR_SWS ((uint32_t)0x0000000C) ¾
RCC_CFGR_SWS_0 ((uint32_t)0x00000004) ¿
RCC_CFGR_SWS_1 ((uint32_t)0x00000008) Á
RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) Â
RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) Ã
RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) Æ
RCC_CFGR_HPRE ((uint32_t)0x000000F0) Ç
RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) È
RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) É
RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) Ê
RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) Ì
RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) Í
RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) Î
RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) Ï
RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) Ð
RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) Ñ
RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) Ò
RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) Ó
RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) Ô
RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) ×
RCC_CFGR_PPRE1 ((uint32_t)0x00000700) Ø
RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) Ù
RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) Ú
RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) Ü
RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) Ý
RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) Þ
RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) ß
RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) à
RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) ã
RCC_CFGR_PPRE2 ((uint32_t)0x00003800) ä
RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) å
RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) æ
RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) è
RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) é
RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) ê
RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) ë
RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) ì
RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) ï
RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) ð
RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) ñ
RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) ó
RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) ô
RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) õ
RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) ö
RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) ø
RCC_CFGR_PLLSRC ((uint32_t)0x00010000) ú
RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) ý
RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) þ
RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) ÿ
RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) ÇRCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) ÈRCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) ÊRCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) ËRCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) ÍRCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) ÎRCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) ÏRCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) ÐRCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) ÑRCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) ÒRCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) ÓRCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) ÔRCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) ÕRCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) ÖRCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) ×RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) ØRCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) ÙRCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) ÚRCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) ÛRCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) ÜRCC_CFGR_USBPRE ((uint32_t)0x00400000) ßRCC_CFGR_MCO ((uint32_t)0x07000000) àRCC_CFGR_MCO_0 ((uint32_t)0x01000000) áRCC_CFGR_MCO_1 ((uint32_t)0x02000000) âRCC_CFGR_MCO_2 ((uint32_t)0x04000000) äRCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) åRCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) æRCC_CFGR_MCO_HSI ((uint32_t)0x05000000) çRCC_CFGR_MCO_HSE ((uint32_t)0x06000000) èRCC_CFGR_MCO_PLL ((uint32_t)0x07000000) ìRCC_CIR_LSIRDYF ((uint32_t)0x00000001) íRCC_CIR_LSERDYF ((uint32_t)0x00000002) îRCC_CIR_HSIRDYF ((uint32_t)0x00000004) ïRCC_CIR_HSERDYF ((uint32_t)0x00000008) ðRCC_CIR_PLLRDYF ((uint32_t)0x00000010) ñRCC_CIR_CSSF ((uint32_t)0x00000080) òRCC_CIR_LSIRDYIE ((uint32_t)0x00000100) óRCC_CIR_LSERDYIE ((uint32_t)0x00000200) ôRCC_CIR_HSIRDYIE ((uint32_t)0x00000400) õRCC_CIR_HSERDYIE ((uint32_t)0x00000800) öRCC_CIR_PLLRDYIE ((uint32_t)0x00001000) ÷RCC_CIR_LSIRDYC ((uint32_t)0x00010000) øRCC_CIR_LSERDYC ((uint32_t)0x00020000) ùRCC_CIR_HSIRDYC ((uint32_t)0x00040000) úRCC_CIR_HSERDYC ((uint32_t)0x00080000) ûRCC_CIR_PLLRDYC ((uint32_t)0x00100000) üRCC_CIR_CSSC ((uint32_t)0x00800000) RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) ¢RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) £RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) ¤RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) ¥RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) ´RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) µRCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) ¶RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) ·RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) ¸RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) »RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) ¾RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) ¿RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) ÂRCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) ÃRCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) ÄRCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) ÅRCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) ÉRCC_APB1RSTR_USBRST ((uint32_t)0x00800000) ÍRCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) ÎRCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) ÏRCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) ÐRCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) ÑRCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) ÒRCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) ÓRCC_APB1RSTR_DACRST ((uint32_t)0x20000000) òRCC_AHBENR_DMA1EN ((uint16_t)0x0001) óRCC_AHBENR_SRAMEN ((uint16_t)0x0004) ôRCC_AHBENR_FLITFEN ((uint16_t)0x0010) õRCC_AHBENR_CRCEN ((uint16_t)0x0040) úRCC_AHBENR_DMA2EN ((uint16_t)0x0002) þRCC_AHBENR_FSMCEN ((uint16_t)0x0100) ÿRCC_AHBENR_SDIOEN ((uint16_t)0x0400) RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) ¤RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) ¨RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) ©RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) ªRCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) «RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) ºRCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) »RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) ¼RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) ½RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) ¾RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) ÁRCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) ÄRCC_APB1ENR_BKPEN ((uint32_t)0x08000000) ÅRCC_APB1ENR_PWREN ((uint32_t)0x10000000) ÈRCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) ÉRCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) ÊRCC_APB1ENR_USART3EN ((uint32_t)0x00040000) ËRCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) ÑRCC_APB1ENR_USBEN ((uint32_t)0x00800000) ×RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) ØRCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) ÙRCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) ÚRCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) ÛRCC_APB1ENR_UART4EN ((uint32_t)0x00080000) ÜRCC_APB1ENR_UART5EN ((uint32_t)0x00100000) ÝRCC_APB1ENR_DACEN ((uint32_t)0x20000000) üRCC_BDCR_LSEON ((uint32_t)0x00000001) ýRCC_BDCR_LSERDY ((uint32_t)0x00000002) þRCC_BDCR_LSEBYP ((uint32_t)0x00000004) RCC_BDCR_RTCSEL ((uint32_t)0x00000300) RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) RCC_BDCR_RTCEN ((uint32_t)0x00008000) RCC_BDCR_BDRST ((uint32_t)0x00010000) RCC_CSR_LSION ((uint32_t)0x00000001) RCC_CSR_LSIRDY ((uint32_t)0x00000002) RCC_CSR_RMVF ((uint32_t)0x01000000) RCC_CSR_PINRSTF ((uint32_t)0x04000000) RCC_CSR_PORRSTF ((uint32_t)0x08000000) RCC_CSR_SFTRSTF ((uint32_t)0x10000000) RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) GPIO_CRL_MODE ((uint32_t)0x33333333) GPIO_CRL_MODE0 ((uint32_t)0x00000003) GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) GPIO_CRL_MODE1 ((uint32_t)0x00000030) GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) ¡GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) £GPIO_CRL_MODE2 ((uint32_t)0x00000300) ¤GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) ¥GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) §GPIO_CRL_MODE3 ((uint32_t)0x00003000) ¨GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) ©GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) «GPIO_CRL_MODE4 ((uint32_t)0x00030000) ¬GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) ¯GPIO_CRL_MODE5 ((uint32_t)0x00300000) °GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) ±GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) ³GPIO_CRL_MODE6 ((uint32_t)0x03000000) ´GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) µGPIO_CRL_MODE6_1 ((uint32_t)0x02000000) ·GPIO_CRL_MODE7 ((uint32_t)0x30000000) ¸GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) ¹GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) »GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) ½GPIO_CRL_CNF0 ((uint32_t)0x0000000C) ¾GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) ¿GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) ÁGPIO_CRL_CNF1 ((uint32_t)0x000000C0) ÂGPIO_CRL_CNF1_0 ((uint32_t)0x00000040) ÃGPIO_CRL_CNF1_1 ((uint32_t)0x00000080) ÅGPIO_CRL_CNF2 ((uint32_t)0x00000C00) ÆGPIO_CRL_CNF2_0 ((uint32_t)0x00000400) ÇGPIO_CRL_CNF2_1 ((uint32_t)0x00000800) ÉGPIO_CRL_CNF3 ((uint32_t)0x0000C000) ÊGPIO_CRL_CNF3_0 ((uint32_t)0x00004000) ËGPIO_CRL_CNF3_1 ((uint32_t)0x00008000) ÍGPIO_CRL_CNF4 ((uint32_t)0x000C0000) ÎGPIO_CRL_CNF4_0 ((uint32_t)0x00040000) ÏGPIO_CRL_CNF4_1 ((uint32_t)0x00080000) ÑGPIO_CRL_CNF5 ((uint32_t)0x00C00000) ÒGPIO_CRL_CNF5_0 ((uint32_t)0x00400000) ÓGPIO_CRL_CNF5_1 ((uint32_t)0x00800000) ÕGPIO_CRL_CNF6 ((uint32_t)0x0C000000) ÖGPIO_CRL_CNF6_0 ((uint32_t)0x04000000) ×GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) ÙGPIO_CRL_CNF7 ((uint32_t)0xC0000000) ÚGPIO_CRL_CNF7_0 ((uint32_t)0x40000000) ÛGPIO_CRL_CNF7_1 ((uint32_t)0x80000000) ÞGPIO_CRH_MODE ((uint32_t)0x33333333) àGPIO_CRH_MODE8 ((uint32_t)0x00000003) áGPIO_CRH_MODE8_0 ((uint32_t)0x00000001) âGPIO_CRH_MODE8_1 ((uint32_t)0x00000002) äGPIO_CRH_MODE9 ((uint32_t)0x00000030) åGPIO_CRH_MODE9_0 ((uint32_t)0x00000010) æGPIO_CRH_MODE9_1 ((uint32_t)0x00000020) èGPIO_CRH_MODE10 ((uint32_t)0x00000300) éGPIO_CRH_MODE10_0 ((uint32_t)0x00000100) êGPIO_CRH_MODE10_1 ((uint32_t)0x00000200) ìGPIO_CRH_MODE11 ((uint32_t)0x00003000) íGPIO_CRH_MODE11_0 ((uint32_t)0x00001000) îGPIO_CRH_MODE11_1 ((uint32_t)0x00002000) ðGPIO_CRH_MODE12 ((uint32_t)0x00030000) ñGPIO_CRH_MODE12_0 ((uint32_t)0x00010000) òGPIO_CRH_MODE12_1 ((uint32_t)0x00020000) ôGPIO_CRH_MODE13 ((uint32_t)0x00300000) õGPIO_CRH_MODE13_0 ((uint32_t)0x00100000) öGPIO_CRH_MODE13_1 ((uint32_t)0x00200000) øGPIO_CRH_MODE14 ((uint32_t)0x03000000) ùGPIO_CRH_MODE14_0 ((uint32_t)0x01000000) úGPIO_CRH_MODE14_1 ((uint32_t)0x02000000) üGPIO_CRH_MODE15 ((uint32_t)0x30000000) ýGPIO_CRH_MODE15_0 ((uint32_t)0x10000000) þGPIO_CRH_MODE15_1 ((uint32_t)0x20000000) GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) GPIO_CRH_CNF8 ((uint32_t)0x0000000C) GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) GPIO_CRH_CNF9 ((uint32_t)0x000000C0) GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) GPIO_CRH_CNF10 ((uint32_t)0x00000C00) GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) GPIO_CRH_CNF11 ((uint32_t)0x0000C000) GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) GPIO_CRH_CNF12 ((uint32_t)0x000C0000) GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) GPIO_CRH_CNF13 ((uint32_t)0x00C00000) GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) GPIO_CRH_CNF14 ((uint32_t)0x0C000000) GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) GPIO_CRH_CNF15 ((uint32_t)0xC0000000) GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) £GPIO_IDR_IDR0 ((uint16_t)0x0001) ¤GPIO_IDR_IDR1 ((uint16_t)0x0002) ¥GPIO_IDR_IDR2 ((uint16_t)0x0004) ¦GPIO_IDR_IDR3 ((uint16_t)0x0008) §GPIO_IDR_IDR4 ((uint16_t)0x0010) ¨GPIO_IDR_IDR5 ((uint16_t)0x0020) ©GPIO_IDR_IDR6 ((uint16_t)0x0040) ªGPIO_IDR_IDR7 ((uint16_t)0x0080) «GPIO_IDR_IDR8 ((uint16_t)0x0100) ¬GPIO_IDR_IDR9 ((uint16_t)0x0200) GPIO_IDR_IDR10 ((uint16_t)0x0400) ®GPIO_IDR_IDR11 ((uint16_t)0x0800) ¯GPIO_IDR_IDR12 ((uint16_t)0x1000) °GPIO_IDR_IDR13 ((uint16_t)0x2000) ±GPIO_IDR_IDR14 ((uint16_t)0x4000) ²GPIO_IDR_IDR15 ((uint16_t)0x8000) µGPIO_ODR_ODR0 ((uint16_t)0x0001) ¶GPIO_ODR_ODR1 ((uint16_t)0x0002) ·GPIO_ODR_ODR2 ((uint16_t)0x0004) ¸GPIO_ODR_ODR3 ((uint16_t)0x0008) ¹GPIO_ODR_ODR4 ((uint16_t)0x0010) ºGPIO_ODR_ODR5 ((uint16_t)0x0020) »GPIO_ODR_ODR6 ((uint16_t)0x0040) ¼GPIO_ODR_ODR7 ((uint16_t)0x0080) ½GPIO_ODR_ODR8 ((uint16_t)0x0100) ¾GPIO_ODR_ODR9 ((uint16_t)0x0200) ¿GPIO_ODR_ODR10 ((uint16_t)0x0400) ÀGPIO_ODR_ODR11 ((uint16_t)0x0800) ÁGPIO_ODR_ODR12 ((uint16_t)0x1000) ÂGPIO_ODR_ODR13 ((uint16_t)0x2000) ÃGPIO_ODR_ODR14 ((uint16_t)0x4000) ÄGPIO_ODR_ODR15 ((uint16_t)0x8000) ÇGPIO_BSRR_BS0 ((uint32_t)0x00000001) ÈGPIO_BSRR_BS1 ((uint32_t)0x00000002) ÉGPIO_BSRR_BS2 ((uint32_t)0x00000004) ÊGPIO_BSRR_BS3 ((uint32_t)0x00000008) ËGPIO_BSRR_BS4 ((uint32_t)0x00000010) ÌGPIO_BSRR_BS5 ((uint32_t)0x00000020) ÍGPIO_BSRR_BS6 ((uint32_t)0x00000040) ÎGPIO_BSRR_BS7 ((uint32_t)0x00000080) ÏGPIO_BSRR_BS8 ((uint32_t)0x00000100) ÐGPIO_BSRR_BS9 ((uint32_t)0x00000200) ÑGPIO_BSRR_BS10 ((uint32_t)0x00000400) ÒGPIO_BSRR_BS11 ((uint32_t)0x00000800) ÓGPIO_BSRR_BS12 ((uint32_t)0x00001000) ÔGPIO_BSRR_BS13 ((uint32_t)0x00002000) ÕGPIO_BSRR_BS14 ((uint32_t)0x00004000) ÖGPIO_BSRR_BS15 ((uint32_t)0x00008000) ØGPIO_BSRR_BR0 ((uint32_t)0x00010000) ÙGPIO_BSRR_BR1 ((uint32_t)0x00020000) ÚGPIO_BSRR_BR2 ((uint32_t)0x00040000) ÛGPIO_BSRR_BR3 ((uint32_t)0x00080000) ÜGPIO_BSRR_BR4 ((uint32_t)0x00100000) ÝGPIO_BSRR_BR5 ((uint32_t)0x00200000) ÞGPIO_BSRR_BR6 ((uint32_t)0x00400000) ßGPIO_BSRR_BR7 ((uint32_t)0x00800000) àGPIO_BSRR_BR8 ((uint32_t)0x01000000) áGPIO_BSRR_BR9 ((uint32_t)0x02000000) âGPIO_BSRR_BR10 ((uint32_t)0x04000000) ãGPIO_BSRR_BR11 ((uint32_t)0x08000000) äGPIO_BSRR_BR12 ((uint32_t)0x10000000) åGPIO_BSRR_BR13 ((uint32_t)0x20000000) æGPIO_BSRR_BR14 ((uint32_t)0x40000000) çGPIO_BSRR_BR15 ((uint32_t)0x80000000) êGPIO_BRR_BR0 ((uint16_t)0x0001) ëGPIO_BRR_BR1 ((uint16_t)0x0002) ìGPIO_BRR_BR2 ((uint16_t)0x0004) íGPIO_BRR_BR3 ((uint16_t)0x0008) îGPIO_BRR_BR4 ((uint16_t)0x0010) ïGPIO_BRR_BR5 ((uint16_t)0x0020) ðGPIO_BRR_BR6 ((uint16_t)0x0040) ñGPIO_BRR_BR7 ((uint16_t)0x0080) òGPIO_BRR_BR8 ((uint16_t)0x0100) óGPIO_BRR_BR9 ((uint16_t)0x0200) ôGPIO_BRR_BR10 ((uint16_t)0x0400) õGPIO_BRR_BR11 ((uint16_t)0x0800) öGPIO_BRR_BR12 ((uint16_t)0x1000) ÷GPIO_BRR_BR13 ((uint16_t)0x2000) øGPIO_BRR_BR14 ((uint16_t)0x4000) ùGPIO_BRR_BR15 ((uint16_t)0x8000) üGPIO_LCKR_LCK0 ((uint32_t)0x00000001) ýGPIO_LCKR_LCK1 ((uint32_t)0x00000002) þGPIO_LCKR_LCK2 ((uint32_t)0x00000004) ÿGPIO_LCKR_LCK3 ((uint32_t)0x00000008) GPIO_LCKR_LCK4 ((uint32_t)0x00000010) GPIO_LCKR_LCK5 ((uint32_t)0x00000020) GPIO_LCKR_LCK6 ((uint32_t)0x00000040) GPIO_LCKR_LCK7 ((uint32_t)0x00000080) GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
GPIO_LCKR_LCK9 ((uint32_t)0x00000200) GPIO_LCKR_LCK10 ((uint32_t)0x00000400) GPIO_LCKR_LCK11 ((uint32_t)0x00000800) GPIO_LCKR_LCK12 ((uint32_t)0x00001000) GPIO_LCKR_LCK13 ((uint32_t)0x00002000) GPIO_LCKR_LCK14 ((uint32_t)0x00004000) GPIO_LCKR_LCK15 ((uint32_t)0x00008000) GPIO_LCKR_LCKK ((uint32_t)0x00010000) AFIO_EVCR_PIN ((uint8_t)0x0F) AFIO_EVCR_PIN_0 ((uint8_t)0x01) AFIO_EVCR_PIN_1 ((uint8_t)0x02) AFIO_EVCR_PIN_2 ((uint8_t)0x04) AFIO_EVCR_PIN_3 ((uint8_t)0x08) AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) ¡AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) ¢AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) £AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) ¤AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) ¥AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) ¦AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) §AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) ©AFIO_EVCR_PORT ((uint8_t)0x70) ªAFIO_EVCR_PORT_0 ((uint8_t)0x10) «AFIO_EVCR_PORT_1 ((uint8_t)0x20) ¬AFIO_EVCR_PORT_2 ((uint8_t)0x40) ¯AFIO_EVCR_PORT_PA ((uint8_t)0x00) °AFIO_EVCR_PORT_PB ((uint8_t)0x10) ±AFIO_EVCR_PORT_PC ((uint8_t)0x20) ²AFIO_EVCR_PORT_PD ((uint8_t)0x30) ³AFIO_EVCR_PORT_PE ((uint8_t)0x40) µAFIO_EVCR_EVOE ((uint8_t)0x80) ¸AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) ¹AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) ºAFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) »AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) ½AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) ¾AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) ¿AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) ÂAFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) ÃAFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) ÄAFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) ÆAFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) ÇAFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) ÈAFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) ËAFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) ÌAFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) ÍAFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) ÏAFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) ÐAFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) ÑAFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) ÔAFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) ÕAFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) ÖAFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) ×AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) ÙAFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) ÚAFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) ÛAFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) ÞAFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) ßAFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) àAFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) âAFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) äAFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) åAFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) æAFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) éAFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) êAFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) ëAFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) íAFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) îAFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) ïAFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) ðAFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) ñAFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) òAFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) õAFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) öAFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) ÷AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) øAFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) úAFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) ûAFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) üAFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) ýAFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) £AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) ¤AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) ¥AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) ¦AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) §AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) ¨AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) ©AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) ¬AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) ®AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) ¯AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) °AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) ±AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) ²AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) µAFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) ¶AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) ·AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) ¸AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) ¹AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) ºAFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) »AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) ¾AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) ¿AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) ÀAFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) ÁAFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) ÄAFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) ÅAFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) ÆAFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) ÇAFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) ÈAFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) ÉAFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) ÊAFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) ÍAFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) ÎAFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) ÏAFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) ÐAFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) ÑAFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) ÒAFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) ÓAFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) ÖAFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) ×AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) ØAFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) ÙAFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) ÚAFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) ÛAFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) ÜAFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) ßAFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) àAFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) áAFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) âAFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) ãAFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) äAFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) åAFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) èAFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) éAFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) êAFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) ëAFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) îAFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) ïAFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) ðAFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) ñAFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) òAFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) óAFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) ôAFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) ÷AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) øAFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) ùAFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) úAFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) ûAFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) üAFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) ýAFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) ¡AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) ¢AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) £AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) ¤AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) ¥AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) ¦AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) §AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) ªAFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) «AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) ¬AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) ®AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) ¯AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) °AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) ³AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) ´AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) µAFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) ¶AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) ·AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) ¸AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) ¹AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) ÞSysTick_CTRL_ENABLE ((uint32_t)0x00000001) ßSysTick_CTRL_TICKINT ((uint32_t)0x00000002) àSysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) áSysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) äSysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) çSysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) êSysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) ëSysTick_CALIB_SKEW ((uint32_t)0x40000000) ìSysTick_CALIB_NOREF ((uint32_t)0x80000000) õNVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) öNVIC_ISER_SETENA_0 ((uint32_t)0x00000001) ÷NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) øNVIC_ISER_SETENA_2 ((uint32_t)0x00000004) ùNVIC_ISER_SETENA_3 ((uint32_t)0x00000008) úNVIC_ISER_SETENA_4 ((uint32_t)0x00000010) ûNVIC_ISER_SETENA_5 ((uint32_t)0x00000020) üNVIC_ISER_SETENA_6 ((uint32_t)0x00000040) ýNVIC_ISER_SETENA_7 ((uint32_t)0x00000080) þNVIC_ISER_SETENA_8 ((uint32_t)0x00000100) ÿNVIC_ISER_SETENA_9 ((uint32_t)0x00000200) NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) NVIC_ISER_SETENA_14 ((uint32_t)0x00004000)
NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) ¡NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) ¢NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) £NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) ¤NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) ¥NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) ¦NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) §NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) ¨NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) ©NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) ªNVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) «NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) ¬NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) ®NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) ¯NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) °NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) ±NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) ²NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) ³NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) ´NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) µNVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) ¶NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) ·NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) ¸NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) »NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) ¼NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) ½NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) ¾NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) ¿NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) ÀNVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) ÁNVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) ÂNVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) ÃNVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) ÄNVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) ÅNVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) ÆNVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) ÇNVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) ÈNVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) ÉNVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) ÊNVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) ËNVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) ÌNVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) ÍNVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) ÎNVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) ÏNVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) ÐNVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) ÑNVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) ÒNVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) ÓNVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) ÔNVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) ÕNVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) ÖNVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) ×NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) ØNVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) ÙNVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) ÚNVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) ÛNVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) ÞNVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) ßNVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) àNVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) áNVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) âNVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) ãNVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) äNVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) åNVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) æNVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) çNVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) èNVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) éNVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) êNVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) ëNVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) ìNVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) íNVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) îNVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) ïNVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) ðNVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) ñNVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) òNVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) óNVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) ôNVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) õNVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) öNVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) ÷NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) øNVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) ùNVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) úNVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) ûNVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) üNVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) ýNVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) þNVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004)
NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) ¡NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) ¤NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) ¥NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) ¦NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) §NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) ªNVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) «NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) ¬NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) °NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) ±NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) ²NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) ³NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) ¶NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) ·NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) ¸NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) ¹NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) ¼NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) ½NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) ¾NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) ¿NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) ÂNVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) ÃNVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) ÄNVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) ÅNVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) ÈNVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) ÉNVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) ÊNVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) ËNVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) ÎNVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) ÏNVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) ÐNVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) ÑNVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) ÔSCB_CPUID_REVISION ((uint32_t)0x0000000F) ÕSCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) ÖSCB_CPUID_Constant ((uint32_t)0x000F0000) ×SCB_CPUID_VARIANT ((uint32_t)0x00F00000) ØSCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) ÛSCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) ÜSCB_ICSR_RETTOBASE ((uint32_t)0x00000800) ÝSCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) ÞSCB_ICSR_ISRPENDING ((uint32_t)0x00400000) ßSCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) àSCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) áSCB_ICSR_PENDSTSET ((uint32_t)0x04000000) âSCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) ãSCB_ICSR_PENDSVSET ((uint32_t)0x10000000) äSCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) çSCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) èSCB_VTOR_TBLBASE ((uint32_t)0x20000000) ëSCB_AIRCR_VECTRESET ((uint32_t)0x00000001) ìSCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) íSCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) ïSCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) ðSCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) ñSCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) òSCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) õSCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) öSCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) ÷SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) øSCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) ùSCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) úSCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) ûSCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) üSCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) þSCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) ÿSCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) SCB_SCR_SLEEPDEEP ((uint8_t)0x04) SCB_SCR_SEVONPEND ((uint8_t)0x10) SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) SCB_CCR_USERSETMPEND ((uint16_t)0x0002) SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) SCB_CCR_STKALIGN ((uint16_t)0x0200) SCB_SHPR_PRI_N ((uint32_t)0x000000FF) SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) ¡SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) ¢SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) ¦SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) §SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) ¨SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) ©SCB_CFSR_MSTKERR ((uint32_t)0x00000010) ªSCB_CFSR_MMARVALID ((uint32_t)0x00000080) ¬SCB_CFSR_IBUSERR ((uint32_t)0x00000100) SCB_CFSR_PRECISERR ((uint32_t)0x00000200) ®SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) ¯SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) °SCB_CFSR_STKERR ((uint32_t)0x00001000) ±SCB_CFSR_BFARVALID ((uint32_t)0x00008000) ³SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) ´SCB_CFSR_INVSTATE ((uint32_t)0x00020000) µSCB_CFSR_INVPC ((uint32_t)0x00040000) ¶SCB_CFSR_NOCP ((uint32_t)0x00080000) ·SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) ¸SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) »SCB_HFSR_VECTTBL ((uint32_t)0x00000002) ¼SCB_HFSR_FORCED ((uint32_t)0x40000000) ½SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) ÀSCB_DFSR_HALTED ((uint8_t)0x01) ÁSCB_DFSR_BKPT ((uint8_t)0x02) ÂSCB_DFSR_DWTTRAP ((uint8_t)0x04) ÃSCB_DFSR_VCATCH ((uint8_t)0x08) ÄSCB_DFSR_EXTERNAL ((uint8_t)0x10) ÇSCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) ÊSCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) ÍSCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) ÖEXTI_IMR_MR0 ((uint32_t)0x00000001) ×EXTI_IMR_MR1 ((uint32_t)0x00000002) ØEXTI_IMR_MR2 ((uint32_t)0x00000004) ÙEXTI_IMR_MR3 ((uint32_t)0x00000008) ÚEXTI_IMR_MR4 ((uint32_t)0x00000010) ÛEXTI_IMR_MR5 ((uint32_t)0x00000020) ÜEXTI_IMR_MR6 ((uint32_t)0x00000040) ÝEXTI_IMR_MR7 ((uint32_t)0x00000080) ÞEXTI_IMR_MR8 ((uint32_t)0x00000100) ßEXTI_IMR_MR9 ((uint32_t)0x00000200) àEXTI_IMR_MR10 ((uint32_t)0x00000400) áEXTI_IMR_MR11 ((uint32_t)0x00000800) âEXTI_IMR_MR12 ((uint32_t)0x00001000) ãEXTI_IMR_MR13 ((uint32_t)0x00002000) äEXTI_IMR_MR14 ((uint32_t)0x00004000) åEXTI_IMR_MR15 ((uint32_t)0x00008000) æEXTI_IMR_MR16 ((uint32_t)0x00010000) çEXTI_IMR_MR17 ((uint32_t)0x00020000) èEXTI_IMR_MR18 ((uint32_t)0x00040000) éEXTI_IMR_MR19 ((uint32_t)0x00080000) ìEXTI_EMR_MR0 ((uint32_t)0x00000001) íEXTI_EMR_MR1 ((uint32_t)0x00000002) îEXTI_EMR_MR2 ((uint32_t)0x00000004) ïEXTI_EMR_MR3 ((uint32_t)0x00000008) ðEXTI_EMR_MR4 ((uint32_t)0x00000010) ñEXTI_EMR_MR5 ((uint32_t)0x00000020) òEXTI_EMR_MR6 ((uint32_t)0x00000040) óEXTI_EMR_MR7 ((uint32_t)0x00000080) ôEXTI_EMR_MR8 ((uint32_t)0x00000100) õEXTI_EMR_MR9 ((uint32_t)0x00000200) öEXTI_EMR_MR10 ((uint32_t)0x00000400) ÷EXTI_EMR_MR11 ((uint32_t)0x00000800) øEXTI_EMR_MR12 ((uint32_t)0x00001000) ùEXTI_EMR_MR13 ((uint32_t)0x00002000) úEXTI_EMR_MR14 ((uint32_t)0x00004000) ûEXTI_EMR_MR15 ((uint32_t)0x00008000) üEXTI_EMR_MR16 ((uint32_t)0x00010000) ýEXTI_EMR_MR17 ((uint32_t)0x00020000) þEXTI_EMR_MR18 ((uint32_t)0x00040000) ÿEXTI_EMR_MR19 ((uint32_t)0x00080000) EXTI_RTSR_TR0 ((uint32_t)0x00000001) EXTI_RTSR_TR1 ((uint32_t)0x00000002) EXTI_RTSR_TR2 ((uint32_t)0x00000004)
EXTI_RTSR_TR3 ((uint32_t)0x00000008) EXTI_RTSR_TR4 ((uint32_t)0x00000010) EXTI_RTSR_TR5 ((uint32_t)0x00000020) EXTI_RTSR_TR6 ((uint32_t)0x00000040) EXTI_RTSR_TR7 ((uint32_t)0x00000080) EXTI_RTSR_TR8 ((uint32_t)0x00000100) EXTI_RTSR_TR9 ((uint32_t)0x00000200) EXTI_RTSR_TR10 ((uint32_t)0x00000400) EXTI_RTSR_TR11 ((uint32_t)0x00000800) EXTI_RTSR_TR12 ((uint32_t)0x00001000) EXTI_RTSR_TR13 ((uint32_t)0x00002000) EXTI_RTSR_TR14 ((uint32_t)0x00004000) EXTI_RTSR_TR15 ((uint32_t)0x00008000) EXTI_RTSR_TR16 ((uint32_t)0x00010000) EXTI_RTSR_TR17 ((uint32_t)0x00020000) EXTI_RTSR_TR18 ((uint32_t)0x00040000) EXTI_RTSR_TR19 ((uint32_t)0x00080000) EXTI_FTSR_TR0 ((uint32_t)0x00000001) EXTI_FTSR_TR1 ((uint32_t)0x00000002) EXTI_FTSR_TR2 ((uint32_t)0x00000004) EXTI_FTSR_TR3 ((uint32_t)0x00000008) EXTI_FTSR_TR4 ((uint32_t)0x00000010) EXTI_FTSR_TR5 ((uint32_t)0x00000020) EXTI_FTSR_TR6 ((uint32_t)0x00000040) EXTI_FTSR_TR7 ((uint32_t)0x00000080) EXTI_FTSR_TR8 ((uint32_t)0x00000100) ¡EXTI_FTSR_TR9 ((uint32_t)0x00000200) ¢EXTI_FTSR_TR10 ((uint32_t)0x00000400) £EXTI_FTSR_TR11 ((uint32_t)0x00000800) ¤EXTI_FTSR_TR12 ((uint32_t)0x00001000) ¥EXTI_FTSR_TR13 ((uint32_t)0x00002000) ¦EXTI_FTSR_TR14 ((uint32_t)0x00004000) §EXTI_FTSR_TR15 ((uint32_t)0x00008000) ¨EXTI_FTSR_TR16 ((uint32_t)0x00010000) ©EXTI_FTSR_TR17 ((uint32_t)0x00020000) ªEXTI_FTSR_TR18 ((uint32_t)0x00040000) «EXTI_FTSR_TR19 ((uint32_t)0x00080000) ®EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) ¯EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) °EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) ±EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) ²EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) ³EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) ´EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) µEXTI_SWIER_SWIER7 ((uint32_t)0x00000080) ¶EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) ·EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) ¸EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) ¹EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) ºEXTI_SWIER_SWIER12 ((uint32_t)0x00001000) »EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) ¼EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) ½EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) ¾EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) ¿EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) ÀEXTI_SWIER_SWIER18 ((uint32_t)0x00040000) ÁEXTI_SWIER_SWIER19 ((uint32_t)0x00080000) ÄEXTI_PR_PR0 ((uint32_t)0x00000001) ÅEXTI_PR_PR1 ((uint32_t)0x00000002) ÆEXTI_PR_PR2 ((uint32_t)0x00000004) ÇEXTI_PR_PR3 ((uint32_t)0x00000008) ÈEXTI_PR_PR4 ((uint32_t)0x00000010) ÉEXTI_PR_PR5 ((uint32_t)0x00000020) ÊEXTI_PR_PR6 ((uint32_t)0x00000040) ËEXTI_PR_PR7 ((uint32_t)0x00000080) ÌEXTI_PR_PR8 ((uint32_t)0x00000100) ÍEXTI_PR_PR9 ((uint32_t)0x00000200) ÎEXTI_PR_PR10 ((uint32_t)0x00000400) ÏEXTI_PR_PR11 ((uint32_t)0x00000800) ÐEXTI_PR_PR12 ((uint32_t)0x00001000) ÑEXTI_PR_PR13 ((uint32_t)0x00002000) ÒEXTI_PR_PR14 ((uint32_t)0x00004000) ÓEXTI_PR_PR15 ((uint32_t)0x00008000) ÔEXTI_PR_PR16 ((uint32_t)0x00010000) ÕEXTI_PR_PR17 ((uint32_t)0x00020000) ÖEXTI_PR_PR18 ((uint32_t)0x00040000) ×EXTI_PR_PR19 ((uint32_t)0x00080000) àDMA_ISR_GIF1 ((uint32_t)0x00000001) áDMA_ISR_TCIF1 ((uint32_t)0x00000002) âDMA_ISR_HTIF1 ((uint32_t)0x00000004) ãDMA_ISR_TEIF1 ((uint32_t)0x00000008) äDMA_ISR_GIF2 ((uint32_t)0x00000010) åDMA_ISR_TCIF2 ((uint32_t)0x00000020) æDMA_ISR_HTIF2 ((uint32_t)0x00000040) çDMA_ISR_TEIF2 ((uint32_t)0x00000080) èDMA_ISR_GIF3 ((uint32_t)0x00000100) éDMA_ISR_TCIF3 ((uint32_t)0x00000200) êDMA_ISR_HTIF3 ((uint32_t)0x00000400) ëDMA_ISR_TEIF3 ((uint32_t)0x00000800) ìDMA_ISR_GIF4 ((uint32_t)0x00001000) íDMA_ISR_TCIF4 ((uint32_t)0x00002000) îDMA_ISR_HTIF4 ((uint32_t)0x00004000) ïDMA_ISR_TEIF4 ((uint32_t)0x00008000) ðDMA_ISR_GIF5 ((uint32_t)0x00010000) ñDMA_ISR_TCIF5 ((uint32_t)0x00020000) òDMA_ISR_HTIF5 ((uint32_t)0x00040000) óDMA_ISR_TEIF5 ((uint32_t)0x00080000) ôDMA_ISR_GIF6 ((uint32_t)0x00100000) õDMA_ISR_TCIF6 ((uint32_t)0x00200000) öDMA_ISR_HTIF6 ((uint32_t)0x00400000) ÷DMA_ISR_TEIF6 ((uint32_t)0x00800000) øDMA_ISR_GIF7 ((uint32_t)0x01000000) ùDMA_ISR_TCIF7 ((uint32_t)0x02000000) úDMA_ISR_HTIF7 ((uint32_t)0x04000000) ûDMA_ISR_TEIF7 ((uint32_t)0x08000000) þDMA_IFCR_CGIF1 ((uint32_t)0x00000001) ÿDMA_IFCR_CTCIF1 ((uint32_t)0x00000002) DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) DMA_IFCR_CGIF2 ((uint32_t)0x00000010) DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) DMA_IFCR_CHTIF2 ((uint32_t)0x00000040)
DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) DMA_IFCR_CGIF3 ((uint32_t)0x00000100) DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) DMA_IFCR_CGIF4 ((uint32_t)0x00001000) DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) DMA_IFCR_CGIF5 ((uint32_t)0x00010000) DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) DMA_IFCR_CGIF6 ((uint32_t)0x00100000) DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) DMA_IFCR_CGIF7 ((uint32_t)0x01000000) DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) DMA_CCR1_EN ((uint16_t)0x0001) DMA_CCR1_TCIE ((uint16_t)0x0002) DMA_CCR1_HTIE ((uint16_t)0x0004) DMA_CCR1_TEIE ((uint16_t)0x0008) DMA_CCR1_DIR ((uint16_t)0x0010) ¡DMA_CCR1_CIRC ((uint16_t)0x0020) ¢DMA_CCR1_PINC ((uint16_t)0x0040) £DMA_CCR1_MINC ((uint16_t)0x0080) ¥DMA_CCR1_PSIZE ((uint16_t)0x0300) ¦DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) §DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) ©DMA_CCR1_MSIZE ((uint16_t)0x0C00) ªDMA_CCR1_MSIZE_0 ((uint16_t)0x0400) «DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) DMA_CCR1_PL ((uint16_t)0x3000) ®DMA_CCR1_PL_0 ((uint16_t)0x1000) ¯DMA_CCR1_PL_1 ((uint16_t)0x2000) ±DMA_CCR1_MEM2MEM ((uint16_t)0x4000) ´DMA_CCR2_EN ((uint16_t)0x0001) µDMA_CCR2_TCIE ((uint16_t)0x0002) ¶DMA_CCR2_HTIE ((uint16_t)0x0004) ·DMA_CCR2_TEIE ((uint16_t)0x0008) ¸DMA_CCR2_DIR ((uint16_t)0x0010) ¹DMA_CCR2_CIRC ((uint16_t)0x0020) ºDMA_CCR2_PINC ((uint16_t)0x0040) »DMA_CCR2_MINC ((uint16_t)0x0080) ½DMA_CCR2_PSIZE ((uint16_t)0x0300) ¾DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) ¿DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) ÁDMA_CCR2_MSIZE ((uint16_t)0x0C00) ÂDMA_CCR2_MSIZE_0 ((uint16_t)0x0400) ÃDMA_CCR2_MSIZE_1 ((uint16_t)0x0800) ÅDMA_CCR2_PL ((uint16_t)0x3000) ÆDMA_CCR2_PL_0 ((uint16_t)0x1000) ÇDMA_CCR2_PL_1 ((uint16_t)0x2000) ÉDMA_CCR2_MEM2MEM ((uint16_t)0x4000) ÌDMA_CCR3_EN ((uint16_t)0x0001) ÍDMA_CCR3_TCIE ((uint16_t)0x0002) ÎDMA_CCR3_HTIE ((uint16_t)0x0004) ÏDMA_CCR3_TEIE ((uint16_t)0x0008) ÐDMA_CCR3_DIR ((uint16_t)0x0010) ÑDMA_CCR3_CIRC ((uint16_t)0x0020) ÒDMA_CCR3_PINC ((uint16_t)0x0040) ÓDMA_CCR3_MINC ((uint16_t)0x0080) ÕDMA_CCR3_PSIZE ((uint16_t)0x0300) ÖDMA_CCR3_PSIZE_0 ((uint16_t)0x0100) ×DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) ÙDMA_CCR3_MSIZE ((uint16_t)0x0C00) ÚDMA_CCR3_MSIZE_0 ((uint16_t)0x0400) ÛDMA_CCR3_MSIZE_1 ((uint16_t)0x0800) ÝDMA_CCR3_PL ((uint16_t)0x3000) ÞDMA_CCR3_PL_0 ((uint16_t)0x1000) ßDMA_CCR3_PL_1 ((uint16_t)0x2000) áDMA_CCR3_MEM2MEM ((uint16_t)0x4000) äDMA_CCR4_EN ((uint16_t)0x0001) åDMA_CCR4_TCIE ((uint16_t)0x0002) æDMA_CCR4_HTIE ((uint16_t)0x0004) çDMA_CCR4_TEIE ((uint16_t)0x0008) èDMA_CCR4_DIR ((uint16_t)0x0010) éDMA_CCR4_CIRC ((uint16_t)0x0020) êDMA_CCR4_PINC ((uint16_t)0x0040) ëDMA_CCR4_MINC ((uint16_t)0x0080) íDMA_CCR4_PSIZE ((uint16_t)0x0300) îDMA_CCR4_PSIZE_0 ((uint16_t)0x0100) ïDMA_CCR4_PSIZE_1 ((uint16_t)0x0200) ñDMA_CCR4_MSIZE ((uint16_t)0x0C00) òDMA_CCR4_MSIZE_0 ((uint16_t)0x0400) óDMA_CCR4_MSIZE_1 ((uint16_t)0x0800) õDMA_CCR4_PL ((uint16_t)0x3000) öDMA_CCR4_PL_0 ((uint16_t)0x1000) ÷DMA_CCR4_PL_1 ((uint16_t)0x2000) ùDMA_CCR4_MEM2MEM ((uint16_t)0x4000) üDMA_CCR5_EN ((uint16_t)0x0001) ýDMA_CCR5_TCIE ((uint16_t)0x0002) þDMA_CCR5_HTIE ((uint16_t)0x0004) ÿDMA_CCR5_TEIE ((uint16_t)0x0008) DMA_CCR5_DIR ((uint16_t)0x0010) DMA_CCR5_CIRC ((uint16_t)0x0020) DMA_CCR5_PINC ((uint16_t)0x0040) DMA_CCR5_MINC ((uint16_t)0x0080)
DMA_CCR5_PSIZE ((uint16_t)0x0300) DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) DMA_CCR5_MSIZE ((uint16_t)0x0C00) DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) DMA_CCR5_PL ((uint16_t)0x3000) DMA_CCR5_PL_0 ((uint16_t)0x1000) DMA_CCR5_PL_1 ((uint16_t)0x2000) DMA_CCR5_MEM2MEM ((uint16_t)0x4000) DMA_CCR6_EN ((uint16_t)0x0001) DMA_CCR6_TCIE ((uint16_t)0x0002) DMA_CCR6_HTIE ((uint16_t)0x0004) DMA_CCR6_TEIE ((uint16_t)0x0008) DMA_CCR6_DIR ((uint16_t)0x0010) DMA_CCR6_CIRC ((uint16_t)0x0020) DMA_CCR6_PINC ((uint16_t)0x0040) DMA_CCR6_MINC ((uint16_t)0x0080) DMA_CCR6_PSIZE ((uint16_t)0x0300) DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) ¡ DMA_CCR6_MSIZE ((uint16_t)0x0C00) ¢ DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) £ DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) ¥ DMA_CCR6_PL ((uint16_t)0x3000) ¦ DMA_CCR6_PL_0 ((uint16_t)0x1000) § DMA_CCR6_PL_1 ((uint16_t)0x2000) © DMA_CCR6_MEM2MEM ((uint16_t)0x4000) ¬ DMA_CCR7_EN ((uint16_t)0x0001) DMA_CCR7_TCIE ((uint16_t)0x0002) ® DMA_CCR7_HTIE ((uint16_t)0x0004) ¯ DMA_CCR7_TEIE ((uint16_t)0x0008) ° DMA_CCR7_DIR ((uint16_t)0x0010) ± DMA_CCR7_CIRC ((uint16_t)0x0020) ² DMA_CCR7_PINC ((uint16_t)0x0040) ³ DMA_CCR7_MINC ((uint16_t)0x0080) µ DMA_CCR7_PSIZE , ((uint16_t)0x0300) ¶ DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) · DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) ¹ DMA_CCR7_MSIZE ((uint16_t)0x0C00) º DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) » DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) ½ DMA_CCR7_PL ((uint16_t)0x3000) ¾ DMA_CCR7_PL_0 ((uint16_t)0x1000) ¿ DMA_CCR7_PL_1 ((uint16_t)0x2000) Á DMA_CCR7_MEM2MEM ((uint16_t)0x4000) Ä DMA_CNDTR1_NDT ((uint16_t)0xFFFF) Ç DMA_CNDTR2_NDT ((uint16_t)0xFFFF) Ê DMA_CNDTR3_NDT ((uint16_t)0xFFFF) Í DMA_CNDTR4_NDT ((uint16_t)0xFFFF) Ð DMA_CNDTR5_NDT ((uint16_t)0xFFFF) Ó DMA_CNDTR6_NDT ((uint16_t)0xFFFF) Ö DMA_CNDTR7_NDT ((uint16_t)0xFFFF) Ù DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) Ü DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) ß DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) ã DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) æ DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) é DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) í DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) ð DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) ó DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) ö DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) ú DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) ý DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) ADC_SR_AWD ((uint8_t)0x01) ADC_SR_EOC ((uint8_t)0x02) ADC_SR_JEOC ((uint8_t)0x04) ADC_SR_JSTRT ((uint8_t)0x08) ADC_SR_STRT ((uint8_t)0x10) ADC_CR1_AWDCH ((uint32_t)0x0000001F) ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) ADC_CR1_EOCIE ((uint32_t)0x00000020) ADC_CR1_AWDIE ((uint32_t)0x00000040) ADC_CR1_JEOCIE ((uint32_t)0x00000080) ADC_CR1_SCAN ((uint32_t)0x00000100) ADC_CR1_AWDSGL ((uint32_t)0x00000200) ADC_CR1_JAUTO ((uint32_t)0x00000400) ADC_CR1_DISCEN ((uint32_t)0x00000800) ¡ ADC_CR1_JDISCEN ((uint32_t)0x00001000) £ ADC_CR1_DISCNUM ((uint32_t)0x0000E000) ¤ ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) ¥ ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) ¦ ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) ¨ ADC_CR1_DUALMOD ((uint32_t)0x000F0000) © ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) ª ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) « ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) ¬ ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) ® ADC_CR1_JAWDEN ((uint32_t)0x00400000) ¯ ADC_CR1_AWDEN ((uint32_t)0x00800000) ³ ADC_CR2_ADON ((uint32_t)0x00000001) ´ ADC_CR2_CONT ((uint32_t)0x00000002) µ ADC_CR2_CAL ((uint32_t)0x00000004) ¶ ADC_CR2_RSTCAL ((uint32_t)0x00000008) · ADC_CR2_DMA ((uint32_t)0x00000100) ¸ ADC_CR2_ALIGN ((uint32_t)0x00000800) º ADC_CR2_JEXTSEL ((uint32_t)0x00007000) » ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) ¼ ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) ½ ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) ¿ ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) Á ADC_CR2_EXTSEL ((uint32_t)0x000E0000) Â ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) Ã ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) Ä ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) Æ ADC_CR2_EXTTRIG ((uint32_t)0x00100000) Ç ADC_CR2_JSWSTART ((uint32_t)0x00200000) È ADC_CR2_SWSTART ((uint32_t)0x00400000) É ADC_CR2_TSVREFE ((uint32_t)0x00800000) Ì ADC_SMPR1_SMP10 ((uint32_t)0x00000007) Í ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) Î ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) Ï ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) Ñ ADC_SMPR1_SMP11 ((uint32_t)0x00000038) Ò ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) Ó ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) Ô ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) Ö ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) × ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) Ø ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) Ù ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) Û ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) Ü ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) Ý ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) Þ ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) à ADC_SMPR1_SMP14 ((uint32_t)0x00007000) á ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) â ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) ã ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) å ADC_SMPR1_SMP15 ((uint32_t)0x00038000) æ ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) ç ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) è ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) ê ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) ë ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) ì ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) í ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) ï ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) ð ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) ñ ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) ò ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) õ ADC_SMPR2_SMP0 ((uint32_t)0x00000007) ö ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) ÷ ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) ø ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) ú ADC_SMPR2_SMP1 ((uint32_t)0x00000038) û ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) ü ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) ý ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) ÿ ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) ADC_SMPR2_SMP4 ((uint32_t)0x00007000) ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) ADC_SMPR2_SMP5 ((uint32_t)0x00038000) ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) ADC_SMPR2_SMP8 ((uint32_t)0x07000000) ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) ¢ ADC_SMPR2_SMP9 ((uint32_t)0x38000000) £ ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) ¤ ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) ¥ ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) ¨ ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) « ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) ® ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) ± ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) ´ ADC_HTR_HT ((uint16_t)0x0FFF) · ADC_LTR_LT ((uint16_t)0x0FFF) º ADC_SQR1_SQ13 ((uint32_t)0x0000001F) » ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) ¼ ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) ½ ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) ¾ ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) ¿ ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) Á ADC_SQR1_SQ14 ((uint32_t)0x000003E0) Â ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) Ã ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) Ä ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) Å ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) Æ ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) È ADC_SQR1_SQ15 ((uint32_t)0x00007C00) É ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) Ê ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) Ë ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) Ì ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) Í ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) Ï ADC_SQR1_SQ16 ((uint32_t)0x000F8000) Ð ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) Ñ ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) Ò ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) Ó ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) Ô ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) Ö ADC_SQR1_L ((uint32_t)0x00F00000) × ADC_SQR1_L_0 ((uint32_t)0x00100000) Ø ADC_SQR1_L_1 ((uint32_t)0x00200000) Ù ADC_SQR1_L_2 ((uint32_t)0x00400000) Ú ADC_SQR1_L_3 ((uint32_t)0x00800000) Ý ADC_SQR2_SQ7 ((uint32_t)0x0000001F) Þ ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) ß ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) à ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) á ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) â ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) ä ADC_SQR2_SQ8 ((uint32_t)0x000003E0) å ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) æ ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) ç ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) è ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) é ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) ë ADC_SQR2_SQ9 ((uint32_t)0x00007C00) ì ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) í ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) î ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) ï ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) ð ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) ò ADC_SQR2_SQ10 ((uint32_t)0x000F8000) ó ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) ô ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) õ ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) ö ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) ÷ ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) ù ADC_SQR2_SQ11 ((uint32_t)0x01F00000) ú ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) û ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) ü ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) ý ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) þ ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) ADC_SQR2_SQ12 ((uint32_t)0x3E000000) ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) ADC_SQR3_SQ1 ((uint32_t)0x0000001F) ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) ADC_SQR3_SQ2 ((uint32_t)0x000003E0) ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) ADC_SQR3_SQ3 ((uint32_t)0x00007C00) ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) ADC_SQR3_SQ4 ((uint32_t)0x000F8000) ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) ¡ ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) ¢ ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) ¤ ADC_SQR3_SQ5 ((uint32_t)0x01F00000) ¥ ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) ¦ ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) § ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) ¨ ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) © ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) « ADC_SQR3_SQ6 ((uint32_t)0x3E000000) ¬ ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) ® ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) ¯ ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) ° ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) ³ ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) ´ ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) µ ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) ¶ ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) · ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) ¸ ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) º ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) » ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) ¼ ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) ½ ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) ¾ ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) ¿ ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) Á ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) Â ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) Ã ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) Ä ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) Å ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) Æ ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) È ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) É ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) Ê ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) Ë ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) Ì ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) Í ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) Ï ADC_JSQR_JL ((uint32_t)0x00300000) Ð ADC_JSQR_JL_0 ((uint32_t)0x00100000) Ñ ADC_JSQR_JL_1 ((uint32_t)0x00200000) Ô ADC_JDR1_JDATA ((uint16_t)0xFFFF) × ADC_JDR2_JDATA ((uint16_t)0xFFFF) Ú ADC_JDR3_JDATA ((uint16_t)0xFFFF) Ý ADC_JDR4_JDATA ((uint16_t)0xFFFF) à ADC_DR_DATA ((uint32_t)0x0000FFFF) á ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) ê DAC_CR_EN1 ((uint32_t)0x00000001) ë DAC_CR_BOFF1 ((uint32_t)0x00000002) ì DAC_CR_TEN1 ((uint32_t)0x00000004) î DAC_CR_TSEL1 ((uint32_t)0x00000038) ï DAC_CR_TSEL1_0 ((uint32_t)0x00000008) ð DAC_CR_TSEL1_1 ((uint32_t)0x00000010) ñ DAC_CR_TSEL1_2 ((uint32_t)0x00000020) ó DAC_CR_WAVE1 ((uint32_t)0x000000C0) ô DAC_CR_WAVE1_0 ((uint32_t)0x00000040) õ DAC_CR_WAVE1_1 ((uint32_t)0x00000080) ÷ DAC_CR_MAMP1 ((uint32_t)0x00000F00) ø DAC_CR_MAMP1_0 ((uint32_t)0x00000100) ù DAC_CR_MAMP1_1 ((uint32_t)0x00000200) ú DAC_CR_MAMP1_2 ((uint32_t)0x00000400) û DAC_CR_MAMP1_3 ((uint32_t)0x00000800) ý DAC_CR_DMAEN1 ((uint32_t)0x00001000) þ DAC_CR_EN2 ((uint32_t)0x00010000) ÿ DAC_CR_BOFF2 ((uint32_t)0x00020000) DAC_CR_TEN2 ((uint32_t)0x00040000) DAC_CR_TSEL2 ((uint32_t)0x00380000) DAC_CR_TSEL2_0 ((uint32_t)0x00080000) DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
DAC_CR_TSEL2_2 ((uint32_t)0x00200000) DAC_CR_WAVE2 ((uint32_t)0x00C00000) DAC_CR_WAVE2_0 ((uint32_t)0x00400000) DAC_CR_WAVE2_1 ((uint32_t)0x00800000) DAC_CR_MAMP2 ((uint32_t)0x0F000000) DAC_CR_MAMP2_0 ((uint32_t)0x01000000) DAC_CR_MAMP2_1 ((uint32_t)0x02000000) DAC_CR_MAMP2_2 ((uint32_t)0x04000000) DAC_CR_MAMP2_3 ((uint32_t)0x08000000) DAC_CR_DMAEN2 ((uint32_t)0x10000000) DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) ¡ DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) ¤ DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) § DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) ª DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) « DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) ® DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) ¯ DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) ² DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) ³ DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) ¶ DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) ¹ DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) ¼ DAC_SR_DMAUDR1 ((uint32_t)0x00002000) ½ DAC_SR_DMAUDR2 ((uint32_t)0x20000000) Å CEC_CFGR_PE ((uint16_t)0x0001) Æ CEC_CFGR_IE ((uint16_t)0x0002) Ç CEC_CFGR_BTEM ((uint16_t)0x0004) È CEC_CFGR_BPEM ((uint16_t)0x0008) Ë CEC_OAR_OA ((uint16_t)0x000F) Ì CEC_OAR_OA_0 ((uint16_t)0x0001) Í CEC_OAR_OA_1 ((uint16_t)0x0002) Î CEC_OAR_OA_2 ((uint16_t)0x0004) Ï CEC_OAR_OA_3 ((uint16_t)0x0008) Ò CEC_PRES_PRES ((uint16_t)0x3FFF) Õ CEC_ESR_BTE ((uint16_t)0x0001) Ö CEC_ESR_BPE ((uint16_t)0x0002) × CEC_ESR_RBTFE ((uint16_t)0x0004) Ø CEC_ESR_SBE ((uint16_t)0x0008) Ù CEC_ESR_ACKE ((uint16_t)0x0010) Ú CEC_ESR_LINE ((uint16_t)0x0020) Û CEC_ESR_TBTFE ((uint16_t)0x0040) Þ CEC_CSR_TSOM ((uint16_t)0x0001) ß CEC_CSR_TEOM ((uint16_t)0x0002) à CEC_CSR_TERR ((uint16_t)0x0004) á CEC_CSR_TBTRF ((uint16_t)0x0008) â CEC_CSR_RSOM ((uint16_t)0x0010) ã CEC_CSR_REOM ((uint16_t)0x0020) ä CEC_CSR_RERR ((uint16_t)0x0040) å CEC_CSR_RBTF ((uint16_t)0x0080) è CEC_TXD_TXD ((uint16_t)0x00FF) ë CEC_RXD_RXD ((uint16_t)0x00FF) ô TIM_CR1_CEN ((uint16_t)0x0001) õ TIM_CR1_UDIS ((uint16_t)0x0002) ö TIM_CR1_URS ((uint16_t)0x0004) ÷ TIM_CR1_OPM ((uint16_t)0x0008) ø TIM_CR1_DIR ((uint16_t)0x0010) ú TIM_CR1_CMS ((uint16_t)0x0060) û TIM_CR1_CMS_0 ((uint16_t)0x0020) ü TIM_CR1_CMS_1 ((uint16_t)0x0040) þ TIM_CR1_ARPE ((uint16_t)0x0080) !TIM_CR1_CKD ((uint16_t)0x0300) !TIM_CR1_CKD_0 ((uint16_t)0x0100) !TIM_CR1_CKD_1 ((uint16_t)0x0200)
!TIM_CR2_CCPC ((uint16_t)0x0001) !TIM_CR2_CCUS ((uint16_t)0x0004) !TIM_CR2_CCDS ((uint16_t)0x0008) !TIM_CR2_MMS ((uint16_t)0x0070) !TIM_CR2_MMS_0 ((uint16_t)0x0010) !TIM_CR2_MMS_1 ((uint16_t)0x0020) !TIM_CR2_MMS_2 ((uint16_t)0x0040) !TIM_CR2_TI1S ((uint16_t)0x0080) !TIM_CR2_OIS1 ((uint16_t)0x0100) !TIM_CR2_OIS1N ((uint16_t)0x0200) !TIM_CR2_OIS2 ((uint16_t)0x0400) !TIM_CR2_OIS2N ((uint16_t)0x0800) !TIM_CR2_OIS3 ((uint16_t)0x1000) !TIM_CR2_OIS3N ((uint16_t)0x2000) !TIM_CR2_OIS4 ((uint16_t)0x4000) !TIM_SMCR_SMS ((uint16_t)0x0007) !TIM_SMCR_SMS_0 ((uint16_t)0x0001) !TIM_SMCR_SMS_1 ((uint16_t)0x0002) !TIM_SMCR_SMS_2 ((uint16_t)0x0004) !TIM_SMCR_TS ((uint16_t)0x0070) !TIM_SMCR_TS_0 ((uint16_t)0x0010) !TIM_SMCR_TS_1 ((uint16_t)0x0020) !TIM_SMCR_TS_2 ((uint16_t)0x0040) ¢!TIM_SMCR_MSM ((uint16_t)0x0080) ¤!TIM_SMCR_ETF ((uint16_t)0x0F00) ¥!TIM_SMCR_ETF_0 ((uint16_t)0x0100) ¦!TIM_SMCR_ETF_1 ((uint16_t)0x0200) §!TIM_SMCR_ETF_2 ((uint16_t)0x0400) ¨!TIM_SMCR_ETF_3 ((uint16_t)0x0800) ª!TIM_SMCR_ETPS ((uint16_t)0x3000) «!TIM_SMCR_ETPS_0 ((uint16_t)0x1000) ¬!TIM_SMCR_ETPS_1 ((uint16_t)0x2000) ®!TIM_SMCR_ECE ((uint16_t)0x4000) ¯!TIM_SMCR_ETP ((uint16_t)0x8000) ²!TIM_DIER_UIE ((uint16_t)0x0001) ³!TIM_DIER_CC1IE ((uint16_t)0x0002) ´!TIM_DIER_CC2IE ((uint16_t)0x0004) µ!TIM_DIER_CC3IE ((uint16_t)0x0008) ¶!TIM_DIER_CC4IE ((uint16_t)0x0010) ·!TIM_DIER_COMIE ((uint16_t)0x0020) ¸!TIM_DIER_TIE ((uint16_t)0x0040) ¹!TIM_DIER_BIE ((uint16_t)0x0080) º!TIM_DIER_UDE ((uint16_t)0x0100) »!TIM_DIER_CC1DE ((uint16_t)0x0200) ¼!TIM_DIER_CC2DE ((uint16_t)0x0400) ½!TIM_DIER_CC3DE ((uint16_t)0x0800) ¾!TIM_DIER_CC4DE ((uint16_t)0x1000) ¿!TIM_DIER_COMDE ((uint16_t)0x2000) À!TIM_DIER_TDE ((uint16_t)0x4000) Ã!TIM_SR_UIF ((uint16_t)0x0001) Ä!TIM_SR_CC1IF ((uint16_t)0x0002) Å!TIM_SR_CC2IF ((uint16_t)0x0004) Æ!TIM_SR_CC3IF ((uint16_t)0x0008) Ç!TIM_SR_CC4IF ((uint16_t)0x0010) È!TIM_SR_COMIF ((uint16_t)0x0020) É!TIM_SR_TIF ((uint16_t)0x0040) Ê!TIM_SR_BIF ((uint16_t)0x0080) Ë!TIM_SR_CC1OF ((uint16_t)0x0200) Ì!TIM_SR_CC2OF ((uint16_t)0x0400) Í!TIM_SR_CC3OF ((uint16_t)0x0800) Î!TIM_SR_CC4OF ((uint16_t)0x1000) Ñ!TIM_EGR_UG ((uint8_t)0x01) Ò!TIM_EGR_CC1G ((uint8_t)0x02) Ó!TIM_EGR_CC2G ((uint8_t)0x04) Ô!TIM_EGR_CC3G ((uint8_t)0x08) Õ!TIM_EGR_CC4G ((uint8_t)0x10) Ö!TIM_EGR_COMG ((uint8_t)0x20) ×!TIM_EGR_TG ((uint8_t)0x40) Ø!TIM_EGR_BG ((uint8_t)0x80) Û!TIM_CCMR1_CC1S ((uint16_t)0x0003) Ü!TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) Ý!TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) ß!TIM_CCMR1_OC1FE ((uint16_t)0x0004) à!TIM_CCMR1_OC1PE ((uint16_t)0x0008) â!TIM_CCMR1_OC1M ((uint16_t)0x0070) ã!TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) ä!TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) å!TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) ç!TIM_CCMR1_OC1CE ((uint16_t)0x0080) é!TIM_CCMR1_CC2S ((uint16_t)0x0300) ê!TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) ë!TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) í!TIM_CCMR1_OC2FE ((uint16_t)0x0400) î!TIM_CCMR1_OC2PE ((uint16_t)0x0800) ð!TIM_CCMR1_OC2M ((uint16_t)0x7000) ñ!TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) ò!TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) ó!TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) õ!TIM_CCMR1_OC2CE ((uint16_t)0x8000) ù!TIM_CCMR1_IC1PSC ((uint16_t)0x000C) ú!TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) û!TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) ý!TIM_CCMR1_IC1F ((uint16_t)0x00F0) þ!TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) ÿ!TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) "TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) "TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) "TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) "TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
"TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) "TIM_CCMR1_IC2F ((uint16_t)0xF000) "TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) "TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) "TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) "TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) "TIM_CCMR2_CC3S ((uint16_t)0x0003) "TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) "TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) "TIM_CCMR2_OC3FE ((uint16_t)0x0004) "TIM_CCMR2_OC3PE ((uint16_t)0x0008) "TIM_CCMR2_OC3M ((uint16_t)0x0070) "TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) "TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) "TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) "TIM_CCMR2_OC3CE ((uint16_t)0x0080) "TIM_CCMR2_CC4S ((uint16_t)0x0300) "TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) "TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) "TIM_CCMR2_OC4FE ((uint16_t)0x0400) ¡"TIM_CCMR2_OC4PE ((uint16_t)0x0800) £"TIM_CCMR2_OC4M ((uint16_t)0x7000) ¤"TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) ¥"TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) ¦"TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) ¨"TIM_CCMR2_OC4CE ((uint16_t)0x8000) ¬"TIM_CCMR2_IC3PSC ((uint16_t)0x000C) "TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) ®"TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) °"TIM_CCMR2_IC3F ((uint16_t)0x00F0) ±"TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) ²"TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) ³"TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) ´"TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) ¶"TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) ·"TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) ¸"TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) º"TIM_CCMR2_IC4F ((uint16_t)0xF000) »"TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) ¼"TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) ½"TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) ¾"TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) Á"TIM_CCER_CC1E ((uint16_t)0x0001) Â"TIM_CCER_CC1P ((uint16_t)0x0002) Ã"TIM_CCER_CC1NE ((uint16_t)0x0004) Ä"TIM_CCER_CC1NP ((uint16_t)0x0008) Å"TIM_CCER_CC2E ((uint16_t)0x0010) Æ"TIM_CCER_CC2P ((uint16_t)0x0020) Ç"TIM_CCER_CC2NE ((uint16_t)0x0040) È"TIM_CCER_CC2NP ((uint16_t)0x0080) É"TIM_CCER_CC3E ((uint16_t)0x0100) Ê"TIM_CCER_CC3P ((uint16_t)0x0200) Ë"TIM_CCER_CC3NE ((uint16_t)0x0400) Ì"TIM_CCER_CC3NP ((uint16_t)0x0800) Í"TIM_CCER_CC4E ((uint16_t)0x1000) Î"TIM_CCER_CC4P ((uint16_t)0x2000) Ï"TIM_CCER_CC4NP ((uint16_t)0x8000) Ò"TIM_CNT_CNT ((uint16_t)0xFFFF) Õ"TIM_PSC_PSC ((uint16_t)0xFFFF) Ø"TIM_ARR_ARR ((uint16_t)0xFFFF) Û"TIM_RCR_REP ((uint8_t)0xFF) Þ"TIM_CCR1_CCR1 ((uint16_t)0xFFFF) á"TIM_CCR2_CCR2 ((uint16_t)0xFFFF) ä"TIM_CCR3_CCR3 ((uint16_t)0xFFFF) ç"TIM_CCR4_CCR4 ((uint16_t)0xFFFF) ê"TIM_BDTR_DTG ((uint16_t)0x00FF) ë"TIM_BDTR_DTG_0 ((uint16_t)0x0001) ì"TIM_BDTR_DTG_1 ((uint16_t)0x0002) í"TIM_BDTR_DTG_2 ((uint16_t)0x0004) î"TIM_BDTR_DTG_3 ((uint16_t)0x0008) ï"TIM_BDTR_DTG_4 ((uint16_t)0x0010) ð"TIM_BDTR_DTG_5 ((uint16_t)0x0020) ñ"TIM_BDTR_DTG_6 ((uint16_t)0x0040) ò"TIM_BDTR_DTG_7 ((uint16_t)0x0080) ô"TIM_BDTR_LOCK ((uint16_t)0x0300) õ"TIM_BDTR_LOCK_0 ((uint16_t)0x0100) ö"TIM_BDTR_LOCK_1 ((uint16_t)0x0200) ø"TIM_BDTR_OSSI ((uint16_t)0x0400) ù"TIM_BDTR_OSSR ((uint16_t)0x0800) ú"TIM_BDTR_BKE ((uint16_t)0x1000) û"TIM_BDTR_BKP ((uint16_t)0x2000) ü"TIM_BDTR_AOE ((uint16_t)0x4000) ý"TIM_BDTR_MOE ((uint16_t)0x8000) #TIM_DCR_DBA ((uint16_t)0x001F) #TIM_DCR_DBA_0 ((uint16_t)0x0001) #TIM_DCR_DBA_1 ((uint16_t)0x0002) #TIM_DCR_DBA_2 ((uint16_t)0x0004) #TIM_DCR_DBA_3 ((uint16_t)0x0008)
#TIM_DCR_DBA_4 ((uint16_t)0x0010) #TIM_DCR_DBL ((uint16_t)0x1F00) #TIM_DCR_DBL_0 ((uint16_t)0x0100) #TIM_DCR_DBL_1 ((uint16_t)0x0200) #TIM_DCR_DBL_2 ((uint16_t)0x0400) #TIM_DCR_DBL_3 ((uint16_t)0x0800) #TIM_DCR_DBL_4 ((uint16_t)0x1000) #TIM_DMAR_DMAB ((uint16_t)0xFFFF) #RTC_CRH_SECIE ((uint8_t)0x01) #RTC_CRH_ALRIE ((uint8_t)0x02) #RTC_CRH_OWIE ((uint8_t)0x04) #RTC_CRL_SECF ((uint8_t)0x01) #RTC_CRL_ALRF ((uint8_t)0x02) #RTC_CRL_OWF ((uint8_t)0x04) #RTC_CRL_RSF ((uint8_t)0x08) ¡#RTC_CRL_CNF ((uint8_t)0x10) ¢#RTC_CRL_RTOFF ((uint8_t)0x20) ¥#RTC_PRLH_PRL ((uint16_t)0x000F) ¨#RTC_PRLL_PRL ((uint16_t)0xFFFF) «#RTC_DIVH_RTC_DIV ((uint16_t)0x000F) ®#RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) ±#RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) ´#RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) ·#RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) º#RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) Ã#IWDG_KR_KEY ((uint16_t)0xFFFF) Æ#IWDG_PR_PR ((uint8_t)0x07) Ç#IWDG_PR_PR_0 ((uint8_t)0x01) È#IWDG_PR_PR_1 ((uint8_t)0x02) É#IWDG_PR_PR_2 ((uint8_t)0x04) Ì#IWDG_RLR_RL ((uint16_t)0x0FFF) Ï#IWDG_SR_PVU ((uint8_t)0x01) Ð#IWDG_SR_RVU ((uint8_t)0x02) Ù#WWDG_CR_T ((uint8_t)0x7F) Ú#WWDG_CR_T0 ((uint8_t)0x01) Û#WWDG_CR_T1 ((uint8_t)0x02) Ü#WWDG_CR_T2 ((uint8_t)0x04) Ý#WWDG_CR_T3 ((uint8_t)0x08) Þ#WWDG_CR_T4 ((uint8_t)0x10) ß#WWDG_CR_T5 ((uint8_t)0x20) à#WWDG_CR_T6 ((uint8_t)0x40) â#WWDG_CR_WDGA ((uint8_t)0x80) å#WWDG_CFR_W ((uint16_t)0x007F) æ#WWDG_CFR_W0 ((uint16_t)0x0001) ç#WWDG_CFR_W1 ((uint16_t)0x0002) è#WWDG_CFR_W2 ((uint16_t)0x0004) é#WWDG_CFR_W3 ((uint16_t)0x0008) ê#WWDG_CFR_W4 ((uint16_t)0x0010) ë#WWDG_CFR_W5 ((uint16_t)0x0020) ì#WWDG_CFR_W6 ((uint16_t)0x0040) î#WWDG_CFR_WDGTB ((uint16_t)0x0180) ï#WWDG_CFR_WDGTB0 ((uint16_t)0x0080) ð#WWDG_CFR_WDGTB1 ((uint16_t)0x0100) ò#WWDG_CFR_EWI ((uint16_t)0x0200) õ#WWDG_SR_EWIF ((uint8_t)0x01) þ#FSMC_BCR1_MBKEN ((uint32_t)0x00000001) ÿ#FSMC_BCR1_MUXEN ((uint32_t)0x00000002) $FSMC_BCR1_MTYP ((uint32_t)0x0000000C) $FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) $FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
$FSMC_BCR1_MWID ((uint32_t)0x00000030) $FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) $FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) $FSMC_BCR1_FACCEN ((uint32_t)0x00000040) $FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) $FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) $FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) $FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) $FSMC_BCR1_WREN ((uint32_t)0x00001000) $FSMC_BCR1_WAITEN ((uint32_t)0x00002000) $FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) $FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) $FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) $FSMC_BCR2_MBKEN ((uint32_t)0x00000001) $FSMC_BCR2_MUXEN ((uint32_t)0x00000002) $FSMC_BCR2_MTYP ((uint32_t)0x0000000C) $FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) $FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) $FSMC_BCR2_MWID ((uint32_t)0x00000030) $FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) $FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) $FSMC_BCR2_FACCEN ((uint32_t)0x00000040) ¡$FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) ¢$FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) £$FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) ¤$FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) ¥$FSMC_BCR2_WREN ((uint32_t)0x00001000) ¦$FSMC_BCR2_WAITEN ((uint32_t)0x00002000) §$FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) ¨$FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) ©$FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) ¬$FSMC_BCR3_MBKEN ((uint32_t)0x00000001) $FSMC_BCR3_MUXEN ((uint32_t)0x00000002) ¯$FSMC_BCR3_MTYP ((uint32_t)0x0000000C) °$FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) ±$FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) ³$FSMC_BCR3_MWID ((uint32_t)0x00000030) ´$FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) µ$FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) ·$FSMC_BCR3_FACCEN ((uint32_t)0x00000040) ¸$FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) ¹$FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) º$FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) »$FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) ¼$FSMC_BCR3_WREN ((uint32_t)0x00001000) ½$FSMC_BCR3_WAITEN ((uint32_t)0x00002000) ¾$FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) ¿$FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) À$FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) Ã$FSMC_BCR4_MBKEN ((uint32_t)0x00000001) Ä$FSMC_BCR4_MUXEN ((uint32_t)0x00000002) Æ$FSMC_BCR4_MTYP ((uint32_t)0x0000000C) Ç$FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) È$FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) Ê$FSMC_BCR4_MWID ((uint32_t)0x00000030) Ë$FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) Ì$FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) Î$FSMC_BCR4_FACCEN ((uint32_t)0x00000040) Ï$FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) Ð$FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) Ñ$FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) Ò$FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) Ó$FSMC_BCR4_WREN ((uint32_t)0x00001000) Ô$FSMC_BCR4_WAITEN ((uint32_t)0x00002000) Õ$FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) Ö$FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) ×$FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) Ú$FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) Û$FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) Ü$FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) Ý$FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) Þ$FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) à$FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) á$FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) â$FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) ã$FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) ä$FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) æ$FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) ç$FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) è$FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) é$FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) ê$FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) ì$FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) í$FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) î$FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) ï$FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) ð$FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) ò$FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) ó$FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) ô$FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) õ$FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) ö$FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) ø$FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) ù$FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) ú$FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) û$FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) ü$FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) þ$FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) ÿ$FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) %FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) %FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) %FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
%FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) %FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) %FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) %FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) %FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) %FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) %FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) %FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) %FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) %FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) %FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) %FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) %FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) %FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) %FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) %FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) %FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) %FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) %FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) %FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) %FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) %FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) %FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) ¡%FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) ¢%FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) £%FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) ¤%FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) ¥%FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) §%FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) ¨%FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) ©%FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) ¬%FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) %FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) ®%FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) ¯%FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) °%FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) ²%FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) ³%FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) ´%FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) µ%FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) ¶%FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) ¸%FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) ¹%FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) º%FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) »%FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) ¼%FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) ¾%FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) ¿%FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) À%FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) Á%FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) Â%FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) Ä%FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) Å%FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) Æ%FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) Ç%FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) È%FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) Ê%FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) Ë%FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) Ì%FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) Í%FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) Î%FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) Ð%FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) Ñ%FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) Ò%FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) Õ%FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) Ö%FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) ×%FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) Ø%FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) Ù%FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) Û%FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) Ü%FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) Ý%FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) Þ%FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) ß%FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) á%FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) â%FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) ã%FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) ä%FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) å%FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) ç%FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) è%FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) é%FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) ê%FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) ë%FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) í%FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) î%FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) ï%FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) ð%FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) ñ%FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) ó%FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) ô%FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) õ%FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) ö%FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) ÷%FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) ù%FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) ú%FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) û%FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) þ%FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) ÿ%FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) &FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) &FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) &FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) &FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
&FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) &FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) &FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) &FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) &FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) &FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) &FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) &FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) &FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) &FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) &FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) &FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) &FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) &FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) &FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) &FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) &FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) &FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) &FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) &FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) &FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) &FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) ¡&FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) ¢&FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) £&FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) ¤&FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) ¥&FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) §&FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) ¨&FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) ©&FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) ª&FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) «&FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) &FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) ®&FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) ¯&FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) °&FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) ±&FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) ³&FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) ´&FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) µ&FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) ¶&FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) ·&FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) ¹&FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) º&FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) »&FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) ¼&FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) ½&FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) ¿&FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) À&FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) Á&FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) Ä&FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) Å&FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) Æ&FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) Ç&FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) È&FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) Ê&FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) Ë&FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) Ì&FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) Í&FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) Î&FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) Ð&FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) Ñ&FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) Ò&FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) Ó&FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) Ô&FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) Ö&FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) ×&FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) Ø&FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) Ù&FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) Ú&FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) Ü&FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) Ý&FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) Þ&FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) ß&FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) à&FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) â&FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) ã&FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) ä&FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) ç&FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) è&FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) é&FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) ê&FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) ë&FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) í&FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) î&FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) ï&FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) ð&FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) ñ&FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) ó&FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) ô&FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) õ&FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) ö&FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) ÷&FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) ù&FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) ú&FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) û&FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) ü&FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) ý&FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) ÿ&FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 'FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 'FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 'FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 'FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
'FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 'FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 'FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 'FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) 'FSMC_PCR2_PBKEN ((uint32_t)0x00000004) 'FSMC_PCR2_PTYP ((uint32_t)0x00000008) 'FSMC_PCR2_PWID ((uint32_t)0x00000030) 'FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) 'FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) 'FSMC_PCR2_ECCEN ((uint32_t)0x00000040) 'FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 'FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 'FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 'FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 'FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) 'FSMC_PCR2_TAR ((uint32_t)0x0001E000) 'FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 'FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 'FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 'FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 'FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) ¡'FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) ¢'FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) £'FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) ¦'FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) §'FSMC_PCR3_PBKEN ((uint32_t)0x00000004) ¨'FSMC_PCR3_PTYP ((uint32_t)0x00000008) ª'FSMC_PCR3_PWID ((uint32_t)0x00000030) «'FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) ¬'FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) ®'FSMC_PCR3_ECCEN ((uint32_t)0x00000040) °'FSMC_PCR3_TCLR ((uint32_t)0x00001E00) ±'FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) ²'FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) ³'FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) ´'FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) ¶'FSMC_PCR3_TAR ((uint32_t)0x0001E000) ·'FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) ¸'FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) ¹'FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) º'FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) ¼'FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) ½'FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) ¾'FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) ¿'FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) Â'FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) Ã'FSMC_PCR4_PBKEN ((uint32_t)0x00000004) Ä'FSMC_PCR4_PTYP ((uint32_t)0x00000008) Æ'FSMC_PCR4_PWID ((uint32_t)0x00000030) Ç'FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) È'FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) Ê'FSMC_PCR4_ECCEN ((uint32_t)0x00000040) Ì'FSMC_PCR4_TCLR ((uint32_t)0x00001E00) Í'FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) Î'FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) Ï'FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) Ð'FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) Ò'FSMC_PCR4_TAR ((uint32_t)0x0001E000) Ó'FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) Ô'FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) Õ'FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) Ö'FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) Ø'FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) Ù'FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) Ú'FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) Û'FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) Þ'FSMC_SR2_IRS ((uint8_t)0x01) ß'FSMC_SR2_ILS ((uint8_t)0x02) à'FSMC_SR2_IFS ((uint8_t)0x04) á'FSMC_SR2_IREN ((uint8_t)0x08) â'FSMC_SR2_ILEN ((uint8_t)0x10) ã'FSMC_SR2_IFEN ((uint8_t)0x20) ä'FSMC_SR2_FEMPT ((uint8_t)0x40) ç'FSMC_SR3_IRS ((uint8_t)0x01) è'FSMC_SR3_ILS ((uint8_t)0x02) é'FSMC_SR3_IFS ((uint8_t)0x04) ê'FSMC_SR3_IREN ((uint8_t)0x08) ë'FSMC_SR3_ILEN ((uint8_t)0x10) ì'FSMC_SR3_IFEN ((uint8_t)0x20) í'FSMC_SR3_FEMPT ((uint8_t)0x40) ð'FSMC_SR4_IRS ((uint8_t)0x01) ñ'FSMC_SR4_ILS ((uint8_t)0x02) ò'FSMC_SR4_IFS ((uint8_t)0x04) ó'FSMC_SR4_IREN ((uint8_t)0x08) ô'FSMC_SR4_ILEN ((uint8_t)0x10) õ'FSMC_SR4_IFEN ((uint8_t)0x20) ö'FSMC_SR4_FEMPT ((uint8_t)0x40) ù'FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) ú'FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) û'FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) ü'FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) ý'FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) þ'FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) ÿ'FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) (FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) (FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) (FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) (FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
(FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) (FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) (FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) (FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) (FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) (FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) (FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) (FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) (FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) (FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) (FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) (FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) (FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) (FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) (FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) (FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) (FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) (FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) (FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) (FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) (FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) (FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) (FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) (FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) (FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) ¢(FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) £(FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) ¤(FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) ¥(FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) ¦(FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) §(FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) ¨(FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) ©(FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) ª(FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) ¬(FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) (FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) ®(FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) ¯(FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) °(FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) ±(FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) ²(FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) ³(FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) ´(FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) ¶(FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) ·(FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) ¸(FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) ¹(FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) º(FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) »(FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) ¼(FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) ½(FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) ¾(FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) À(FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) Á(FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) Â(FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) Ã(FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) Ä(FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) Å(FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) Æ(FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) Ç(FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) È(FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) Ë(FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) Ì(FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) Í(FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) Î(FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) Ï(FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) Ð(FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) Ñ(FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) Ò(FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) Ó(FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) Õ(FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) Ö(FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) ×(FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) Ø(FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) Ù(FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) Ú(FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) Û(FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) Ü(FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) Ý(FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) ß(FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) à(FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) á(FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) â(FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) ã(FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) ä(FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) å(FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) æ(FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) ç(FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) é(FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) ê(FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) ë(FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) ì(FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) í(FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) î(FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) ï(FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) ð(FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) ñ(FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) ô(FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) õ(FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) ö(FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) ÷(FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) ø(FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) ù(FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) ú(FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) û(FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) ü(FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) þ(FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) ÿ(FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) )FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) )FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) )FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) )FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) )FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
)FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) )FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) )FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) )FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) )FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) )FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) )FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) )FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) )FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) )FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) )FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) )FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) )FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) )FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) )FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) )FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) )FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) )FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) )FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) )FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) )FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) )FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) )FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) )FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) ¡)FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) ¢)FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) £)FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) ¤)FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) ¥)FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) §)FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) ¨)FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) ©)FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) ª)FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) «)FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) ¬)FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) )FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) ®)FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) ¯)FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) ±)FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) ²)FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) ³)FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) ´)FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) µ)FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) ¶)FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) ·)FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) ¸)FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) ¹)FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) »)FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) ¼)FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) ½)FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) ¾)FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) ¿)FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) À)FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) Á)FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) Â)FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) Ã)FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) Æ)FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) Ç)FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) È)FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) É)FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) Ê)FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) Ë)FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) Ì)FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) Í)FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) Î)FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) Ð)FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) Ñ)FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) Ò)FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) Ó)FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) Ô)FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) Õ)FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) Ö)FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) ×)FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) Ø)FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) Ú)FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) Û)FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) Ü)FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) Ý)FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) Þ)FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) ß)FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) à)FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) á)FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) â)FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) ä)FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) å)FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) æ)FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) ç)FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) è)FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) é)FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) ê)FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) ë)FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) ì)FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) ï)FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) ð)FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) ñ)FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) ò)FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) ó)FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) ô)FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) õ)FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) ö)FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) ÷)FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) ù)FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) ú)FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) û)FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) ü)FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) ý)FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) þ)FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) ÿ)FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) *FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) *FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) *FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) *FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
*FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) *FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) *FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) *FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) *FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) *FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) *FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) *FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) *FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) *FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) *FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) *FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) *FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) *FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) *FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) *FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) *FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) *FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) ¤*SDIO_POWER_PWRCTRL ((uint8_t)0x03) ¥*SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) ¦*SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) ©*SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) ª*SDIO_CLKCR_CLKEN ((uint16_t)0x0100) «*SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) ¬*SDIO_CLKCR_BYPASS ((uint16_t)0x0400) ®*SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) ¯*SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) °*SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) ²*SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) ³*SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) ¶*SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) ¹*SDIO_CMD_CMDINDEX ((uint16_t)0x003F) »*SDIO_CMD_WAITRESP ((uint16_t)0x00C0) ¼*SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) ½*SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) ¿*SDIO_CMD_WAITINT ((uint16_t)0x0100) À*SDIO_CMD_WAITPEND ((uint16_t)0x0200) Á*SDIO_CMD_CPSMEN ((uint16_t)0x0400) Â*SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) Ã*SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) Ä*SDIO_CMD_NIEN ((uint16_t)0x2000) Å*SDIO_CMD_CEATACMD ((uint16_t)0x4000) È*SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) Ë*SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) Î*SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) Ñ*SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) Ô*SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) ×*SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) Ú*SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) Ý*SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) à*SDIO_DCTRL_DTEN ((uint16_t)0x0001) á*SDIO_DCTRL_DTDIR ((uint16_t)0x0002) â*SDIO_DCTRL_DTMODE ((uint16_t)0x0004) ã*SDIO_DCTRL_DMAEN ((uint16_t)0x0008) å*SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) æ*SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) ç*SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) è*SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) é*SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) ë*SDIO_DCTRL_RWSTART ((uint16_t)0x0100) ì*SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) í*SDIO_DCTRL_RWMOD ((uint16_t)0x0400) î*SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) ñ*SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) ô*SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) õ*SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) ö*SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) ÷*SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) ø*SDIO_STA_TXUNDERR ((uint32_t)0x00000010) ù*SDIO_STA_RXOVERR ((uint32_t)0x00000020) ú*SDIO_STA_CMDREND ((uint32_t)0x00000040) û*SDIO_STA_CMDSENT ((uint32_t)0x00000080) ü*SDIO_STA_DATAEND ((uint32_t)0x00000100) ý*SDIO_STA_STBITERR ((uint32_t)0x00000200) þ*SDIO_STA_DBCKEND ((uint32_t)0x00000400) ÿ*SDIO_STA_CMDACT ((uint32_t)0x00000800) +SDIO_STA_TXACT ((uint32_t)0x00001000) +SDIO_STA_RXACT ((uint32_t)0x00002000) +SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) +SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) +SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
+SDIO_STA_RXFIFOF ((uint32_t)0x00020000) +SDIO_STA_TXFIFOE ((uint32_t)0x00040000) +SDIO_STA_RXFIFOE ((uint32_t)0x00080000) +SDIO_STA_TXDAVL ((uint32_t)0x00100000) +SDIO_STA_RXDAVL ((uint32_t)0x00200000) +SDIO_STA_SDIOIT ((uint32_t)0x00400000) +SDIO_STA_CEATAEND ((uint32_t)0x00800000) +SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) +SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) +SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) +SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) +SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) +SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) +SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) +SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) +SDIO_ICR_DATAENDC ((uint32_t)0x00000100) +SDIO_ICR_STBITERRC ((uint32_t)0x00000200) +SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) +SDIO_ICR_SDIOITC ((uint32_t)0x00400000) +SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) +SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) +SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) +SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) +SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) ¡+SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) ¢+SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) £+SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) ¤+SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) ¥+SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) ¦+SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) §+SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) ¨+SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) ©+SDIO_MASK_TXACTIE ((uint32_t)0x00001000) ª+SDIO_MASK_RXACTIE ((uint32_t)0x00002000) «+SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) ¬+SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) +SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) ®+SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) ¯+SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) °+SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) ±+SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) ²+SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) ³+SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) ´+SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) ·+SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) º+SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) Ä+USB_EP0R_EA ((uint16_t)0x000F) Æ+USB_EP0R_STAT_TX ((uint16_t)0x0030) Ç+USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) È+USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) Ê+USB_EP0R_DTOG_TX ((uint16_t)0x0040) Ë+USB_EP0R_CTR_TX ((uint16_t)0x0080) Ì+USB_EP0R_EP_KIND ((uint16_t)0x0100) Î+USB_EP0R_EP_TYPE ((uint16_t)0x0600) Ï+USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) Ð+USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) Ò+USB_EP0R_SETUP ((uint16_t)0x0800) Ô+USB_EP0R_STAT_RX ((uint16_t)0x3000) Õ+USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) Ö+USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) Ø+USB_EP0R_DTOG_RX ((uint16_t)0x4000) Ù+USB_EP0R_CTR_RX ((uint16_t)0x8000) Ü+USB_EP1R_EA ((uint16_t)0x000F) Þ+USB_EP1R_STAT_TX ((uint16_t)0x0030) ß+USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) à+USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) â+USB_EP1R_DTOG_TX ((uint16_t)0x0040) ã+USB_EP1R_CTR_TX ((uint16_t)0x0080) ä+USB_EP1R_EP_KIND ((uint16_t)0x0100) æ+USB_EP1R_EP_TYPE ((uint16_t)0x0600) ç+USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) è+USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) ê+USB_EP1R_SETUP ((uint16_t)0x0800) ì+USB_EP1R_STAT_RX ((uint16_t)0x3000) í+USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) î+USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) ð+USB_EP1R_DTOG_RX ((uint16_t)0x4000) ñ+USB_EP1R_CTR_RX ((uint16_t)0x8000) ô+USB_EP2R_EA ((uint16_t)0x000F) ö+USB_EP2R_STAT_TX ((uint16_t)0x0030) ÷+USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) ø+USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) ú+USB_EP2R_DTOG_TX ((uint16_t)0x0040) û+USB_EP2R_CTR_TX ((uint16_t)0x0080) ü+USB_EP2R_EP_KIND ((uint16_t)0x0100) þ+USB_EP2R_EP_TYPE ((uint16_t)0x0600) ÿ+USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) ,USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) ,USB_EP2R_SETUP ((uint16_t)0x0800) ,USB_EP2R_STAT_RX ((uint16_t)0x3000)
,USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) ,USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) ,USB_EP2R_DTOG_RX ((uint16_t)0x4000) ,USB_EP2R_CTR_RX ((uint16_t)0x8000) ,USB_EP3R_EA ((uint16_t)0x000F) ,USB_EP3R_STAT_TX ((uint16_t)0x0030) ,USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) ,USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) ,USB_EP3R_DTOG_TX ((uint16_t)0x0040) ,USB_EP3R_CTR_TX ((uint16_t)0x0080) ,USB_EP3R_EP_KIND ((uint16_t)0x0100) ,USB_EP3R_EP_TYPE ((uint16_t)0x0600) ,USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) ,USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) ,USB_EP3R_SETUP ((uint16_t)0x0800) ,USB_EP3R_STAT_RX ((uint16_t)0x3000) ,USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) ,USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) ,USB_EP3R_DTOG_RX ((uint16_t)0x4000) ¡,USB_EP3R_CTR_RX ((uint16_t)0x8000) ¤,USB_EP4R_EA ((uint16_t)0x000F) ¦,USB_EP4R_STAT_TX ((uint16_t)0x0030) §,USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) ¨,USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) ª,USB_EP4R_DTOG_TX ((uint16_t)0x0040) «,USB_EP4R_CTR_TX ((uint16_t)0x0080) ¬,USB_EP4R_EP_KIND ((uint16_t)0x0100) ®,USB_EP4R_EP_TYPE ((uint16_t)0x0600) ¯,USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) °,USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) ²,USB_EP4R_SETUP ((uint16_t)0x0800) ´,USB_EP4R_STAT_RX ((uint16_t)0x3000) µ,USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) ¶,USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) ¸,USB_EP4R_DTOG_RX ((uint16_t)0x4000) ¹,USB_EP4R_CTR_RX ((uint16_t)0x8000) ¼,USB_EP5R_EA ((uint16_t)0x000F) ¾,USB_EP5R_STAT_TX ((uint16_t)0x0030) ¿,USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) À,USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) Â,USB_EP5R_DTOG_TX ((uint16_t)0x0040) Ã,USB_EP5R_CTR_TX ((uint16_t)0x0080) Ä,USB_EP5R_EP_KIND ((uint16_t)0x0100) Æ,USB_EP5R_EP_TYPE ((uint16_t)0x0600) Ç,USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) È,USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) Ê,USB_EP5R_SETUP ((uint16_t)0x0800) Ì,USB_EP5R_STAT_RX ((uint16_t)0x3000) Í,USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) Î,USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) Ð,USB_EP5R_DTOG_RX ((uint16_t)0x4000) Ñ,USB_EP5R_CTR_RX ((uint16_t)0x8000) Ô,USB_EP6R_EA ((uint16_t)0x000F) Ö,USB_EP6R_STAT_TX ((uint16_t)0x0030) ×,USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) Ø,USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) Ú,USB_EP6R_DTOG_TX ((uint16_t)0x0040) Û,USB_EP6R_CTR_TX ((uint16_t)0x0080) Ü,USB_EP6R_EP_KIND ((uint16_t)0x0100) Þ,USB_EP6R_EP_TYPE ((uint16_t)0x0600) ß,USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) à,USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) â,USB_EP6R_SETUP ((uint16_t)0x0800) ä,USB_EP6R_STAT_RX ((uint16_t)0x3000) å,USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) æ,USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) è,USB_EP6R_DTOG_RX ((uint16_t)0x4000) é,USB_EP6R_CTR_RX ((uint16_t)0x8000) ì,USB_EP7R_EA ((uint16_t)0x000F) î,USB_EP7R_STAT_TX ((uint16_t)0x0030) ï,USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) ð,USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) ò,USB_EP7R_DTOG_TX ((uint16_t)0x0040) ó,USB_EP7R_CTR_TX ((uint16_t)0x0080) ô,USB_EP7R_EP_KIND ((uint16_t)0x0100) ö,USB_EP7R_EP_TYPE ((uint16_t)0x0600) ÷,USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) ø,USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) ú,USB_EP7R_SETUP ((uint16_t)0x0800) ü,USB_EP7R_STAT_RX ((uint16_t)0x3000) ý,USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) þ,USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) -USB_EP7R_DTOG_RX ((uint16_t)0x4000) -USB_EP7R_CTR_RX ((uint16_t)0x8000)
-USB_CNTR_FRES ((uint16_t)0x0001) -USB_CNTR_PDWN ((uint16_t)0x0002) -USB_CNTR_LP_MODE ((uint16_t)0x0004) -USB_CNTR_FSUSP ((uint16_t)0x0008) -USB_CNTR_RESUME ((uint16_t)0x0010) -USB_CNTR_ESOFM ((uint16_t)0x0100) -USB_CNTR_SOFM ((uint16_t)0x0200) -USB_CNTR_RESETM ((uint16_t)0x0400) -USB_CNTR_SUSPM ((uint16_t)0x0800) -USB_CNTR_WKUPM ((uint16_t)0x1000) -USB_CNTR_ERRM ((uint16_t)0x2000) -USB_CNTR_PMAOVRM ((uint16_t)0x4000) -USB_CNTR_CTRM ((uint16_t)0x8000) -USB_ISTR_EP_ID ((uint16_t)0x000F) -USB_ISTR_DIR ((uint16_t)0x0010) -USB_ISTR_ESOF ((uint16_t)0x0100) -USB_ISTR_SOF ((uint16_t)0x0200) -USB_ISTR_RESET ((uint16_t)0x0400) -USB_ISTR_SUSP ((uint16_t)0x0800) -USB_ISTR_WKUP ((uint16_t)0x1000) -USB_ISTR_ERR ((uint16_t)0x2000) -USB_ISTR_PMAOVR ((uint16_t)0x4000) -USB_ISTR_CTR ((uint16_t)0x8000) -USB_FNR_FN ((uint16_t)0x07FF) ¡-USB_FNR_LSOF ((uint16_t)0x1800) ¢-USB_FNR_LCK ((uint16_t)0x2000) £-USB_FNR_RXDM ((uint16_t)0x4000) ¤-USB_FNR_RXDP ((uint16_t)0x8000) §-USB_DADDR_ADD ((uint8_t)0x7F) ¨-USB_DADDR_ADD0 ((uint8_t)0x01) ©-USB_DADDR_ADD1 ((uint8_t)0x02) ª-USB_DADDR_ADD2 ((uint8_t)0x04) «-USB_DADDR_ADD3 ((uint8_t)0x08) ¬-USB_DADDR_ADD4 ((uint8_t)0x10) -USB_DADDR_ADD5 ((uint8_t)0x20) ®-USB_DADDR_ADD6 ((uint8_t)0x40) °-USB_DADDR_EF ((uint8_t)0x80) ³-USB_BTABLE_BTABLE ((uint16_t)0xFFF8) ·-USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) º-USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) ½-USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) À-USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) Ã-USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) Æ-USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) É-USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) Ì-USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) Ñ-USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) Ô-USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) ×-USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) Ú-USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) Ý-USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) à-USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) ã-USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) æ-USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) ë-USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) î-USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) ñ-USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) ô-USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) ÷-USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) ú-USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) ý-USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) .USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) .USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) .USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) .USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) .USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) .USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) .USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) .USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) .USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) .USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) .USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) £.USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) ¦.USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) ©.USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) ¬.USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) ¯.USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) ².USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) ·.USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) ¹.USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) º.USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ».USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ¼.USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ½.USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ¾.USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) À.USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) Ã.USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) Å.USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) Æ.USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) Ç.USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) È.USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) É.USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) Ê.USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Ì.USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) Ï.USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) Ñ.USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) Ò.USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) Ó.USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) Ô.USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) Õ.USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) Ö.USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Ø.USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) Û.USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) Ý.USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) Þ.USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ß.USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) à.USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) á.USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) â.USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ä.USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) ç.USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) é.USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) ê.USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ë.USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ì.USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) í.USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) î.USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ð.USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) ó.USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) õ.USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) ö.USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ÷.USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ø.USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ù.USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ú.USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ü.USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) ÿ.USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000)
/USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ¢/USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ¥/USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) §/USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) ¨/USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ©/USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ª/USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) «/USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¬/USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ®/USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ±/USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) ³/USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ´/USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) µ/USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ¶/USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ·/USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) ¸/USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) º/USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ½/USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) ¿/USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) À/USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Á/USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Â/USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Ã/USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ä/USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Æ/USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) É/USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) Ë/USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Ì/USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Í/USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Î/USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Ï/USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) Ð/USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) Ò/USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) Õ/USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) ×/USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Ø/USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Ù/USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Ú/USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Û/USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ü/USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Þ/USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) á/USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) ã/USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ä/USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) å/USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) æ/USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ç/USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) è/USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ê/USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) í/USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) ï/USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) ð/USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ñ/USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ò/USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ó/USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ô/USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ö/USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ù/USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) û/USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ü/USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) ý/USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) þ/USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ÿ/USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 0USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 0USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000)
0USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) 0USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 0USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 0USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 0USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 0USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 0USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 0USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 0USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) 0USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 0USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 0USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 0USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 0USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 0USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 0USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 0USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) 0USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ¡0USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ¢0USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) £0USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¤0USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ¦0USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ©0USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) «0USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ¬0USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 0USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ®0USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ¯0USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) °0USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ²0USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) µ0USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) ·0USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) ¸0USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ¹0USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) º0USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) »0USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¼0USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ¾0USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) Á0USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) Ã0USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Ä0USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Å0USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Æ0USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Ç0USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) È0USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) Ê0USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) Í0USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) Ï0USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Ð0USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Ñ0USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Ò0USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Ó0USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ô0USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Ö0USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) à0CAN_MCR_INRQ ((uint16_t)0x0001) á0CAN_MCR_SLEEP ((uint16_t)0x0002) â0CAN_MCR_TXFP ((uint16_t)0x0004) ã0CAN_MCR_RFLM ((uint16_t)0x0008) ä0CAN_MCR_NART ((uint16_t)0x0010) å0CAN_MCR_AWUM ((uint16_t)0x0020) æ0CAN_MCR_ABOM ((uint16_t)0x0040) ç0CAN_MCR_TTCM ((uint16_t)0x0080) è0CAN_MCR_RESET ((uint16_t)0x8000) ë0CAN_MSR_INAK ((uint16_t)0x0001) ì0CAN_MSR_SLAK ((uint16_t)0x0002) í0CAN_MSR_ERRI ((uint16_t)0x0004) î0CAN_MSR_WKUI ((uint16_t)0x0008) ï0CAN_MSR_SLAKI ((uint16_t)0x0010) ð0CAN_MSR_TXM ((uint16_t)0x0100) ñ0CAN_MSR_RXM ((uint16_t)0x0200) ò0CAN_MSR_SAMP ((uint16_t)0x0400) ó0CAN_MSR_RX ((uint16_t)0x0800) ö0CAN_TSR_RQCP0 ((uint32_t)0x00000001) ÷0CAN_TSR_TXOK0 ((uint32_t)0x00000002) ø0CAN_TSR_ALST0 ((uint32_t)0x00000004) ù0CAN_TSR_TERR0 ((uint32_t)0x00000008) ú0CAN_TSR_ABRQ0 ((uint32_t)0x00000080) û0CAN_TSR_RQCP1 ((uint32_t)0x00000100) ü0CAN_TSR_TXOK1 ((uint32_t)0x00000200) ý0CAN_TSR_ALST1 ((uint32_t)0x00000400) þ0CAN_TSR_TERR1 ((uint32_t)0x00000800) ÿ0CAN_TSR_ABRQ1 ((uint32_t)0x00008000) 1CAN_TSR_RQCP2 ((uint32_t)0x00010000) 1CAN_TSR_TXOK2 ((uint32_t)0x00020000) 1CAN_TSR_ALST2 ((uint32_t)0x00040000) 1CAN_TSR_TERR2 ((uint32_t)0x00080000) 1CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
1CAN_TSR_CODE ((uint32_t)0x03000000) 1CAN_TSR_TME ((uint32_t)0x1C000000) 1CAN_TSR_TME0 ((uint32_t)0x04000000) 1CAN_TSR_TME1 ((uint32_t)0x08000000) 1CAN_TSR_TME2 ((uint32_t)0x10000000) 1CAN_TSR_LOW ((uint32_t)0xE0000000) 1CAN_TSR_LOW0 ((uint32_t)0x20000000) 1CAN_TSR_LOW1 ((uint32_t)0x40000000) 1CAN_TSR_LOW2 ((uint32_t)0x80000000) 1CAN_RF0R_FMP0 ((uint8_t)0x03) 1CAN_RF0R_FULL0 ((uint8_t)0x08) 1CAN_RF0R_FOVR0 ((uint8_t)0x10) 1CAN_RF0R_RFOM0 ((uint8_t)0x20) 1CAN_RF1R_FMP1 ((uint8_t)0x03) 1CAN_RF1R_FULL1 ((uint8_t)0x08) 1CAN_RF1R_FOVR1 ((uint8_t)0x10) 1CAN_RF1R_RFOM1 ((uint8_t)0x20) 1CAN_IER_TMEIE ((uint32_t)0x00000001) 1CAN_IER_FMPIE0 ((uint32_t)0x00000002) 1CAN_IER_FFIE0 ((uint32_t)0x00000004) ¡1CAN_IER_FOVIE0 ((uint32_t)0x00000008) ¢1CAN_IER_FMPIE1 ((uint32_t)0x00000010) £1CAN_IER_FFIE1 ((uint32_t)0x00000020) ¤1CAN_IER_FOVIE1 ((uint32_t)0x00000040) ¥1CAN_IER_EWGIE ((uint32_t)0x00000100) ¦1CAN_IER_EPVIE ((uint32_t)0x00000200) §1CAN_IER_BOFIE ((uint32_t)0x00000400) ¨1CAN_IER_LECIE ((uint32_t)0x00000800) ©1CAN_IER_ERRIE ((uint32_t)0x00008000) ª1CAN_IER_WKUIE ((uint32_t)0x00010000) «1CAN_IER_SLKIE ((uint32_t)0x00020000) ®1CAN_ESR_EWGF ((uint32_t)0x00000001) ¯1CAN_ESR_EPVF ((uint32_t)0x00000002) °1CAN_ESR_BOFF ((uint32_t)0x00000004) ²1CAN_ESR_LEC ((uint32_t)0x00000070) ³1CAN_ESR_LEC_0 ((uint32_t)0x00000010) ´1CAN_ESR_LEC_1 ((uint32_t)0x00000020) µ1CAN_ESR_LEC_2 ((uint32_t)0x00000040) ·1CAN_ESR_TEC ((uint32_t)0x00FF0000) ¸1CAN_ESR_REC ((uint32_t)0xFF000000) »1CAN_BTR_BRP ((uint32_t)0x000003FF) ¼1CAN_BTR_TS1 ((uint32_t)0x000F0000) ½1CAN_BTR_TS2 ((uint32_t)0x00700000) ¾1CAN_BTR_SJW ((uint32_t)0x03000000) ¿1CAN_BTR_LBKM ((uint32_t)0x40000000) À1CAN_BTR_SILM ((uint32_t)0x80000000) Ä1CAN_TI0R_TXRQ ((uint32_t)0x00000001) Å1CAN_TI0R_RTR ((uint32_t)0x00000002) Æ1CAN_TI0R_IDE ((uint32_t)0x00000004) Ç1CAN_TI0R_EXID ((uint32_t)0x001FFFF8) È1CAN_TI0R_STID ((uint32_t)0xFFE00000) Ë1CAN_TDT0R_DLC ((uint32_t)0x0000000F) Ì1CAN_TDT0R_TGT ((uint32_t)0x00000100) Í1CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) Ð1CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) Ñ1CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) Ò1CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) Ó1CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) Ö1CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) ×1CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) Ø1CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) Ù1CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) Ü1CAN_TI1R_TXRQ ((uint32_t)0x00000001) Ý1CAN_TI1R_RTR ((uint32_t)0x00000002) Þ1CAN_TI1R_IDE ((uint32_t)0x00000004) ß1CAN_TI1R_EXID ((uint32_t)0x001FFFF8) à1CAN_TI1R_STID ((uint32_t)0xFFE00000) ã1CAN_TDT1R_DLC ((uint32_t)0x0000000F) ä1CAN_TDT1R_TGT ((uint32_t)0x00000100) å1CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) è1CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) é1CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) ê1CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) ë1CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) î1CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) ï1CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) ð1CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) ñ1CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) ô1CAN_TI2R_TXRQ ((uint32_t)0x00000001) õ1CAN_TI2R_RTR ((uint32_t)0x00000002) ö1CAN_TI2R_IDE ((uint32_t)0x00000004) ÷1CAN_TI2R_EXID ((uint32_t)0x001FFFF8) ø1CAN_TI2R_STID ((uint32_t)0xFFE00000) û1CAN_TDT2R_DLC ((uint32_t)0x0000000F) ü1CAN_TDT2R_TGT ((uint32_t)0x00000100) ý1CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) 2CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) 2CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) 2CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) 2CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) 2CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) 2CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) 2CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) 2CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) 2CAN_RI0R_RTR ((uint32_t)0x00000002) 2CAN_RI0R_IDE ((uint32_t)0x00000004) 2CAN_RI0R_EXID ((uint32_t)0x001FFFF8) 2CAN_RI0R_STID ((uint32_t)0xFFE00000) 2CAN_RDT0R_DLC ((uint32_t)0x0000000F) 2CAN_RDT0R_FMI ((uint32_t)0x0000FF00) 2CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 2CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 2CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 2CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) 2CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 2CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 2CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 2CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 2CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) £2CAN_RI1R_RTR ((uint32_t)0x00000002) ¤2CAN_RI1R_IDE ((uint32_t)0x00000004) ¥2CAN_RI1R_EXID ((uint32_t)0x001FFFF8) ¦2CAN_RI1R_STID ((uint32_t)0xFFE00000) ©2CAN_RDT1R_DLC ((uint32_t)0x0000000F) ª2CAN_RDT1R_FMI ((uint32_t)0x0000FF00) «2CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) ®2CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) ¯2CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) °2CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) ±2CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) ´2CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) µ2CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) ¶2CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) ·2CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) »2CAN_FMR_FINIT ((uint8_t)0x01) ¾2CAN_FM1R_FBM ((uint16_t)0x3FFF) ¿2CAN_FM1R_FBM0 ((uint16_t)0x0001) À2CAN_FM1R_FBM1 ((uint16_t)0x0002) Á2CAN_FM1R_FBM2 ((uint16_t)0x0004) Â2CAN_FM1R_FBM3 ((uint16_t)0x0008) Ã2CAN_FM1R_FBM4 ((uint16_t)0x0010) Ä2CAN_FM1R_FBM5 ((uint16_t)0x0020) Å2CAN_FM1R_FBM6 ((uint16_t)0x0040) Æ2CAN_FM1R_FBM7 ((uint16_t)0x0080) Ç2CAN_FM1R_FBM8 ((uint16_t)0x0100) È2CAN_FM1R_FBM9 ((uint16_t)0x0200) É2CAN_FM1R_FBM10 ((uint16_t)0x0400) Ê2CAN_FM1R_FBM11 ((uint16_t)0x0800) Ë2CAN_FM1R_FBM12 ((uint16_t)0x1000) Ì2CAN_FM1R_FBM13 ((uint16_t)0x2000) Ï2CAN_FS1R_FSC ((uint16_t)0x3FFF) Ð2CAN_FS1R_FSC0 ((uint16_t)0x0001) Ñ2CAN_FS1R_FSC1 ((uint16_t)0x0002) Ò2CAN_FS1R_FSC2 ((uint16_t)0x0004) Ó2CAN_FS1R_FSC3 ((uint16_t)0x0008) Ô2CAN_FS1R_FSC4 ((uint16_t)0x0010) Õ2CAN_FS1R_FSC5 ((uint16_t)0x0020) Ö2CAN_FS1R_FSC6 ((uint16_t)0x0040) ×2CAN_FS1R_FSC7 ((uint16_t)0x0080) Ø2CAN_FS1R_FSC8 ((uint16_t)0x0100) Ù2CAN_FS1R_FSC9 ((uint16_t)0x0200) Ú2CAN_FS1R_FSC10 ((uint16_t)0x0400) Û2CAN_FS1R_FSC11 ((uint16_t)0x0800) Ü2CAN_FS1R_FSC12 ((uint16_t)0x1000) Ý2CAN_FS1R_FSC13 ((uint16_t)0x2000) à2CAN_FFA1R_FFA ((uint16_t)0x3FFF) á2CAN_FFA1R_FFA0 ((uint16_t)0x0001) â2CAN_FFA1R_FFA1 ((uint16_t)0x0002) ã2CAN_FFA1R_FFA2 ((uint16_t)0x0004) ä2CAN_FFA1R_FFA3 ((uint16_t)0x0008) å2CAN_FFA1R_FFA4 ((uint16_t)0x0010) æ2CAN_FFA1R_FFA5 ((uint16_t)0x0020) ç2CAN_FFA1R_FFA6 ((uint16_t)0x0040) è2CAN_FFA1R_FFA7 ((uint16_t)0x0080) é2CAN_FFA1R_FFA8 ((uint16_t)0x0100) ê2CAN_FFA1R_FFA9 ((uint16_t)0x0200) ë2CAN_FFA1R_FFA10 ((uint16_t)0x0400) ì2CAN_FFA1R_FFA11 ((uint16_t)0x0800) í2CAN_FFA1R_FFA12 ((uint16_t)0x1000) î2CAN_FFA1R_FFA13 ((uint16_t)0x2000) ñ2CAN_FA1R_FACT ((uint16_t)0x3FFF) ò2CAN_FA1R_FACT0 ((uint16_t)0x0001) ó2CAN_FA1R_FACT1 ((uint16_t)0x0002) ô2CAN_FA1R_FACT2 ((uint16_t)0x0004) õ2CAN_FA1R_FACT3 ((uint16_t)0x0008) ö2CAN_FA1R_FACT4 ((uint16_t)0x0010) ÷2CAN_FA1R_FACT5 ((uint16_t)0x0020) ø2CAN_FA1R_FACT6 ((uint16_t)0x0040) ù2CAN_FA1R_FACT7 ((uint16_t)0x0080) ú2CAN_FA1R_FACT8 ((uint16_t)0x0100) û2CAN_FA1R_FACT9 ((uint16_t)0x0200) ü2CAN_FA1R_FACT10 ((uint16_t)0x0400) ý2CAN_FA1R_FACT11 ((uint16_t)0x0800) þ2CAN_FA1R_FACT12 ((uint16_t)0x1000) ÿ2CAN_FA1R_FACT13 ((uint16_t)0x2000) 3CAN_F0R1_FB0 ((uint32_t)0x00000001) 3CAN_F0R1_FB1 ((uint32_t)0x00000002) 3CAN_F0R1_FB2 ((uint32_t)0x00000004)
3CAN_F0R1_FB3 ((uint32_t)0x00000008) 3CAN_F0R1_FB4 ((uint32_t)0x00000010) 3CAN_F0R1_FB5 ((uint32_t)0x00000020) 3CAN_F0R1_FB6 ((uint32_t)0x00000040) 3CAN_F0R1_FB7 ((uint32_t)0x00000080) 3CAN_F0R1_FB8 ((uint32_t)0x00000100) 3CAN_F0R1_FB9 ((uint32_t)0x00000200) 3CAN_F0R1_FB10 ((uint32_t)0x00000400) 3CAN_F0R1_FB11 ((uint32_t)0x00000800) 3CAN_F0R1_FB12 ((uint32_t)0x00001000) 3CAN_F0R1_FB13 ((uint32_t)0x00002000) 3CAN_F0R1_FB14 ((uint32_t)0x00004000) 3CAN_F0R1_FB15 ((uint32_t)0x00008000) 3CAN_F0R1_FB16 ((uint32_t)0x00010000) 3CAN_F0R1_FB17 ((uint32_t)0x00020000) 3CAN_F0R1_FB18 ((uint32_t)0x00040000) 3CAN_F0R1_FB19 ((uint32_t)0x00080000) 3CAN_F0R1_FB20 ((uint32_t)0x00100000) 3CAN_F0R1_FB21 ((uint32_t)0x00200000) 3CAN_F0R1_FB22 ((uint32_t)0x00400000) 3CAN_F0R1_FB23 ((uint32_t)0x00800000) 3CAN_F0R1_FB24 ((uint32_t)0x01000000) 3CAN_F0R1_FB25 ((uint32_t)0x02000000) 3CAN_F0R1_FB26 ((uint32_t)0x04000000) 3CAN_F0R1_FB27 ((uint32_t)0x08000000) 3CAN_F0R1_FB28 ((uint32_t)0x10000000) 3CAN_F0R1_FB29 ((uint32_t)0x20000000) 3CAN_F0R1_FB30 ((uint32_t)0x40000000) ¡3CAN_F0R1_FB31 ((uint32_t)0x80000000) ¤3CAN_F1R1_FB0 ((uint32_t)0x00000001) ¥3CAN_F1R1_FB1 ((uint32_t)0x00000002) ¦3CAN_F1R1_FB2 ((uint32_t)0x00000004) §3CAN_F1R1_FB3 ((uint32_t)0x00000008) ¨3CAN_F1R1_FB4 ((uint32_t)0x00000010) ©3CAN_F1R1_FB5 ((uint32_t)0x00000020) ª3CAN_F1R1_FB6 ((uint32_t)0x00000040) «3CAN_F1R1_FB7 ((uint32_t)0x00000080) ¬3CAN_F1R1_FB8 ((uint32_t)0x00000100) 3CAN_F1R1_FB9 ((uint32_t)0x00000200) ®3CAN_F1R1_FB10 ((uint32_t)0x00000400) ¯3CAN_F1R1_FB11 ((uint32_t)0x00000800) °3CAN_F1R1_FB12 ((uint32_t)0x00001000) ±3CAN_F1R1_FB13 ((uint32_t)0x00002000) ²3CAN_F1R1_FB14 ((uint32_t)0x00004000) ³3CAN_F1R1_FB15 ((uint32_t)0x00008000) ´3CAN_F1R1_FB16 ((uint32_t)0x00010000) µ3CAN_F1R1_FB17 ((uint32_t)0x00020000) ¶3CAN_F1R1_FB18 ((uint32_t)0x00040000) ·3CAN_F1R1_FB19 ((uint32_t)0x00080000) ¸3CAN_F1R1_FB20 ((uint32_t)0x00100000) ¹3CAN_F1R1_FB21 ((uint32_t)0x00200000) º3CAN_F1R1_FB22 ((uint32_t)0x00400000) »3CAN_F1R1_FB23 ((uint32_t)0x00800000) ¼3CAN_F1R1_FB24 ((uint32_t)0x01000000) ½3CAN_F1R1_FB25 ((uint32_t)0x02000000) ¾3CAN_F1R1_FB26 ((uint32_t)0x04000000) ¿3CAN_F1R1_FB27 ((uint32_t)0x08000000) À3CAN_F1R1_FB28 ((uint32_t)0x10000000) Á3CAN_F1R1_FB29 ((uint32_t)0x20000000) Â3CAN_F1R1_FB30 ((uint32_t)0x40000000) Ã3CAN_F1R1_FB31 ((uint32_t)0x80000000) Æ3CAN_F2R1_FB0 ((uint32_t)0x00000001) Ç3CAN_F2R1_FB1 ((uint32_t)0x00000002) È3CAN_F2R1_FB2 ((uint32_t)0x00000004) É3CAN_F2R1_FB3 ((uint32_t)0x00000008) Ê3CAN_F2R1_FB4 ((uint32_t)0x00000010) Ë3CAN_F2R1_FB5 ((uint32_t)0x00000020) Ì3CAN_F2R1_FB6 ((uint32_t)0x00000040) Í3CAN_F2R1_FB7 ((uint32_t)0x00000080) Î3CAN_F2R1_FB8 ((uint32_t)0x00000100) Ï3CAN_F2R1_FB9 ((uint32_t)0x00000200) Ð3CAN_F2R1_FB10 ((uint32_t)0x00000400) Ñ3CAN_F2R1_FB11 ((uint32_t)0x00000800) Ò3CAN_F2R1_FB12 ((uint32_t)0x00001000) Ó3CAN_F2R1_FB13 ((uint32_t)0x00002000) Ô3CAN_F2R1_FB14 ((uint32_t)0x00004000) Õ3CAN_F2R1_FB15 ((uint32_t)0x00008000) Ö3CAN_F2R1_FB16 ((uint32_t)0x00010000) ×3CAN_F2R1_FB17 ((uint32_t)0x00020000) Ø3CAN_F2R1_FB18 ((uint32_t)0x00040000) Ù3CAN_F2R1_FB19 ((uint32_t)0x00080000) Ú3CAN_F2R1_FB20 ((uint32_t)0x00100000) Û3CAN_F2R1_FB21 ((uint32_t)0x00200000) Ü3CAN_F2R1_FB22 ((uint32_t)0x00400000) Ý3CAN_F2R1_FB23 ((uint32_t)0x00800000) Þ3CAN_F2R1_FB24 ((uint32_t)0x01000000) ß3CAN_F2R1_FB25 ((uint32_t)0x02000000) à3CAN_F2R1_FB26 ((uint32_t)0x04000000) á3CAN_F2R1_FB27 ((uint32_t)0x08000000) â3CAN_F2R1_FB28 ((uint32_t)0x10000000) ã3CAN_F2R1_FB29 ((uint32_t)0x20000000) ä3CAN_F2R1_FB30 ((uint32_t)0x40000000) å3CAN_F2R1_FB31 ((uint32_t)0x80000000) è3CAN_F3R1_FB0 ((uint32_t)0x00000001) é3CAN_F3R1_FB1 ((uint32_t)0x00000002) ê3CAN_F3R1_FB2 ((uint32_t)0x00000004) ë3CAN_F3R1_FB3 ((uint32_t)0x00000008) ì3CAN_F3R1_FB4 ((uint32_t)0x00000010) í3CAN_F3R1_FB5 ((uint32_t)0x00000020) î3CAN_F3R1_FB6 ((uint32_t)0x00000040) ï3CAN_F3R1_FB7 ((uint32_t)0x00000080) ð3CAN_F3R1_FB8 ((uint32_t)0x00000100) ñ3CAN_F3R1_FB9 ((uint32_t)0x00000200) ò3CAN_F3R1_FB10 ((uint32_t)0x00000400) ó3CAN_F3R1_FB11 ((uint32_t)0x00000800) ô3CAN_F3R1_FB12 ((uint32_t)0x00001000) õ3CAN_F3R1_FB13 ((uint32_t)0x00002000) ö3CAN_F3R1_FB14 ((uint32_t)0x00004000) ÷3CAN_F3R1_FB15 ((uint32_t)0x00008000) ø3CAN_F3R1_FB16 ((uint32_t)0x00010000) ù3CAN_F3R1_FB17 ((uint32_t)0x00020000) ú3CAN_F3R1_FB18 ((uint32_t)0x00040000) û3CAN_F3R1_FB19 ((uint32_t)0x00080000) ü3CAN_F3R1_FB20 ((uint32_t)0x00100000) ý3CAN_F3R1_FB21 ((uint32_t)0x00200000) þ3CAN_F3R1_FB22 ((uint32_t)0x00400000) ÿ3CAN_F3R1_FB23 ((uint32_t)0x00800000) 4CAN_F3R1_FB24 ((uint32_t)0x01000000) 4CAN_F3R1_FB25 ((uint32_t)0x02000000) 4CAN_F3R1_FB26 ((uint32_t)0x04000000) 4CAN_F3R1_FB27 ((uint32_t)0x08000000) 4CAN_F3R1_FB28 ((uint32_t)0x10000000)
4CAN_F3R1_FB29 ((uint32_t)0x20000000) 4CAN_F3R1_FB30 ((uint32_t)0x40000000) 4CAN_F3R1_FB31 ((uint32_t)0x80000000) 4CAN_F4R1_FB0 ((uint32_t)0x00000001) 4CAN_F4R1_FB1 ((uint32_t)0x00000002) 4CAN_F4R1_FB2 ((uint32_t)0x00000004) 4CAN_F4R1_FB3 ((uint32_t)0x00000008) 4CAN_F4R1_FB4 ((uint32_t)0x00000010) 4CAN_F4R1_FB5 ((uint32_t)0x00000020) 4CAN_F4R1_FB6 ((uint32_t)0x00000040) 4CAN_F4R1_FB7 ((uint32_t)0x00000080) 4CAN_F4R1_FB8 ((uint32_t)0x00000100) 4CAN_F4R1_FB9 ((uint32_t)0x00000200) 4CAN_F4R1_FB10 ((uint32_t)0x00000400) 4CAN_F4R1_FB11 ((uint32_t)0x00000800) 4CAN_F4R1_FB12 ((uint32_t)0x00001000) 4CAN_F4R1_FB13 ((uint32_t)0x00002000) 4CAN_F4R1_FB14 ((uint32_t)0x00004000) 4CAN_F4R1_FB15 ((uint32_t)0x00008000) 4CAN_F4R1_FB16 ((uint32_t)0x00010000) 4CAN_F4R1_FB17 ((uint32_t)0x00020000) 4CAN_F4R1_FB18 ((uint32_t)0x00040000) 4CAN_F4R1_FB19 ((uint32_t)0x00080000) 4CAN_F4R1_FB20 ((uint32_t)0x00100000) 4CAN_F4R1_FB21 ((uint32_t)0x00200000) 4CAN_F4R1_FB22 ((uint32_t)0x00400000) ¡4CAN_F4R1_FB23 ((uint32_t)0x00800000) ¢4CAN_F4R1_FB24 ((uint32_t)0x01000000) £4CAN_F4R1_FB25 ((uint32_t)0x02000000) ¤4CAN_F4R1_FB26 ((uint32_t)0x04000000) ¥4CAN_F4R1_FB27 ((uint32_t)0x08000000) ¦4CAN_F4R1_FB28 ((uint32_t)0x10000000) §4CAN_F4R1_FB29 ((uint32_t)0x20000000) ¨4CAN_F4R1_FB30 ((uint32_t)0x40000000) ©4CAN_F4R1_FB31 ((uint32_t)0x80000000) ¬4CAN_F5R1_FB0 ((uint32_t)0x00000001) 4CAN_F5R1_FB1 ((uint32_t)0x00000002) ®4CAN_F5R1_FB2 ((uint32_t)0x00000004) ¯4CAN_F5R1_FB3 ((uint32_t)0x00000008) °4CAN_F5R1_FB4 ((uint32_t)0x00000010) ±4CAN_F5R1_FB5 ((uint32_t)0x00000020) ²4CAN_F5R1_FB6 ((uint32_t)0x00000040) ³4CAN_F5R1_FB7 ((uint32_t)0x00000080) ´4CAN_F5R1_FB8 ((uint32_t)0x00000100) µ4CAN_F5R1_FB9 ((uint32_t)0x00000200) ¶4CAN_F5R1_FB10 ((uint32_t)0x00000400) ·4CAN_F5R1_FB11 ((uint32_t)0x00000800) ¸4CAN_F5R1_FB12 ((uint32_t)0x00001000) ¹4CAN_F5R1_FB13 ((uint32_t)0x00002000) º4CAN_F5R1_FB14 ((uint32_t)0x00004000) »4CAN_F5R1_FB15 ((uint32_t)0x00008000) ¼4CAN_F5R1_FB16 ((uint32_t)0x00010000) ½4CAN_F5R1_FB17 ((uint32_t)0x00020000) ¾4CAN_F5R1_FB18 ((uint32_t)0x00040000) ¿4CAN_F5R1_FB19 ((uint32_t)0x00080000) À4CAN_F5R1_FB20 ((uint32_t)0x00100000) Á4CAN_F5R1_FB21 ((uint32_t)0x00200000) Â4CAN_F5R1_FB22 ((uint32_t)0x00400000) Ã4CAN_F5R1_FB23 ((uint32_t)0x00800000) Ä4CAN_F5R1_FB24 ((uint32_t)0x01000000) Å4CAN_F5R1_FB25 ((uint32_t)0x02000000) Æ4CAN_F5R1_FB26 ((uint32_t)0x04000000) Ç4CAN_F5R1_FB27 ((uint32_t)0x08000000) È4CAN_F5R1_FB28 ((uint32_t)0x10000000) É4CAN_F5R1_FB29 ((uint32_t)0x20000000) Ê4CAN_F5R1_FB30 ((uint32_t)0x40000000) Ë4CAN_F5R1_FB31 ((uint32_t)0x80000000) Î4CAN_F6R1_FB0 ((uint32_t)0x00000001) Ï4CAN_F6R1_FB1 ((uint32_t)0x00000002) Ð4CAN_F6R1_FB2 ((uint32_t)0x00000004) Ñ4CAN_F6R1_FB3 ((uint32_t)0x00000008) Ò4CAN_F6R1_FB4 ((uint32_t)0x00000010) Ó4CAN_F6R1_FB5 ((uint32_t)0x00000020) Ô4CAN_F6R1_FB6 ((uint32_t)0x00000040) Õ4CAN_F6R1_FB7 ((uint32_t)0x00000080) Ö4CAN_F6R1_FB8 ((uint32_t)0x00000100) ×4CAN_F6R1_FB9 ((uint32_t)0x00000200) Ø4CAN_F6R1_FB10 ((uint32_t)0x00000400) Ù4CAN_F6R1_FB11 ((uint32_t)0x00000800) Ú4CAN_F6R1_FB12 ((uint32_t)0x00001000) Û4CAN_F6R1_FB13 ((uint32_t)0x00002000) Ü4CAN_F6R1_FB14 ((uint32_t)0x00004000) Ý4CAN_F6R1_FB15 ((uint32_t)0x00008000) Þ4CAN_F6R1_FB16 ((uint32_t)0x00010000) ß4CAN_F6R1_FB17 ((uint32_t)0x00020000) à4CAN_F6R1_FB18 ((uint32_t)0x00040000) á4CAN_F6R1_FB19 ((uint32_t)0x00080000) â4CAN_F6R1_FB20 ((uint32_t)0x00100000) ã4CAN_F6R1_FB21 ((uint32_t)0x00200000) ä4CAN_F6R1_FB22 ((uint32_t)0x00400000) å4CAN_F6R1_FB23 ((uint32_t)0x00800000) æ4CAN_F6R1_FB24 ((uint32_t)0x01000000) ç4CAN_F6R1_FB25 ((uint32_t)0x02000000) è4CAN_F6R1_FB26 ((uint32_t)0x04000000) é4CAN_F6R1_FB27 ((uint32_t)0x08000000) ê4CAN_F6R1_FB28 ((uint32_t)0x10000000) ë4CAN_F6R1_FB29 ((uint32_t)0x20000000) ì4CAN_F6R1_FB30 ((uint32_t)0x40000000) í4CAN_F6R1_FB31 ((uint32_t)0x80000000) ð4CAN_F7R1_FB0 ((uint32_t)0x00000001) ñ4CAN_F7R1_FB1 ((uint32_t)0x00000002) ò4CAN_F7R1_FB2 ((uint32_t)0x00000004) ó4CAN_F7R1_FB3 ((uint32_t)0x00000008) ô4CAN_F7R1_FB4 ((uint32_t)0x00000010) õ4CAN_F7R1_FB5 ((uint32_t)0x00000020) ö4CAN_F7R1_FB6 ((uint32_t)0x00000040) ÷4CAN_F7R1_FB7 ((uint32_t)0x00000080) ø4CAN_F7R1_FB8 ((uint32_t)0x00000100) ù4CAN_F7R1_FB9 ((uint32_t)0x00000200) ú4CAN_F7R1_FB10 ((uint32_t)0x00000400) û4CAN_F7R1_FB11 ((uint32_t)0x00000800) ü4CAN_F7R1_FB12 ((uint32_t)0x00001000) ý4CAN_F7R1_FB13 ((uint32_t)0x00002000) þ4CAN_F7R1_FB14 ((uint32_t)0x00004000) ÿ4CAN_F7R1_FB15 ((uint32_t)0x00008000) 5CAN_F7R1_FB16 ((uint32_t)0x00010000) 5CAN_F7R1_FB17 ((uint32_t)0x00020000) 5CAN_F7R1_FB18 ((uint32_t)0x00040000) 5CAN_F7R1_FB19 ((uint32_t)0x00080000) 5CAN_F7R1_FB20 ((uint32_t)0x00100000)
5CAN_F7R1_FB21 ((uint32_t)0x00200000) 5CAN_F7R1_FB22 ((uint32_t)0x00400000) 5CAN_F7R1_FB23 ((uint32_t)0x00800000) 5CAN_F7R1_FB24 ((uint32_t)0x01000000) 5CAN_F7R1_FB25 ((uint32_t)0x02000000) 5CAN_F7R1_FB26 ((uint32_t)0x04000000) 5CAN_F7R1_FB27 ((uint32_t)0x08000000) 5CAN_F7R1_FB28 ((uint32_t)0x10000000) 5CAN_F7R1_FB29 ((uint32_t)0x20000000) 5CAN_F7R1_FB30 ((uint32_t)0x40000000) 5CAN_F7R1_FB31 ((uint32_t)0x80000000) 5CAN_F8R1_FB0 ((uint32_t)0x00000001) 5CAN_F8R1_FB1 ((uint32_t)0x00000002) 5CAN_F8R1_FB2 ((uint32_t)0x00000004) 5CAN_F8R1_FB3 ((uint32_t)0x00000008) 5CAN_F8R1_FB4 ((uint32_t)0x00000010) 5CAN_F8R1_FB5 ((uint32_t)0x00000020) 5CAN_F8R1_FB6 ((uint32_t)0x00000040) 5CAN_F8R1_FB7 ((uint32_t)0x00000080) 5CAN_F8R1_FB8 ((uint32_t)0x00000100) 5CAN_F8R1_FB9 ((uint32_t)0x00000200) 5CAN_F8R1_FB10 ((uint32_t)0x00000400) 5CAN_F8R1_FB11 ((uint32_t)0x00000800) 5CAN_F8R1_FB12 ((uint32_t)0x00001000) 5CAN_F8R1_FB13 ((uint32_t)0x00002000) 5CAN_F8R1_FB14 ((uint32_t)0x00004000) ¡5CAN_F8R1_FB15 ((uint32_t)0x00008000) ¢5CAN_F8R1_FB16 ((uint32_t)0x00010000) £5CAN_F8R1_FB17 ((uint32_t)0x00020000) ¤5CAN_F8R1_FB18 ((uint32_t)0x00040000) ¥5CAN_F8R1_FB19 ((uint32_t)0x00080000) ¦5CAN_F8R1_FB20 ((uint32_t)0x00100000) §5CAN_F8R1_FB21 ((uint32_t)0x00200000) ¨5CAN_F8R1_FB22 ((uint32_t)0x00400000) ©5CAN_F8R1_FB23 ((uint32_t)0x00800000) ª5CAN_F8R1_FB24 ((uint32_t)0x01000000) «5CAN_F8R1_FB25 ((uint32_t)0x02000000) ¬5CAN_F8R1_FB26 ((uint32_t)0x04000000) 5CAN_F8R1_FB27 ((uint32_t)0x08000000) ®5CAN_F8R1_FB28 ((uint32_t)0x10000000) ¯5CAN_F8R1_FB29 ((uint32_t)0x20000000) °5CAN_F8R1_FB30 ((uint32_t)0x40000000) ±5CAN_F8R1_FB31 ((uint32_t)0x80000000) ´5CAN_F9R1_FB0 ((uint32_t)0x00000001) µ5CAN_F9R1_FB1 ((uint32_t)0x00000002) ¶5CAN_F9R1_FB2 ((uint32_t)0x00000004) ·5CAN_F9R1_FB3 ((uint32_t)0x00000008) ¸5CAN_F9R1_FB4 ((uint32_t)0x00000010) ¹5CAN_F9R1_FB5 ((uint32_t)0x00000020) º5CAN_F9R1_FB6 ((uint32_t)0x00000040) »5CAN_F9R1_FB7 ((uint32_t)0x00000080) ¼5CAN_F9R1_FB8 ((uint32_t)0x00000100) ½5CAN_F9R1_FB9 ((uint32_t)0x00000200) ¾5CAN_F9R1_FB10 ((uint32_t)0x00000400) ¿5CAN_F9R1_FB11 ((uint32_t)0x00000800) À5CAN_F9R1_FB12 ((uint32_t)0x00001000) Á5CAN_F9R1_FB13 ((uint32_t)0x00002000) Â5CAN_F9R1_FB14 ((uint32_t)0x00004000) Ã5CAN_F9R1_FB15 ((uint32_t)0x00008000) Ä5CAN_F9R1_FB16 ((uint32_t)0x00010000) Å5CAN_F9R1_FB17 ((uint32_t)0x00020000) Æ5CAN_F9R1_FB18 ((uint32_t)0x00040000) Ç5CAN_F9R1_FB19 ((uint32_t)0x00080000) È5CAN_F9R1_FB20 ((uint32_t)0x00100000) É5CAN_F9R1_FB21 ((uint32_t)0x00200000) Ê5CAN_F9R1_FB22 ((uint32_t)0x00400000) Ë5CAN_F9R1_FB23 ((uint32_t)0x00800000) Ì5CAN_F9R1_FB24 ((uint32_t)0x01000000) Í5CAN_F9R1_FB25 ((uint32_t)0x02000000) Î5CAN_F9R1_FB26 ((uint32_t)0x04000000) Ï5CAN_F9R1_FB27 ((uint32_t)0x08000000) Ð5CAN_F9R1_FB28 ((uint32_t)0x10000000) Ñ5CAN_F9R1_FB29 ((uint32_t)0x20000000) Ò5CAN_F9R1_FB30 ((uint32_t)0x40000000) Ó5CAN_F9R1_FB31 ((uint32_t)0x80000000) Ö5CAN_F10R1_FB0 ((uint32_t)0x00000001) ×5CAN_F10R1_FB1 ((uint32_t)0x00000002) Ø5CAN_F10R1_FB2 ((uint32_t)0x00000004) Ù5CAN_F10R1_FB3 ((uint32_t)0x00000008) Ú5CAN_F10R1_FB4 ((uint32_t)0x00000010) Û5CAN_F10R1_FB5 ((uint32_t)0x00000020) Ü5CAN_F10R1_FB6 ((uint32_t)0x00000040) Ý5CAN_F10R1_FB7 ((uint32_t)0x00000080) Þ5CAN_F10R1_FB8 ((uint32_t)0x00000100) ß5CAN_F10R1_FB9 ((uint32_t)0x00000200) à5CAN_F10R1_FB10 ((uint32_t)0x00000400) á5CAN_F10R1_FB11 ((uint32_t)0x00000800) â5CAN_F10R1_FB12 ((uint32_t)0x00001000) ã5CAN_F10R1_FB13 ((uint32_t)0x00002000) ä5CAN_F10R1_FB14 ((uint32_t)0x00004000) å5CAN_F10R1_FB15 ((uint32_t)0x00008000) æ5CAN_F10R1_FB16 ((uint32_t)0x00010000) ç5CAN_F10R1_FB17 ((uint32_t)0x00020000) è5CAN_F10R1_FB18 ((uint32_t)0x00040000) é5CAN_F10R1_FB19 ((uint32_t)0x00080000) ê5CAN_F10R1_FB20 ((uint32_t)0x00100000) ë5CAN_F10R1_FB21 ((uint32_t)0x00200000) ì5CAN_F10R1_FB22 ((uint32_t)0x00400000) í5CAN_F10R1_FB23 ((uint32_t)0x00800000) î5CAN_F10R1_FB24 ((uint32_t)0x01000000) ï5CAN_F10R1_FB25 ((uint32_t)0x02000000) ð5CAN_F10R1_FB26 ((uint32_t)0x04000000) ñ5CAN_F10R1_FB27 ((uint32_t)0x08000000) ò5CAN_F10R1_FB28 ((uint32_t)0x10000000) ó5CAN_F10R1_FB29 ((uint32_t)0x20000000) ô5CAN_F10R1_FB30 ((uint32_t)0x40000000) õ5CAN_F10R1_FB31 ((uint32_t)0x80000000) ø5CAN_F11R1_FB0 ((uint32_t)0x00000001) ù5CAN_F11R1_FB1 ((uint32_t)0x00000002) ú5CAN_F11R1_FB2 ((uint32_t)0x00000004) û5CAN_F11R1_FB3 ((uint32_t)0x00000008) ü5CAN_F11R1_FB4 ((uint32_t)0x00000010) ý5CAN_F11R1_FB5 ((uint32_t)0x00000020) þ5CAN_F11R1_FB6 ((uint32_t)0x00000040) ÿ5CAN_F11R1_FB7 ((uint32_t)0x00000080) 6CAN_F11R1_FB8 ((uint32_t)0x00000100) 6CAN_F11R1_FB9 ((uint32_t)0x00000200) 6CAN_F11R1_FB10 ((uint32_t)0x00000400) 6CAN_F11R1_FB11 ((uint32_t)0x00000800) 6CAN_F11R1_FB12 ((uint32_t)0x00001000)
6CAN_F11R1_FB13 ((uint32_t)0x00002000) 6CAN_F11R1_FB14 ((uint32_t)0x00004000) 6CAN_F11R1_FB15 ((uint32_t)0x00008000) 6CAN_F11R1_FB16 ((uint32_t)0x00010000) 6CAN_F11R1_FB17 ((uint32_t)0x00020000) 6CAN_F11R1_FB18 ((uint32_t)0x00040000) 6CAN_F11R1_FB19 ((uint32_t)0x00080000) 6CAN_F11R1_FB20 ((uint32_t)0x00100000) 6CAN_F11R1_FB21 ((uint32_t)0x00200000) 6CAN_F11R1_FB22 ((uint32_t)0x00400000) 6CAN_F11R1_FB23 ((uint32_t)0x00800000) 6CAN_F11R1_FB24 ((uint32_t)0x01000000) 6CAN_F11R1_FB25 ((uint32_t)0x02000000) 6CAN_F11R1_FB26 ((uint32_t)0x04000000) 6CAN_F11R1_FB27 ((uint32_t)0x08000000) 6CAN_F11R1_FB28 ((uint32_t)0x10000000) 6CAN_F11R1_FB29 ((uint32_t)0x20000000) 6CAN_F11R1_FB30 ((uint32_t)0x40000000) 6CAN_F11R1_FB31 ((uint32_t)0x80000000) 6CAN_F12R1_FB0 ((uint32_t)0x00000001) 6CAN_F12R1_FB1 ((uint32_t)0x00000002) 6CAN_F12R1_FB2 ((uint32_t)0x00000004) 6CAN_F12R1_FB3 ((uint32_t)0x00000008) 6CAN_F12R1_FB4 ((uint32_t)0x00000010) 6CAN_F12R1_FB5 ((uint32_t)0x00000020) 6CAN_F12R1_FB6 ((uint32_t)0x00000040) ¡6CAN_F12R1_FB7 ((uint32_t)0x00000080) ¢6CAN_F12R1_FB8 ((uint32_t)0x00000100) £6CAN_F12R1_FB9 ((uint32_t)0x00000200) ¤6CAN_F12R1_FB10 ((uint32_t)0x00000400) ¥6CAN_F12R1_FB11 ((uint32_t)0x00000800) ¦6CAN_F12R1_FB12 ((uint32_t)0x00001000) §6CAN_F12R1_FB13 ((uint32_t)0x00002000) ¨6CAN_F12R1_FB14 ((uint32_t)0x00004000) ©6CAN_F12R1_FB15 ((uint32_t)0x00008000) ª6CAN_F12R1_FB16 ((uint32_t)0x00010000) «6CAN_F12R1_FB17 ((uint32_t)0x00020000) ¬6CAN_F12R1_FB18 ((uint32_t)0x00040000) 6CAN_F12R1_FB19 ((uint32_t)0x00080000) ®6CAN_F12R1_FB20 ((uint32_t)0x00100000) ¯6CAN_F12R1_FB21 ((uint32_t)0x00200000) °6CAN_F12R1_FB22 ((uint32_t)0x00400000) ±6CAN_F12R1_FB23 ((uint32_t)0x00800000) ²6CAN_F12R1_FB24 ((uint32_t)0x01000000) ³6CAN_F12R1_FB25 ((uint32_t)0x02000000) ´6CAN_F12R1_FB26 ((uint32_t)0x04000000) µ6CAN_F12R1_FB27 ((uint32_t)0x08000000) ¶6CAN_F12R1_FB28 ((uint32_t)0x10000000) ·6CAN_F12R1_FB29 ((uint32_t)0x20000000) ¸6CAN_F12R1_FB30 ((uint32_t)0x40000000) ¹6CAN_F12R1_FB31 ((uint32_t)0x80000000) ¼6CAN_F13R1_FB0 ((uint32_t)0x00000001) ½6CAN_F13R1_FB1 ((uint32_t)0x00000002) ¾6CAN_F13R1_FB2 ((uint32_t)0x00000004) ¿6CAN_F13R1_FB3 ((uint32_t)0x00000008) À6CAN_F13R1_FB4 ((uint32_t)0x00000010) Á6CAN_F13R1_FB5 ((uint32_t)0x00000020) Â6CAN_F13R1_FB6 ((uint32_t)0x00000040) Ã6CAN_F13R1_FB7 ((uint32_t)0x00000080) Ä6CAN_F13R1_FB8 ((uint32_t)0x00000100) Å6CAN_F13R1_FB9 ((uint32_t)0x00000200) Æ6CAN_F13R1_FB10 ((uint32_t)0x00000400) Ç6CAN_F13R1_FB11 ((uint32_t)0x00000800) È6CAN_F13R1_FB12 ((uint32_t)0x00001000) É6CAN_F13R1_FB13 ((uint32_t)0x00002000) Ê6CAN_F13R1_FB14 ((uint32_t)0x00004000) Ë6CAN_F13R1_FB15 ((uint32_t)0x00008000) Ì6CAN_F13R1_FB16 ((uint32_t)0x00010000) Í6CAN_F13R1_FB17 ((uint32_t)0x00020000) Î6CAN_F13R1_FB18 ((uint32_t)0x00040000) Ï6CAN_F13R1_FB19 ((uint32_t)0x00080000) Ð6CAN_F13R1_FB20 ((uint32_t)0x00100000) Ñ6CAN_F13R1_FB21 ((uint32_t)0x00200000) Ò6CAN_F13R1_FB22 ((uint32_t)0x00400000) Ó6CAN_F13R1_FB23 ((uint32_t)0x00800000) Ô6CAN_F13R1_FB24 ((uint32_t)0x01000000) Õ6CAN_F13R1_FB25 ((uint32_t)0x02000000) Ö6CAN_F13R1_FB26 ((uint32_t)0x04000000) ×6CAN_F13R1_FB27 ((uint32_t)0x08000000) Ø6CAN_F13R1_FB28 ((uint32_t)0x10000000) Ù6CAN_F13R1_FB29 ((uint32_t)0x20000000) Ú6CAN_F13R1_FB30 ((uint32_t)0x40000000) Û6CAN_F13R1_FB31 ((uint32_t)0x80000000) Þ6CAN_F0R2_FB0 ((uint32_t)0x00000001) ß6CAN_F0R2_FB1 ((uint32_t)0x00000002) à6CAN_F0R2_FB2 ((uint32_t)0x00000004) á6CAN_F0R2_FB3 ((uint32_t)0x00000008) â6CAN_F0R2_FB4 ((uint32_t)0x00000010) ã6CAN_F0R2_FB5 ((uint32_t)0x00000020) ä6CAN_F0R2_FB6 ((uint32_t)0x00000040) å6CAN_F0R2_FB7 ((uint32_t)0x00000080) æ6CAN_F0R2_FB8 ((uint32_t)0x00000100) ç6CAN_F0R2_FB9 ((uint32_t)0x00000200) è6CAN_F0R2_FB10 ((uint32_t)0x00000400) é6CAN_F0R2_FB11 ((uint32_t)0x00000800) ê6CAN_F0R2_FB12 ((uint32_t)0x00001000) ë6CAN_F0R2_FB13 ((uint32_t)0x00002000) ì6CAN_F0R2_FB14 ((uint32_t)0x00004000) í6CAN_F0R2_FB15 ((uint32_t)0x00008000) î6CAN_F0R2_FB16 ((uint32_t)0x00010000) ï6CAN_F0R2_FB17 ((uint32_t)0x00020000) ð6CAN_F0R2_FB18 ((uint32_t)0x00040000) ñ6CAN_F0R2_FB19 ((uint32_t)0x00080000) ò6CAN_F0R2_FB20 ((uint32_t)0x00100000) ó6CAN_F0R2_FB21 ((uint32_t)0x00200000) ô6CAN_F0R2_FB22 ((uint32_t)0x00400000) õ6CAN_F0R2_FB23 ((uint32_t)0x00800000) ö6CAN_F0R2_FB24 ((uint32_t)0x01000000) ÷6CAN_F0R2_FB25 ((uint32_t)0x02000000) ø6CAN_F0R2_FB26 ((uint32_t)0x04000000) ù6CAN_F0R2_FB27 ((uint32_t)0x08000000) ú6CAN_F0R2_FB28 ((uint32_t)0x10000000) û6CAN_F0R2_FB29 ((uint32_t)0x20000000) ü6CAN_F0R2_FB30 ((uint32_t)0x40000000) ý6CAN_F0R2_FB31 ((uint32_t)0x80000000) 7CAN_F1R2_FB0 ((uint32_t)0x00000001) 7CAN_F1R2_FB1 ((uint32_t)0x00000002) 7CAN_F1R2_FB2 ((uint32_t)0x00000004) 7CAN_F1R2_FB3 ((uint32_t)0x00000008) 7CAN_F1R2_FB4 ((uint32_t)0x00000010)
7CAN_F1R2_FB5 ((uint32_t)0x00000020) 7CAN_F1R2_FB6 ((uint32_t)0x00000040) 7CAN_F1R2_FB7 ((uint32_t)0x00000080) 7CAN_F1R2_FB8 ((uint32_t)0x00000100) 7CAN_F1R2_FB9 ((uint32_t)0x00000200) 7CAN_F1R2_FB10 ((uint32_t)0x00000400) 7CAN_F1R2_FB11 ((uint32_t)0x00000800) 7CAN_F1R2_FB12 ((uint32_t)0x00001000) 7CAN_F1R2_FB13 ((uint32_t)0x00002000) 7CAN_F1R2_FB14 ((uint32_t)0x00004000) 7CAN_F1R2_FB15 ((uint32_t)0x00008000) 7CAN_F1R2_FB16 ((uint32_t)0x00010000) 7CAN_F1R2_FB17 ((uint32_t)0x00020000) 7CAN_F1R2_FB18 ((uint32_t)0x00040000) 7CAN_F1R2_FB19 ((uint32_t)0x00080000) 7CAN_F1R2_FB20 ((uint32_t)0x00100000) 7CAN_F1R2_FB21 ((uint32_t)0x00200000) 7CAN_F1R2_FB22 ((uint32_t)0x00400000) 7CAN_F1R2_FB23 ((uint32_t)0x00800000) 7CAN_F1R2_FB24 ((uint32_t)0x01000000) 7CAN_F1R2_FB25 ((uint32_t)0x02000000) 7CAN_F1R2_FB26 ((uint32_t)0x04000000) 7CAN_F1R2_FB27 ((uint32_t)0x08000000) 7CAN_F1R2_FB28 ((uint32_t)0x10000000) 7CAN_F1R2_FB29 ((uint32_t)0x20000000) 7CAN_F1R2_FB30 ((uint32_t)0x40000000) 7CAN_F1R2_FB31 ((uint32_t)0x80000000) ¢7CAN_F2R2_FB0 ((uint32_t)0x00000001) £7CAN_F2R2_FB1 ((uint32_t)0x00000002) ¤7CAN_F2R2_FB2 ((uint32_t)0x00000004) ¥7CAN_F2R2_FB3 ((uint32_t)0x00000008) ¦7CAN_F2R2_FB4 ((uint32_t)0x00000010) §7CAN_F2R2_FB5 ((uint32_t)0x00000020) ¨7CAN_F2R2_FB6 ((uint32_t)0x00000040) ©7CAN_F2R2_FB7 ((uint32_t)0x00000080) ª7CAN_F2R2_FB8 ((uint32_t)0x00000100) «7CAN_F2R2_FB9 ((uint32_t)0x00000200) ¬7CAN_F2R2_FB10 ((uint32_t)0x00000400) 7CAN_F2R2_FB11 ((uint32_t)0x00000800) ®7CAN_F2R2_FB12 ((uint32_t)0x00001000) ¯7CAN_F2R2_FB13 ((uint32_t)0x00002000) °7CAN_F2R2_FB14 ((uint32_t)0x00004000) ±7CAN_F2R2_FB15 ((uint32_t)0x00008000) ²7CAN_F2R2_FB16 ((uint32_t)0x00010000) ³7CAN_F2R2_FB17 ((uint32_t)0x00020000) ´7CAN_F2R2_FB18 ((uint32_t)0x00040000) µ7CAN_F2R2_FB19 ((uint32_t)0x00080000) ¶7CAN_F2R2_FB20 ((uint32_t)0x00100000) ·7CAN_F2R2_FB21 ((uint32_t)0x00200000) ¸7CAN_F2R2_FB22 ((uint32_t)0x00400000) ¹7CAN_F2R2_FB23 ((uint32_t)0x00800000) º7CAN_F2R2_FB24 ((uint32_t)0x01000000) »7CAN_F2R2_FB25 ((uint32_t)0x02000000) ¼7CAN_F2R2_FB26 ((uint32_t)0x04000000) ½7CAN_F2R2_FB27 ((uint32_t)0x08000000) ¾7CAN_F2R2_FB28 ((uint32_t)0x10000000) ¿7CAN_F2R2_FB29 ((uint32_t)0x20000000) À7CAN_F2R2_FB30 ((uint32_t)0x40000000) Á7CAN_F2R2_FB31 ((uint32_t)0x80000000) Ä7CAN_F3R2_FB0 ((uint32_t)0x00000001) Å7CAN_F3R2_FB1 ((uint32_t)0x00000002) Æ7CAN_F3R2_FB2 ((uint32_t)0x00000004) Ç7CAN_F3R2_FB3 ((uint32_t)0x00000008) È7CAN_F3R2_FB4 ((uint32_t)0x00000010) É7CAN_F3R2_FB5 ((uint32_t)0x00000020) Ê7CAN_F3R2_FB6 ((uint32_t)0x00000040) Ë7CAN_F3R2_FB7 ((uint32_t)0x00000080) Ì7CAN_F3R2_FB8 ((uint32_t)0x00000100) Í7CAN_F3R2_FB9 ((uint32_t)0x00000200) Î7CAN_F3R2_FB10 ((uint32_t)0x00000400) Ï7CAN_F3R2_FB11 ((uint32_t)0x00000800) Ð7CAN_F3R2_FB12 ((uint32_t)0x00001000) Ñ7CAN_F3R2_FB13 ((uint32_t)0x00002000) Ò7CAN_F3R2_FB14 ((uint32_t)0x00004000) Ó7CAN_F3R2_FB15 ((uint32_t)0x00008000) Ô7CAN_F3R2_FB16 ((uint32_t)0x00010000) Õ7CAN_F3R2_FB17 ((uint32_t)0x00020000) Ö7CAN_F3R2_FB18 ((uint32_t)0x00040000) ×7CAN_F3R2_FB19 ((uint32_t)0x00080000) Ø7CAN_F3R2_FB20 ((uint32_t)0x00100000) Ù7CAN_F3R2_FB21 ((uint32_t)0x00200000) Ú7CAN_F3R2_FB22 ((uint32_t)0x00400000) Û7CAN_F3R2_FB23 ((uint32_t)0x00800000) Ü7CAN_F3R2_FB24 ((uint32_t)0x01000000) Ý7CAN_F3R2_FB25 ((uint32_t)0x02000000) Þ7CAN_F3R2_FB26 ((uint32_t)0x04000000) ß7CAN_F3R2_FB27 ((uint32_t)0x08000000) à7CAN_F3R2_FB28 ((uint32_t)0x10000000) á7CAN_F3R2_FB29 ((uint32_t)0x20000000) â7CAN_F3R2_FB30 ((uint32_t)0x40000000) ã7CAN_F3R2_FB31 ((uint32_t)0x80000000) æ7CAN_F4R2_FB0 ((uint32_t)0x00000001) ç7CAN_F4R2_FB1 ((uint32_t)0x00000002) è7CAN_F4R2_FB2 ((uint32_t)0x00000004) é7CAN_F4R2_FB3 ((uint32_t)0x00000008) ê7CAN_F4R2_FB4 ((uint32_t)0x00000010) ë7CAN_F4R2_FB5 ((uint32_t)0x00000020) ì7CAN_F4R2_FB6 ((uint32_t)0x00000040) í7CAN_F4R2_FB7 ((uint32_t)0x00000080) î7CAN_F4R2_FB8 ((uint32_t)0x00000100) ï7CAN_F4R2_FB9 ((uint32_t)0x00000200) ð7CAN_F4R2_FB10 ((uint32_t)0x00000400) ñ7CAN_F4R2_FB11 ((uint32_t)0x00000800) ò7CAN_F4R2_FB12 ((uint32_t)0x00001000) ó7CAN_F4R2_FB13 ((uint32_t)0x00002000) ô7CAN_F4R2_FB14 ((uint32_t)0x00004000) õ7CAN_F4R2_FB15 ((uint32_t)0x00008000) ö7CAN_F4R2_FB16 ((uint32_t)0x00010000) ÷7CAN_F4R2_FB17 ((uint32_t)0x00020000) ø7CAN_F4R2_FB18 ((uint32_t)0x00040000) ù7CAN_F4R2_FB19 ((uint32_t)0x00080000) ú7CAN_F4R2_FB20 ((uint32_t)0x00100000) û7CAN_F4R2_FB21 ((uint32_t)0x00200000) ü7CAN_F4R2_FB22 ((uint32_t)0x00400000) ý7CAN_F4R2_FB23 ((uint32_t)0x00800000) þ7CAN_F4R2_FB24 ((uint32_t)0x01000000) ÿ7CAN_F4R2_FB25 ((uint32_t)0x02000000) 8CAN_F4R2_FB26 ((uint32_t)0x04000000) 8CAN_F4R2_FB27 ((uint32_t)0x08000000) 8CAN_F4R2_FB28 ((uint32_t)0x10000000) 8CAN_F4R2_FB29 ((uint32_t)0x20000000) 8CAN_F4R2_FB30 ((uint32_t)0x40000000)
8CAN_F4R2_FB31 ((uint32_t)0x80000000) 8CAN_F5R2_FB0 ((uint32_t)0x00000001) 8CAN_F5R2_FB1 ((uint32_t)0x00000002) 8CAN_F5R2_FB2 ((uint32_t)0x00000004) 8CAN_F5R2_FB3 ((uint32_t)0x00000008) 8CAN_F5R2_FB4 ((uint32_t)0x00000010) 8CAN_F5R2_FB5 ((uint32_t)0x00000020) 8CAN_F5R2_FB6 ((uint32_t)0x00000040) 8CAN_F5R2_FB7 ((uint32_t)0x00000080) 8CAN_F5R2_FB8 ((uint32_t)0x00000100) 8CAN_F5R2_FB9 ((uint32_t)0x00000200) 8CAN_F5R2_FB10 ((uint32_t)0x00000400) 8CAN_F5R2_FB11 ((uint32_t)0x00000800) 8CAN_F5R2_FB12 ((uint32_t)0x00001000) 8CAN_F5R2_FB13 ((uint32_t)0x00002000) 8CAN_F5R2_FB14 ((uint32_t)0x00004000) 8CAN_F5R2_FB15 ((uint32_t)0x00008000) 8CAN_F5R2_FB16 ((uint32_t)0x00010000) 8CAN_F5R2_FB17 ((uint32_t)0x00020000) 8CAN_F5R2_FB18 ((uint32_t)0x00040000) 8CAN_F5R2_FB19 ((uint32_t)0x00080000) 8CAN_F5R2_FB20 ((uint32_t)0x00100000) 8CAN_F5R2_FB21 ((uint32_t)0x00200000) 8CAN_F5R2_FB22 ((uint32_t)0x00400000) 8CAN_F5R2_FB23 ((uint32_t)0x00800000) 8CAN_F5R2_FB24 ((uint32_t)0x01000000) ¡8CAN_F5R2_FB25 ((uint32_t)0x02000000) ¢8CAN_F5R2_FB26 ((uint32_t)0x04000000) £8CAN_F5R2_FB27 ((uint32_t)0x08000000) ¤8CAN_F5R2_FB28 ((uint32_t)0x10000000) ¥8CAN_F5R2_FB29 ((uint32_t)0x20000000) ¦8CAN_F5R2_FB30 ((uint32_t)0x40000000) §8CAN_F5R2_FB31 ((uint32_t)0x80000000) ª8CAN_F6R2_FB0 ((uint32_t)0x00000001) «8CAN_F6R2_FB1 ((uint32_t)0x00000002) ¬8CAN_F6R2_FB2 ((uint32_t)0x00000004) 8CAN_F6R2_FB3 ((uint32_t)0x00000008) ®8CAN_F6R2_FB4 ((uint32_t)0x00000010) ¯8CAN_F6R2_FB5 ((uint32_t)0x00000020) °8CAN_F6R2_FB6 ((uint32_t)0x00000040) ±8CAN_F6R2_FB7 ((uint32_t)0x00000080) ²8CAN_F6R2_FB8 ((uint32_t)0x00000100) ³8CAN_F6R2_FB9 ((uint32_t)0x00000200) ´8CAN_F6R2_FB10 ((uint32_t)0x00000400) µ8CAN_F6R2_FB11 ((uint32_t)0x00000800) ¶8CAN_F6R2_FB12 ((uint32_t)0x00001000) ·8CAN_F6R2_FB13 ((uint32_t)0x00002000) ¸8CAN_F6R2_FB14 ((uint32_t)0x00004000) ¹8CAN_F6R2_FB15 ((uint32_t)0x00008000) º8CAN_F6R2_FB16 ((uint32_t)0x00010000) »8CAN_F6R2_FB17 ((uint32_t)0x00020000) ¼8CAN_F6R2_FB18 ((uint32_t)0x00040000) ½8CAN_F6R2_FB19 ((uint32_t)0x00080000) ¾8CAN_F6R2_FB20 ((uint32_t)0x00100000) ¿8CAN_F6R2_FB21 ((uint32_t)0x00200000) À8CAN_F6R2_FB22 ((uint32_t)0x00400000) Á8CAN_F6R2_FB23 ((uint32_t)0x00800000) Â8CAN_F6R2_FB24 ((uint32_t)0x01000000) Ã8CAN_F6R2_FB25 ((uint32_t)0x02000000) Ä8CAN_F6R2_FB26 ((uint32_t)0x04000000) Å8CAN_F6R2_FB27 ((uint32_t)0x08000000) Æ8CAN_F6R2_FB28 ((uint32_t)0x10000000) Ç8CAN_F6R2_FB29 ((uint32_t)0x20000000) È8CAN_F6R2_FB30 ((uint32_t)0x40000000) É8CAN_F6R2_FB31 ((uint32_t)0x80000000) Ì8CAN_F7R2_FB0 ((uint32_t)0x00000001) Í8CAN_F7R2_FB1 ((uint32_t)0x00000002) Î8CAN_F7R2_FB2 ((uint32_t)0x00000004) Ï8CAN_F7R2_FB3 ((uint32_t)0x00000008) Ð8CAN_F7R2_FB4 ((uint32_t)0x00000010) Ñ8CAN_F7R2_FB5 ((uint32_t)0x00000020) Ò8CAN_F7R2_FB6 ((uint32_t)0x00000040) Ó8CAN_F7R2_FB7 ((uint32_t)0x00000080) Ô8CAN_F7R2_FB8 ((uint32_t)0x00000100) Õ8CAN_F7R2_FB9 ((uint32_t)0x00000200) Ö8CAN_F7R2_FB10 ((uint32_t)0x00000400) ×8CAN_F7R2_FB11 ((uint32_t)0x00000800) Ø8CAN_F7R2_FB12 ((uint32_t)0x00001000) Ù8CAN_F7R2_FB13 ((uint32_t)0x00002000) Ú8CAN_F7R2_FB14 ((uint32_t)0x00004000) Û8CAN_F7R2_FB15 ((uint32_t)0x00008000) Ü8CAN_F7R2_FB16 ((uint32_t)0x00010000) Ý8CAN_F7R2_FB17 ((uint32_t)0x00020000) Þ8CAN_F7R2_FB18 ((uint32_t)0x00040000) ß8CAN_F7R2_FB19 ((uint32_t)0x00080000) à8CAN_F7R2_FB20 ((uint32_t)0x00100000) á8CAN_F7R2_FB21 ((uint32_t)0x00200000) â8CAN_F7R2_FB22 ((uint32_t)0x00400000) ã8CAN_F7R2_FB23 ((uint32_t)0x00800000) ä8CAN_F7R2_FB24 ((uint32_t)0x01000000) å8CAN_F7R2_FB25 ((uint32_t)0x02000000) æ8CAN_F7R2_FB26 ((uint32_t)0x04000000) ç8CAN_F7R2_FB27 ((uint32_t)0x08000000) è8CAN_F7R2_FB28 ((uint32_t)0x10000000) é8CAN_F7R2_FB29 ((uint32_t)0x20000000) ê8CAN_F7R2_FB30 ((uint32_t)0x40000000) ë8CAN_F7R2_FB31 ((uint32_t)0x80000000) î8CAN_F8R2_FB0 ((uint32_t)0x00000001) ï8CAN_F8R2_FB1 ((uint32_t)0x00000002) ð8CAN_F8R2_FB2 ((uint32_t)0x00000004) ñ8CAN_F8R2_FB3 ((uint32_t)0x00000008) ò8CAN_F8R2_FB4 ((uint32_t)0x00000010) ó8CAN_F8R2_FB5 ((uint32_t)0x00000020) ô8CAN_F8R2_FB6 ((uint32_t)0x00000040) õ8CAN_F8R2_FB7 ((uint32_t)0x00000080) ö8CAN_F8R2_FB8 ((uint32_t)0x00000100) ÷8CAN_F8R2_FB9 ((uint32_t)0x00000200) ø8CAN_F8R2_FB10 ((uint32_t)0x00000400) ù8CAN_F8R2_FB11 ((uint32_t)0x00000800) ú8CAN_F8R2_FB12 ((uint32_t)0x00001000) û8CAN_F8R2_FB13 ((uint32_t)0x00002000) ü8CAN_F8R2_FB14 ((uint32_t)0x00004000) ý8CAN_F8R2_FB15 ((uint32_t)0x00008000) þ8CAN_F8R2_FB16 ((uint32_t)0x00010000) ÿ8CAN_F8R2_FB17 ((uint32_t)0x00020000) 9CAN_F8R2_FB18 ((uint32_t)0x00040000) 9CAN_F8R2_FB19 ((uint32_t)0x00080000) 9CAN_F8R2_FB20 ((uint32_t)0x00100000) 9CAN_F8R2_FB21 ((uint32_t)0x00200000) 9CAN_F8R2_FB22 ((uint32_t)0x00400000)
9CAN_F8R2_FB23 ((uint32_t)0x00800000) 9CAN_F8R2_FB24 ((uint32_t)0x01000000) 9CAN_F8R2_FB25 ((uint32_t)0x02000000) 9CAN_F8R2_FB26 ((uint32_t)0x04000000) 9CAN_F8R2_FB27 ((uint32_t)0x08000000) 9CAN_F8R2_FB28 ((uint32_t)0x10000000) 9CAN_F8R2_FB29 ((uint32_t)0x20000000) 9CAN_F8R2_FB30 ((uint32_t)0x40000000) 9CAN_F8R2_FB31 ((uint32_t)0x80000000) 9CAN_F9R2_FB0 ((uint32_t)0x00000001) 9CAN_F9R2_FB1 ((uint32_t)0x00000002) 9CAN_F9R2_FB2 ((uint32_t)0x00000004) 9CAN_F9R2_FB3 ((uint32_t)0x00000008) 9CAN_F9R2_FB4 ((uint32_t)0x00000010) 9CAN_F9R2_FB5 ((uint32_t)0x00000020) 9CAN_F9R2_FB6 ((uint32_t)0x00000040) 9CAN_F9R2_FB7 ((uint32_t)0x00000080) 9CAN_F9R2_FB8 ((uint32_t)0x00000100) 9CAN_F9R2_FB9 ((uint32_t)0x00000200) 9CAN_F9R2_FB10 ((uint32_t)0x00000400) 9CAN_F9R2_FB11 ((uint32_t)0x00000800) 9CAN_F9R2_FB12 ((uint32_t)0x00001000) 9CAN_F9R2_FB13 ((uint32_t)0x00002000) 9CAN_F9R2_FB14 ((uint32_t)0x00004000) 9CAN_F9R2_FB15 ((uint32_t)0x00008000) 9CAN_F9R2_FB16 ((uint32_t)0x00010000) ¡9CAN_F9R2_FB17 ((uint32_t)0x00020000) ¢9CAN_F9R2_FB18 ((uint32_t)0x00040000) £9CAN_F9R2_FB19 ((uint32_t)0x00080000) ¤9CAN_F9R2_FB20 ((uint32_t)0x00100000) ¥9CAN_F9R2_FB21 ((uint32_t)0x00200000) ¦9CAN_F9R2_FB22 ((uint32_t)0x00400000) §9CAN_F9R2_FB23 ((uint32_t)0x00800000) ¨9CAN_F9R2_FB24 ((uint32_t)0x01000000) ©9CAN_F9R2_FB25 ((uint32_t)0x02000000) ª9CAN_F9R2_FB26 ((uint32_t)0x04000000) «9CAN_F9R2_FB27 ((uint32_t)0x08000000) ¬9CAN_F9R2_FB28 ((uint32_t)0x10000000) 9CAN_F9R2_FB29 ((uint32_t)0x20000000) ®9CAN_F9R2_FB30 ((uint32_t)0x40000000) ¯9CAN_F9R2_FB31 ((uint32_t)0x80000000) ²9CAN_F10R2_FB0 ((uint32_t)0x00000001) ³9CAN_F10R2_FB1 ((uint32_t)0x00000002) ´9CAN_F10R2_FB2 ((uint32_t)0x00000004) µ9CAN_F10R2_FB3 ((uint32_t)0x00000008) ¶9CAN_F10R2_FB4 ((uint32_t)0x00000010) ·9CAN_F10R2_FB5 ((uint32_t)0x00000020) ¸9CAN_F10R2_FB6 ((uint32_t)0x00000040) ¹9CAN_F10R2_FB7 ((uint32_t)0x00000080) º9CAN_F10R2_FB8 ((uint32_t)0x00000100) »9CAN_F10R2_FB9 ((uint32_t)0x00000200) ¼9CAN_F10R2_FB10 ((uint32_t)0x00000400) ½9CAN_F10R2_FB11 ((uint32_t)0x00000800) ¾9CAN_F10R2_FB12 ((uint32_t)0x00001000) ¿9CAN_F10R2_FB13 ((uint32_t)0x00002000) À9CAN_F10R2_FB14 ((uint32_t)0x00004000) Á9CAN_F10R2_FB15 ((uint32_t)0x00008000) Â9CAN_F10R2_FB16 ((uint32_t)0x00010000) Ã9CAN_F10R2_FB17 ((uint32_t)0x00020000) Ä9CAN_F10R2_FB18 ((uint32_t)0x00040000) Å9CAN_F10R2_FB19 ((uint32_t)0x00080000) Æ9CAN_F10R2_FB20 ((uint32_t)0x00100000) Ç9CAN_F10R2_FB21 ((uint32_t)0x00200000) È9CAN_F10R2_FB22 ((uint32_t)0x00400000) É9CAN_F10R2_FB23 ((uint32_t)0x00800000) Ê9CAN_F10R2_FB24 ((uint32_t)0x01000000) Ë9CAN_F10R2_FB25 ((uint32_t)0x02000000) Ì9CAN_F10R2_FB26 ((uint32_t)0x04000000) Í9CAN_F10R2_FB27 ((uint32_t)0x08000000) Î9CAN_F10R2_FB28 ((uint32_t)0x10000000) Ï9CAN_F10R2_FB29 ((uint32_t)0x20000000) Ð9CAN_F10R2_FB30 ((uint32_t)0x40000000) Ñ9CAN_F10R2_FB31 ((uint32_t)0x80000000) Ô9CAN_F11R2_FB0 ((uint32_t)0x00000001) Õ9CAN_F11R2_FB1 ((uint32_t)0x00000002) Ö9CAN_F11R2_FB2 ((uint32_t)0x00000004) ×9CAN_F11R2_FB3 ((uint32_t)0x00000008) Ø9CAN_F11R2_FB4 ((uint32_t)0x00000010) Ù9CAN_F11R2_FB5 ((uint32_t)0x00000020) Ú9CAN_F11R2_FB6 ((uint32_t)0x00000040) Û9CAN_F11R2_FB7 ((uint32_t)0x00000080) Ü9CAN_F11R2_FB8 ((uint32_t)0x00000100) Ý9CAN_F11R2_FB9 ((uint32_t)0x00000200) Þ9CAN_F11R2_FB10 ((uint32_t)0x00000400) ß9CAN_F11R2_FB11 ((uint32_t)0x00000800) à9CAN_F11R2_FB12 ((uint32_t)0x00001000) á9CAN_F11R2_FB13 ((uint32_t)0x00002000) â9CAN_F11R2_FB14 ((uint32_t)0x00004000) ã9CAN_F11R2_FB15 ((uint32_t)0x00008000) ä9CAN_F11R2_FB16 ((uint32_t)0x00010000) å9CAN_F11R2_FB17 ((uint32_t)0x00020000) æ9CAN_F11R2_FB18 ((uint32_t)0x00040000) ç9CAN_F11R2_FB19 ((uint32_t)0x00080000) è9CAN_F11R2_FB20 ((uint32_t)0x00100000) é9CAN_F11R2_FB21 ((uint32_t)0x00200000) ê9CAN_F11R2_FB22 ((uint32_t)0x00400000) ë9CAN_F11R2_FB23 ((uint32_t)0x00800000) ì9CAN_F11R2_FB24 ((uint32_t)0x01000000) í9CAN_F11R2_FB25 ((uint32_t)0x02000000) î9CAN_F11R2_FB26 ((uint32_t)0x04000000) ï9CAN_F11R2_FB27 ((uint32_t)0x08000000) ð9CAN_F11R2_FB28 ((uint32_t)0x10000000) ñ9CAN_F11R2_FB29 ((uint32_t)0x20000000) ò9CAN_F11R2_FB30 ((uint32_t)0x40000000) ó9CAN_F11R2_FB31 ((uint32_t)0x80000000) ö9CAN_F12R2_FB0 ((uint32_t)0x00000001) ÷9CAN_F12R2_FB1 ((uint32_t)0x00000002) ø9CAN_F12R2_FB2 ((uint32_t)0x00000004) ù9CAN_F12R2_FB3 ((uint32_t)0x00000008) ú9CAN_F12R2_FB4 ((uint32_t)0x00000010) û9CAN_F12R2_FB5 ((uint32_t)0x00000020) ü9CAN_F12R2_FB6 ((uint32_t)0x00000040) ý9CAN_F12R2_FB7 ((uint32_t)0x00000080) þ9CAN_F12R2_FB8 ((uint32_t)0x00000100) ÿ9CAN_F12R2_FB9 ((uint32_t)0x00000200) :CAN_F12R2_FB10 ((uint32_t)0x00000400) :CAN_F12R2_FB11 ((uint32_t)0x00000800) :CAN_F12R2_FB12 ((uint32_t)0x00001000) :CAN_F12R2_FB13 ((uint32_t)0x00002000) :CAN_F12R2_FB14 ((uint32_t)0x00004000)
:CAN_F12R2_FB15 ((uint32_t)0x00008000) :CAN_F12R2_FB16 ((uint32_t)0x00010000) :CAN_F12R2_FB17 ((uint32_t)0x00020000) :CAN_F12R2_FB18 ((uint32_t)0x00040000) :CAN_F12R2_FB19 ((uint32_t)0x00080000) :CAN_F12R2_FB20 ((uint32_t)0x00100000) :CAN_F12R2_FB21 ((uint32_t)0x00200000) :CAN_F12R2_FB22 ((uint32_t)0x00400000) :CAN_F12R2_FB23 ((uint32_t)0x00800000) :CAN_F12R2_FB24 ((uint32_t)0x01000000) :CAN_F12R2_FB25 ((uint32_t)0x02000000) :CAN_F12R2_FB26 ((uint32_t)0x04000000) :CAN_F12R2_FB27 ((uint32_t)0x08000000) :CAN_F12R2_FB28 ((uint32_t)0x10000000) :CAN_F12R2_FB29 ((uint32_t)0x20000000) :CAN_F12R2_FB30 ((uint32_t)0x40000000) :CAN_F12R2_FB31 ((uint32_t)0x80000000) :CAN_F13R2_FB0 ((uint32_t)0x00000001) :CAN_F13R2_FB1 ((uint32_t)0x00000002) :CAN_F13R2_FB2 ((uint32_t)0x00000004) :CAN_F13R2_FB3 ((uint32_t)0x00000008) :CAN_F13R2_FB4 ((uint32_t)0x00000010) :CAN_F13R2_FB5 ((uint32_t)0x00000020) :CAN_F13R2_FB6 ((uint32_t)0x00000040) :CAN_F13R2_FB7 ((uint32_t)0x00000080) :CAN_F13R2_FB8 ((uint32_t)0x00000100) ¡:CAN_F13R2_FB9 ((uint32_t)0x00000200) ¢:CAN_F13R2_FB10 ((uint32_t)0x00000400) £:CAN_F13R2_FB11 ((uint32_t)0x00000800) ¤:CAN_F13R2_FB12 ((uint32_t)0x00001000) ¥:CAN_F13R2_FB13 ((uint32_t)0x00002000) ¦:CAN_F13R2_FB14 ((uint32_t)0x00004000) §:CAN_F13R2_FB15 ((uint32_t)0x00008000) ¨:CAN_F13R2_FB16 ((uint32_t)0x00010000) ©:CAN_F13R2_FB17 ((uint32_t)0x00020000) ª:CAN_F13R2_FB18 ((uint32_t)0x00040000) «:CAN_F13R2_FB19 ((uint32_t)0x00080000) ¬:CAN_F13R2_FB20 ((uint32_t)0x00100000) :CAN_F13R2_FB21 ((uint32_t)0x00200000) ®:CAN_F13R2_FB22 ((uint32_t)0x00400000) ¯:CAN_F13R2_FB23 ((uint32_t)0x00800000) °:CAN_F13R2_FB24 ((uint32_t)0x01000000) ±:CAN_F13R2_FB25 ((uint32_t)0x02000000) ²:CAN_F13R2_FB26 ((uint32_t)0x04000000) ³:CAN_F13R2_FB27 ((uint32_t)0x08000000) ´:CAN_F13R2_FB28 ((uint32_t)0x10000000) µ:CAN_F13R2_FB29 ((uint32_t)0x20000000) ¶:CAN_F13R2_FB30 ((uint32_t)0x40000000) ·:CAN_F13R2_FB31 ((uint32_t)0x80000000) À:SPI_CR1_CPHA ((uint16_t)0x0001) Á:SPI_CR1_CPOL ((uint16_t)0x0002) Â:SPI_CR1_MSTR ((uint16_t)0x0004) Ä:SPI_CR1_BR ((uint16_t)0x0038) Å:SPI_CR1_BR_0 ((uint16_t)0x0008) Æ:SPI_CR1_BR_1 ((uint16_t)0x0010) Ç:SPI_CR1_BR_2 ((uint16_t)0x0020) É:SPI_CR1_SPE ((uint16_t)0x0040) Ê:SPI_CR1_LSBFIRST ((uint16_t)0x0080) Ë:SPI_CR1_SSI ((uint16_t)0x0100) Ì:SPI_CR1_SSM ((uint16_t)0x0200) Í:SPI_CR1_RXONLY ((uint16_t)0x0400) Î:SPI_CR1_DFF ((uint16_t)0x0800) Ï:SPI_CR1_CRCNEXT ((uint16_t)0x1000) Ð:SPI_CR1_CRCEN ((uint16_t)0x2000) Ñ:SPI_CR1_BIDIOE ((uint16_t)0x4000) Ò:SPI_CR1_BIDIMODE ((uint16_t)0x8000) Õ:SPI_CR2_RXDMAEN ((uint8_t)0x01) Ö:SPI_CR2_TXDMAEN ((uint8_t)0x02) ×:SPI_CR2_SSOE ((uint8_t)0x04) Ø:SPI_CR2_ERRIE ((uint8_t)0x20) Ù:SPI_CR2_RXNEIE ((uint8_t)0x40) Ú:SPI_CR2_TXEIE ((uint8_t)0x80) Ý:SPI_SR_RXNE ((uint8_t)0x01) Þ:SPI_SR_TXE ((uint8_t)0x02) ß:SPI_SR_CHSIDE ((uint8_t)0x04) à:SPI_SR_UDR ((uint8_t)0x08) á:SPI_SR_CRCERR ((uint8_t)0x10) â:SPI_SR_MODF ((uint8_t)0x20) ã:SPI_SR_OVR ((uint8_t)0x40) ä:SPI_SR_BSY ((uint8_t)0x80) ç:SPI_DR_DR ((uint16_t)0xFFFF) ê:SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) í:SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) ð:SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) ó:SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) õ:SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) ö:SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) ÷:SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) ù:SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) û:SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) ü:SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) ý:SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) ÿ:SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) ;SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) ;SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) ;SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
;SPI_I2SCFGR_I2SE ((uint16_t)0x0400) ;SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) ;SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) ;SPI_I2SPR_ODD ((uint16_t)0x0100) ;SPI_I2SPR_MCKOE ((uint16_t)0x0200) ;I2C_CR1_PE ((uint16_t)0x0001) ;I2C_CR1_SMBUS ((uint16_t)0x0002) ;I2C_CR1_SMBTYPE ((uint16_t)0x0008) ;I2C_CR1_ENARP ((uint16_t)0x0010) ;I2C_CR1_ENPEC ((uint16_t)0x0020) ;I2C_CR1_ENGC ((uint16_t)0x0040) ;I2C_CR1_NOSTRETCH ((uint16_t)0x0080) ;I2C_CR1_START ((uint16_t)0x0100) ;I2C_CR1_STOP ((uint16_t)0x0200) ;I2C_CR1_ACK ((uint16_t)0x0400) ;I2C_CR1_POS ((uint16_t)0x0800) ;I2C_CR1_PEC ((uint16_t)0x1000) ;I2C_CR1_ALERT ((uint16_t)0x2000) ¡;I2C_CR1_SWRST ((uint16_t)0x8000) ¤;I2C_CR2_FREQ ((uint16_t)0x003F) ¥;I2C_CR2_FREQ_0 ((uint16_t)0x0001) ¦;I2C_CR2_FREQ_1 ((uint16_t)0x0002) §;I2C_CR2_FREQ_2 ((uint16_t)0x0004) ¨;I2C_CR2_FREQ_3 ((uint16_t)0x0008) ©;I2C_CR2_FREQ_4 ((uint16_t)0x0010) ª;I2C_CR2_FREQ_5 ((uint16_t)0x0020) ¬;I2C_CR2_ITERREN ((uint16_t)0x0100) ;I2C_CR2_ITEVTEN ((uint16_t)0x0200) ®;I2C_CR2_ITBUFEN ((uint16_t)0x0400) ¯;I2C_CR2_DMAEN ((uint16_t)0x0800) °;I2C_CR2_LAST ((uint16_t)0x1000) ³;I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) ´;I2C_OAR1_ADD8_9 ((uint16_t)0x0300) ¶;I2C_OAR1_ADD0 ((uint16_t)0x0001) ·;I2C_OAR1_ADD1 ((uint16_t)0x0002) ¸;I2C_OAR1_ADD2 ((uint16_t)0x0004) ¹;I2C_OAR1_ADD3 ((uint16_t)0x0008) º;I2C_OAR1_ADD4 ((uint16_t)0x0010) »;I2C_OAR1_ADD5 ((uint16_t)0x0020) ¼;I2C_OAR1_ADD6 ((uint16_t)0x0040) ½;I2C_OAR1_ADD7 ((uint16_t)0x0080) ¾;I2C_OAR1_ADD8 ((uint16_t)0x0100) ¿;I2C_OAR1_ADD9 ((uint16_t)0x0200) Á;I2C_OAR1_ADDMODE ((uint16_t)0x8000) Ä;I2C_OAR2_ENDUAL ((uint8_t)0x01) Å;I2C_OAR2_ADD2 ((uint8_t)0xFE) È;I2C_DR_DR ((uint8_t)0xFF) Ë;I2C_SR1_SB ((uint16_t)0x0001) Ì;I2C_SR1_ADDR ((uint16_t)0x0002) Í;I2C_SR1_BTF ((uint16_t)0x0004) Î;I2C_SR1_ADD10 ((uint16_t)0x0008) Ï;I2C_SR1_STOPF ((uint16_t)0x0010) Ð;I2C_SR1_RXNE ((uint16_t)0x0040) Ñ;I2C_SR1_TXE ((uint16_t)0x0080) Ò;I2C_SR1_BERR ((uint16_t)0x0100) Ó;I2C_SR1_ARLO ((uint16_t)0x0200) Ô;I2C_SR1_AF ((uint16_t)0x0400) Õ;I2C_SR1_OVR ((uint16_t)0x0800) Ö;I2C_SR1_PECERR ((uint16_t)0x1000) ×;I2C_SR1_TIMEOUT ((uint16_t)0x4000) Ø;I2C_SR1_SMBALERT ((uint16_t)0x8000) Û;I2C_SR2_MSL ((uint16_t)0x0001) Ü;I2C_SR2_BUSY ((uint16_t)0x0002) Ý;I2C_SR2_TRA ((uint16_t)0x0004) Þ;I2C_SR2_GENCALL ((uint16_t)0x0010) ß;I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) à;I2C_SR2_SMBHOST ((uint16_t)0x0040) á;I2C_SR2_DUALF ((uint16_t)0x0080) â;I2C_SR2_PEC ((uint16_t)0xFF00) å;I2C_CCR_CCR ((uint16_t)0x0FFF) æ;I2C_CCR_DUTY ((uint16_t)0x4000) ç;I2C_CCR_FS ((uint16_t)0x8000) ê;I2C_TRISE_TRISE ((uint8_t)0x3F) ó;USART_SR_PE ((uint16_t)0x0001) ô;USART_SR_FE ((uint16_t)0x0002) õ;USART_SR_NE ((uint16_t)0x0004) ö;USART_SR_ORE ((uint16_t)0x0008) ÷;USART_SR_IDLE ((uint16_t)0x0010) ø;USART_SR_RXNE ((uint16_t)0x0020) ù;USART_SR_TC ((uint16_t)0x0040) ú;USART_SR_TXE ((uint16_t)0x0080) û;USART_SR_LBD ((uint16_t)0x0100) ü;USART_SR_CTS ((uint16_t)0x0200) ÿ;USART_DR_DR ((uint16_t)0x01FF) <USART_BRR_DIV_Fraction ((uint16_t)0x000F) <USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) <USART_CR1_SBK ((uint16_t)0x0001) <USART_CR1_RWU ((uint16_t)0x0002) <USART_CR1_RE ((uint16_t)0x0004) <USART_CR1_TE ((uint16_t)0x0008) <USART_CR1_IDLEIE ((uint16_t)0x0010) <USART_CR1_RXNEIE ((uint16_t)0x0020) <USART_CR1_TCIE ((uint16_t)0x0040) <USART_CR1_TXEIE ((uint16_t)0x0080) <USART_CR1_PEIE ((uint16_t)0x0100) <USART_CR1_PS ((uint16_t)0x0200) <USART_CR1_PCE ((uint16_t)0x0400) <USART_CR1_WAKE ((uint16_t)0x0800) <USART_CR1_M ((uint16_t)0x1000) <USART_CR1_UE ((uint16_t)0x2000) <USART_CR1_OVER8 ((uint16_t)0x8000) <USART_CR2_ADD ((uint16_t)0x000F) <USART_CR2_LBDL ((uint16_t)0x0020) <USART_CR2_LBDIE ((uint16_t)0x0040) <USART_CR2_LBCL ((uint16_t)0x0100) <USART_CR2_CPHA ((uint16_t)0x0200) <USART_CR2_CPOL ((uint16_t)0x0400) <USART_CR2_CLKEN ((uint16_t)0x0800) <USART_CR2_STOP ((uint16_t)0x3000) <USART_CR2_STOP_0 ((uint16_t)0x1000) ¡<USART_CR2_STOP_1 ((uint16_t)0x2000) £<USART_CR2_LINEN ((uint16_t)0x4000) ¦<USART_CR3_EIE ((uint16_t)0x0001) §<USART_CR3_IREN ((uint16_t)0x0002) ¨<USART_CR3_IRLP ((uint16_t)0x0004) ©<USART_CR3_HDSEL ((uint16_t)0x0008) ª<USART_CR3_NACK ((uint16_t)0x0010) «<USART_CR3_SCEN ((uint16_t)0x0020) ¬<USART_CR3_DMAR ((uint16_t)0x0040) <USART_CR3_DMAT ((uint16_t)0x0080) ®<USART_CR3_RTSE ((uint16_t)0x0100) ¯<USART_CR3_CTSE ((uint16_t)0x0200) °<USART_CR3_CTSIE ((uint16_t)0x0400) ±<USART_CR3_ONEBIT ((uint16_t)0x0800) ´<USART_GTPR_PSC ((uint16_t)0x00FF) µ<USART_GTPR_PSC_0 ((uint16_t)0x0001) ¶<USART_GTPR_PSC_1 ((uint16_t)0x0002) ·<USART_GTPR_PSC_2 ((uint16_t)0x0004) ¸<USART_GTPR_PSC_3 ((uint16_t)0x0008) ¹<USART_GTPR_PSC_4 ((uint16_t)0x0010) º<USART_GTPR_PSC_5 ((uint16_t)0x0020) »<USART_GTPR_PSC_6 ((uint16_t)0x0040) ¼<USART_GTPR_PSC_7 ((uint16_t)0x0080) ¾<USART_GTPR_GT ((uint16_t)0xFF00) Ç<DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) É<DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) Ê<DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) Ë<DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) Ì<DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) Í<DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) Î<DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) Ï<DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) Ð<DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) Ñ<DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) Ò<DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) Ó<DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) Ô<DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) Õ<DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) Ö<DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) ×<DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) Ø<DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) Ù<DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) Ü<DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) Ý<DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) Þ<DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) ß<DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) á<DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) â<DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) ã<DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) å<DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) æ<DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) ç<DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) è<DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) é<DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) ê<DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) ë<DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) ì<DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) í<DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) î<DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) ï<DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) ð<DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) ñ<DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) ò<DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) ó<DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) ô<DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) õ<DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) ö<DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) ÷<DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) ø<DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) ù<DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) ú<DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) û<DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) =FLASH_ACR_LATENCY ((uint8_t)0x03)
=FLASH_ACR_LATENCY_0 ((uint8_t)0x00) =FLASH_ACR_LATENCY_1 ((uint8_t)0x01) =FLASH_ACR_LATENCY_2 ((uint8_t)0x02) =FLASH_ACR_HLFCYA ((uint8_t)0x08) =FLASH_ACR_PRFTBE ((uint8_t)0x10) =FLASH_ACR_PRFTBS ((uint8_t)0x20) =FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) =FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) =FLASH_SR_BSY ((uint8_t)0x01) =FLASH_SR_PGERR ((uint8_t)0x04) =FLASH_SR_WRPRTERR ((uint8_t)0x10) =FLASH_SR_EOP ((uint8_t)0x20) =FLASH_CR_PG ((uint16_t)0x0001) =FLASH_CR_PER ((uint16_t)0x0002) =FLASH_CR_MER ((uint16_t)0x0004) =FLASH_CR_OPTPG ((uint16_t)0x0010) =FLASH_CR_OPTER ((uint16_t)0x0020) =FLASH_CR_STRT ((uint16_t)0x0040) =FLASH_CR_LOCK ((uint16_t)0x0080) ¡=FLASH_CR_OPTWRE ((uint16_t)0x0200) ¢=FLASH_CR_ERRIE ((uint16_t)0x0400) £=FLASH_CR_EOPIE ((uint16_t)0x1000) ¦=FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) ©=FLASH_OBR_OPTERR ((uint16_t)0x0001) ª=FLASH_OBR_RDPRT ((uint16_t)0x0002) ¬=FLASH_OBR_USER ((uint16_t)0x03FC) =FLASH_OBR_WDG_SW ((uint16_t)0x0004) ®=FLASH_OBR_nRST_STOP ((uint16_t)0x0008) ¯=FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) °=FLASH_OBR_BFB2 ((uint16_t)0x0020) ³=FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) ¸=FLASH_RDP_RDP ((uint32_t)0x000000FF) ¹=FLASH_RDP_nRDP ((uint32_t)0x0000FF00) ¼=FLASH_USER_USER ((uint32_t)0x00FF0000) ½=FLASH_USER_nUSER ((uint32_t)0xFF000000) À=FLASH_Data0_Data0 ((uint32_t)0x000000FF) Á=FLASH_Data0_nData0 ((uint32_t)0x0000FF00) Ä=FLASH_Data1_Data1 ((uint32_t)0x00FF0000) Å=FLASH_Data1_nData1 ((uint32_t)0xFF000000) È=FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) É=FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) Ì=FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) Í=FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) Ð=FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) Ñ=FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) Ô=FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) Õ=FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000)
ASET_BIT(REG,BIT) ((REG) |= (BIT)) ACLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) AREAD_BIT(REG,BIT) ((REG) & (BIT)) ACLEAR_REG(REG) ((REG) = (0x0)) AWRITE_REG(REG,VAL) ((REG) = (VAL)) AREAD_REG(REG) ((REG)) AMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) (_CHSTREAMS_H_ -_base_sequential_stream_methods size_t (*write)(void *instance, const uint8_t *bp, size_t n); size_t (*read)(void *instance, uint8_t *bp, size_t n); msg_t (*put)(void *instance, uint8_t b); msg_t (*get)(void *instance); <_base_sequential_stream_data achSequentialStreamWrite(ip,bp,n) ((ip)->vmt->write(ip, bp, n)) pchSequentialStreamRead(ip,bp,n) ((ip)->vmt->read(ip, bp, n)) chSequentialStreamPut(ip,b) ((ip)->vmt->put(ip, b)) chSequentialStreamGet(ip) ((ip)->vmt->get(ip)) _CHQUEUES_H_ &Q_OK RDY_OK 'Q_TIMEOUT RDY_TIMEOUT (Q_RESET RDY_RESET )Q_EMPTY -3 *Q_FULL -4 VchQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer)) bchQSpaceI(qp) ((qp)->q_counter) mchQGetLink(qp) ((qp)->q_link) chIQGetFullI(iqp) chQSpaceI(iqp) chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp)) ¡chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0)) chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && ((iqp)->q_counter != 0))) ¼chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) Ê_INPUTQUEUE_DATA(name,buffer,size,inotify,link) { _THREADSQUEUE_DATA(name), 0, (uint8_t *)(buffer), (uint8_t *)(buffer) + (size), (uint8_t *)(buffer), (uint8_t *)(buffer), (inotify), (link) } àINPUTQUEUE_DECL(name,buffer,size,inotify,link) InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link) ýchOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp)) chOQGetEmptyI(oqp) chQSpaceI(oqp) chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && ((oqp)->q_counter != 0))) ¡chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0)) ±chOQPut(oqp,b) chOQPutTimeout(oqp, b, TIME_INFINITE) ¿_OUTPUTQUEUE_DATA(name,buffer,size,onotify,link) { _THREADSQUEUE_DATA(name), (size), (uint8_t *)(buffer), (uint8_t *)(buffer) + (size), (uint8_t *)(buffer), (uint8_t *)(buffer), (onotify), (link) } ÕOUTPUTQUEUE_DECL(name,buffer,size,onotify,link) OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) _CHTHREADS_H_ $THD_STATE_READY 0 %THD_STATE_CURRENT 1 &THD_STATE_SUSPENDED 2 'THD_STATE_WTSEM 3 (THD_STATE_WTMTX 4 )THD_STATE_WTCOND 5 +THD_STATE_SLEEPING 6 -THD_STATE_WTEXIT 7 .THD_STATE_WTOREVT 8 /THD_STATE_WTANDEVT 9 0THD_STATE_SNDMSGQ 10 1THD_STATE_SNDMSG 11 3THD_STATE_WTMSG 12 4THD_STATE_WTQUEUE 13 5THD_STATE_FINAL 14 <THD_STATE_NAMES "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", "FINAL" FTHD_MEM_MODE_MASK 3 GTHD_MEM_MODE_STATIC 0 HTHD_MEM_MODE_HEAP 1 JTHD_MEM_MODE_MEMPOOL 2 LTHD_TERMINATE 4 êchThdSelf() currp òchThdGetPriority() (currp->p_prio) þchThdGetTicks(tp) ((tp)->p_time) chThdLS() (void *)(currp + 1) chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) ¦chThdResumeI(tp) chSchReadyI(tp) ´chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) ÀchThdSleepSeconds(sec) chThdSleep(S2ST(sec)) ÍchThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) ÚchThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) _CHMEMPOOLS_H_ >_MEMORYPOOL_DATA(name,size,provider) {NULL, size, provider} KMEMORYPOOL_DECL(name,size,provider) MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) achPoolAdd(mp,objp) chPoolFree(mp, objp) rchPoolAddI(mp,objp) chPoolFreeI(mp, objp) _CHHEAP_H_ _CHMEMCORE_H_ -MEM_ALIGN_SIZE sizeof(stkalign_t) 2MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1) 7MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) <MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) BMEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) !_CHEVENTS_H_ K_EVENTSOURCE_DATA(name) {(void *)(&name)} TEVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) YALL_EVENTS ((eventmask_t)-1) ^EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) schEvtRegister(esp,elp,eid) chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) chEvtInit(esp) ((esp)->es_next = (EventListener *)(void *)(esp)) chEvtIsListeningI(esp) ((void *)(esp) != (void *)(esp)->es_next) chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0) ¢chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0) _CHMTX_H_ D_MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} MMUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) YchMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) _CHVT_H_ .S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) :MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) GUS2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) chVTDoTickI() { vtlist.vt_systime++; if (&vtlist != (VTList *)vtlist.vt_next) { VirtualTimer *vtp; --vtlist.vt_next->vt_time; while (!(vtp = vtlist.vt_next)->vt_time) { vtfunc_t fn = vtp->vt_func; vtp->vt_func = (vtfunc_t)NULL; vtp->vt_next->vt_prev = (void *)&vtlist; (&vtlist)->vt_next = vtp->vt_next; chSysUnlockFromIsr(); fn(vtp->vt_par); chSysLockFromIsr(); } } } chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) ®chVTSet(vtp,time,vtfunc,par) { chSysLock(); chVTSetI(vtp, time, vtfunc, par); chSysUnlock(); } ¼chVTReset(vtp) { chSysLock(); if (chVTIsArmedI(vtp)) chVTResetI(vtp); chSysUnlock(); } ÎchTimeNow() (vtlist.vt_systime) _CHCORE_V7M_H_ 'CORTEX_BASEPRI_DISABLED 0 ;PORT_IDLE_THREAD_STACK_SIZE 16 HPORT_INT_REQUIRED_STACK 32 OCORTEX_ENABLE_WFI_IDLE FALSE XCORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) cCORTEX_USE_FPU CORTEX_HAS_FPU oCORTEX_SIMPLIFIED_PRIORITY FALSE zCORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) CORTEX_VTOR_INIT 0x00000000 CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) ¬CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL ¶CH_ARCHITECTURE_ARM_v7M »CH_ARCHITECTURE_NAME "ARMv7-M" ÀCH_CORE_VARIANT_NAME "Cortex-M3" ÐCH_PORT_INFO "Advanced kernel mode" ¹SETUP_CONTEXT(workspace,wsize,pf,arg) { tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + wsize - sizeof(struct intctx)); tp->p_ctx.r13->r4 = (regarm_t)pf; tp->p_ctx.r13->r5 = (regarm_t)arg; tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; } ÅSTACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) ÊTHD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + sizeof(struct intctx) + sizeof(struct extctx) + (n) + (PORT_INT_REQUIRED_STACK)) ÔWORKING_AREA(s,n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] ÛPORT_IRQ_PROLOGUE() âPORT_IRQ_EPILOGUE() _port_irq_epilogue() éPORT_IRQ_HANDLER(id) void id(void) ðPORT_FAST_IRQ_HANDLER(id) void id(void) õport_init() _port_init() þport_lock() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_KERNEL; } port_unlock() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_DISABLED; } port_lock_from_isr() port_lock() ¥port_unlock_from_isr() port_unlock() port_disable() __disable_irq() µport_suspend() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_KERNEL; } Âport_enable() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_DISABLED; __enable_irq(); } Öport_wait_for_interrupt() äport_switch(ntp,otp) _port_switch(ntp, otp) !_CHLISTS_H_ *queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); 1list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) 9isempty(p) ((p)->p_next == (Thread *)(p)) Anotempty(p) ((p)->p_next != (Thread *)(p)) J_THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} STHREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) _CHTYPES_H_ !"4INLINE __inline :ROMCONST const @PACK_STRUCT_STRUCT EPACK_STRUCT_BEGIN __packed KPACK_STRUCT_END __stdint_h __ARMCLIB_VERSION 5030024 __STDINT_DECLS __CLIBNS __CLIBNS \INT8_MIN -128 ]INT16_MIN -32768 ^INT32_MIN (~0x7fffffff) _INT64_MIN __ESCAPE__(~0x7fffffffffffffffll) bINT8_MAX 127 cINT16_MAX 32767 dINT32_MAX 2147483647 eINT64_MAX __ESCAPE__(9223372036854775807ll) hUINT8_MAX 255 iUINT16_MAX 65535 jUINT32_MAX 4294967295u kUINT64_MAX __ESCAPE__(18446744073709551615ull) pINT_LEAST8_MIN -128 qINT_LEAST16_MIN -32768 rINT_LEAST32_MIN (~0x7fffffff) sINT_LEAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) vINT_LEAST8_MAX 127 wINT_LEAST16_MAX 32767 xINT_LEAST32_MAX 2147483647 yINT_LEAST64_MAX __ESCAPE__(9223372036854775807ll) |UINT_LEAST8_MAX 255 }UINT_LEAST16_MAX 65535 ~UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull) INT_FAST8_MIN (~0x7fffffff)
INT_FAST16_MIN (~0x7fffffff) INT_FAST32_MIN (~0x7fffffff) INT_FAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) INT_FAST8_MAX 2147483647 INT_FAST16_MAX 2147483647 INT_FAST32_MAX 2147483647 INT_FAST64_MAX __ESCAPE__(9223372036854775807ll) UINT_FAST8_MAX 4294967295u UINT_FAST16_MAX 4294967295u UINT_FAST32_MAX 4294967295u UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull) INTPTR_MIN (~0x7fffffff) INTPTR_MAX 2147483647 UINTPTR_MAX 4294967295u £INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ¦INTMAX_MAX __ESCAPE__(9223372036854775807ll) ©UINTMAX_MAX __ESCAPE__(18446744073709551615ull) ®PTRDIFF_MIN (~0x7fffffff) ¯PTRDIFF_MAX 2147483647 ²SIG_ATOMIC_MIN (~0x7fffffff) ³SIG_ATOMIC_MAX 2147483647 ¶SIZE_MAX 4294967295u »WCHAR_MIN ¼WCHAR_MAX ÂWCHAR_MIN 0 ÃWCHAR_MAX 65535 ÇWINT_MIN (~0x7fffffff) ÈWINT_MAX 2147483647 ÏINT8_C(x) (x) ÐINT16_C(x) (x) ÑINT32_C(x) (x) ÒINT64_C(x) __ESCAPE__(x##ll) ÔUINT8_C(x) (x##u) ÕUINT16_C(x) (x##u) ÖUINT32_C(x) (x##u) ×UINT64_C(x) __ESCAPE__(x##ull) ÚINTMAX_C(x) __ESCAPE__(x##ll) ÛUINTMAX_C(x) __ESCAPE__(x##ull) __stddef_h __ARMCLIB_VERSION 5030024 __STDDEF_DECLS __CLIBNS __CLIBNS GNULL HNULL 0 Loffsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb))) % ( d Þ dekoduj_zpravu_GPS " ô Ò GPGGA_informace 4 <` Ð ó dekodujPrikaz GPGGA_informace ¸ main . 8 | Î tp_odpal ä uvitaci_zprava 4 ´ \ þ hal_lld_init 2 stm32_clock_init : è _pal_lld_init A _pal_lld_setgroupmode % Hd P ö gpt_lld_stop_timer ø | VectorB0 e gpt_lld_init gpt_lld_start Á gpt_lld_stop ï gpt_lld_start_timer 4 gpt_lld_polled_delay t î GPTD2 Y x Q VectorD4 o VectorD8 sd_lld_init ® sd_lld_start sd_lld_stop ¤ 8 SD1 % SD2 D¥ Ä ú VectorB4 8 VectorB8 v pwm_lld_init pwm_lld_start Þ pwm_lld_stop pwm_lld_enable_channel x pwm_lld_disable_channel " ¨ î PWMD3 PWMD4 © ì chprintf l å tmObjectInit ¬ ] tmInit h ¬® ð M sdInit h sdObjectInit ³ sdStart sdStop d sdIncomingDataI sdRequestDataI ´ 8 ê pwmInit pwmObjectInit 4 pwmStart pwmStop ç pwmChangePeriod P pwmEnableChannel È pwmDisableChannel % 8n < æ halIsCounterWithin - È· ´ ê halInit 6 halPolledDelay M to x æ gptStartContinuousI gptStartOneShotI S gptStopTimerI ª |¹ | ê gptInit gptObjectInit 4 gptStart gptStop ç gptChangeInterval t gptStartContinuous " gptStartOneShot Ç gptStopTimer 9 gptPolledDelay % PO ÿ pal_default_config J ø½ ø ø _vt_init chVTSetI i chVTResetI chTimeIsWithin ð¿ ø â vtlist ? ,u ü _thread_init D chThdCreateI ¨ chThdExitS ª èÀ chThdCreateStatic chThdSetPriority chThdResume chThdTerminate á chThdSleep 7 chThdSleepUntil chThdYield chThdExit
chThdWait D Ç è ù _idle_thread chSysInit d chSysTimerHandlerI " ìÈ ã _idle_thread_wa g x| Ä ö chSchReadyI 2 chSchGoSleepS b chSchDoRescheduleAhead chSchDoRescheduleBehind w ðÉ ì ú _scheduler_init E chSchGoSleepTimeoutS K chSchWakeupS 1 chSchRescheduleS chSchDoReschedule ÜÏ ü ä rlist ØÐ è ch_debug ¯ ØÑ p ü chIQInit P chIQResetI ¨ chIQPutI chIQGetTimeout chIQReadTimeout 0 chOQInit
chOQResetI Þ chOQPutTimeout Û chOQGetI M chOQWriteTimeout / X h ý chMtxLockS / chMtxTryLockS o HÙ \ ï chMtxInit " chMtxLock chMtxTryLock - chMtxUnlock ü chMtxUnlockS ¢ chMtxUnlockAll > ´ ú chPoolFreeI * chPoolFree s chPoolAllocI A ¤Þ , þ chPoolInit Ë chPoolLoadArray chPoolAlloc X Ì ù chCoreAllocI A Image$$RW_IRAM1$$ZI$$Limit l Image$$RW_IRAM2$$Base > Ðá ý _core_init D chCoreAlloc Ù chCoreStatus \ ôä ú _heap_init chHeapInit d chHeapAlloc Î chHeapFree chHeapStatus 8 \ h þ chEvtSignalI ) chEvtBroadcastFlagsI P è t ò chEvtRegisterMask d chEvtUnregister Ñ chEvtGetAndClearEvents T chEvtAddEvents , chEvtGetAndClearFlags ± chEvtSignal 2 chEvtBroadcastFlags å chEvtGetAndClearFlagsI A chEvtDispatch chEvtWaitOne chEvtWaitAny chEvtWaitAll
chEvtWaitOneTimeout Û chEvtWaitAnyTimeout ª chEvtWaitAllTimeout e ôñ 0 ý chThdAddRef i chThdRelease Ê chThdCreateFromHeap chThdCreateFromMemoryPool Z $õ Ø nvicEnableVector I nvicDisableVector nvicSetSystemHandlerPriority % È \ ý _port_irq_epilogue @ ø D F SysTickVector Ý SVCallVector # _port_init \L x ] SD1 i SD2 " @ ` B PWMD3 P PWMD4 $ ¼ « GPTD2 (w ô Ü vtlist - Äü @ ý __early_init boardInit % þ ñ pal_default_config
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.ARM.Collect$$libshutdown$$0000000F ../clib/angel/rt.s ../clib/signal.s ../clib/angel/dclz77c.s !!dclz77c ../clib/angel/scatter.s !!!scatter ../clib/angel/handlers.s !!handler_zi BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 __ARM_use_no_argv __Vectors __main __scatterload __scatterload_rt2 __scatterload_rt2_thumb_only __scatterload_null __decompress __decompress2 __scatterload_zeroinit __rt_lib_init __rt_lib_init_alloca_1 __rt_lib_init_argv_1 __rt_lib_init_atexit_1 __rt_lib_init_clock_1 __rt_lib_init_cpp_1 __rt_lib_init_exceptions_1 __rt_lib_init_fp_1 __rt_lib_init_fp_trap_1 __rt_lib_init_getenv_1 __rt_lib_init_heap_1 __rt_lib_init_lc_collate_1 __rt_lib_init_lc_ctype_1 __rt_lib_init_lc_monetary_1 __rt_lib_init_lc_numeric_1 __rt_lib_init_lc_time_1 __rt_lib_init_rand_1 __rt_lib_init_return __rt_lib_init_signal_1 __rt_lib_init_stdio_1 __rt_lib_init_user_alloc_1 __rt_lib_shutdown __rt_lib_shutdown_fp_trap_1 __rt_lib_shutdown_heap_1 __rt_lib_shutdown_return __rt_lib_shutdown_signal_1 __rt_lib_shutdown_stdio_1 __rt_lib_shutdown_user_alloc_1 __rt_entry __rt_entry_presh_1 __rt_entry_sh __rt_entry_li __rt_entry_postsh_1 __rt_entry_main __rt_entry_postli_1 __rt_exit __rt_exit_ls __rt_exit_prels_1 __rt_exit_exit __early_init boardInit Reset_Handler __user_initial_stackheap _port_switch _port_thread_start _port_switch_from_isr _port_exit_from_isr _port_irq_epilogue SysTickVector SVCallVector _port_init BusFaultVector DebugMonitorVector HardFaultVector MemManageVector NMIVector PendSVVector UsageFaultVector Vector1C Vector20 Vector24 Vector28 Vector34 Vector40 Vector44 Vector48 Vector4C Vector50 Vector54 Vector58 Vector5C Vector60 Vector64 Vector68 Vector6C Vector70 Vector74 Vector78 Vector7C Vector80 Vector84 Vector88 Vector8C Vector90 Vector94 Vector98 Vector9C VectorA0 VectorA4 VectorA8 VectorAC VectorBC VectorC0 VectorC4 VectorC8 VectorCC VectorD0 VectorDC VectorE0 VectorE4 VectorE8 VectorEC VectorF0 _unhandled_exception nvicEnableVector nvicDisableVector nvicSetSystemHandlerPriority chThdAddRef chThdRelease chThdCreateFromHeap chThdCreateFromMemoryPool chEvtRegisterMask chEvtUnregister chEvtGetAndClearEvents chEvtAddEvents chEvtSignalI chEvtBroadcastFlagsI chEvtGetAndClearFlags chEvtSignal chEvtBroadcastFlags chEvtGetAndClearFlagsI chEvtDispatch chEvtWaitOne chEvtWaitAny chEvtWaitAll chEvtWaitOneTimeout chEvtWaitAnyTimeout chEvtWaitAllTimeout _heap_init chHeapInit chHeapAlloc chHeapFree chHeapStatus _core_init chCoreAllocI chCoreAlloc chCoreStatus chPoolInit chPoolFreeI chPoolFree chPoolLoadArray chPoolAllocI chPoolAlloc chMtxInit chMtxLockS chMtxLock chMtxTryLockS chMtxTryLock chMtxUnlock chMtxUnlockS chMtxUnlockAll chIQInit chIQResetI chIQPutI chIQGetTimeout chIQReadTimeout chOQInit chOQResetI chOQPutTimeout chOQGetI chOQWriteTimeout _scheduler_init chSchReadyI chSchGoSleepS chSchGoSleepTimeoutS chSchWakeupS chSchDoRescheduleAhead chSchRescheduleS chSchDoRescheduleBehind chSchDoReschedule _idle_thread chSysInit chSysTimerHandlerI _thread_init chThdCreateI chThdCreateStatic chThdSetPriority chThdResume chThdTerminate chThdSleep chThdSleepUntil chThdYield chThdExitS chThdExit chThdWait _vt_init chVTSetI chVTResetI chTimeIsWithin gptInit gptObjectInit gptStart gptStop gptChangeInterval gptStartContinuousI gptStartContinuous gptStartOneShotI gptStartOneShot gptStopTimerI gptStopTimer gptPolledDelay halInit halIsCounterWithin halPolledDelay pwmInit pwmObjectInit pwmStart pwmStop pwmChangePeriod pwmEnableChannel pwmDisableChannel sdInit sdObjectInit sdStart sdStop sdIncomingDataI sdRequestDataI tmObjectInit tmInit chprintf VectorB4 VectorB8 pwm_lld_init pwm_lld_start pwm_lld_stop pwm_lld_enable_channel pwm_lld_disable_channel VectorD4 VectorD8 sd_lld_init sd_lld_start sd_lld_stop gpt_lld_stop_timer VectorB0 gpt_lld_init gpt_lld_start gpt_lld_stop gpt_lld_start_timer gpt_lld_polled_delay _pal_lld_init _pal_lld_setgroupmode hal_lld_init stm32_clock_init dekodujPrikaz main dekoduj_zpravu_GPS strstr __aeabi_memcpy4 __aeabi_memcpy8 __rt_memcpy_w _memcpy_lastbytes_aligned strncpy strcmp __use_two_region_memory __rt_heap_escrow$2region __rt_heap_expand$2region __aeabi_memclr __rt_memclr _memset __aeabi_memclr4 __aeabi_memclr8 __rt_memclr_w _memset_w exit _sys_exit __I$use$semihosting __use_no_semihosting_swi __semihosting_library_function pal_default_config ch_debug Region$$Table$$Base Region$$Table$$Limit tp_odpal uvitaci_zprava rlist _idle_thread_wa vtlist PWMD3 PWMD4 SD1 SD2 GPTD2 GPGGA_informace __main_thread_stack_base__ __initial_sp Image$$RW_IRAM1$$ZI$$Limit __initial_msp Image$$RW_IRAM2$$Base @ARM ARM Linker, 5.03 [Build 24]
ArmLink --strict --callgraph --map --symbols --xref --cpu=Cortex-M3 --fpu=SoftVFP --list=.\lst\ch.map --output=.\obj\ch.axf --scatter=.\obj\ch.sct --info=summarysizes,sizes,totals,unused,veneers
C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\c_w.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\fz_ws.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\h_w.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\m_ws.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\vfpsupport.l Input Comments: board.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\board.o --vfemode=force
Input Comments: p44e0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p44e0-2 board.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\board.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\board.crf cstartup.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\cstartup.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program chcoreasm_v7m.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\chcoreasm_v7m.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program chcore.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcore.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcore.crf chcore_v7m.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcore_v7m.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcore_v7m.crf nvic.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\nvic.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\nvic.crf chmempools.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmempools.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmempools.crf chregistry.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chregistry.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chregistry.crf chvt.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chvt.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chvt.crf vectors.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\vectors.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program chcond.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcond.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcond.crf chdebug.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chdebug.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chdebug.crf chdynamic.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chdynamic.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chdynamic.crf chevents.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chevents.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chevents.crf chheap.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chheap.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chheap.crf chlists.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chlists.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chlists.crf chmboxes.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmboxes.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmboxes.crf chmemcore.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmemcore.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmemcore.crf chmsg.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmsg.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmsg.crf chmtx.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmtx.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmtx.crf chqueues.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chqueues.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chqueues.crf chschd.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chschd.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chschd.crf chsem.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chsem.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chsem.crf chsys.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chsys.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chsys.crf chthreads.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chthreads.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chthreads.crf usb.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\usb.o --vfemode=force
Input Comments: p52a4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p52a4-2 usb.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\usb.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\usb.crf adc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\adc.o --vfemode=force
Input Comments: p46c0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p46c0-2 adc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\adc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\adc.crf can.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\can.o --vfemode=force
Input Comments: p4e28-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4e28-2 can.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\can.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\can.crf ext.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\ext.o --vfemode=force
Input Comments: p4524-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4524-2 ext.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\ext.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\ext.crf gpt.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\gpt.o --vfemode=force
Input Comments: p5324-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5324-2 gpt.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gpt.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gpt.crf hal.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\hal.o --vfemode=force
Input Comments: p502c-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p502c-2 hal.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\hal.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\hal.crf i2c.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\i2c.o --vfemode=force
Input Comments: p4f78-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4f78-2 i2c.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\i2c.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\i2c.crf icu.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\icu.o --vfemode=force
Input Comments: p51d0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p51d0-2 icu.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\icu.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\icu.crf mac.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mac.o --vfemode=force
Input Comments: p4e1c-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4e1c-2 mac.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mac.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mac.crf mmc_spi.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mmc_spi.o --vfemode=force
Input Comments: p4244-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4244-2 mmc_spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mmc_spi.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mmc_spi.crf pal.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pal.o --vfemode=force
Input Comments: p5164-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5164-2 pal.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pal.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pal.crf pwm.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pwm.o --vfemode=force
Input Comments: p42f0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p42f0-2 pwm.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pwm.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pwm.crf rtc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\rtc.o --vfemode=force
Input Comments: p534c-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p534c-2 rtc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\rtc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\rtc.crf sdc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\sdc.o --vfemode=force
Input Comments: p1c24-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p1c24-2 sdc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\sdc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\sdc.crf serial.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial.o --vfemode=force
Input Comments: p51b0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p51b0-2 serial.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial.crf serial_usb.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial_usb.o --vfemode=force
Input Comments: p2c64-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p2c64-2 serial_usb.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial_usb.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial_usb.crf spi.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\spi.o --vfemode=force
Input Comments: p5184-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5184-2 spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\spi.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\spi.crf tm.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\tm.o --vfemode=force
Input Comments: p3d8c-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p3d8c-2 tm.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\tm.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\tm.crf uart.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\uart.o --vfemode=force
Input Comments: p53d0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p53d0-2 uart.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\uart.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\uart.crf chprintf.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chprintf.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chprintf.crf mac_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mac_lld.o --vfemode=force
Input Comments: p4e98-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4e98-2 mac_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mac_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mac_lld.crf pwm_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pwm_lld.o --vfemode=force
Input Comments: p50dc-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p50dc-2 pwm_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pwm_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pwm_lld.crf serial_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial_lld.o --vfemode=force
Input Comments: p50d0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p50d0-2 serial_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial_lld.crf stm32_dma.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\stm32_dma.o --vfemode=force
Input Comments: p1eb0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p1eb0-2 stm32_dma.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\stm32_dma.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\stm32_dma.crf adc_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\adc_lld.o --vfemode=force
Input Comments: p5098-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5098-2 adc_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\adc_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\adc_lld.crf gpt_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\gpt_lld.o --vfemode=force
Input Comments: p4f90-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p4f90-2 gpt_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gpt_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gpt_lld.crf pal_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pal_lld.o --vfemode=force
Input Comments: p5258-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5258-2 pal_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pal_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pal_lld.crf hal_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\hal_lld.o --vfemode=force
Input Comments: p10b4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p10b4-2 hal_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\hal_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\hal_lld.crf main.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\main.o --vfemode=force
Input Comments: p5b14-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Jichy\AppData\Local\Temp\p5b14-2 main.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\main.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\main.crf gps_dekoduj.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gps_dekoduj.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gps_dekoduj.crf kom_uziv.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\kom_uziv.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv1 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32F1xx -I..\..\..\boards\MLAB_STM32F10xRxT01A -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\kom_uziv.crf argv_veneer.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_execstack --no_generate_mapping_symbols --diag_suppress=6642 --cpu=7-M --fpu=None --no_unaligned_access --output=argv_veneer.o --vfemode=force --branchpatch=m3-ldrd
Input Comments: ER_IROM1 RW_IRAM1 RW_IRAM2 .debug_abbrev .debug_frame .debug_info .debug_line .debug_loc .debug_macinfo .debug_pubnames .symtab .strtab .note .comment .shstrtab 4 <4 I 4 \3
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