Ø HÞ@ ¶Ù, ..\..\..\os\kernel\include\ch.h ìïé ¡Ù ..\chconf.h Á¸ Ù4 (..\..\..\os\ports\RVCT\ARMCMx\chtypes.h Èϳ ÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stddef.h Уç 'ÙD 8C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdint.h Уç ÙE 9C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdbool.h Ð£ç ¨Ù1 %..\..\..\os\kernel\include\chlists.h á´ Ù3 '..\..\..\os\ports\RVCT\ARMCMx\chcore.h á´ ,Ù? 3..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx\cmparams.h á´ Ù7 +..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h á´ «Ù3 '..\..\..\os\ports\common\ARMCMx\nvic.h á´ ¦Ù/ #..\..\..\os\kernel\include\chsys.h á´ ÔÙ. "..\..\..\os\kernel\include\chvt.h Èþ Ù0 $..\..\..\os\kernel\include\chschd.h á´ Ù/ #..\..\..\os\kernel\include\chsem.h á´ îÙ0 $..\..\..\os\kernel\include\chbsem.h á´ Ù/ #..\..\..\os\kernel\include\chmtx.h á´ ÚÙ0 $..\..\..\os\kernel\include\chcond.h á´ Ù2 &..\..\..\os\kernel\include\chevents.h ¹§ ÏÙ/ #..\..\..\os\kernel\include\chmsg.h á´ ìÙ2 &..\..\..\os\kernel\include\chmboxes.h á´ Ù3 '..\..\..\os\kernel\include\chmemcore.h á´ CÙ0 $..\..\..\os\kernel\include\chheap.h á´ Ù4 (..\..\..\os\kernel\include\chmempools.h á´ ½Ù3 '..\..\..\os\kernel\include\chthreads.h ÿ 5Ù3 '..\..\..\os\kernel\include\chdynamic.h á´ FÙ4 (..\..\..\os\kernel\include\chregistry.h á´ °Ù2 &..\..\..\os\kernel\include\chinline.h á´ ®Ù2 &..\..\..\os\kernel\include\chqueues.h á´ Ù3 '..\..\..\os\kernel\include\chstreams.h á´ ,Ù1 %..\..\..\os\kernel\include\chfiles.h á´ Ù1 %..\..\..\os\kernel\include\chdebug.h ÜÏõ µÙ* ..\..\..\os\hal\include\hal.h á´ Ù9 -..\..\..\boards\MLAB_STM32F10xRxT01A\board.h »Ô½ 6Ù
..\halconf.h ËÞ« ñÙ
..\mcuconf.h Á²º Ù: ...\..\..\os\hal\platforms\STM32F1xx\hal_lld.h å¶Û Ù4 (..\..\..\os\hal\platforms\STM32\stm32.h å¶Û Ù< 0..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h ¸Ãö ïÙE 9..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cm3.h ⺤þ ÙI =..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmInstr.h ⺤þ ¡ÙH <..\..\..\os\ports\common\ARMCMx\CMSIS\include\core_cmFunc.h ÒÀ¤þ 1Ù? 3..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h å¶Û ¨Ù< 0..\..\..\os\hal\platforms\STM32F1xx\stm32_isr.h å¶Û qÙ< 0..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h å¶Û Ù< 0..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h å¶Û Ù1 %..\..\..\os\hal\include\io_channel.h Ìç Ù/ #..\..\..\os\hal\include\io_block.h Õ
CÙ, ..\..\..\os\hal\include\mmcsd.h Ü QÙ) ..\..\..\os\hal\include\tm.h á´ uÙ* ..\..\..\os\hal\include\pal.h á´ Ù= 1..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h å¶Û 2Ù* ..\..\..\os\hal\include\adc.h Ë©³ 3Ù* ..\..\..\os\hal\include\can.h Ó¸§ Ù* ..\..\..\os\hal\include\ext.h á´ Ù* ..\..\..\os\hal\include\gpt.h ÄØ Ù6 *..\..\..\os\hal\platforms\STM32\gpt_lld.h þ ÉÙ* ..\..\..\os\hal\include\i2c.h Òâì ãÙ* ..\..\..\os\hal\include\icu.h á´ Ù* ..\..\..\os\hal\include\mac.h á´ #Ù* ..\..\..\os\hal\include\pwm.h ± \Ù6 *..\..\..\os\hal\platforms\STM32\pwm_lld.h ý¶ Ù* ..\..\..\os\hal\include\rtc.h á´ Ù- !..\..\..\os\hal\include\serial.h á´ ÎÙA 5..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h å¶Û Ù* ..\..\..\os\hal\include\sdc.h á´ Ù* ..\..\..\os\hal\include\spi.h á´ Ù+ ..\..\..\os\hal\include\uart.h á´ Ù* ..\..\..\os\hal\include\usb.h ¤õ Ù. "..\..\..\os\hal\include\mmc_spi.h
ÞÙ1 %..\..\..\os\hal\include\serial_usb.h ë«
-Ù& ..\..\..\os\hal\src\mac.c Á¾ åÚ P _CH_H_ ÏÚ P
_CHIBIOS_RT_ ïÚ P CH_KERNEL_VERSION yÚ P CH_KERNEL_MAJOR *Ú P CH_KERNEL_MINOR Ú P CH_KERNEL_PATCH 3Ú P FALSE VÚ
P TRUE Ú P CH_SUCCESS ´Ú P
CH_FAILED *Ú P _CHCONF_H_ ¡Ú P
CH_FREQUENCY Ú P CH_TIME_QUANTUM
Ú P CH_MEMCORE_SIZE !Ú P CH_NO_IDLE_THREAD Ú P CH_OPTIMIZE_SPEED ~Ú P CH_USE_REGISTRY þÚ P CH_USE_WAITEXIT Ú P CH_USE_SEMAPHORES |Ú# P CH_USE_SEMAPHORES_PRIORITY Ú P
CH_USE_SEMSW îÚ P CH_USE_MUTEXES NÚ P CH_USE_CONDVARS Ú P CH_USE_CONDVARS_TIMEOUT Ú P CH_USE_EVENTS ¦Ú P CH_USE_EVENTS_TIMEOUT Ú P CH_USE_MESSAGES Ú! P CH_USE_MESSAGES_PRIORITY ,Ú P CH_USE_MAILBOXES ÑÚ P CH_USE_QUEUES £Ú P CH_USE_MEMCORE qÚ P CH_USE_HEAP aÚ P CH_USE_MALLOC_HEAP <Ú P CH_USE_MEMPOOLS Ú P CH_USE_DYNAMIC tÚ" P CH_DBG_SYSTEM_STATE_CHECK Ú P CH_DBG_ENABLE_CHECKS ÖÚ P CH_DBG_ENABLE_ASSERTS `Ú P CH_DBG_ENABLE_TRACE Ú" P CH_DBG_ENABLE_STACK_CHECK JÚ P CH_DBG_FILL_THREADS þÚ! P CH_DBG_THREADS_PROFILING qÚ P THREAD_EXT_FIELDS Ú P THREAD_EXT_INIT_HOOK xÚ P THREAD_EXT_EXIT_HOOK rÚ# P THREAD_CONTEXT_SWITCH_HOOK Ú P IDLE_LOOP_HOOK hÚ P SYSTEM_TICK_EVENT_HOOK ¿Ú P SYSTEM_HALT_HOOK ®Ú P _CHTYPES_H_ 0Ú P __stddef_h ¸Ú P __ARMCLIB_VERSION lÚ P __STDDEF_DECLS mÚ P __CLIBNS BÚ P __cplusplus
Ú
ptrdiff_t -Ú size_t gÚ wchar_t Ú
P NULL Ú P offsetof _Ú P __stdint_h Ú P __STDINT_DECLS QÚ int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ
int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú
int_fast16_t WÚ
int_fast32_t YÚ
int_fast64_t TÚ
uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ intptr_t }Ú
uintptr_t Ú intmax_t Ú
uintmax_t Ú P INT8_MIN UÚ P
INT16_MIN $Ú P
INT32_MIN &Ú P
INT64_MIN !Ú P INT8_MAX SÚ P
INT16_MAX "Ú P
INT32_MAX $Ú P
INT64_MAX Ú P
UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P
WCHAR_MIN Ú P
WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P
UINTMAX_C ñÚ& P __bool_true_false_are_defined ÙÚ
P bool Ú
P true Ú P false ¶Ú bool_t vÚ tmode_t Ú tstate_t Ú trefs_t üÚ
tslices_t %Ú tprio_t òÚ msg_t ÝÚ
eventid_t -Ú eventmask_t JÚ flagsmask_t _Ú
systime_t Ú cnt_t ßÚ P INLINE Ú P ROMCONST FÚ P PACK_STRUCT_STRUCT Ú P PACK_STRUCT_BEGIN Ú P PACK_STRUCT_END Ú P _CHLISTS_H_ 6Ú 8 Thread aÚ Thread Ú P queue_init Ú P
list_init êÚ P isempty ²Ú P notempty ;Ú P _THREADSQUEUE_DATA ?Ú P THREADSQUEUE_DECL ¢Ú 8
<unnamed> QÚ " ¶p_next jÚ " ¶p_prev lÚ
ThreadsQueue Ú 8
<unnamed> QÚ " ºp_next fÚ ThreadsList Ú P _CHCORE_H_ Ú P
CORTEX_M0 Ú P
CORTEX_M1 Ú P
CORTEX_M3 Ú P
CORTEX_M4 Ú P
_CMPARAMS_H_ úÚ P
CORTEX_MODEL Ú P CORTEX_HAS_ST Ú P CORTEX_HAS_MPU NÚ P CORTEX_HAS_FPU UÚ P CORTEX_PRIORITY_BITS \Ú P CORTEX_PRIORITY_LEVELS ¿Ú P CORTEX_MINIMUM_PRIORITY lÚ P CORTEX_MAXIMUM_PRIORITY jÚ! P CORTEX_IS_VALID_PRIORITY Ú( P CORTEX_IS_VALID_KERNEL_PRIORITY íÚ P CORTEX_PRIORITY_MASK bÚ P CH_ARCHITECTURE_ARM ùÚ P CH_COMPILER_NAME æÚ P _CHCORE_V7M_H_ ]Ú P CORTEX_BASEPRI_DISABLED ÌÚ$ P PORT_IDLE_THREAD_STACK_SIZE MÚ P PORT_INT_REQUIRED_STACK yÚ P CORTEX_ENABLE_WFI_IDLE Ú P CORTEX_PRIORITY_SYSTICK ^Ú P CORTEX_USE_FPU DÚ# P CORTEX_SIMPLIFIED_PRIORITY Ú P CORTEX_PRIORITY_SVCALL ÅÚ P CORTEX_VTOR_INIT Ú P CORTEX_PRIGROUP_INIT dÚ# P CORTEX_MAX_KERNEL_PRIORITY |Ú P CORTEX_BASEPRI_KERNEL GÚ P CORTEX_PRIORITY_PENDSV ºÚ P CH_ARCHITECTURE_ARM_v7M Ú P CH_ARCHITECTURE_NAME ¶Ú P CH_CORE_VARIANT_NAME Ú P
CH_PORT_INFO ùÚ regarm_t Ú stkalign_t ½Ú 8 extctx Ú
" är0 0Ú
" är1 /Ú
" är2 .Ú
" är3 -Ú " är12 ûÚ " älr_thd MÚ
" äpc ÿÚ " äxpsr Ú 8 intctx Ú
" ír4 #Ú
" ír5 "Ú
" ír6 !Ú
" ír7 Ú
" ír8 Ú
" ír9 Ú " ír10 ôÚ " ír11 óÚ
" ílr ëÚ 8 context ²Ú " ÷r13 çÚ P SETUP_CONTEXT Ú P STACK_ALIGN uÚ P THD_WA_SIZE DÚ P
WORKING_AREA Ú P PORT_IRQ_PROLOGUE MÚ P PORT_IRQ_EPILOGUE `Ú P PORT_IRQ_HANDLER ¾Ú P PORT_FAST_IRQ_HANDLER 'Ú P
port_init áÚ P
port_lock ìÚ P port_unlock Ú P port_lock_from_isr Ú P port_unlock_from_isr 3Ú P
port_disable »Ú P
port_suspend Ú P port_enable *Ú P port_wait_for_interrupt ÒÚ P port_switch ÿÚ
port_halt Ú _port_init Ú _port_irq_epilogue <Ú _port_switch_from_isr éÚ _port_exit_from_isr ÅÚ , ntp yÚ , otp xÚ
_port_switch »Ú _port_thread_start <Ú P _NVIC_H_ &Ú P HANDLER_MEM_MANAGE cÚ P HANDLER_BUS_FAULT Ú P HANDLER_USAGE_FAULT øÚ P HANDLER_RESERVED_3 XÚ P HANDLER_RESERVED_4 WÚ P HANDLER_RESERVED_5 VÚ P HANDLER_RESERVED_6 UÚ P HANDLER_SVCALL Ú P HANDLER_DEBUG_MONITOR VÚ P HANDLER_RESERVED_9 RÚ P HANDLER_PENDSV Ú P HANDLER_SYSTICK &Ú IOREG8 GÚ IOREG32 Ú P
NVIC_ITCR øÚ 8
<unnamed> QÚ
" ¤CSR 5Ú
" ¤RVR #Ú
" ¤CVR 2Ú
" ¤CBVR îÚ CMx_ST çÚ P STBase Ú P ST_CSR ÑÚ P ST_RVR ¿Ú P ST_CVR ÎÚ P ST_CBVR Ú P CSR_ENABLE_MASK 4Ú P ENABLE_OFF_BITS ;Ú P ENABLE_ON_BITS {Ú P CSR_TICKINT_MASK ÃÚ P TICKINT_DISABLED_BITS cÚ P TICKINT_ENABLED_BITS ²Ú P CSR_CLKSOURCE_MASK *Ú P CLKSOURCE_EXT_BITS Ú P CLKSOURCE_CORE_BITS áÚ P CSR_COUNTFLAG_MASK 2Ú P RVR_RELOAD_MASK Ú P CVR_CURRENT_MASK ³Ú P CBVR_TENMS_MASK Ú P CBVR_SKEW_MASK ^Ú P CBVR_NOREF_MASK Ú 8
<unnamed> QÚ <" ¾ISER Ú <" `¾unused1 ¨Ú <" ¾ICER Ú <" `¾unused2 §Ú <" ¾ISPR uÚ <" `¾unused3 ¦Ú <" ¾ICPR
Ú <" `¾unused4 ¥Ú <" ¾IABR Ú <" à¾unused5 "Ú <" ð¾IPR øÚ <" ¾unused6 ^Ú
" ¾STIR ¿Ú CMx_NVIC ZÚ P NVICBase Ú P
NVIC_ISER ÷Ú P
NVIC_ICER Ú P
NVIC_ISPR ìÚ P
NVIC_ICPR üÚ P
NVIC_IABR Ú P NVIC_IPR AÚ P
NVIC_STIR èÚ 8
<unnamed> QÚ
" ÕCPUID sÚ
" ÕICSR ¹Ú
" ÕVTOR Ú
" ÕAIRCR wÚ
" ÕSCR Ú
" ÕCCR Ú <" ÕSHPR sÚ
" ÕSHCSR eÚ
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" ÕHFSR ·Ú
" ÕDFSR »Ú
" ÕMMFAR uÚ
" ÕBFAR ÏÚ
" ÕAFSR ¾Ú <" ÕPFR ÎÚ
" ÕDFR Ú
" ÕADR Ú <" ÕMMFR zÚ <" ÕSAR ÄÚ <" Õunused1 ÝÚ
" ÕCPACR Ú CMx_SCB ´Ú P SCBBase jÚ P
SCB_CPUID
Ú P SCB_ICSR SÚ P SCB_VTOR 9Ú P
SCB_AIRCR Ú P SCB_SCR Ú P SCB_CCR ®Ú P SCB_SHPR GÚ P
SCB_SHCSR ÿÚ P SCB_CFSR VÚ P SCB_HFSR QÚ P SCB_DFSR UÚ P
SCB_MMFAR Ú P SCB_BFAR iÚ P SCB_AFSR XÚ P SCB_PFR Ú P SCB_DFR ªÚ P SCB_ADR ¯Ú P SCB_MMFR RÚ P SCB_SAR Ú P
SCB_CPACR Ú P ICSR_VECTACTIVE_MASK Ú P ICSR_RETTOBASE vÚ P ICSR_VECTPENDING_MASK OÚ P ICSR_ISRPENDING *Ú P ICSR_ISRPREEMPT Ú P ICSR_PENDSTCLR pÚ P ICSR_PENDSTSET eÚ P ICSR_PENDSVCLR nÚ P ICSR_PENDSVSET cÚ P ICSR_NMIPENDSET &Ú P AIRCR_VECTKEY ÆÚ P AIRCR_PRIGROUP_MASK ÒÚ P AIRCR_PRIGROUP gÚ 8
<unnamed> QÚ <" unused1 3Ú
" FPCCR ÀÚ
" FPCAR ÂÚ
" FPDSCR jÚ
" MVFR0 ÃÚ
" MVFR1 ÂÚ CMx_FPU ¡Ú P FPUBase WÚ P
SCB_FPCCR Ú P
SCB_FPCAR Ú P SCB_FPDSCR ¾Ú P
SCB_MVFR0 Ú P
SCB_MVFR1 Ú P FPCCR_ASPEN qÚ P FPCCR_LSPEN fÚ P
FPCCR_MONRDY
Ú P FPCCR_BFRDY qÚ P FPCCR_MMRDY _Ú P FPCCR_HFRDY kÚ P
FPCCR_THREAD .Ú P FPCCR_USER «Ú P
FPCCR_LSPACT Ú P FPDSCR_AHP ½Ú P
FPDSCR_DN Ú P
FPDSCR_FZ øÚ P
FPDSCR_RMODE Ú 8
<unnamed> QÚ
" ©DHCSR Ú
" ©DCRSR Ú
" ©DCRDR ¤Ú
" ©DEMCR ¨Ú CMx_SCS £Ú P SCSBase YÚ P
SCS_DHCSR ýÚ P
SCS_DCRSR óÚ P
SCS_DCRDR Ú P
SCS_DEMCR Ú P SCS_DEMCR_TRCENA ÜÚ 8
<unnamed> QÚ
" µCTRL ÔÚ
" µCYCCNT AÚ
" µCPICNT DÚ
" µEXCCNT @Ú
" µ SLEEPCNT £Ú
" µLSUCNT ,Ú
" µFOLDCNT ùÚ
" µPCSR ÑÚ CMx_DWT Ú P DWTBase SÚ P DWT_CTRL 8Ú P DWT_CYCCNT ¥Ú P DWT_CPICNT ¨Ú P DWT_EXCCNT ¤Ú P
DWT_SLEEPCNT Ú P DWT_LSUCNT Ú P DWT_FOLDCNT ]Ú P DWT_PCSR 5Ú P DWT_CTRL_CYCCNTENA -Ú
,
n oÚ
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prio Ú nvicEnableVector ^Ú
,
n oÚ nvicDisableVector ïÚ ,
handler óÚ
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prio Ú% nvicSetSystemHandlerPriority /Ú, P $PORT_OPTIMIZED_ISPREEMPTIONREQUIRED ÍÚ" P chSchIsPreemptionRequired Ú P
_CHSYS_H_ ÊÚ P chSysGetIdleThread §Ú P
chSysHalt &Ú P chSysSwitch 9Ú P
chSysDisable õÚ P
chSysSuspend ÇÚ P chSysEnable dÚ P
chSysLock &Ú P chSysUnlock ?Ú P chSysLockFromIsr VÚ P chSysUnlockFromIsr oÚ P CH_IRQ_PROLOGUE Ú P CH_IRQ_EPILOGUE Ú P CH_IRQ_HANDLER |Ú P CH_FAST_IRQ_HANDLER åÚ
chSysInit 8Ú chSysTimerHandlerI ²Ú P _CHVT_H_ !Ú
P S2ST Ú P MS2ST HÚ P US2ST @Ú vtfunc_t Ú 8
VirtualTimer ÅÚ
VirtualTimer Ú " évt_next ¹Ú " évt_prev »Ú
" évt_time ×Ú " évt_func ÌÚ " évt_par 7Ú 8
<unnamed> QÚ " ðvt_next ²Ú " ðvt_prev ´Ú
" ðvt_time ÐÚ
" ð vt_systime kÚ VTList ¯Ú P chVTDoTickI ¹Ú P
chVTIsArmedI PÚ P chVTSet Ú P
chVTReset AÚ P
chTimeNow +Ú vtlist +Ú _vt_init |Ú , vtp qÚ
,
time (Ú , vtfunc /Ú , par Ú chVTSetI îÚ , vtp qÚ chVTResetI Ú ,
start §Ú ,
end ¢Ú chTimeIsWithin CÚ P _CHSCHD_H_ ¥Ú P RDY_OK ×Ú P RDY_TIMEOUT @Ú P
RDY_RESET èÚ P NOPRIO èÚ P IDLEPRIO cÚ P LOWPRIO Ú P NORMALPRIO ´Ú P HIGHPRIO aÚ P ABSPRIO Ú P TIME_IMMEDIATE Ú P TIME_INFINITE ÍÚ P
firstprio ×Ú 8
<unnamed> QÚ " r_queue Ú
" r_prio Ú " r_ctx õÚ " r_newer #Ú " r_older .Ú "
r_current =Ú
ReadyList ^Ú rlist Ú P currp Ú P setcurrp CÚ _scheduler_init Ú , tp éÚ chSchReadyI «Ú , newstate kÚ chSchGoSleepS ãÚ , newstate kÚ
,
time (Ú chSchGoSleepTimeoutS îÚ , tp éÚ , msg Ú
chSchWakeupS 'Ú chSchRescheduleS Ú chSchDoRescheduleBehind ÐÚ chSchDoRescheduleAhead IÚ chSchDoReschedule &Ú P chSchIsRescRequiredI çÚ P chSchCanYieldS jÚ P chSchDoYieldS ËÚ P chSchPreemption ¡Ú P
_CHSEM_H_ äÚ 8
Semaphore Ú " ³s_queue ÷Ú " ³s_cnt óÚ
Semaphore KÚ , sp êÚ
, n qÚ
chSemInit RÚ , sp êÚ
, n qÚ chSemReset áÚ , sp êÚ
, n qÚ chSemResetI Ú , sp êÚ
chSemWait QÚ , sp êÚ chSemWaitS üÚ , sp êÚ
,
time (Ú chSemWaitTimeout \Ú , sp êÚ
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time (Ú chSemWaitTimeoutS Ú , sp êÚ chSemSignal Ú , sp êÚ
chSemSignalI 9Ú , sp êÚ
, n qÚ chSemAddCounterI ¦Ú , sps uÚ , spw qÚ chSemSignalWait çÚ P _SEMAPHORE_DATA 1Ú P SEMAPHORE_DECL Ú P chSemFastWaitI SÚ P chSemFastSignalI Ú P chSemGetCounterI rÚ P _CHBSEM_H_ Ú 8
<unnamed> QÚ " Úbs_sem LÚ BinarySemaphore ÚÚ P _BSEMAPHORE_DATA íÚ P BSEMAPHORE_DECL PÚ P chBSemInit ñÚ P chBSemWait ðÚ P chBSemWaitS Ú P chBSemWaitTimeout ûÚ P chBSemWaitTimeoutS ¦Ú P chBSemReset Ú P
chBSemResetI 5Ú P
chBSemSignal #Ú P chBSemSignalI ØÚ P chBSemGetStateI Ú P
_CHMTX_H_ ÐÚ 8 Mutex ¨Ú " êm_queue ÆÚ " êm_owner ÈÚ " êm_next 6Ú Mutex äÚ , mp ðÚ
chMtxInit >Ú , mp ðÚ
chMtxLock IÚ , mp ðÚ chMtxLockS ôÚ , mp ðÚ
chMtxTryLock Ú , mp ðÚ chMtxTryLockS ¯Ú chMtxUnlock bÚ
chMtxUnlockS
Ú chMtxUnlockAll CÚ P _MUTEX_DATA JÚ P MUTEX_DECL Ú P chMtxQueueNotEmptyS Ú P _CHCOND_H_ £Ú 8 CondVar
Ú " c_queue 9Ú CondVar FÚ , cp úÚ chCondInit ñÚ , cp úÚ
chCondSignal #Ú , cp úÚ chCondSignalI ØÚ , cp úÚ chCondBroadcast èÚ , cp úÚ chCondBroadcastI Ú , cp úÚ chCondWait ðÚ , cp úÚ chCondWaitS Ú , cp úÚ
,
time (Ú chCondWaitTimeout ûÚ , cp úÚ
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time (Ú chCondWaitTimeoutS ¦Ú P _CONDVAR_DATA ÌÚ P
CONDVAR_DECL /Ú P
_CHEVENTS_H_ îÚ 8 EventListener cÚ EventListener Ú " el_next Ú " el_listener pÚ
" el_mask @Ú
" el_flags ÝÚ 8 EventSource <Ú " es_next Ú EventSource xÚ evhandler_t _Ú P _EVENTSOURCE_DATA ~Ú P EVENTSOURCE_DECL áÚ P ALL_EVENTS ªÚ P EVENT_MASK ªÚ P chEvtRegister rÚ P
chEvtInit +Ú P chEvtIsListeningI ýÚ P chEvtBroadcast "Ú P chEvtBroadcastI ×Ú , esp Ú , elp Ú
,
mask +Ú chEvtRegisterMask ûÚ , esp Ú , elp Ú chEvtUnregister ¨Ú
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mask +Ú chEvtGetAndClearEvents 3Ú
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mask +Ú chEvtAddEvents TÚ , elp Ú chEvtGetAndClearFlags ½Ú , elp Ú chEvtGetAndClearFlagsI rÚ , tp éÚ
,
mask +Ú chEvtSignal zÚ , tp éÚ
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mask +Ú
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flags ÈÚ chEvtBroadcastFlags HÚ , esp Ú ,
flags ÈÚ chEvtBroadcastFlagsI ýÚ , handlers pÚ
,
mask +Ú chEvtDispatch ¤Ú
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chEvtWaitOne Ú
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mask +Ú
chEvtWaitAny Ú
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mask +Ú
chEvtWaitAll (Ú
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mask +Ú
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time (Ú chEvtWaitOneTimeout *Ú
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mask +Ú
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time (Ú chEvtWaitAnyTimeout $Ú
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time (Ú chEvtWaitAllTimeout 3Ú P
_CHMSG_H_ âÚ P chMsgIsPendingI ñÚ P chMsgGet ©Ú P chMsgReleaseS «Ú , tp éÚ , msg Ú
chMsgSend ZÚ
chMsgWait OÚ , tp éÚ , msg Ú
chMsgRelease Ú P
_CHMBOXES_H_ õÚ 8
<unnamed> QÚ " æ
mb_buffer Ú " æmb_top CÚ " æ mb_wrptr SÚ " æ mb_rdptr fÚ " æ mb_fullsem Ú " æ mb_emptysem Ú Mailbox 'Ú , mbp Ú , buf Ú
, n qÚ chMBInit êÚ , mbp Ú
chMBReset yÚ , mbp Ú , msg Ú ,
timeout ÊÚ chMBPost ØÚ , mbp Ú , msg Ú ,
timeout ÊÚ
chMBPostS Ú , mbp Ú , msg Ú
chMBPostI Ú , mbp Ú , msg Ú ,
timeout ÊÚ chMBPostAhead ûÚ , mbp Ú , msg Ú ,
timeout ÊÚ chMBPostAheadS ¦Ú , mbp Ú , msg Ú chMBPostAheadI °Ú , mbp Ú
, msgp Ú ,
timeout ÊÚ
chMBFetch Ú , mbp Ú
, msgp Ú ,
timeout ÊÚ chMBFetchS =Ú , mbp Ú
, msgp Ú chMBFetchI GÚ P
chMBSizeI {Ú P chMBGetFreeCountI [Ú P chMBGetUsedCountI LÚ P
chMBPeekI Ú P _MAILBOX_DATA ÍÚ P
MAILBOX_DECL 0Ú P _CHMEMCORE_H_ ¹Ú
memgetfunc_t ëÚ P MEM_ALIGN_SIZE lÚ P MEM_ALIGN_MASK {Ú P MEM_ALIGN_PREV jÚ P MEM_ALIGN_NEXT hÚ P MEM_IS_ALIGNED Ú _core_init ¹Ú
,
size Ú chCoreAlloc Ú
,
size Ú
chCoreAllocI HÚ
chCoreStatus øÚ P _CHHEAP_H_ ©Ú 8 memory_heap Ú MemoryHeap öÚ 8 heap_header KÚ (" «align áÚ 8
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STM32_ADCPRE LÚ! P STM32_USB_CLOCK_REQUIRED nÚ P
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STM32_MCOSEL 8Ú P
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STM32_PLS Ú P STM32_ADC_USE_ADC1 Ú$ P STM32_ADC_ADC1_DMA_PRIORITY «Ú$ P STM32_ADC_ADC1_IRQ_PRIORITY Ú P STM32_CAN_USE_CAN1 oÚ$ P STM32_CAN_CAN1_IRQ_PRIORITY }Ú% P STM32_EXT_EXTI0_IRQ_PRIORITY õÚ% P STM32_EXT_EXTI1_IRQ_PRIORITY ôÚ% P STM32_EXT_EXTI2_IRQ_PRIORITY óÚ% P STM32_EXT_EXTI3_IRQ_PRIORITY òÚ% P STM32_EXT_EXTI4_IRQ_PRIORITY ñÚ' P STM32_EXT_EXTI5_9_IRQ_PRIORITY TÚ) P !STM32_EXT_EXTI10_15_IRQ_PRIORITY ÷Ú& P STM32_EXT_EXTI16_IRQ_PRIORITY ¼Ú& P STM32_EXT_EXTI17_IRQ_PRIORITY »Ú& P STM32_EXT_EXTI18_IRQ_PRIORITY ºÚ& P STM32_EXT_EXTI19_IRQ_PRIORITY ¹Ú P STM32_GPT_USE_TIM1 >Ú P STM32_GPT_USE_TIM2 =Ú P STM32_GPT_USE_TIM3 <Ú P STM32_GPT_USE_TIM4 ;Ú P STM32_GPT_USE_TIM5 :Ú P STM32_GPT_USE_TIM8 7Ú$ P STM32_GPT_TIM1_IRQ_PRIORITY LÚ$ P STM32_GPT_TIM2_IRQ_PRIORITY KÚ$ P STM32_GPT_TIM3_IRQ_PRIORITY JÚ$ P STM32_GPT_TIM4_IRQ_PRIORITY IÚ$ P STM32_GPT_TIM5_IRQ_PRIORITY HÚ$ P STM32_GPT_TIM8_IRQ_PRIORITY EÚ P STM32_I2C_USE_I2C1 Ú P STM32_I2C_USE_I2C2 Ú P STM32_I2C_USE_I2C3 Ú$ P STM32_I2C_I2C1_IRQ_PRIORITY ¥Ú$ P STM32_I2C_I2C2_IRQ_PRIORITY ¤Ú$ P STM32_I2C_I2C3_IRQ_PRIORITY £Ú$ P STM32_I2C_I2C1_DMA_PRIORITY ¿Ú$ P STM32_I2C_I2C2_DMA_PRIORITY ¾Ú$ P STM32_I2C_I2C3_DMA_PRIORITY ½Ú& P STM32_I2C_I2C1_DMA_ERROR_HOOK #Ú& P STM32_I2C_I2C2_DMA_ERROR_HOOK "Ú& P STM32_I2C_I2C3_DMA_ERROR_HOOK !Ú P STM32_ICU_USE_TIM1 HÚ P STM32_ICU_USE_TIM2 GÚ P STM32_ICU_USE_TIM3 FÚ P STM32_ICU_USE_TIM4 EÚ P STM32_ICU_USE_TIM5 DÚ P STM32_ICU_USE_TIM8 AÚ$ P STM32_ICU_TIM1_IRQ_PRIORITY VÚ$ P STM32_ICU_TIM2_IRQ_PRIORITY UÚ$ P STM32_ICU_TIM3_IRQ_PRIORITY TÚ$ P STM32_ICU_TIM4_IRQ_PRIORITY SÚ$ P STM32_ICU_TIM5_IRQ_PRIORITY RÚ$ P STM32_ICU_TIM8_IRQ_PRIORITY OÚ P STM32_PWM_USE_ADVANCED Ú P STM32_PWM_USE_TIM1 5Ú P STM32_PWM_USE_TIM2 4Ú P STM32_PWM_USE_TIM3 3Ú P STM32_PWM_USE_TIM4 2Ú P STM32_PWM_USE_TIM5 1Ú P STM32_PWM_USE_TIM8 .Ú$ P STM32_PWM_TIM1_IRQ_PRIORITY CÚ$ P STM32_PWM_TIM2_IRQ_PRIORITY BÚ$ P STM32_PWM_TIM3_IRQ_PRIORITY AÚ$ P STM32_PWM_TIM4_IRQ_PRIORITY @Ú$ P STM32_PWM_TIM5_IRQ_PRIORITY ?Ú$ P STM32_PWM_TIM8_IRQ_PRIORITY <Ú P STM32_RTC_IRQ_PRIORITY ÒÚ P STM32_SERIAL_USE_USART1 ºÚ P STM32_SERIAL_USE_USART2 ¹Ú P STM32_SERIAL_USE_USART3 ¸Ú P STM32_SERIAL_USE_UART4 Ú P STM32_SERIAL_USE_UART5 Ú P STM32_SERIAL_USE_USART6 µÚ% P STM32_SERIAL_USART1_PRIORITY Ú% P STM32_SERIAL_USART2_PRIORITY Ú% P STM32_SERIAL_USART3_PRIORITY Ú$ P STM32_SERIAL_UART4_PRIORITY mÚ$ P STM32_SERIAL_UART5_PRIORITY lÚ% P STM32_SERIAL_USART6_PRIORITY Ú P STM32_SPI_USE_SPI1 ;Ú P STM32_SPI_USE_SPI2 :Ú P STM32_SPI_USE_SPI3 9Ú$ P STM32_SPI_SPI1_DMA_PRIORITY cÚ$ P STM32_SPI_SPI2_DMA_PRIORITY bÚ$ P STM32_SPI_SPI3_DMA_PRIORITY aÚ$ P STM32_SPI_SPI1_IRQ_PRIORITY IÚ$ P STM32_SPI_SPI2_IRQ_PRIORITY HÚ$ P STM32_SPI_SPI3_IRQ_PRIORITY GÚ! P STM32_SPI_DMA_ERROR_HOOK MÚ P STM32_UART_USE_USART1 BÚ P STM32_UART_USE_USART2 AÚ P STM32_UART_USE_USART3 @Ú' P STM32_UART_USART1_IRQ_PRIORITY PÚ' P STM32_UART_USART2_IRQ_PRIORITY OÚ' P STM32_UART_USART3_IRQ_PRIORITY NÚ' P STM32_UART_USART1_DMA_PRIORITY jÚ' P STM32_UART_USART2_DMA_PRIORITY iÚ' P STM32_UART_USART3_DMA_PRIORITY hÚ" P STM32_UART_DMA_ERROR_HOOK ûÚ P STM32_USB_USE_USB1 ?Ú' P STM32_USB_LOW_POWER_ON_SUSPEND 3Ú' P STM32_USB_USB1_HP_IRQ_PRIORITY PÚ' P STM32_USB_USB1_LP_IRQ_PRIORITY LÚ P HAL_USE_TM Ú P HAL_USE_PAL XÚ P HAL_USE_ADC mÚ P HAL_USE_CAN cÚ P HAL_USE_EXT DÚ P HAL_USE_GPT JÚ P HAL_USE_I2C wÚ P HAL_USE_ICU TÚ P HAL_USE_MAC dÚ P HAL_USE_MMC_SPI Ú P HAL_USE_PWM AÚ P HAL_USE_RTC LÚ P HAL_USE_SDC [Ú P HAL_USE_SERIAL oÚ P HAL_USE_SERIAL_USB Ú P HAL_USE_SPI IÚ P
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USB_LP_CAN1_RX0_IRQn Ú " à
CAN1_RX1_IRQn áÚ " à
CAN1_SCE_IRQn áÚ " à
EXTI9_5_IRQn Ú " à
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" µ ADR +Ú <" µ MMFR Ú <" µ ISAR Ú <" µ
RESERVED0 $Ú
" µ CPACR Ú SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_RETTOBASE_Pos Ú P SCB_ICSR_RETTOBASE_Msk ¥Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_VTOR_TBLBASE_Pos 4Ú P SCB_VTOR_TBLBASE_Msk ;Ú P SCB_VTOR_TBLOFF_Pos vÚ P SCB_VTOR_TBLOFF_Msk }Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ P SCB_AIRCR_PRIGROUP_Pos Ú P SCB_AIRCR_PRIGROUP_Msk Ú" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_AIRCR_VECTRESET_Pos PÚ P SCB_AIRCR_VECTRESET_Msk WÚ P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_BFHFNMIGN_Pos Ú P SCB_CCR_BFHFNMIGN_Msk Ú P SCB_CCR_DIV_0_TRP_Pos ÛÚ P SCB_CCR_DIV_0_TRP_Msk âÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ! P SCB_CCR_USERSETMPEND_Pos ýÚ! P SCB_CCR_USERSETMPEND_Msk Ú# P SCB_CCR_NONBASETHRDENA_Pos Ú# P SCB_CCR_NONBASETHRDENA_Msk Ú" P SCB_SHCSR_USGFAULTENA_Pos °Ú" P SCB_SHCSR_USGFAULTENA_Msk ·Ú" P SCB_SHCSR_BUSFAULTENA_Pos µÚ" P SCB_SHCSR_BUSFAULTENA_Msk ¼Ú" P SCB_SHCSR_MEMFAULTENA_Pos ÀÚ" P SCB_SHCSR_MEMFAULTENA_Msk ÇÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú% P SCB_SHCSR_BUSFAULTPENDED_Pos ÓÚ% P SCB_SHCSR_BUSFAULTPENDED_Msk ÚÚ% P SCB_SHCSR_MEMFAULTPENDED_Pos ÞÚ% P SCB_SHCSR_MEMFAULTPENDED_Msk åÚ% P SCB_SHCSR_USGFAULTPENDED_Pos ÎÚ% P SCB_SHCSR_USGFAULTPENDED_Msk ÕÚ! P SCB_SHCSR_SYSTICKACT_Pos ïÚ! P SCB_SHCSR_SYSTICKACT_Msk öÚ P SCB_SHCSR_PENDSVACT_Pos KÚ P SCB_SHCSR_PENDSVACT_Msk RÚ! P SCB_SHCSR_MONITORACT_Pos ñÚ! P SCB_SHCSR_MONITORACT_Msk øÚ P SCB_SHCSR_SVCALLACT_Pos VÚ P SCB_SHCSR_SVCALLACT_Msk ]Ú" P SCB_SHCSR_USGFAULTACT_Pos ¬Ú" P SCB_SHCSR_USGFAULTACT_Msk ³Ú" P SCB_SHCSR_BUSFAULTACT_Pos ±Ú" P SCB_SHCSR_BUSFAULTACT_Msk ¸Ú" P SCB_SHCSR_MEMFAULTACT_Pos ¼Ú" P SCB_SHCSR_MEMFAULTACT_Msk ÃÚ P SCB_CFSR_USGFAULTSR_Pos 8Ú P SCB_CFSR_USGFAULTSR_Msk ?Ú P SCB_CFSR_BUSFAULTSR_Pos =Ú P SCB_CFSR_BUSFAULTSR_Msk DÚ P SCB_CFSR_MEMFAULTSR_Pos HÚ P SCB_CFSR_MEMFAULTSR_Msk OÚ P SCB_HFSR_DEBUGEVT_Pos ñÚ P SCB_HFSR_DEBUGEVT_Msk øÚ P SCB_HFSR_FORCED_Pos Ú P SCB_HFSR_FORCED_Msk Ú P SCB_HFSR_VECTTBL_Pos 5Ú P SCB_HFSR_VECTTBL_Msk <Ú P SCB_DFSR_EXTERNAL_Pos èÚ P SCB_DFSR_EXTERNAL_Msk ïÚ P SCB_DFSR_VCATCH_Pos Ú P SCB_DFSR_VCATCH_Msk Ú P SCB_DFSR_DWTTRAP_Pos 'Ú P SCB_DFSR_DWTTRAP_Msk .Ú P SCB_DFSR_BKPT_Pos "Ú P SCB_DFSR_BKPT_Msk )Ú P SCB_DFSR_HALTED_Pos Ú P SCB_DFSR_HALTED_Msk ¤Ú 8
<unnamed> QÚ <" À
RESERVED0 (Ú
" À
ICTR ÂÚ <" À
RESERVED1 'Ú SCnSCB_Type Ú$ P SCnSCB_ICTR_INTLINESNUM_Pos âÚ$ P SCnSCB_ICTR_INTLINESNUM_Msk éÚ! P SCnSCB_ACTLR_DISFOLD_Pos õÚ! P SCnSCB_ACTLR_DISFOLD_Msk üÚ$ P SCnSCB_ACTLR_DISDEFWBUF_Pos Ú$ P SCnSCB_ACTLR_DISDEFWBUF_Msk Ú$ P SCnSCB_ACTLR_DISMCYCINT_Pos ýÚ$ P SCnSCB_ACTLR_DISMCYCINT_Msk Ú 8
<unnamed> QÚ
" Í
CTRL ²Ú
" Í
LOAD ÇÚ
" Í
VAL Ú
" Í
CALIB Ú
SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú 8
<unnamed> QÚ 8
<unnamed> SÚ
" æ
u8 ,Ú " æ
u16 òÚ
" æ
u32 öÚ <" å
PORT ÚÚ <" å
RESERVED0 kÚ
" å
TER æÚ <" <å
RESERVED1 ÊÚ
" å
TPR ÛÚ <" <å
RESERVED2 ÉÚ
" å
TCR èÚ <" tå
RESERVED3 Ú
" å
IWR ßÚ
" å
IRR äÚ
" å
IMCR ¤Ú <" ¬å
RESERVED4 UÚ
" å
LAR òÚ
" å
LSR àÚ <" å
RESERVED5 êÚ
" å
PID4 ¾Ú
" å
PID5 ½Ú
" å
PID6 ¼Ú
" å
PID7 »Ú
" å
PID0 ÂÚ
" å
PID1 ÁÚ
" å
PID2 ÀÚ
" å
PID3 ¿Ú
" å
CID0 ÏÚ
" å
CID1 ÎÚ
" å
CID2 ÍÚ
" å
CID3 ÌÚ ITM_Type Ú P ITM_TPR_PRIVMASK_Pos Ú P ITM_TPR_PRIVMASK_Msk Ú P ITM_TCR_BUSY_Pos FÚ P ITM_TCR_BUSY_Msk MÚ P ITM_TCR_TraceBusID_Pos ×Ú P ITM_TCR_TraceBusID_Msk ÞÚ P ITM_TCR_GTSFREQ_Pos gÚ P ITM_TCR_GTSFREQ_Msk nÚ P ITM_TCR_TSPrescale_Pos §Ú P ITM_TCR_TSPrescale_Msk ®Ú P ITM_TCR_SWOENA_Pos ¸Ú P ITM_TCR_SWOENA_Msk ¿Ú P ITM_TCR_DWTENA_Pos ÂÚ P ITM_TCR_DWTENA_Msk ÉÚ P ITM_TCR_SYNCENA_Pos rÚ P ITM_TCR_SYNCENA_Msk yÚ P ITM_TCR_TSENA_Pos Ú P ITM_TCR_TSENA_Msk Ú P ITM_TCR_ITMENA_Pos ÇÚ P ITM_TCR_ITMENA_Msk ÎÚ P ITM_IWR_ATVALIDM_Pos &Ú P ITM_IWR_ATVALIDM_Msk -Ú P ITM_IRR_ATREADYM_Pos &Ú P ITM_IRR_ATREADYM_Msk -Ú! P ITM_IMCR_INTEGRATION_Pos óÚ! P ITM_IMCR_INTEGRATION_Msk úÚ P ITM_LSR_ByteAcc_Pos àÚ P ITM_LSR_ByteAcc_Msk çÚ P ITM_LSR_Access_Pos +Ú P ITM_LSR_Access_Msk 2Ú P ITM_LSR_Present_Pos Ú P ITM_LSR_Present_Msk ¡Ú 8
<unnamed> QÚ
" ¦CTRL ØÚ
" ¦CYCCNT EÚ
" ¦CPICNT HÚ
" ¦EXCCNT DÚ
" ¦ SLEEPCNT §Ú
" ¦LSUCNT 0Ú
" ¦FOLDCNT ýÚ
" ¦PCSR ÕÚ
" ¦COMP0 ¬Ú
" ¦MASK0 ¯Ú
" ¦
FUNCTION0 mÚ <" ¦
RESERVED0 AÚ
" ¦COMP1 «Ú
" ¦MASK1 ®Ú
" ¦
FUNCTION1 lÚ <" ¦
RESERVED1 @Ú
" ¦COMP2 ªÚ
" ¦MASK2 Ú
" ¦
FUNCTION2 kÚ <" ¦
RESERVED2 ?Ú
" ¦COMP3 ©Ú
" ¦MASK3 ¬Ú
" ¦
FUNCTION3 jÚ DWT_Type Ú P DWT_CTRL_NUMCOMP_Pos Ú P DWT_CTRL_NUMCOMP_Msk Ú P DWT_CTRL_NOTRCPKT_Pos ¹Ú P DWT_CTRL_NOTRCPKT_Msk ÀÚ P DWT_CTRL_NOEXTTRIG_Pos hÚ P DWT_CTRL_NOEXTTRIG_Msk oÚ P DWT_CTRL_NOCYCCNT_Pos ÍÚ P DWT_CTRL_NOCYCCNT_Msk ÔÚ P DWT_CTRL_NOPRFCNT_Pos ÄÚ P DWT_CTRL_NOPRFCNT_Msk ËÚ P DWT_CTRL_CYCEVTENA_Pos Ú P DWT_CTRL_CYCEVTENA_Msk Ú P DWT_CTRL_FOLDEVTENA_Pos BÚ P DWT_CTRL_FOLDEVTENA_Msk IÚ P DWT_CTRL_LSUEVTENA_Pos uÚ P DWT_CTRL_LSUEVTENA_Msk |Ú! P DWT_CTRL_SLEEPEVTENA_Pos ìÚ! P DWT_CTRL_SLEEPEVTENA_Msk óÚ P DWT_CTRL_EXCEVTENA_Pos Ú P DWT_CTRL_EXCEVTENA_Msk Ú P DWT_CTRL_CPIEVTENA_Pos Ú P DWT_CTRL_CPIEVTENA_Msk Ú P DWT_CTRL_EXCTRCENA_Pos Ú P DWT_CTRL_EXCTRCENA_Msk Ú P DWT_CTRL_PCSAMPLENA_Pos FÚ P DWT_CTRL_PCSAMPLENA_Msk MÚ P DWT_CTRL_SYNCTAP_Pos Ú P DWT_CTRL_SYNCTAP_Msk Ú P DWT_CTRL_CYCTAP_Pos nÚ P DWT_CTRL_CYCTAP_Msk uÚ P DWT_CTRL_POSTINIT_Pos ´Ú P DWT_CTRL_POSTINIT_Msk »Ú P DWT_CTRL_POSTPRESET_Pos Ú P DWT_CTRL_POSTPRESET_Msk Ú P DWT_CTRL_CYCCNTENA_Pos Ú P DWT_CTRL_CYCCNTENA_Msk Ú P DWT_CPICNT_CPICNT_Pos áÚ P DWT_CPICNT_CPICNT_Msk èÚ P DWT_EXCCNT_EXCCNT_Pos ÙÚ P DWT_EXCCNT_EXCCNT_Msk àÚ" P DWT_SLEEPCNT_SLEEPCNT_Pos Ú" P DWT_SLEEPCNT_SLEEPCNT_Msk ¦Ú P DWT_LSUCNT_LSUCNT_Pos ±Ú P DWT_LSUCNT_LSUCNT_Msk ¸Ú P DWT_FOLDCNT_FOLDCNT_Pos KÚ P DWT_FOLDCNT_FOLDCNT_Msk RÚ P DWT_MASK_MASK_Pos Ú P DWT_MASK_MASK_Msk Ú! P DWT_FUNCTION_MATCHED_Pos Ú! P DWT_FUNCTION_MATCHED_Msk Ú$ P DWT_FUNCTION_DATAVADDR1_Pos 5Ú$ P DWT_FUNCTION_DATAVADDR1_Msk <Ú$ P DWT_FUNCTION_DATAVADDR0_Pos 6Ú$ P DWT_FUNCTION_DATAVADDR0_Msk =Ú# P DWT_FUNCTION_DATAVSIZE_Pos HÚ# P DWT_FUNCTION_DATAVSIZE_Msk OÚ! P DWT_FUNCTION_LNK1ENA_Pos
Ú! P DWT_FUNCTION_LNK1ENA_Msk Ú$ P DWT_FUNCTION_DATAVMATCH_Pos Ú$ P DWT_FUNCTION_DATAVMATCH_Msk Ú" P DWT_FUNCTION_CYCMATCH_Pos ©Ú" P DWT_FUNCTION_CYCMATCH_Msk °Ú# P DWT_FUNCTION_EMITRANGE_Pos WÚ# P DWT_FUNCTION_EMITRANGE_Msk ^Ú" P DWT_FUNCTION_FUNCTION_Pos Ú" P DWT_FUNCTION_FUNCTION_Msk Ú 8
<unnamed> QÚ
" SSPSR Ú
" CSPSR ¤Ú <"
RESERVED0 aÚ
" ACPR Ú <" Ü
RESERVED1 Ú
" SPPR ìÚ <"
RESERVED2 ÖÚ
" FFSR Ú
" FFCR Ú
" FSCR Ú <" Ü
RESERVED3 rÚ
" TRIGGER Ú
" FIFO0 ÛÚ
"
ITATBCTR2 Ú <"
RESERVED4 aÚ
"
ITATBCTR0 Ú
" FIFO1 ÚÚ
" ITCTRL [Ú <"
RESERVED5 ÆÚ
" CLAIMSET ×Ú
" CLAIMCLR âÚ <"
RESERVED7 BÚ
" DEVID ÃÚ
" DEVTYPE
Ú TPI_Type Ú P TPI_ACPR_PRESCALER_Pos Ú P TPI_ACPR_PRESCALER_Msk £Ú P TPI_SPPR_TXMODE_Pos SÚ P TPI_SPPR_TXMODE_Msk ZÚ P TPI_FFSR_FtNonStop_Pos §Ú P TPI_FFSR_FtNonStop_Msk ®Ú P TPI_FFSR_TCPresent_Pos ºÚ P TPI_FFSR_TCPresent_Msk ÁÚ P TPI_FFSR_FtStopped_Pos Ú P TPI_FFSR_FtStopped_Msk Ú P TPI_FFSR_FlInProg_Pos 3Ú P TPI_FFSR_FlInProg_Msk :Ú P TPI_FFCR_TrigIn_Pos ûÚ P TPI_FFCR_TrigIn_Msk Ú P TPI_FFCR_EnFCont_Pos ¹Ú P TPI_FFCR_EnFCont_Msk ÀÚ P TPI_TRIGGER_TRIGGER_Pos 9Ú P TPI_TRIGGER_TRIGGER_Msk @Ú" P TPI_FIFO0_ITM_ATVALID_Pos »Ú" P TPI_FIFO0_ITM_ATVALID_Msk ÂÚ$ P TPI_FIFO0_ITM_bytecount_Pos ßÚ$ P TPI_FIFO0_ITM_bytecount_Msk æÚ" P TPI_FIFO0_ETM_ATVALID_Pos ¿Ú" P TPI_FIFO0_ETM_ATVALID_Msk ÆÚ$ P TPI_FIFO0_ETM_bytecount_Pos ãÚ$ P TPI_FIFO0_ETM_bytecount_Msk êÚ P TPI_FIFO0_ETM2_Pos ÿÚ P TPI_FIFO0_ETM2_Msk Ú P TPI_FIFO0_ETM1_Pos Ú P TPI_FIFO0_ETM1_Msk Ú P TPI_FIFO0_ETM0_Pos Ú P TPI_FIFO0_ETM0_Msk Ú" P TPI_ITATBCTR2_ATREADY_Pos ÄÚ" P TPI_ITATBCTR2_ATREADY_Msk ËÚ" P TPI_FIFO1_ITM_ATVALID_Pos ºÚ" P TPI_FIFO1_ITM_ATVALID_Msk ÁÚ$ P TPI_FIFO1_ITM_bytecount_Pos ÞÚ$ P TPI_FIFO1_ITM_bytecount_Msk åÚ" P TPI_FIFO1_ETM_ATVALID_Pos ¾Ú" P TPI_FIFO1_ETM_ATVALID_Msk ÅÚ$ P TPI_FIFO1_ETM_bytecount_Pos âÚ$ P TPI_FIFO1_ETM_bytecount_Msk éÚ P TPI_FIFO1_ITM2_Pos úÚ P TPI_FIFO1_ITM2_Msk Ú P TPI_FIFO1_ITM1_Pos ûÚ P TPI_FIFO1_ITM1_Msk Ú P TPI_FIFO1_ITM0_Pos üÚ P TPI_FIFO1_ITM0_Msk Ú" P TPI_ITATBCTR0_ATREADY_Pos ÆÚ" P TPI_ITATBCTR0_ATREADY_Msk ÍÚ P TPI_ITCTRL_Mode_Pos Ú P TPI_ITCTRL_Mode_Msk Ú P TPI_DEVID_NRZVALID_Pos Ú P TPI_DEVID_NRZVALID_Msk Ú P TPI_DEVID_MANCVALID_Pos fÚ P TPI_DEVID_MANCVALID_Msk mÚ P TPI_DEVID_PTINVALID_Pos JÚ P TPI_DEVID_PTINVALID_Msk QÚ P TPI_DEVID_MinBufSz_Pos éÚ P TPI_DEVID_MinBufSz_Msk ðÚ P TPI_DEVID_AsynClkIn_Pos Ú P TPI_DEVID_AsynClkIn_Msk Ú# P TPI_DEVID_NrTraceInput_Pos 0Ú# P TPI_DEVID_NrTraceInput_Msk 7Ú P TPI_DEVTYPE_SubType_Pos tÚ P TPI_DEVTYPE_SubType_Msk {Ú" P TPI_DEVTYPE_MajorType_Pos ¡Ú" P TPI_DEVTYPE_MajorType_Msk ¨Ú 8
<unnamed> QÚ
" ßDHCSR ]Ú
" ßDCRSR SÚ
" ßDCRDR bÚ
" ßDEMCR fÚ CoreDebug_Type tÚ# P CoreDebug_DHCSR_DBGKEY_Pos ®Ú# P CoreDebug_DHCSR_DBGKEY_Msk µÚ' P CoreDebug_DHCSR_S_RESET_ST_Pos !Ú' P CoreDebug_DHCSR_S_RESET_ST_Msk (Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Pos ×Ú( P CoreDebug_DHCSR_S_RETIRE_ST_Msk ÞÚ% P CoreDebug_DHCSR_S_LOCKUP_Pos àÚ% P CoreDebug_DHCSR_S_LOCKUP_Msk çÚ$ P CoreDebug_DHCSR_S_SLEEP_Pos 7Ú$ P CoreDebug_DHCSR_S_SLEEP_Msk >Ú# P CoreDebug_DHCSR_S_HALT_Pos Ú# P CoreDebug_DHCSR_S_HALT_Msk Ú% P CoreDebug_DHCSR_S_REGRDY_Pos áÚ% P CoreDebug_DHCSR_S_REGRDY_Msk èÚ( P CoreDebug_DHCSR_C_SNAPSTALL_Pos Ú( P CoreDebug_DHCSR_C_SNAPSTALL_Msk
Ú' P CoreDebug_DHCSR_C_MASKINTS_Pos PÚ' P CoreDebug_DHCSR_C_MASKINTS_Msk WÚ# P CoreDebug_DHCSR_C_STEP_Pos Ú# P CoreDebug_DHCSR_C_STEP_Msk Ú# P CoreDebug_DHCSR_C_HALT_Pos Ú# P CoreDebug_DHCSR_C_HALT_Msk Ú& P CoreDebug_DHCSR_C_DEBUGEN_Pos ÂÚ& P CoreDebug_DHCSR_C_DEBUGEN_Msk ÉÚ# P CoreDebug_DCRSR_REGWnR_Pos eÚ# P CoreDebug_DCRSR_REGWnR_Msk lÚ# P CoreDebug_DCRSR_REGSEL_Pos Ú# P CoreDebug_DCRSR_REGSEL_Msk Ú# P CoreDebug_DEMCR_TRCENA_Pos °Ú# P CoreDebug_DEMCR_TRCENA_Msk ·Ú$ P CoreDebug_DEMCR_MON_REQ_Pos :Ú$ P CoreDebug_DEMCR_MON_REQ_Msk AÚ% P CoreDebug_DEMCR_MON_STEP_Pos äÚ% P CoreDebug_DEMCR_MON_STEP_Msk ëÚ% P CoreDebug_DEMCR_MON_PEND_Pos ùÚ% P CoreDebug_DEMCR_MON_PEND_Msk Ú# P CoreDebug_DEMCR_MON_EN_Pos Ú# P CoreDebug_DEMCR_MON_EN_Msk Ú' P CoreDebug_DEMCR_VC_HARDERR_Pos eÚ' P CoreDebug_DEMCR_VC_HARDERR_Msk lÚ& P CoreDebug_DEMCR_VC_INTERR_Pos Ú& P CoreDebug_DEMCR_VC_INTERR_Msk ¢Ú& P CoreDebug_DEMCR_VC_BUSERR_Pos Ú& P CoreDebug_DEMCR_VC_BUSERR_Msk £Ú' P CoreDebug_DEMCR_VC_STATERR_Pos HÚ' P CoreDebug_DEMCR_VC_STATERR_Msk OÚ& P CoreDebug_DEMCR_VC_CHKERR_Pos °Ú& P CoreDebug_DEMCR_VC_CHKERR_Msk ·Ú' P CoreDebug_DEMCR_VC_NOCPERR_Pos TÚ' P CoreDebug_DEMCR_VC_NOCPERR_Msk [Ú% P CoreDebug_DEMCR_VC_MMERR_Pos îÚ% P CoreDebug_DEMCR_VC_MMERR_Msk õÚ) P !CoreDebug_DEMCR_VC_CORERESET_Pos ½Ú) P !CoreDebug_DEMCR_VC_CORERESET_Msk ÄÚ P SCS_BASE XÚ P ITM_BASE WÚ P DWT_BASE RÚ P TPI_BASE TÚ P CoreDebug_BASE ÅÚ P
SysTick_BASE oÚ P
NVIC_BASE Ú P SCB_BASE iÚ P SCnSCB ãÚ P SCB íÚ P SysTick óÚ
P NVIC Ú P ITM ÛÚ P DWT ÖÚ P TPI ØÚ P
CoreDebug IÚ! NVIC_SetPriorityGrouping \Ú ,
" «PriorityGroup yÚ
" «
reg_value ZÚ
" «PriorityGroupTmp fÚ! NVIC_GetPriorityGrouping hÚ NVIC_EnableIRQ Ú ,"" °IRQn Ú NVIC_DisableIRQ §Ú ,"" ²IRQn Ú NVIC_GetPendingIRQ pÚ ,"" ´IRQn Ú NVIC_SetPendingIRQ dÚ ,"" ¶IRQn Ú NVIC_ClearPendingIRQ ¥Ú ,"" ¸IRQn ~Ú NVIC_GetActive ÍÚ ,"" ºIRQn |Ú NVIC_SetPriority ·Ú ,"" ¼IRQn zÚ ,
" ¼ priority _Ú NVIC_GetPriority ÃÚ ,"" ¿IRQn wÚ NVIC_EncodePriority Ú ,
" ÁPriorityGroup cÚ ,
" ÁPreemptPriority Ú ,
" Á SubPriority JÚ
" ÁPriorityGroupTmp PÚ
" ÁPreemptPriorityBits Ú
" ÁSubPriorityBits ÔÚ NVIC_DecodePriority Ú ,
" È Priority sÚ ,
" ÈPriorityGroup \Ú ," ÈpPreemptPriority Ú ," È
pSubPriority ÃÚ
" ÈPriorityGroupTmp IÚ
" ÈPreemptPriorityBits Ú
" ÈSubPriorityBits ÍÚ NVIC_SystemReset ½Ú __dsb çÚ SysTick_Config YÚ ,
" Òticks ³Ú
ITM_RxBuffer xÚ P ITM_RXBUFFER_EMPTY Ú
ITM_SendChar Ú
,
" Öch Ú ITM_ReceiveChar LÚ
" Øch ,Ú ITM_CheckChar 5Ú s32 #Ú s16 !Ú s8 RÚ
sc32 ¾Ú
sc16 ¼Ú sc8 íÚ
vs32 «Ú
vs16 ©Ú vs8 ÚÚ vsc32 FÚ vsc16 DÚ
vsc8 uÚ u32 !Ú u16 Ú u8 PÚ
uc32 ¼Ú
uc16 ºÚ uc8 ëÚ
vu32 ©Ú
vu16 §Ú vu8 ØÚ vuc32 DÚ vuc16 BÚ
vuc8 sÚ RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunctionalState ÏÚ P IS_FUNCTIONAL_STATE ×Ú ERROR iÚ SUCCESS ÖÚ ErrorStatus ]Ú P HSEStartUp_TimeOut ÎÚ P
HSE_Value }Ú P
HSI_Value yÚ 8
<unnamed> QÚ
" SR Ú
" CR1 kÚ
" CR2 jÚ
" SMPR1 ºÚ
" SMPR2 ¹Ú
" JOFR1 ËÚ
" JOFR2 ÊÚ
" JOFR3 ÉÚ
" JOFR4 ÈÚ
" HTR CÚ
" LTR ?Ú
" SQR1 Ú
" SQR2 Ú
" SQR3 Ú
" JSQR ïÚ
" JDR1 Ú
" JDR2 Ú
" JDR3 Ú
" JDR4 Ú
" DR Ú ADC_TypeDef Ú 8
<unnamed> QÚ
"
RESERVED0 Ú " DR1 RÚ "
RESERVED1 |Ú " DR2 QÚ "
RESERVED2 {Ú " DR3 PÚ "
RESERVED3 zÚ " DR4 OÚ "
RESERVED4 yÚ " DR5 NÚ "
RESERVED5 xÚ " DR6 MÚ "
RESERVED6 wÚ " DR7 LÚ "
RESERVED7 vÚ " DR8 KÚ "
RESERVED8 uÚ " DR9 JÚ "
RESERVED9 tÚ " DR10 Ú " RESERVED10 JÚ " RTCCR Ú " RESERVED11 IÚ
" CR Ú " RESERVED12 HÚ " CSR 1Ú <"
RESERVED13 Ú " DR11 Ú " RESERVED14 FÚ " DR12 Ú " RESERVED15 EÚ " DR13 Ú " RESERVED16 DÚ " DR14 Ú " RESERVED17 CÚ " DR15 Ú " RESERVED18 BÚ " DR16 Ú " RESERVED19 AÚ " DR17 Ú " RESERVED20 IÚ " DR18 Ú " RESERVED21 HÚ " DR19 Ú " RESERVED22 GÚ " DR20 Ú " RESERVED23 FÚ " DR21 Ú " RESERVED24 EÚ " DR22 Ú " RESERVED25 DÚ " DR23 Ú " RESERVED26 CÚ " DR24 Ú " RESERVED27 BÚ " DR25 Ú " RESERVED28 AÚ " DR26 Ú " RESERVED29 @Ú " DR27 Ú " RESERVED30 HÚ " DR28 Ú " RESERVED31 GÚ " DR29 Ú " RESERVED32 FÚ " DR30 Ú " RESERVED33 EÚ " DR31 Ú " RESERVED34 DÚ " DR32 Ú " RESERVED35 CÚ " DR33 Ú " RESERVED36 BÚ " DR34 Ú " RESERVED37 AÚ " DR35 Ú " RESERVED38 @Ú " DR36 Ú " RESERVED39 ?Ú " DR37 Ú " RESERVED40 GÚ " DR38 Ú " RESERVED41 FÚ " DR39 Ú " RESERVED42 EÚ " DR40 Ú " RESERVED43 DÚ " DR41 Ú " RESERVED44 CÚ " DR42 Ú " RESERVED45 BÚ BKP_TypeDef þÚ 8
<unnamed> QÚ
" ôTIR ÏÚ
" ôTDTR ~Ú
" ôTDLR Ú
" ôTDHR Ú CAN_TxMailBox_TypeDef Ú 8
<unnamed> QÚ
" úRIR ËÚ
" úRDTR zÚ
" úRDLR Ú
" úRDHR Ú CAN_FIFOMailBox_TypeDef ÂÚ 8
<unnamed> QÚ
" FR1 hÚ
" FR2 gÚ# CAN_FilterRegister_TypeDef áÚ 8
<unnamed> QÚ
" MCR KÚ
" MSR ;Ú
" TSR 4Ú
" RF0R Ú
" RF1R Ú
" IER MÚ
" ESR CÚ
" BTR EÚ <" à
RESERVED0 Ú <" 0 sTxMailBox ÖÚ <"
sFIFOMailBox Ú <" 0
RESERVED1 2Ú
" FMR HÚ
" FM1R Ú
"
RESERVED2 Ú
" FS1R Ú
"
RESERVED3 Ú
" FFA1R ÙÚ
"
RESERVED4 Ú
" FA1R !Ú <"
RESERVED5 >Ú <" psFilterRegister YÚ CAN_TypeDef Ú 8
<unnamed> QÚ
" CFGR ñÚ
" OAR 3Ú
" PRES ÙÚ
" ESR +Ú
" CSR -Ú
" TXD %Ú
" RXD 'Ú CEC_TypeDef Ú 8
<unnamed> QÚ
" ¥DR xÚ " ¥IDR 4Ú " ¥
RESERVED0 wÚ " ¥
RESERVED1 mÚ
" ¥CR yÚ CRC_TypeDef Ú 8
<unnamed> QÚ
" ¬CR rÚ
" ¬SWTRIGR ËÚ
" ¬DHR12R1 9Ú
" ¬DHR12L1 ?Ú
" ¬DHR8R1 fÚ
" ¬DHR12R2 8Ú
" ¬DHR12L2 >Ú
" ¬DHR8R2 eÚ
" ¬DHR12RD &Ú
" ¬DHR12LD ,Ú
" ¬DHR8RD SÚ
" ¬DOR1 íÚ
" ¬DOR2 ìÚ DAC_TypeDef Ú 8
<unnamed> QÚ
" »IDCODE HÚ
" »CR cÚ DBGMCU_TypeDef #Ú 8
<unnamed> QÚ
" ¿CCR Ú
" ¿CNDTR sÚ
" ¿CPAR ÊÚ
" ¿CMAR ÍÚ DMA_Channel_TypeDef áÚ 8
<unnamed> QÚ
" ÅISR þÚ
" ÅIFCR ÆÚ DMA_TypeDef Ú 8
<unnamed> QÚ
" ÉMACCR ~Ú
" ÉMACFFR 3Ú
" ÉMACHTHR ÙÚ
" ÉMACHTLR ÕÚ
" É MACMIIAR Ú
" É MACMIIDR Ú
" ÉMACFCR 6Ú
" É
MACVLANTR 4Ú <" É
RESERVED0 Ú
" É
MACRWUFFR /Ú
" É
MACPMTCSR 2Ú <" É
RESERVED1 Ú
" ÉMACSR nÚ
" ÉMACIMR )Ú
" ÉMACA0HR Ú
" ÉMACA0LR Ú
" ÉMACA1HR Ú
" ÉMACA1LR ÿÚ
" ÉMACA2HR Ú
" ÉMACA2LR þÚ
" ÉMACA3HR Ú
" ÉMACA3LR ýÚ <" É
RESERVED2 zÚ
" ÉMMCCR rÚ
" ÉMMCRIR Ú
" ÉMMCTIR Ú
" ÉMMCRIMR ÉÚ
" ÉMMCTIMR ÇÚ <" 8É
RESERVED3 ãÚ
" É MMCTGFSCCR ñÚ
" É MMCTGFMSCCR ¢Ú <" É
RESERVED4 Ú
" É MMCTGFCR Ú <" (É
RESERVED5 ñÚ
" É
MMCRFCECR JÚ
" É
MMCRFAECR LÚ <" (É
RESERVED6 ðÚ
" É
MMCRGUFCR 6Ú <" ¸
É
RESERVED7 TÚ
" ÉPTPTSCR °Ú
" ÉPTPSSIR «Ú
" ÉPTPTSHR «Ú
" ÉPTPTSLR §Ú
" É PTPTSHUR TÚ
" É PTPTSLUR PÚ
" ÉPTPTSAR ²Ú
" ÉPTPTTHR ªÚ
" ÉPTPTTLR ¦Ú <" ÜÉ
RESERVED8 (Ú
" ÉDMABMR /Ú
" ÉDMATPDR ÔÚ
" ÉDMARPDR ÖÚ
" É DMARDLAR Ú
" É DMATDLAR Ú
" ÉDMASR mÚ
" ÉDMAOMR "Ú
" ÉDMAIER 0Ú
" É
DMAMFBOCR QÚ <" $É
RESERVED9 ñÚ
" É DMACHTDR Ú
" É DMACHRDR Ú
" É
DMACHTBAR VÚ
" É
DMACHRBAR XÚ ETH_TypeDef úÚ 8
<unnamed> QÚ
" IMR >Ú
" EMR BÚ
" RTSR ÙÚ
" FTSR åÚ
" SWIER Ú
" PR Ú
EXTI_TypeDef Ú 8
<unnamed> QÚ
" ACR HÚ
" KEYR áÚ
" OPTKEYR èÚ
" SR {Ú
" CR Ú
" AR Ú
" RESERVED ´Ú
" OBR ;Ú
" WRPR ÑÚ FLASH_TypeDef iÚ 8
<unnamed> QÚ " RDP +Ú " USER ÐÚ " Data0 cÚ " Data1 bÚ " WRP0 æÚ " WRP1 åÚ " WRP2 äÚ " WRP3 ãÚ OB_TypeDef LÚ 8
<unnamed> QÚ <" §BTCR Ú FSMC_Bank1_TypeDef Ú 8
<unnamed> QÚ <" ªBWTR {Ú FSMC_Bank1E_TypeDef QÚ 8
<unnamed> QÚ
" PCR2 êÚ
" SR2 ,Ú
" PMEM2 Ú
" PATT2 Ú
"
RESERVED0 gÚ
" ECCR2 °Ú FSMC_Bank2_TypeDef Ú 8
<unnamed> QÚ
" µPCR3 áÚ
" µSR3 #Ú
" µPMEM3 Ú
" µPATT3 Ú
" µ
RESERVED0 _Ú
" µECCR3 §Ú FSMC_Bank3_TypeDef Ú 8
<unnamed> QÚ
" ½PCR4 ØÚ
" ½SR4 Ú
" ½PMEM4 Ú
" ½PATT4 Ú
" ½PIO4 ÕÚ FSMC_Bank4_TypeDef Ú 8
<unnamed> QÚ
" ÄCRL Ú
" ÄCRH Ú
" ÄIDR
Ú
" ÄODR Ú
" ÄBSRR ±Ú
" ÄBRR Ú
" ÄLCKR ¾Ú
GPIO_TypeDef ªÚ 8
<unnamed> QÚ
" ÍEVCR ±Ú
" ÍMAPR ±Ú <" ÍEXTICR ÐÚ
" Í
RESERVED0 GÚ
" ÍMAPR2 }Ú
AFIO_TypeDef ºÚ 8
<unnamed> QÚ " ÔCR1 Ú " Ô
RESERVED0 >Ú " ÔCR2 Ú " Ô
RESERVED1 =Ú " ÔOAR1 ÅÚ " Ô
RESERVED2 <Ú " ÔOAR2 ÄÚ " Ô
RESERVED3 ;Ú
" ÔDR FÚ " Ô
RESERVED4 :Ú " ÔSR1 Ú " Ô
RESERVED5 9Ú " ÔSR2 Ú " Ô
RESERVED6 8Ú " ÔCCR Ú " Ô
RESERVED7 7Ú " ÔTRISE OÚ " Ô
RESERVED8 6Ú I2C_TypeDef Ú 8
<unnamed> QÚ
" èKR -Ú
" èPR (Ú
" èRLR ØÚ
" èSR %Ú
IWDG_TypeDef ®Ú 8
<unnamed> QÚ
" îCR /Ú
" îCSR ÚÚ PWR_TypeDef âÚ 8
<unnamed> QÚ
" òCR +Ú
" òCFGR Ú
" òCIR àÚ
" ò APB2RSTR dÚ
" ò APB1RSTR eÚ
" òAHBENR Ú
" òAPB2ENR ÌÚ
" òAPB1ENR ÍÚ
" òBDCR ¡Ú
" òCSR ÖÚ RCC_TypeDef Ú 8
<unnamed> QÚ " þCRH ÓÚ " þ
RESERVED0 Ú " þCRL ÏÚ " þ
RESERVED1 Ú " þPRLH xÚ " þ
RESERVED2 Ú " þPRLL tÚ " þ
RESERVED3 Ú " þDIVH Ú " þ
RESERVED4 Ú " þDIVL Ú " þ
RESERVED5 Ú " þCNTH Ú " þ
RESERVED6 Ú " þCNTL }Ú " þ
RESERVED7
Ú " þALRH Ú " þ
RESERVED8 Ú " þALRL Ú " þ
RESERVED9 Ú RTC_TypeDef òÚ 8
<unnamed> QÚ
" POWER Ú
" CLKCR ¨Ú
" ARG AÚ
" CMD GÚ
" RESPCMD Ú
" RESP1 ¬Ú
" RESP2 «Ú
" RESP3 ªÚ
" RESP4 ©Ú
" DTIMER PÚ
" DLEN öÚ
" DCTRL Ú
" DCOUNT HÚ
" STA 3Ú
" ICR =Ú
" MASK íÚ <"
RESERVED0 IÚ
" FIFOCNT
Ú <" 4
RESERVED1 Ú
" FIFO õÚ
SDIO_TypeDef ªÚ 8
<unnamed> QÚ " ªCR1 =Ú " ª
RESERVED0 gÚ " ªCR2 <Ú " ª
RESERVED1 fÚ
" ªSR `Ú " ª
RESERVED2 eÚ
" ªDR oÚ " ª
RESERVED3 dÚ " ªCRCPR
Ú " ª
RESERVED4 cÚ " ªRXCRCR )Ú " ª
RESERVED5 bÚ " ªTXCRCR 'Ú " ª
RESERVED6 aÚ " ªI2SCFGR Ú " ª
RESERVED7 `Ú " ªI2SPR Ú " ª
RESERVED8 _Ú SPI_TypeDef ïÚ 8
<unnamed> QÚ " ¾CR1 )Ú " ¾
RESERVED0 SÚ " ¾CR2 (Ú " ¾
RESERVED1 RÚ " ¾SMCR ¸Ú " ¾
RESERVED2 QÚ " ¾DIER ÉÚ " ¾
RESERVED3 PÚ
" ¾SR LÚ " ¾
RESERVED4 OÚ " ¾EGR Ú " ¾
RESERVED5 NÚ " ¾CCMR1 Ú " ¾
RESERVED6 MÚ " ¾CCMR2 Ú " ¾
RESERVED7 LÚ " ¾CCER ÐÚ " ¾
RESERVED8 KÚ " ¾CNT
Ú " ¾
RESERVED9 JÚ " ¾PSC Ú " ¾ RESERVED10 Ú " ¾ARR
Ú " ¾ RESERVED11 Ú " ¾RCR Ú " ¾ RESERVED12 Ú " ¾CCR1 äÚ " ¾ RESERVED13 Ú " ¾CCR2 ãÚ " ¾ RESERVED14 Ú " ¾CCR3 âÚ " ¾ RESERVED15 Ú " ¾CCR4 áÚ " ¾ RESERVED16 Ú " ¾BDTR ÁÚ " ¾ RESERVED17 Ú " ¾DCR Ú " ¾ RESERVED18 Ú " ¾DMAR ÉÚ " ¾ RESERVED19 Ú TIM_TypeDef ñÚ 8
<unnamed> QÚ
" èSR "Ú " è
RESERVED0 )Ú
" èDR 1Ú " è
RESERVED1 (Ú " èBRR ßÚ " è
RESERVED2 'Ú " èCR1 ÿÚ " è
RESERVED3 &Ú " èCR2 þÚ " è
RESERVED4 %Ú " èCR3 ýÚ " è
RESERVED5 $Ú " èGTPR Ú " è
RESERVED6 #Ú USART_TypeDef HÚ 8
<unnamed> QÚ
" øCR $Ú
" øCFR ÜÚ
" øSR Ú
WWDG_TypeDef Ú P FLASH_BASE ÏÚ P
SRAM_BASE Ú P PERIPH_BASE sÚ P
SRAM_BB_BASE #Ú P PERIPH_BB_BASE Ú P FSMC_R_BASE aÚ P APB1PERIPH_BASE gÚ P APB2PERIPH_BASE fÚ P AHBPERIPH_BASE ¢Ú P
TIM2_BASE #Ú P
TIM3_BASE "Ú P
TIM4_BASE !Ú P
TIM5_BASE Ú P
TIM6_BASE Ú P
TIM7_BASE Ú P TIM12_BASE ðÚ P TIM13_BASE ïÚ P TIM14_BASE îÚ P RTC_BASE XÚ P
WWDG_BASE Ú P
IWDG_BASE Ú P
SPI2_BASE !Ú P
SPI3_BASE Ú P USART2_BASE zÚ P USART3_BASE yÚ P UART4_BASE ÍÚ P UART5_BASE ÌÚ P
I2C1_BASE PÚ P
I2C2_BASE OÚ P
CAN1_BASE <Ú P
CAN2_BASE ;Ú P BKP_BASE dÚ P PWR_BASE HÚ P DAC_BASE yÚ P CEC_BASE vÚ P
AFIO_BASE Ú P
EXTI_BASE Ú P GPIOA_BASE ÍÚ P GPIOB_BASE ÌÚ P GPIOC_BASE ËÚ P GPIOD_BASE ÊÚ P GPIOE_BASE ÉÚ P GPIOF_BASE ÈÚ P GPIOG_BASE ÇÚ P
ADC1_BASE FÚ P
ADC2_BASE EÚ P
TIM1_BASE $Ú P
SPI1_BASE "Ú P
TIM8_BASE Ú P USART1_BASE {Ú P
ADC3_BASE DÚ P TIM15_BASE íÚ P TIM16_BASE ìÚ P TIM17_BASE ëÚ P
TIM9_BASE Ú P TIM10_BASE òÚ P TIM11_BASE ñÚ P
SDIO_BASE Ú P
DMA1_BASE <Ú P DMA1_Channel1_BASE áÚ P DMA1_Channel2_BASE àÚ P DMA1_Channel3_BASE ßÚ P DMA1_Channel4_BASE ÞÚ P DMA1_Channel5_BASE ÝÚ P DMA1_Channel6_BASE ÜÚ P DMA1_Channel7_BASE ÛÚ P
DMA2_BASE ;Ú P DMA2_Channel1_BASE àÚ P DMA2_Channel2_BASE ßÚ P DMA2_Channel3_BASE ÞÚ P DMA2_Channel4_BASE ÝÚ P DMA2_Channel5_BASE ÜÚ P RCC_BASE iÚ P CRC_BASE iÚ P
FLASH_R_BASE Ú P OB_BASE ²Ú P ETH_BASE `Ú P
ETH_MAC_BASE (Ú P
ETH_MMC_BASE Ú P
ETH_PTP_BASE Ú P
ETH_DMA_BASE 'Ú P FSMC_Bank1_R_BASE IÚ P FSMC_Bank1E_R_BASE Ú P FSMC_Bank2_R_BASE HÚ P FSMC_Bank3_R_BASE GÚ P FSMC_Bank4_R_BASE FÚ P DBGMCU_BASE Ú
P TIM2 §Ú
P TIM3 ¦Ú
P TIM4 ¥Ú
P TIM5 ¤Ú
P TIM6 £Ú
P TIM7 ¢Ú P TIM12 tÚ P TIM13 sÚ P TIM14 rÚ P RTC ÜÚ
P WWDG Ú
P IWDG Ú
P SPI2 ¥Ú
P SPI3 ¤Ú P USART2 þÚ P USART3 ýÚ P UART4 QÚ P UART5 PÚ
P I2C1 ÔÚ
P I2C2 ÓÚ
P CAN1 ÀÚ
P CAN2 ¿Ú P BKP èÚ P PWR ÌÚ P DAC ýÚ P CEC úÚ
P AFIO ¤Ú
P EXTI Ú P GPIOA QÚ P GPIOB PÚ P GPIOC OÚ P GPIOD NÚ P GPIOE MÚ P GPIOF LÚ P GPIOG KÚ
P ADC1 ÊÚ
P ADC2 ÉÚ
P TIM1 ¨Ú
P SPI1 ¦Ú
P TIM8 ¡Ú P USART1 ÿÚ
P ADC3 ÈÚ P TIM15 qÚ P TIM16 pÚ P TIM17 oÚ
P TIM9 Ú P TIM10 vÚ P TIM11 uÚ
P SDIO Ú
P DMA1 ÀÚ
P DMA2 ¿Ú P DMA1_Channel1 eÚ P DMA1_Channel2 dÚ P DMA1_Channel3 cÚ P DMA1_Channel4 bÚ P DMA1_Channel5 aÚ P DMA1_Channel6 `Ú P DMA1_Channel7 _Ú P DMA2_Channel1 dÚ P DMA2_Channel2 cÚ P DMA2_Channel3 bÚ P DMA2_Channel4 aÚ P DMA2_Channel5 `Ú P RCC íÚ P CRC íÚ P FLASH SÚ P OB 6Ú P ETH äÚ P FSMC_Bank1 Ú P FSMC_Bank1E ;Ú P FSMC_Bank2 Ú P FSMC_Bank3 Ú P FSMC_Bank4 Ú P DBGMCU
Ú P
CRC_DR_DR ÷Ú P CRC_IDR_IDR aÚ P
CRC_CR_RESET Ú P PWR_CR_LPDS 6Ú P PWR_CR_PDDS >Ú P PWR_CR_CWUF 4Ú P PWR_CR_CSBF KÚ P PWR_CR_PVDE :Ú P PWR_CR_PLS |Ú P
PWR_CR_PLS_0 éÚ P
PWR_CR_PLS_1 èÚ P
PWR_CR_PLS_2 çÚ P PWR_CR_PLS_2V2 [Ú P PWR_CR_PLS_2V3 ZÚ P PWR_CR_PLS_2V4 YÚ P PWR_CR_PLS_2V5 XÚ P PWR_CR_PLS_2V6 WÚ P PWR_CR_PLS_2V7 VÚ P PWR_CR_PLS_2V8 UÚ P PWR_CR_PLS_2V9 TÚ P PWR_CR_DBP Ú P PWR_CSR_WUF $Ú P PWR_CSR_SBF ;Ú P
PWR_CSR_PVDO ÛÚ P
PWR_CSR_EWUP ÓÚ P
BKP_DR1_D Ú P
BKP_DR2_D Ú P
BKP_DR3_D Ú P
BKP_DR4_D Ú P
BKP_DR5_D Ú P
BKP_DR6_D Ú P
BKP_DR7_D
Ú P
BKP_DR8_D Ú P
BKP_DR9_D Ú P BKP_DR10_D áÚ P BKP_DR11_D àÚ P BKP_DR12_D ßÚ P BKP_DR13_D ÞÚ P BKP_DR14_D ÝÚ P BKP_DR15_D ÜÚ P BKP_DR16_D ÛÚ P BKP_DR17_D ÚÚ P BKP_DR18_D ÙÚ P BKP_DR19_D ØÚ P BKP_DR20_D àÚ P BKP_DR21_D ßÚ P BKP_DR22_D ÞÚ P BKP_DR23_D ÝÚ P BKP_DR24_D ÜÚ P BKP_DR25_D ÛÚ P BKP_DR26_D ÚÚ P BKP_DR27_D ÙÚ P BKP_DR28_D ØÚ P BKP_DR29_D ×Ú P BKP_DR30_D ßÚ P BKP_DR31_D ÞÚ P BKP_DR32_D ÝÚ P BKP_DR33_D ÜÚ P BKP_DR34_D ÛÚ P BKP_DR35_D ÚÚ P BKP_DR36_D ÙÚ P BKP_DR37_D ØÚ P BKP_DR38_D ×Ú P BKP_DR39_D ÖÚ P BKP_DR40_D ÞÚ P BKP_DR41_D ÝÚ P BKP_DR42_D ÜÚ P BKP_RTCCR_CAL ÈÚ P BKP_RTCCR_CCO ÃÚ P BKP_RTCCR_ASOE nÚ P BKP_RTCCR_ASOS `Ú P BKP_CR_TPE Ú P BKP_CR_TPAL TÚ P BKP_CSR_CTE VÚ P BKP_CSR_CTI RÚ P
BKP_CSR_TPIE þÚ P BKP_CSR_TEF SÚ P BKP_CSR_TIF OÚ P
RCC_CR_HSION Ú P RCC_CR_HSIRDY ³Ú P RCC_CR_HSITRIM dÚ P RCC_CR_HSICAL ÒÚ P
RCC_CR_HSEON Ú P RCC_CR_HSERDY ·Ú P RCC_CR_HSEBYP »Ú P
RCC_CR_CSSON Ú P
RCC_CR_PLLON Ú P RCC_CR_PLLRDY ¯Ú P RCC_CFGR_SW SÚ P RCC_CFGR_SW_0 ÀÚ P RCC_CFGR_SW_1 ¿Ú P RCC_CFGR_SW_HSI Ú P RCC_CFGR_SW_HSE Ú P RCC_CFGR_SW_PLL Ú P
RCC_CFGR_SWS þÚ P RCC_CFGR_SWS_0 kÚ P RCC_CFGR_SWS_1 jÚ P RCC_CFGR_SWS_HSI ³Ú P RCC_CFGR_SWS_HSE ·Ú P RCC_CFGR_SWS_PLL ¯Ú P RCC_CFGR_HPRE ÊÚ P RCC_CFGR_HPRE_0 7Ú P RCC_CFGR_HPRE_1 6Ú P RCC_CFGR_HPRE_2 5Ú P RCC_CFGR_HPRE_3 4Ú P RCC_CFGR_HPRE_DIV1 MÚ P RCC_CFGR_HPRE_DIV2 LÚ P RCC_CFGR_HPRE_DIV4 JÚ P RCC_CFGR_HPRE_DIV8 FÚ P RCC_CFGR_HPRE_DIV16 Ú P RCC_CFGR_HPRE_DIV64 Ú P RCC_CFGR_HPRE_DIV128 ßÚ P RCC_CFGR_HPRE_DIV256 ÝÚ P RCC_CFGR_HPRE_DIV512 âÚ P RCC_CFGR_PPRE1 Ú P RCC_CFGR_PPRE1_0 üÚ P RCC_CFGR_PPRE1_1 ûÚ P RCC_CFGR_PPRE1_2 úÚ P RCC_CFGR_PPRE1_DIV1 Ú P RCC_CFGR_PPRE1_DIV2 Ú P RCC_CFGR_PPRE1_DIV4 Ú P RCC_CFGR_PPRE1_DIV8 Ú P RCC_CFGR_PPRE1_DIV16 ÚÚ P RCC_CFGR_PPRE2 Ú P RCC_CFGR_PPRE2_0 ûÚ P RCC_CFGR_PPRE2_1 úÚ P RCC_CFGR_PPRE2_2 ùÚ P RCC_CFGR_PPRE2_DIV1 Ú P RCC_CFGR_PPRE2_DIV2 Ú P RCC_CFGR_PPRE2_DIV4 Ú P RCC_CFGR_PPRE2_DIV8
Ú P RCC_CFGR_PPRE2_DIV16 ÙÚ P RCC_CFGR_ADCPRE FÚ P RCC_CFGR_ADCPRE_0 ³Ú P RCC_CFGR_ADCPRE_1 ²Ú P RCC_CFGR_ADCPRE_DIV2 ÈÚ P RCC_CFGR_ADCPRE_DIV4 ÆÚ P RCC_CFGR_ADCPRE_DIV6 ÄÚ P RCC_CFGR_ADCPRE_DIV8 ÂÚ P RCC_CFGR_PLLSRC %Ú P RCC_CFGR_PLLXTPRE vÚ P RCC_CFGR_PLLMULL ÑÚ P RCC_CFGR_PLLMULL_0 >Ú P RCC_CFGR_PLLMULL_1 =Ú P RCC_CFGR_PLLMULL_2 <Ú P RCC_CFGR_PLLMULL_3 ;Ú! P RCC_CFGR_PLLSRC_HSI_Div2 Ú P RCC_CFGR_PLLSRC_HSE ÞÚ P RCC_CFGR_PLLXTPRE_HSE /Ú# P RCC_CFGR_PLLXTPRE_HSE_Div2 qÚ P RCC_CFGR_PLLMULL2 Ú P RCC_CFGR_PLLMULL3 Ú P RCC_CFGR_PLLMULL4 Ú P RCC_CFGR_PLLMULL5 Ú P RCC_CFGR_PLLMULL6 Ú P RCC_CFGR_PLLMULL7 Ú P RCC_CFGR_PLLMULL8 Ú P RCC_CFGR_PLLMULL9 Ú P RCC_CFGR_PLLMULL10 lÚ P RCC_CFGR_PLLMULL11 kÚ P RCC_CFGR_PLLMULL12 jÚ P RCC_CFGR_PLLMULL13 iÚ P RCC_CFGR_PLLMULL14 hÚ P RCC_CFGR_PLLMULL15 gÚ P RCC_CFGR_PLLMULL16 fÚ P RCC_CFGR_USBPRE $Ú P
RCC_CFGR_MCO Ú P RCC_CFGR_MCO_0 Ú P RCC_CFGR_MCO_1 Ú P RCC_CFGR_MCO_2 Ú P RCC_CFGR_MCO_NOCLOCK ¤Ú P RCC_CFGR_MCO_SYSCLK ÖÚ P RCC_CFGR_MCO_HSI ÑÚ P RCC_CFGR_MCO_HSE ÕÚ P RCC_CFGR_MCO_PLL ÍÚ P RCC_CIR_LSIRDYF Ú P RCC_CIR_LSERDYF Ú P RCC_CIR_HSIRDYF Ú P RCC_CIR_HSERDYF $Ú P RCC_CIR_PLLRDYF Ú P
RCC_CIR_CSSF Ú P RCC_CIR_LSIRDYIE ÒÚ P RCC_CIR_LSERDYIE ÖÚ P RCC_CIR_HSIRDYIE ÖÚ P RCC_CIR_HSERDYIE ÚÚ P RCC_CIR_PLLRDYIE ÒÚ P RCC_CIR_LSIRDYC Ú P RCC_CIR_LSERDYC #Ú P RCC_CIR_HSIRDYC #Ú P RCC_CIR_HSERDYC 'Ú P RCC_CIR_PLLRDYC Ú P
RCC_CIR_CSSC Ú P RCC_APB2RSTR_AFIORST ¥Ú P RCC_APB2RSTR_IOPARST Ú P RCC_APB2RSTR_IOPBRST Ú P RCC_APB2RSTR_IOPCRST Ú P RCC_APB2RSTR_IOPDRST Ú P RCC_APB2RSTR_ADC1RST ËÚ P RCC_APB2RSTR_ADC2RST ÊÚ P RCC_APB2RSTR_TIM1RST ©Ú P RCC_APB2RSTR_SPI1RST §Ú P RCC_APB2RSTR_USART1RST Ú P RCC_APB2RSTR_IOPERST Ú P RCC_APB2RSTR_IOPFRST Ú P RCC_APB2RSTR_IOPGRST Ú P RCC_APB2RSTR_TIM8RST ¢Ú P RCC_APB2RSTR_ADC3RST ÉÚ P RCC_APB1RSTR_TIM2RST ©Ú P RCC_APB1RSTR_TIM3RST ¨Ú P RCC_APB1RSTR_WWDGRST Ú P RCC_APB1RSTR_USART2RST Ú P RCC_APB1RSTR_I2C1RST ÖÚ P RCC_APB1RSTR_CAN1RST ÂÚ P RCC_APB1RSTR_BKPRST êÚ P RCC_APB1RSTR_PWRRST ÎÚ P RCC_APB1RSTR_TIM4RST §Ú P RCC_APB1RSTR_SPI2RST §Ú P RCC_APB1RSTR_USART3RST ÿÚ P RCC_APB1RSTR_I2C2RST ÕÚ P RCC_APB1RSTR_USBRST ÝÚ P RCC_APB1RSTR_TIM5RST ¦Ú P RCC_APB1RSTR_TIM6RST ¥Ú P RCC_APB1RSTR_TIM7RST ¤Ú P RCC_APB1RSTR_SPI3RST ¦Ú P RCC_APB1RSTR_UART4RST SÚ P RCC_APB1RSTR_UART5RST RÚ P RCC_APB1RSTR_DACRST ÿÚ P RCC_AHBENR_DMA1EN ÍÚ P RCC_AHBENR_SRAMEN Ú P RCC_AHBENR_FLITFEN YÚ P RCC_AHBENR_CRCEN úÚ P RCC_AHBENR_DMA2EN ÌÚ P RCC_AHBENR_FSMCEN §Ú P RCC_AHBENR_SDIOEN ¡Ú P RCC_APB2ENR_AFIOEN uÚ P RCC_APB2ENR_IOPAEN kÚ P RCC_APB2ENR_IOPBEN jÚ P RCC_APB2ENR_IOPCEN iÚ P RCC_APB2ENR_IOPDEN hÚ P RCC_APB2ENR_ADC1EN Ú P RCC_APB2ENR_ADC2EN Ú P RCC_APB2ENR_TIM1EN yÚ P RCC_APB2ENR_SPI1EN wÚ P RCC_APB2ENR_USART1EN ÐÚ P RCC_APB2ENR_IOPEEN gÚ P RCC_APB2ENR_IOPFEN fÚ P RCC_APB2ENR_IOPGEN eÚ P RCC_APB2ENR_TIM8EN rÚ P RCC_APB2ENR_ADC3EN Ú P RCC_APB1ENR_TIM2EN yÚ P RCC_APB1ENR_TIM3EN xÚ P RCC_APB1ENR_WWDGEN \Ú P RCC_APB1ENR_USART2EN ÐÚ P RCC_APB1ENR_I2C1EN ¦Ú P RCC_APB1ENR_CAN1EN Ú P RCC_APB1ENR_BKPEN ºÚ P RCC_APB1ENR_PWREN Ú P RCC_APB1ENR_TIM4EN wÚ P RCC_APB1ENR_SPI2EN wÚ P RCC_APB1ENR_USART3EN ÏÚ P RCC_APB1ENR_I2C2EN ¥Ú P RCC_APB1ENR_USBEN Ú P RCC_APB1ENR_TIM5EN vÚ P RCC_APB1ENR_TIM6EN uÚ P RCC_APB1ENR_TIM7EN tÚ P RCC_APB1ENR_SPI3EN vÚ P RCC_APB1ENR_UART4EN #Ú P RCC_APB1ENR_UART5EN "Ú P RCC_APB1ENR_DACEN ÏÚ P RCC_BDCR_LSEON }Ú P RCC_BDCR_LSERDY )Ú P RCC_BDCR_LSEBYP -Ú P RCC_BDCR_RTCSEL /Ú P RCC_BDCR_RTCSEL_0 Ú P RCC_BDCR_RTCSEL_1 Ú P RCC_BDCR_RTCSEL_NOCLOCK ·Ú P RCC_BDCR_RTCSEL_LSE äÚ P RCC_BDCR_RTCSEL_LSI àÚ P RCC_BDCR_RTCSEL_HSE èÚ P RCC_BDCR_RTCEN Ú P RCC_BDCR_BDRST Ú P RCC_CSR_LSION ®Ú P RCC_CSR_LSIRDY ZÚ P
RCC_CSR_RMVF úÚ P RCC_CSR_PINRSTF Ú P RCC_CSR_PORRSTF ÿÚ P RCC_CSR_SFTRSTF Ú P RCC_CSR_IWDGRSTF ÃÚ P RCC_CSR_WWDGRSTF µÚ P RCC_CSR_LPWRRSTF ©Ú P GPIO_CRL_MODE ¾Ú P GPIO_CRL_MODE0 Ú P GPIO_CRL_MODE0_0 ùÚ P GPIO_CRL_MODE0_1 øÚ P GPIO_CRL_MODE1 Ú P GPIO_CRL_MODE1_0 øÚ P GPIO_CRL_MODE1_1 ÷Ú P GPIO_CRL_MODE2 Ú P GPIO_CRL_MODE2_0 ÷Ú P GPIO_CRL_MODE2_1 öÚ P GPIO_CRL_MODE3 Ú P GPIO_CRL_MODE3_0 öÚ P GPIO_CRL_MODE3_1 õÚ P GPIO_CRL_MODE4 Ú P GPIO_CRL_MODE4_0 õÚ P GPIO_CRL_MODE4_1 ôÚ P GPIO_CRL_MODE5 Ú P GPIO_CRL_MODE5_0 ôÚ P GPIO_CRL_MODE5_1 óÚ P GPIO_CRL_MODE6 Ú P GPIO_CRL_MODE6_0 óÚ P GPIO_CRL_MODE6_1 òÚ P GPIO_CRL_MODE7
Ú P GPIO_CRL_MODE7_0 òÚ P GPIO_CRL_MODE7_1 ñÚ P
GPIO_CRL_CNF Ú P GPIO_CRL_CNF0 ÜÚ P GPIO_CRL_CNF0_0 IÚ P GPIO_CRL_CNF0_1 HÚ P GPIO_CRL_CNF1 ÛÚ P GPIO_CRL_CNF1_0 HÚ P GPIO_CRL_CNF1_1 GÚ P GPIO_CRL_CNF2 ÚÚ P GPIO_CRL_CNF2_0 GÚ P GPIO_CRL_CNF2_1 FÚ P GPIO_CRL_CNF3 ÙÚ P GPIO_CRL_CNF3_0 FÚ P GPIO_CRL_CNF3_1 EÚ P GPIO_CRL_CNF4 ØÚ P GPIO_CRL_CNF4_0 EÚ P GPIO_CRL_CNF4_1 DÚ P GPIO_CRL_CNF5 ×Ú P GPIO_CRL_CNF5_0 DÚ P GPIO_CRL_CNF5_1 CÚ P GPIO_CRL_CNF6 ÖÚ P GPIO_CRL_CNF6_0 CÚ P GPIO_CRL_CNF6_1 BÚ P GPIO_CRL_CNF7 ÕÚ P GPIO_CRL_CNF7_0 BÚ P GPIO_CRL_CNF7_1 AÚ P GPIO_CRH_MODE ÂÚ P GPIO_CRH_MODE8 Ú P GPIO_CRH_MODE8_0 õÚ P GPIO_CRH_MODE8_1 ôÚ P GPIO_CRH_MODE9 Ú P GPIO_CRH_MODE9_0 ôÚ P GPIO_CRH_MODE9_1 óÚ P GPIO_CRH_MODE10 ]Ú P GPIO_CRH_MODE10_0 ÊÚ P GPIO_CRH_MODE10_1 ÉÚ P GPIO_CRH_MODE11 \Ú P GPIO_CRH_MODE11_0 ÉÚ P GPIO_CRH_MODE11_1 ÈÚ P GPIO_CRH_MODE12 [Ú P GPIO_CRH_MODE12_0 ÈÚ P GPIO_CRH_MODE12_1 ÇÚ P GPIO_CRH_MODE13 ZÚ P GPIO_CRH_MODE13_0 ÇÚ P GPIO_CRH_MODE13_1 ÆÚ P GPIO_CRH_MODE14 YÚ P GPIO_CRH_MODE14_0 ÆÚ P GPIO_CRH_MODE14_1 ÅÚ P GPIO_CRH_MODE15 XÚ P GPIO_CRH_MODE15_0 ÅÚ P GPIO_CRH_MODE15_1 ÄÚ P
GPIO_CRH_CNF Ú P GPIO_CRH_CNF8 ØÚ P GPIO_CRH_CNF8_0 EÚ P GPIO_CRH_CNF8_1 DÚ P GPIO_CRH_CNF9 ×Ú P GPIO_CRH_CNF9_0 DÚ P GPIO_CRH_CNF9_1 CÚ P GPIO_CRH_CNF10 Ú P GPIO_CRH_CNF10_0 Ú P GPIO_CRH_CNF10_1 Ú P GPIO_CRH_CNF11 ¬Ú P GPIO_CRH_CNF11_0 Ú P GPIO_CRH_CNF11_1 Ú P GPIO_CRH_CNF12 «Ú P GPIO_CRH_CNF12_0 Ú P GPIO_CRH_CNF12_1 Ú P GPIO_CRH_CNF13 ªÚ P GPIO_CRH_CNF13_0 Ú P GPIO_CRH_CNF13_1 Ú P GPIO_CRH_CNF14 ©Ú P GPIO_CRH_CNF14_0 Ú P GPIO_CRH_CNF14_1 Ú P GPIO_CRH_CNF15 ¨Ú P GPIO_CRH_CNF15_0 Ú P GPIO_CRH_CNF15_1 Ú P GPIO_IDR_IDR0 ÖÚ P GPIO_IDR_IDR1 ÕÚ P GPIO_IDR_IDR2 ÔÚ P GPIO_IDR_IDR3 ÓÚ P GPIO_IDR_IDR4 ÒÚ P GPIO_IDR_IDR5 ÑÚ P GPIO_IDR_IDR6 ÐÚ P GPIO_IDR_IDR7 ÏÚ P GPIO_IDR_IDR8 ÎÚ P GPIO_IDR_IDR9 ÍÚ P GPIO_IDR_IDR10 £Ú P GPIO_IDR_IDR11 ¢Ú P GPIO_IDR_IDR12 ¡Ú P GPIO_IDR_IDR13 Ú P GPIO_IDR_IDR14 Ú P GPIO_IDR_IDR15 Ú P GPIO_ODR_ODR0 ÊÚ P GPIO_ODR_ODR1 ÉÚ P GPIO_ODR_ODR2 ÈÚ P GPIO_ODR_ODR3 ÇÚ P GPIO_ODR_ODR4 ÆÚ P GPIO_ODR_ODR5 ÅÚ P GPIO_ODR_ODR6 ÄÚ P GPIO_ODR_ODR7 ÃÚ P GPIO_ODR_ODR8 ÂÚ P GPIO_ODR_ODR9 ÁÚ P GPIO_ODR_ODR10 Ú P GPIO_ODR_ODR11 Ú P GPIO_ODR_ODR12 Ú P GPIO_ODR_ODR13 Ú P GPIO_ODR_ODR14 Ú P GPIO_ODR_ODR15 Ú P GPIO_BSRR_BS0 ÆÚ P GPIO_BSRR_BS1 ÅÚ P GPIO_BSRR_BS2 ÄÚ P GPIO_BSRR_BS3 ÃÚ P GPIO_BSRR_BS4 ÂÚ P GPIO_BSRR_BS5 ÁÚ P GPIO_BSRR_BS6 ÀÚ P GPIO_BSRR_BS7 ¿Ú P GPIO_BSRR_BS8 ¾Ú P GPIO_BSRR_BS9 ½Ú P GPIO_BSRR_BS10 Ú P GPIO_BSRR_BS11 Ú P GPIO_BSRR_BS12 Ú P GPIO_BSRR_BS13 Ú P GPIO_BSRR_BS14 Ú P GPIO_BSRR_BS15 Ú P GPIO_BSRR_BR0 ÇÚ P GPIO_BSRR_BR1 ÆÚ P GPIO_BSRR_BR2 ÅÚ P GPIO_BSRR_BR3 ÄÚ P GPIO_BSRR_BR4 ÃÚ P GPIO_BSRR_BR5 ÂÚ P GPIO_BSRR_BR6 ÁÚ P GPIO_BSRR_BR7 ÀÚ P GPIO_BSRR_BR8 ¿Ú P GPIO_BSRR_BR9 ¾Ú P GPIO_BSRR_BR10 Ú P GPIO_BSRR_BR11 Ú P GPIO_BSRR_BR12 Ú P GPIO_BSRR_BR13 Ú P GPIO_BSRR_BR14 Ú P GPIO_BSRR_BR15 Ú P
GPIO_BRR_BR0 Ú P
GPIO_BRR_BR1 Ú P
GPIO_BRR_BR2 Ú P
GPIO_BRR_BR3 Ú P
GPIO_BRR_BR4 Ú P
GPIO_BRR_BR5 Ú P
GPIO_BRR_BR6 Ú P
GPIO_BRR_BR7 Ú P
GPIO_BRR_BR8 Ú P
GPIO_BRR_BR9 Ú P GPIO_BRR_BR10 éÚ P GPIO_BRR_BR11 èÚ P GPIO_BRR_BR12 çÚ P GPIO_BRR_BR13 æÚ P GPIO_BRR_BR14 åÚ P GPIO_BRR_BR15 äÚ P GPIO_LCKR_LCK0 Ú P GPIO_LCKR_LCK1 Ú P GPIO_LCKR_LCK2 Ú P GPIO_LCKR_LCK3 Ú P GPIO_LCKR_LCK4 Ú P GPIO_LCKR_LCK5 Ú P GPIO_LCKR_LCK6 Ú P GPIO_LCKR_LCK7
Ú P GPIO_LCKR_LCK8 Ú P GPIO_LCKR_LCK9 Ú P GPIO_LCKR_LCK10 YÚ P GPIO_LCKR_LCK11 XÚ P GPIO_LCKR_LCK12 WÚ P GPIO_LCKR_LCK13 VÚ P GPIO_LCKR_LCK14 UÚ P GPIO_LCKR_LCK15 TÚ P GPIO_LCKR_LCKK qÚ P AFIO_EVCR_PIN ½Ú P AFIO_EVCR_PIN_0 *Ú P AFIO_EVCR_PIN_1 )Ú P AFIO_EVCR_PIN_2 (Ú P AFIO_EVCR_PIN_3 'Ú P AFIO_EVCR_PIN_PX0 ~Ú P AFIO_EVCR_PIN_PX1 }Ú P AFIO_EVCR_PIN_PX2 |Ú P AFIO_EVCR_PIN_PX3 {Ú P AFIO_EVCR_PIN_PX4 zÚ P AFIO_EVCR_PIN_PX5 yÚ P AFIO_EVCR_PIN_PX6 xÚ P AFIO_EVCR_PIN_PX7 wÚ P AFIO_EVCR_PIN_PX8 vÚ P AFIO_EVCR_PIN_PX9 uÚ P AFIO_EVCR_PIN_PX10 KÚ P AFIO_EVCR_PIN_PX11 JÚ P AFIO_EVCR_PIN_PX12 IÚ P AFIO_EVCR_PIN_PX13 HÚ P AFIO_EVCR_PIN_PX14 GÚ P AFIO_EVCR_PIN_PX15 FÚ P AFIO_EVCR_PORT ]Ú P AFIO_EVCR_PORT_0 ÊÚ P AFIO_EVCR_PORT_1 ÉÚ P AFIO_EVCR_PORT_2 ÈÚ P AFIO_EVCR_PORT_PA gÚ P AFIO_EVCR_PORT_PB fÚ P AFIO_EVCR_PORT_PC eÚ P AFIO_EVCR_PORT_PD dÚ P AFIO_EVCR_PORT_PE cÚ P AFIO_EVCR_EVOE sÚ P AFIO_MAPR_SPI1_REMAP ¥Ú P AFIO_MAPR_I2C1_REMAP ÓÚ P AFIO_MAPR_USART1_REMAP þÚ P AFIO_MAPR_USART2_REMAP ýÚ P AFIO_MAPR_USART3_REMAP üÚ! P AFIO_MAPR_USART3_REMAP_0 iÚ! P AFIO_MAPR_USART3_REMAP_1 hÚ' P AFIO_MAPR_USART3_REMAP_NOREMAP {Ú, P $AFIO_MAPR_USART3_REMAP_PARTIALREMAP Ú) P !AFIO_MAPR_USART3_REMAP_FULLREMAP áÚ P AFIO_MAPR_TIM1_REMAP §Ú P AFIO_MAPR_TIM1_REMAP_0 Ú P AFIO_MAPR_TIM1_REMAP_1 Ú% P AFIO_MAPR_TIM1_REMAP_NOREMAP &Ú* P "AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ¬Ú' P AFIO_MAPR_TIM1_REMAP_FULLREMAP Ú P AFIO_MAPR_TIM2_REMAP ¦Ú P AFIO_MAPR_TIM2_REMAP_0 Ú P AFIO_MAPR_TIM2_REMAP_1 Ú% P AFIO_MAPR_TIM2_REMAP_NOREMAP %Ú+ P #AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 xÚ+ P #AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 wÚ' P AFIO_MAPR_TIM2_REMAP_FULLREMAP Ú P AFIO_MAPR_TIM3_REMAP ¥Ú P AFIO_MAPR_TIM3_REMAP_0 Ú P AFIO_MAPR_TIM3_REMAP_1 Ú% P AFIO_MAPR_TIM3_REMAP_NOREMAP $Ú* P "AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ªÚ' P AFIO_MAPR_TIM3_REMAP_FULLREMAP Ú P AFIO_MAPR_TIM4_REMAP ¤Ú P AFIO_MAPR_CAN_REMAP òÚ P AFIO_MAPR_CAN_REMAP_0 _Ú P AFIO_MAPR_CAN_REMAP_1 ^Ú# P AFIO_MAPR_CAN_REMAP_REMAP1 ßÚ# P AFIO_MAPR_CAN_REMAP_REMAP2 ÞÚ# P AFIO_MAPR_CAN_REMAP_REMAP3 ÝÚ P AFIO_MAPR_PD01_REMAP ÍÚ! P AFIO_MAPR_TIM5CH4_IREMAP Ú% P AFIO_MAPR_ADC1_ETRGINJ_REMAP GÚ% P AFIO_MAPR_ADC1_ETRGREG_REMAP JÚ% P AFIO_MAPR_ADC2_ETRGINJ_REMAP FÚ% P AFIO_MAPR_ADC2_ETRGREG_REMAP IÚ P AFIO_MAPR_SWJ_CFG yÚ P AFIO_MAPR_SWJ_CFG_0 æÚ P AFIO_MAPR_SWJ_CFG_1 åÚ P AFIO_MAPR_SWJ_CFG_2 äÚ P AFIO_MAPR_SWJ_CFG_RESET Ú# P AFIO_MAPR_SWJ_CFG_NOJNTRST Ú& P AFIO_MAPR_SWJ_CFG_JTAGDISABLE èÚ" P AFIO_MAPR_SWJ_CFG_DISABLE Ú P AFIO_EXTICR1_EXTI0 `Ú P AFIO_EXTICR1_EXTI1 _Ú P AFIO_EXTICR1_EXTI2 ^Ú P AFIO_EXTICR1_EXTI3 ]Ú P AFIO_EXTICR1_EXTI0_PA jÚ P AFIO_EXTICR1_EXTI0_PB iÚ P AFIO_EXTICR1_EXTI0_PC hÚ P AFIO_EXTICR1_EXTI0_PD gÚ P AFIO_EXTICR1_EXTI0_PE fÚ P AFIO_EXTICR1_EXTI0_PF eÚ P AFIO_EXTICR1_EXTI0_PG dÚ P AFIO_EXTICR1_EXTI1_PA iÚ P AFIO_EXTICR1_EXTI1_PB hÚ P AFIO_EXTICR1_EXTI1_PC gÚ P AFIO_EXTICR1_EXTI1_PD fÚ P AFIO_EXTICR1_EXTI1_PE eÚ P AFIO_EXTICR1_EXTI1_PF dÚ P AFIO_EXTICR1_EXTI1_PG cÚ P AFIO_EXTICR1_EXTI2_PA hÚ P AFIO_EXTICR1_EXTI2_PB gÚ P AFIO_EXTICR1_EXTI2_PC fÚ P AFIO_EXTICR1_EXTI2_PD eÚ P AFIO_EXTICR1_EXTI2_PE dÚ P AFIO_EXTICR1_EXTI2_PF cÚ P AFIO_EXTICR1_EXTI2_PG bÚ P AFIO_EXTICR1_EXTI3_PA gÚ P AFIO_EXTICR1_EXTI3_PB fÚ P AFIO_EXTICR1_EXTI3_PC eÚ P AFIO_EXTICR1_EXTI3_PD dÚ P AFIO_EXTICR1_EXTI3_PE cÚ P AFIO_EXTICR1_EXTI3_PF bÚ P AFIO_EXTICR1_EXTI3_PG aÚ P AFIO_EXTICR2_EXTI4 [Ú P AFIO_EXTICR2_EXTI5 ZÚ P AFIO_EXTICR2_EXTI6 YÚ P AFIO_EXTICR2_EXTI7 XÚ P AFIO_EXTICR2_EXTI4_PA eÚ P AFIO_EXTICR2_EXTI4_PB dÚ P AFIO_EXTICR2_EXTI4_PC cÚ P AFIO_EXTICR2_EXTI4_PD bÚ P AFIO_EXTICR2_EXTI4_PE aÚ P AFIO_EXTICR2_EXTI4_PF `Ú P AFIO_EXTICR2_EXTI4_PG _Ú P AFIO_EXTICR2_EXTI5_PA dÚ P AFIO_EXTICR2_EXTI5_PB cÚ P AFIO_EXTICR2_EXTI5_PC bÚ P AFIO_EXTICR2_EXTI5_PD aÚ P AFIO_EXTICR2_EXTI5_PE `Ú P AFIO_EXTICR2_EXTI5_PF _Ú P AFIO_EXTICR2_EXTI5_PG ^Ú P AFIO_EXTICR2_EXTI6_PA cÚ P AFIO_EXTICR2_EXTI6_PB bÚ P AFIO_EXTICR2_EXTI6_PC aÚ P AFIO_EXTICR2_EXTI6_PD `Ú P AFIO_EXTICR2_EXTI6_PE _Ú P AFIO_EXTICR2_EXTI6_PF ^Ú P AFIO_EXTICR2_EXTI6_PG ]Ú P AFIO_EXTICR2_EXTI7_PA bÚ P AFIO_EXTICR2_EXTI7_PB aÚ P AFIO_EXTICR2_EXTI7_PC `Ú P AFIO_EXTICR2_EXTI7_PD _Ú P AFIO_EXTICR2_EXTI7_PE ^Ú P AFIO_EXTICR2_EXTI7_PF ]Ú P AFIO_EXTICR2_EXTI7_PG \Ú P AFIO_EXTICR3_EXTI8 VÚ P AFIO_EXTICR3_EXTI9 UÚ P AFIO_EXTICR3_EXTI10 +Ú P AFIO_EXTICR3_EXTI11 *Ú P AFIO_EXTICR3_EXTI8_PA `Ú P AFIO_EXTICR3_EXTI8_PB _Ú P AFIO_EXTICR3_EXTI8_PC ^Ú P AFIO_EXTICR3_EXTI8_PD ]Ú P AFIO_EXTICR3_EXTI8_PE \Ú P AFIO_EXTICR3_EXTI8_PF [Ú P AFIO_EXTICR3_EXTI8_PG ZÚ P AFIO_EXTICR3_EXTI9_PA _Ú P AFIO_EXTICR3_EXTI9_PB ^Ú P AFIO_EXTICR3_EXTI9_PC ]Ú P AFIO_EXTICR3_EXTI9_PD \Ú P AFIO_EXTICR3_EXTI9_PE [Ú P AFIO_EXTICR3_EXTI9_PF ZÚ P AFIO_EXTICR3_EXTI9_PG YÚ P AFIO_EXTICR3_EXTI10_PA 5Ú P AFIO_EXTICR3_EXTI10_PB 4Ú P AFIO_EXTICR3_EXTI10_PC 3Ú P AFIO_EXTICR3_EXTI10_PD 2Ú P AFIO_EXTICR3_EXTI10_PE 1Ú P AFIO_EXTICR3_EXTI10_PF 0Ú P AFIO_EXTICR3_EXTI10_PG /Ú P AFIO_EXTICR3_EXTI11_PA 4Ú P AFIO_EXTICR3_EXTI11_PB 3Ú P AFIO_EXTICR3_EXTI11_PC 2Ú P AFIO_EXTICR3_EXTI11_PD 1Ú P AFIO_EXTICR3_EXTI11_PE 0Ú P AFIO_EXTICR3_EXTI11_PF /Ú P AFIO_EXTICR3_EXTI11_PG .Ú P AFIO_EXTICR4_EXTI12 (Ú P AFIO_EXTICR4_EXTI13 'Ú P AFIO_EXTICR4_EXTI14 &Ú P AFIO_EXTICR4_EXTI15 %Ú P AFIO_EXTICR4_EXTI12_PA 2Ú P AFIO_EXTICR4_EXTI12_PB 1Ú P AFIO_EXTICR4_EXTI12_PC 0Ú P AFIO_EXTICR4_EXTI12_PD /Ú P AFIO_EXTICR4_EXTI12_PE .Ú P AFIO_EXTICR4_EXTI12_PF -Ú P AFIO_EXTICR4_EXTI12_PG ,Ú P AFIO_EXTICR4_EXTI13_PA 1Ú P AFIO_EXTICR4_EXTI13_PB 0Ú P AFIO_EXTICR4_EXTI13_PC /Ú P AFIO_EXTICR4_EXTI13_PD .Ú P AFIO_EXTICR4_EXTI13_PE -Ú P AFIO_EXTICR4_EXTI13_PF ,Ú P AFIO_EXTICR4_EXTI13_PG +Ú P AFIO_EXTICR4_EXTI14_PA 0Ú P AFIO_EXTICR4_EXTI14_PB /Ú P AFIO_EXTICR4_EXTI14_PC .Ú P AFIO_EXTICR4_EXTI14_PD -Ú P AFIO_EXTICR4_EXTI14_PE ,Ú P AFIO_EXTICR4_EXTI14_PF +Ú P AFIO_EXTICR4_EXTI14_PG *Ú P AFIO_EXTICR4_EXTI15_PA /Ú P AFIO_EXTICR4_EXTI15_PB .Ú P AFIO_EXTICR4_EXTI15_PC -Ú P AFIO_EXTICR4_EXTI15_PD ,Ú P AFIO_EXTICR4_EXTI15_PE +Ú P AFIO_EXTICR4_EXTI15_PF *Ú P AFIO_EXTICR4_EXTI15_PG )Ú P SysTick_CTRL_ENABLE AÚ P SysTick_CTRL_TICKINT ÐÚ P SysTick_CTRL_CLKSOURCE 7Ú P SysTick_CTRL_COUNTFLAG ?Ú P SysTick_LOAD_RELOAD FÚ P SysTick_VAL_CURRENT Ú P SysTick_CALIB_TENMS ;Ú P SysTick_CALIB_SKEW Ú P SysTick_CALIB_NOREF HÚ P NVIC_ISER_SETENA ÊÚ P NVIC_ISER_SETENA_0 7Ú P NVIC_ISER_SETENA_1 6Ú P NVIC_ISER_SETENA_2 5Ú P NVIC_ISER_SETENA_3 4Ú P NVIC_ISER_SETENA_4 3Ú P NVIC_ISER_SETENA_5 2Ú P NVIC_ISER_SETENA_6 1Ú P NVIC_ISER_SETENA_7 0Ú P NVIC_ISER_SETENA_8 /Ú P NVIC_ISER_SETENA_9 .Ú P NVIC_ISER_SETENA_10 Ú P NVIC_ISER_SETENA_11 Ú P NVIC_ISER_SETENA_12 Ú P NVIC_ISER_SETENA_13 Ú P NVIC_ISER_SETENA_14 Ú P NVIC_ISER_SETENA_15 ÿÚ P NVIC_ISER_SETENA_16 þÚ P NVIC_ISER_SETENA_17 ýÚ P NVIC_ISER_SETENA_18 üÚ P NVIC_ISER_SETENA_19 ûÚ P NVIC_ISER_SETENA_20 Ú P NVIC_ISER_SETENA_21 Ú P NVIC_ISER_SETENA_22 Ú P NVIC_ISER_SETENA_23 Ú P NVIC_ISER_SETENA_24 ÿÚ P NVIC_ISER_SETENA_25 þÚ P NVIC_ISER_SETENA_26 ýÚ P NVIC_ISER_SETENA_27 üÚ P NVIC_ISER_SETENA_28 ûÚ P NVIC_ISER_SETENA_29 úÚ P NVIC_ISER_SETENA_30 Ú P NVIC_ISER_SETENA_31 Ú P NVIC_ICER_CLRENA åÚ P NVIC_ICER_CLRENA_0 RÚ P NVIC_ICER_CLRENA_1 QÚ P NVIC_ICER_CLRENA_2 PÚ P NVIC_ICER_CLRENA_3 OÚ P NVIC_ICER_CLRENA_4 NÚ P NVIC_ICER_CLRENA_5 MÚ P NVIC_ICER_CLRENA_6 LÚ P NVIC_ICER_CLRENA_7 KÚ P NVIC_ICER_CLRENA_8 JÚ P NVIC_ICER_CLRENA_9 IÚ P NVIC_ICER_CLRENA_10 Ú P NVIC_ICER_CLRENA_11 Ú P NVIC_ICER_CLRENA_12 Ú P NVIC_ICER_CLRENA_13 Ú P NVIC_ICER_CLRENA_14 Ú P NVIC_ICER_CLRENA_15 Ú P NVIC_ICER_CLRENA_16 Ú P NVIC_ICER_CLRENA_17 Ú P NVIC_ICER_CLRENA_18 Ú P NVIC_ICER_CLRENA_19 Ú P NVIC_ICER_CLRENA_20 Ú P NVIC_ICER_CLRENA_21 Ú P NVIC_ICER_CLRENA_22 Ú P NVIC_ICER_CLRENA_23 Ú P NVIC_ICER_CLRENA_24 Ú P NVIC_ICER_CLRENA_25 Ú P NVIC_ICER_CLRENA_26 Ú P NVIC_ICER_CLRENA_27 Ú P NVIC_ICER_CLRENA_28 Ú P NVIC_ICER_CLRENA_29 Ú P NVIC_ICER_CLRENA_30 Ú P NVIC_ICER_CLRENA_31 Ú P NVIC_ISPR_SETPEND jÚ P NVIC_ISPR_SETPEND_0 ×Ú P NVIC_ISPR_SETPEND_1 ÖÚ P NVIC_ISPR_SETPEND_2 ÕÚ P NVIC_ISPR_SETPEND_3 ÔÚ P NVIC_ISPR_SETPEND_4 ÓÚ P NVIC_ISPR_SETPEND_5 ÒÚ P NVIC_ISPR_SETPEND_6 ÑÚ P NVIC_ISPR_SETPEND_7 ÐÚ P NVIC_ISPR_SETPEND_8 ÏÚ P NVIC_ISPR_SETPEND_9 ÎÚ P NVIC_ISPR_SETPEND_10 ¤Ú P NVIC_ISPR_SETPEND_11 £Ú P NVIC_ISPR_SETPEND_12 ¢Ú P NVIC_ISPR_SETPEND_13 ¡Ú P NVIC_ISPR_SETPEND_14 Ú P NVIC_ISPR_SETPEND_15 Ú P NVIC_ISPR_SETPEND_16 Ú P NVIC_ISPR_SETPEND_17 Ú P NVIC_ISPR_SETPEND_18 Ú P NVIC_ISPR_SETPEND_19 Ú P NVIC_ISPR_SETPEND_20 £Ú P NVIC_ISPR_SETPEND_21 ¢Ú P NVIC_ISPR_SETPEND_22 ¡Ú P NVIC_ISPR_SETPEND_23 Ú P NVIC_ISPR_SETPEND_24 Ú P NVIC_ISPR_SETPEND_25 Ú P NVIC_ISPR_SETPEND_26 Ú P NVIC_ISPR_SETPEND_27 Ú P NVIC_ISPR_SETPEND_28 Ú P NVIC_ISPR_SETPEND_29 Ú P NVIC_ISPR_SETPEND_30 ¢Ú P NVIC_ISPR_SETPEND_31 ¡Ú P NVIC_ICPR_CLRPEND
Ú P NVIC_ICPR_CLRPEND_0 òÚ P NVIC_ICPR_CLRPEND_1 ñÚ P NVIC_ICPR_CLRPEND_2 ðÚ P NVIC_ICPR_CLRPEND_3 ïÚ P NVIC_ICPR_CLRPEND_4 îÚ P NVIC_ICPR_CLRPEND_5 íÚ P NVIC_ICPR_CLRPEND_6 ìÚ P NVIC_ICPR_CLRPEND_7 ëÚ P NVIC_ICPR_CLRPEND_8 êÚ P NVIC_ICPR_CLRPEND_9 éÚ P NVIC_ICPR_CLRPEND_10 ¿Ú P NVIC_ICPR_CLRPEND_11 ¾Ú P NVIC_ICPR_CLRPEND_12 ½Ú P NVIC_ICPR_CLRPEND_13 ¼Ú P NVIC_ICPR_CLRPEND_14 »Ú P NVIC_ICPR_CLRPEND_15 ºÚ P NVIC_ICPR_CLRPEND_16 ¹Ú P NVIC_ICPR_CLRPEND_17 ¸Ú P NVIC_ICPR_CLRPEND_18 ·Ú P NVIC_ICPR_CLRPEND_19 ¶Ú P NVIC_ICPR_CLRPEND_20 ¾Ú P NVIC_ICPR_CLRPEND_21 ½Ú P NVIC_ICPR_CLRPEND_22 ¼Ú P NVIC_ICPR_CLRPEND_23 »Ú P NVIC_ICPR_CLRPEND_24 ºÚ P NVIC_ICPR_CLRPEND_25 ¹Ú P NVIC_ICPR_CLRPEND_26 ¸Ú P NVIC_ICPR_CLRPEND_27 ·Ú P NVIC_ICPR_CLRPEND_28 ¶Ú P NVIC_ICPR_CLRPEND_29 µÚ P NVIC_ICPR_CLRPEND_30 ½Ú P NVIC_ICPR_CLRPEND_31 ¼Ú P NVIC_IABR_ACTIVE ãÚ P NVIC_IABR_ACTIVE_0 PÚ P NVIC_IABR_ACTIVE_1 OÚ P NVIC_IABR_ACTIVE_2 NÚ P NVIC_IABR_ACTIVE_3 MÚ P NVIC_IABR_ACTIVE_4 LÚ P NVIC_IABR_ACTIVE_5 KÚ P NVIC_IABR_ACTIVE_6 JÚ P NVIC_IABR_ACTIVE_7 IÚ P NVIC_IABR_ACTIVE_8 HÚ P NVIC_IABR_ACTIVE_9 GÚ P NVIC_IABR_ACTIVE_10 Ú P NVIC_IABR_ACTIVE_11 Ú P NVIC_IABR_ACTIVE_12 Ú P NVIC_IABR_ACTIVE_13 Ú P NVIC_IABR_ACTIVE_14 Ú P NVIC_IABR_ACTIVE_15 Ú P NVIC_IABR_ACTIVE_16 Ú P NVIC_IABR_ACTIVE_17 Ú P NVIC_IABR_ACTIVE_18 Ú P NVIC_IABR_ACTIVE_19 Ú P NVIC_IABR_ACTIVE_20 Ú P NVIC_IABR_ACTIVE_21 Ú P NVIC_IABR_ACTIVE_22 Ú P NVIC_IABR_ACTIVE_23 Ú P NVIC_IABR_ACTIVE_24 Ú P NVIC_IABR_ACTIVE_25 Ú P NVIC_IABR_ACTIVE_26 Ú P NVIC_IABR_ACTIVE_27 Ú P NVIC_IABR_ACTIVE_28 Ú P NVIC_IABR_ACTIVE_29 Ú P NVIC_IABR_ACTIVE_30 Ú P NVIC_IABR_ACTIVE_31 Ú P NVIC_IPR0_PRI_0 *Ú P NVIC_IPR0_PRI_1 )Ú P NVIC_IPR0_PRI_2 (Ú P NVIC_IPR0_PRI_3 'Ú P NVIC_IPR1_PRI_4 %Ú P NVIC_IPR1_PRI_5 $Ú P NVIC_IPR1_PRI_6 #Ú P NVIC_IPR1_PRI_7 "Ú P NVIC_IPR2_PRI_8 Ú P NVIC_IPR2_PRI_9 Ú P NVIC_IPR2_PRI_10 õÚ P NVIC_IPR2_PRI_11 ôÚ P NVIC_IPR3_PRI_12 òÚ P NVIC_IPR3_PRI_13 ñÚ P NVIC_IPR3_PRI_14 ðÚ P NVIC_IPR3_PRI_15 ïÚ P NVIC_IPR4_PRI_16 íÚ P NVIC_IPR4_PRI_17 ìÚ P NVIC_IPR4_PRI_18 ëÚ P NVIC_IPR4_PRI_19 êÚ P NVIC_IPR5_PRI_20 ñÚ P NVIC_IPR5_PRI_21 ðÚ P NVIC_IPR5_PRI_22 ïÚ P NVIC_IPR5_PRI_23 îÚ P NVIC_IPR6_PRI_24 ìÚ P NVIC_IPR6_PRI_25 ëÚ P NVIC_IPR6_PRI_26 êÚ P NVIC_IPR6_PRI_27 éÚ P NVIC_IPR7_PRI_28 çÚ P NVIC_IPR7_PRI_29 æÚ P NVIC_IPR7_PRI_30 îÚ P NVIC_IPR7_PRI_31 íÚ P SCB_CPUID_REVISION -Ú P SCB_CPUID_PARTNO ÌÚ P SCB_CPUID_Constant RÚ P SCB_CPUID_VARIANT Ú P SCB_CPUID_IMPLEMENTER TÚ P SCB_ICSR_VECTACTIVE ðÚ P SCB_ICSR_RETTOBASE 7Ú P SCB_ICSR_VECTPENDING ¥Ú P SCB_ICSR_ISRPENDING ëÚ P SCB_ICSR_ISRPREEMPT ÓÚ P SCB_ICSR_PENDSTCLR 1Ú P SCB_ICSR_PENDSTSET &Ú P SCB_ICSR_PENDSVCLR /Ú P SCB_ICSR_PENDSVSET $Ú P SCB_ICSR_NMIPENDSET çÚ P SCB_VTOR_TBLOFF Ú P SCB_VTOR_TBLBASE ÍÚ P SCB_AIRCR_VECTRESET éÚ P SCB_AIRCR_VECTCLRACTIVE ÇÚ P SCB_AIRCR_SYSRESETREQ 0Ú P SCB_AIRCR_PRIGROUP (Ú P SCB_AIRCR_PRIGROUP_0 Ú P SCB_AIRCR_PRIGROUP_1 Ú P SCB_AIRCR_PRIGROUP_2 Ú P SCB_AIRCR_PRIGROUP0 öÚ P SCB_AIRCR_PRIGROUP1 õÚ P SCB_AIRCR_PRIGROUP2 ôÚ P SCB_AIRCR_PRIGROUP3 óÚ P SCB_AIRCR_PRIGROUP4 òÚ P SCB_AIRCR_PRIGROUP5 ñÚ P SCB_AIRCR_PRIGROUP6 ðÚ P SCB_AIRCR_PRIGROUP7 ïÚ P SCB_AIRCR_ENDIANESS Ú P SCB_AIRCR_VECTKEY Ú P SCB_SCR_SLEEPONEXIT ×Ú P SCB_SCR_SLEEPDEEP Ú P SCB_SCR_SEVONPEND yÚ P SCB_CCR_NONBASETHRDENA %Ú P SCB_CCR_USERSETMPEND Ú P SCB_CCR_UNALIGN_TRP ÔÚ P SCB_CCR_DIV_0_TRP tÚ P SCB_CCR_BFHFNMIGN ¬Ú P SCB_CCR_STKALIGN àÚ P SCB_SHPR_PRI_N DÚ P SCB_SHPR_PRI_N1 Ú P SCB_SHPR_PRI_N2 Ú P SCB_SHPR_PRI_N3 Ú P SCB_SHCSR_MEMFAULTACT UÚ P SCB_SHCSR_BUSFAULTACT JÚ P SCB_SHCSR_USGFAULTACT EÚ P SCB_SHCSR_SVCALLACT ïÚ P SCB_SHCSR_MONITORACT Ú P SCB_SHCSR_PENDSVACT äÚ P SCB_SHCSR_SYSTICKACT Ú! P SCB_SHCSR_USGFAULTPENDED gÚ! P SCB_SHCSR_MEMFAULTPENDED wÚ! P SCB_SHCSR_BUSFAULTPENDED lÚ P SCB_SHCSR_SVCALLPENDED Ú P SCB_SHCSR_MEMFAULTENA YÚ P SCB_SHCSR_BUSFAULTENA NÚ P SCB_SHCSR_USGFAULTENA IÚ P SCB_CFSR_IACCVIOL Ú P SCB_CFSR_DACCVIOL Ú P SCB_CFSR_MUNSTKERR Ú P SCB_CFSR_MSTKERR ¿Ú P SCB_CFSR_MMARVALID FÚ P SCB_CFSR_IBUSERR ËÚ P SCB_CFSR_PRECISERR 4Ú P SCB_CFSR_IMPRECISERR Ú P SCB_CFSR_UNSTKERR gÚ P SCB_CFSR_STKERR Ú P SCB_CFSR_BFARVALID XÚ P SCB_CFSR_UNDEFINSTR ßÚ P SCB_CFSR_INVSTATE wÚ P SCB_CFSR_INVPC kÚ P SCB_CFSR_NOCP ½Ú P SCB_CFSR_UNALIGNED LÚ P SCB_CFSR_DIVBYZERO %Ú P SCB_HFSR_VECTTBL ÎÚ P SCB_HFSR_FORCED 1Ú P SCB_HFSR_DEBUGEVT Ú P SCB_DFSR_HALTED 6Ú P SCB_DFSR_BKPT »Ú P SCB_DFSR_DWTTRAP ÀÚ P SCB_DFSR_VCATCH /Ú P SCB_DFSR_EXTERNAL Ú P SCB_MMFAR_ADDRESS Ú P SCB_BFAR_ADDRESS ôÚ P SCB_AFSR_IMPDEF 6Ú P
EXTI_IMR_MR0 Ú P
EXTI_IMR_MR1 Ú P
EXTI_IMR_MR2 Ú P
EXTI_IMR_MR3 Ú P
EXTI_IMR_MR4 Ú P
EXTI_IMR_MR5 ÿÚ P
EXTI_IMR_MR6 þÚ P
EXTI_IMR_MR7 ýÚ P
EXTI_IMR_MR8 üÚ P
EXTI_IMR_MR9 ûÚ P EXTI_IMR_MR10 ÑÚ P EXTI_IMR_MR11 ÐÚ P EXTI_IMR_MR12 ÏÚ P EXTI_IMR_MR13 ÎÚ P EXTI_IMR_MR14 ÍÚ P EXTI_IMR_MR15 ÌÚ P EXTI_IMR_MR16 ËÚ P EXTI_IMR_MR17 ÊÚ P EXTI_IMR_MR18 ÉÚ P EXTI_IMR_MR19 ÈÚ P
EXTI_EMR_MR0 Ú P
EXTI_EMR_MR1 Ú P
EXTI_EMR_MR2 Ú P
EXTI_EMR_MR3 Ú P
EXTI_EMR_MR4 Ú P
EXTI_EMR_MR5 Ú P
EXTI_EMR_MR6 Ú P
EXTI_EMR_MR7 Ú P
EXTI_EMR_MR8 Ú P
EXTI_EMR_MR9 ÿÚ P EXTI_EMR_MR10 ÕÚ P EXTI_EMR_MR11 ÔÚ P EXTI_EMR_MR12 ÓÚ P EXTI_EMR_MR13 ÒÚ P EXTI_EMR_MR14 ÑÚ P EXTI_EMR_MR15 ÐÚ P EXTI_EMR_MR16 ÏÚ P EXTI_EMR_MR17 ÎÚ P EXTI_EMR_MR18 ÍÚ P EXTI_EMR_MR19 ÌÚ P EXTI_RTSR_TR0 Ú P EXTI_RTSR_TR1 Ú P EXTI_RTSR_TR2 Ú P EXTI_RTSR_TR3 Ú P EXTI_RTSR_TR4 Ú P EXTI_RTSR_TR5 Ú P EXTI_RTSR_TR6 Ú P EXTI_RTSR_TR7 Ú P EXTI_RTSR_TR8 Ú P EXTI_RTSR_TR9 Ú P EXTI_RTSR_TR10 eÚ P EXTI_RTSR_TR11 dÚ P EXTI_RTSR_TR12 cÚ P EXTI_RTSR_TR13 bÚ P EXTI_RTSR_TR14 aÚ P EXTI_RTSR_TR15 `Ú P EXTI_RTSR_TR16 _Ú P EXTI_RTSR_TR17 ^Ú P EXTI_RTSR_TR18 ]Ú P EXTI_RTSR_TR19 \Ú P EXTI_FTSR_TR0 ¤Ú P EXTI_FTSR_TR1 £Ú P EXTI_FTSR_TR2 ¢Ú P EXTI_FTSR_TR3 ¡Ú P EXTI_FTSR_TR4 Ú P EXTI_FTSR_TR5 Ú P EXTI_FTSR_TR6 Ú P EXTI_FTSR_TR7 Ú P EXTI_FTSR_TR8 Ú P EXTI_FTSR_TR9 Ú P EXTI_FTSR_TR10 qÚ P EXTI_FTSR_TR11 pÚ P EXTI_FTSR_TR12 oÚ P EXTI_FTSR_TR13 nÚ P EXTI_FTSR_TR14 mÚ P EXTI_FTSR_TR15 lÚ P EXTI_FTSR_TR16 kÚ P EXTI_FTSR_TR17 jÚ P EXTI_FTSR_TR18 iÚ P EXTI_FTSR_TR19 hÚ P EXTI_SWIER_SWIER0 mÚ P EXTI_SWIER_SWIER1 lÚ P EXTI_SWIER_SWIER2 kÚ P EXTI_SWIER_SWIER3 jÚ P EXTI_SWIER_SWIER4 iÚ P EXTI_SWIER_SWIER5 hÚ P EXTI_SWIER_SWIER6 gÚ P EXTI_SWIER_SWIER7 fÚ P EXTI_SWIER_SWIER8 eÚ P EXTI_SWIER_SWIER9 dÚ P EXTI_SWIER_SWIER10 :Ú P EXTI_SWIER_SWIER11 9Ú P EXTI_SWIER_SWIER12 8Ú P EXTI_SWIER_SWIER13 7Ú P EXTI_SWIER_SWIER14 6Ú P EXTI_SWIER_SWIER15 5Ú P EXTI_SWIER_SWIER16 4Ú P EXTI_SWIER_SWIER17 3Ú P EXTI_SWIER_SWIER18 2Ú P EXTI_SWIER_SWIER19 1Ú P EXTI_PR_PR0 IÚ P EXTI_PR_PR1 HÚ P EXTI_PR_PR2 GÚ P EXTI_PR_PR3 FÚ P EXTI_PR_PR4 EÚ P EXTI_PR_PR5 DÚ P EXTI_PR_PR6 CÚ P EXTI_PR_PR7 BÚ P EXTI_PR_PR8 AÚ P EXTI_PR_PR9 @Ú P
EXTI_PR_PR10 Ú P
EXTI_PR_PR11 Ú P
EXTI_PR_PR12 Ú P
EXTI_PR_PR13 Ú P
EXTI_PR_PR14 Ú P
EXTI_PR_PR15 Ú P
EXTI_PR_PR16 Ú P
EXTI_PR_PR17 Ú P
EXTI_PR_PR18 Ú P
EXTI_PR_PR19
Ú P
DMA_ISR_GIF1 .Ú P DMA_ISR_TCIF1 ÜÚ P DMA_ISR_HTIF1 ×Ú P DMA_ISR_TEIF1 ÚÚ P
DMA_ISR_GIF2 -Ú P DMA_ISR_TCIF2 ÛÚ P DMA_ISR_HTIF2 ÖÚ P DMA_ISR_TEIF2 ÙÚ P
DMA_ISR_GIF3 ,Ú P DMA_ISR_TCIF3 ÚÚ P DMA_ISR_HTIF3 ÕÚ P DMA_ISR_TEIF3 ØÚ P
DMA_ISR_GIF4 +Ú P DMA_ISR_TCIF4 ÙÚ P DMA_ISR_HTIF4 ÔÚ P DMA_ISR_TEIF4 ×Ú P
DMA_ISR_GIF5 *Ú P DMA_ISR_TCIF5 ØÚ P DMA_ISR_HTIF5 ÓÚ P DMA_ISR_TEIF5 ÖÚ P
DMA_ISR_GIF6 )Ú P DMA_ISR_TCIF6 ×Ú P DMA_ISR_HTIF6 ÒÚ P DMA_ISR_TEIF6 ÕÚ P
DMA_ISR_GIF7 (Ú P DMA_ISR_TCIF7 ÖÚ P DMA_ISR_HTIF7 ÑÚ P DMA_ISR_TEIF7 ÔÚ P DMA_IFCR_CGIF1 ±Ú P DMA_IFCR_CTCIF1 _Ú P DMA_IFCR_CHTIF1 ZÚ P DMA_IFCR_CTEIF1 ]Ú P DMA_IFCR_CGIF2 °Ú P DMA_IFCR_CTCIF2 ^Ú P DMA_IFCR_CHTIF2 YÚ P DMA_IFCR_CTEIF2 \Ú P DMA_IFCR_CGIF3 ¯Ú P DMA_IFCR_CTCIF3 ]Ú P DMA_IFCR_CHTIF3 XÚ P DMA_IFCR_CTEIF3 [Ú P DMA_IFCR_CGIF4 ®Ú P DMA_IFCR_CTCIF4 \Ú P DMA_IFCR_CHTIF4 WÚ P DMA_IFCR_CTEIF4 ZÚ P DMA_IFCR_CGIF5 Ú P DMA_IFCR_CTCIF5 [Ú P DMA_IFCR_CHTIF5 VÚ P DMA_IFCR_CTEIF5 YÚ P DMA_IFCR_CGIF6 ¬Ú P DMA_IFCR_CTCIF6 ZÚ P DMA_IFCR_CHTIF6 UÚ P DMA_IFCR_CTEIF6 XÚ P DMA_IFCR_CGIF7 «Ú P DMA_IFCR_CTCIF7 YÚ P DMA_IFCR_CHTIF7 TÚ P DMA_IFCR_CTEIF7 WÚ P DMA_CCR1_EN Ú P DMA_CCR1_TCIE óÚ P DMA_CCR1_HTIE îÚ P DMA_CCR1_TEIE ñÚ P
DMA_CCR1_DIR ;Ú P DMA_CCR1_CIRC ÷Ú P DMA_CCR1_PINC îÚ P DMA_CCR1_MINC ñÚ P DMA_CCR1_PSIZE Ú P DMA_CCR1_PSIZE_0 øÚ P DMA_CCR1_PSIZE_1 ÷Ú P DMA_CCR1_MSIZE Ú P DMA_CCR1_MSIZE_0 ûÚ P DMA_CCR1_MSIZE_1 úÚ P DMA_CCR1_PL Ú P DMA_CCR1_PL_0 íÚ P DMA_CCR1_PL_1 ìÚ P DMA_CCR1_MEM2MEM "Ú P DMA_CCR2_EN Ú P DMA_CCR2_TCIE òÚ P DMA_CCR2_HTIE íÚ P DMA_CCR2_TEIE ðÚ P
DMA_CCR2_DIR :Ú P DMA_CCR2_CIRC öÚ P DMA_CCR2_PINC íÚ P DMA_CCR2_MINC ðÚ P DMA_CCR2_PSIZE Ú P DMA_CCR2_PSIZE_0 ÷Ú P DMA_CCR2_PSIZE_1 öÚ P DMA_CCR2_MSIZE Ú P DMA_CCR2_MSIZE_0 úÚ P DMA_CCR2_MSIZE_1 ùÚ P DMA_CCR2_PL Ú P DMA_CCR2_PL_0 ìÚ P DMA_CCR2_PL_1 ëÚ P DMA_CCR2_MEM2MEM !Ú P DMA_CCR3_EN Ú P DMA_CCR3_TCIE ñÚ P DMA_CCR3_HTIE ìÚ P DMA_CCR3_TEIE ïÚ P
DMA_CCR3_DIR 9Ú P DMA_CCR3_CIRC õÚ P DMA_CCR3_PINC ìÚ P DMA_CCR3_MINC ïÚ P DMA_CCR3_PSIZE Ú P DMA_CCR3_PSIZE_0 öÚ P DMA_CCR3_PSIZE_1 õÚ P DMA_CCR3_MSIZE Ú P DMA_CCR3_MSIZE_0 ùÚ P DMA_CCR3_MSIZE_1 øÚ P DMA_CCR3_PL ~Ú P DMA_CCR3_PL_0 ëÚ P DMA_CCR3_PL_1 êÚ P DMA_CCR3_MEM2MEM Ú P DMA_CCR4_EN Ú P DMA_CCR4_TCIE ðÚ P DMA_CCR4_HTIE ëÚ P DMA_CCR4_TEIE îÚ P
DMA_CCR4_DIR 8Ú P DMA_CCR4_CIRC ôÚ P DMA_CCR4_PINC ëÚ P DMA_CCR4_MINC îÚ P DMA_CCR4_PSIZE Ú P DMA_CCR4_PSIZE_0 õÚ P DMA_CCR4_PSIZE_1 ôÚ P DMA_CCR4_MSIZE Ú P DMA_CCR4_MSIZE_0 øÚ P DMA_CCR4_MSIZE_1 ÷Ú P DMA_CCR4_PL }Ú P DMA_CCR4_PL_0 êÚ P DMA_CCR4_PL_1 éÚ P DMA_CCR4_MEM2MEM Ú P DMA_CCR5_EN
Ú P DMA_CCR5_TCIE ïÚ P DMA_CCR5_HTIE êÚ P DMA_CCR5_TEIE íÚ P
DMA_CCR5_DIR 7Ú P DMA_CCR5_CIRC óÚ P DMA_CCR5_PINC êÚ P DMA_CCR5_MINC íÚ P DMA_CCR5_PSIZE Ú P DMA_CCR5_PSIZE_0 ôÚ P DMA_CCR5_PSIZE_1 óÚ P DMA_CCR5_MSIZE Ú P DMA_CCR5_MSIZE_0 ÷Ú P DMA_CCR5_MSIZE_1 öÚ P DMA_CCR5_PL |Ú P DMA_CCR5_PL_0 éÚ P DMA_CCR5_PL_1 èÚ P DMA_CCR5_MEM2MEM Ú P DMA_CCR6_EN Ú P DMA_CCR6_TCIE îÚ P DMA_CCR6_HTIE éÚ P DMA_CCR6_TEIE ìÚ P
DMA_CCR6_DIR 6Ú P DMA_CCR6_CIRC òÚ P DMA_CCR6_PINC éÚ P DMA_CCR6_MINC ìÚ P DMA_CCR6_PSIZE Ú P DMA_CCR6_PSIZE_0 óÚ P DMA_CCR6_PSIZE_1 òÚ P DMA_CCR6_MSIZE Ú P DMA_CCR6_MSIZE_0 öÚ P DMA_CCR6_MSIZE_1 õÚ P DMA_CCR6_PL {Ú P DMA_CCR6_PL_0 èÚ P DMA_CCR6_PL_1 çÚ P DMA_CCR6_MEM2MEM Ú P DMA_CCR7_EN Ú P DMA_CCR7_TCIE íÚ P DMA_CCR7_HTIE èÚ P DMA_CCR7_TEIE ëÚ P
DMA_CCR7_DIR 5Ú P DMA_CCR7_CIRC ñÚ P DMA_CCR7_PINC èÚ P DMA_CCR7_MINC ëÚ P DMA_CCR7_PSIZE
Ú P DMA_CCR7_PSIZE_0 òÚ P DMA_CCR7_PSIZE_1 ñÚ P DMA_CCR7_MSIZE Ú P DMA_CCR7_MSIZE_0 õÚ P DMA_CCR7_MSIZE_1 ôÚ P DMA_CCR7_PL zÚ P DMA_CCR7_PL_0 çÚ P DMA_CCR7_PL_1 æÚ P DMA_CCR7_MEM2MEM Ú P DMA_CNDTR1_NDT Ú P DMA_CNDTR2_NDT Ú P DMA_CNDTR3_NDT Ú P DMA_CNDTR4_NDT Ú P DMA_CNDTR5_NDT Ú P DMA_CNDTR6_NDT Ú P DMA_CNDTR7_NDT Ú P
DMA_CPAR1_PA ;Ú P
DMA_CPAR2_PA :Ú P
DMA_CPAR3_PA 9Ú P
DMA_CPAR4_PA 8Ú P
DMA_CPAR5_PA 7Ú P
DMA_CPAR6_PA 6Ú P
DMA_CPAR7_PA 5Ú P
DMA_CMAR1_MA AÚ P
DMA_CMAR2_MA @Ú P
DMA_CMAR3_MA ?Ú P
DMA_CMAR4_MA >Ú P
DMA_CMAR5_MA =Ú P
DMA_CMAR6_MA <Ú P
DMA_CMAR7_MA ;Ú P ADC_SR_AWD °Ú P ADC_SR_EOC µÚ P ADC_SR_JEOC iÚ P
ADC_SR_JSTRT ñÚ P ADC_SR_STRT =Ú P ADC_CR1_AWDCH þÚ P ADC_CR1_AWDCH_0 kÚ P ADC_CR1_AWDCH_1 jÚ P ADC_CR1_AWDCH_2 iÚ P ADC_CR1_AWDCH_3 hÚ P ADC_CR1_AWDCH_4 gÚ P ADC_CR1_EOCIE Ú P ADC_CR1_AWDIE ûÚ P ADC_CR1_JEOCIE ´Ú P
ADC_CR1_SCAN BÚ P ADC_CR1_AWDSGL ¡Ú P ADC_CR1_JAUTO âÚ P ADC_CR1_DISCEN Ú P ADC_CR1_JDISCEN aÚ P ADC_CR1_DISCNUM NÚ P ADC_CR1_DISCNUM_0 »Ú P ADC_CR1_DISCNUM_1 ºÚ P ADC_CR1_DISCNUM_2 ¹Ú P ADC_CR1_DUALMOD [Ú P ADC_CR1_DUALMOD_0 ÈÚ P ADC_CR1_DUALMOD_1 ÇÚ P ADC_CR1_DUALMOD_2 ÆÚ P ADC_CR1_DUALMOD_3 ÅÚ P ADC_CR1_JAWDEN ªÚ P ADC_CR1_AWDEN öÚ P
ADC_CR2_ADON DÚ P
ADC_CR2_CONT 2Ú P ADC_CR2_CAL Ú P ADC_CR2_RSTCAL Ú P ADC_CR2_DMA Ú P ADC_CR2_ALIGN ùÚ P ADC_CR2_JEXTSEL AÚ P ADC_CR2_JEXTSEL_0 ®Ú P ADC_CR2_JEXTSEL_1 Ú P ADC_CR2_JEXTSEL_2 ¬Ú P ADC_CR2_JEXTTRIG íÚ P ADC_CR2_EXTSEL Ú P ADC_CR2_EXTSEL_0 úÚ P ADC_CR2_EXTSEL_1 ùÚ P ADC_CR2_EXTSEL_2 øÚ P ADC_CR2_EXTTRIG 9Ú P ADC_CR2_JSWSTART ÜÚ P ADC_CR2_SWSTART (Ú P ADC_CR2_TSVREFE AÚ P ADC_SMPR1_SMP10 cÚ P ADC_SMPR1_SMP10_0 ÐÚ P ADC_SMPR1_SMP10_1 ÏÚ P ADC_SMPR1_SMP10_2 ÎÚ P ADC_SMPR1_SMP11 bÚ P ADC_SMPR1_SMP11_0 ÏÚ P ADC_SMPR1_SMP11_1 ÎÚ P ADC_SMPR1_SMP11_2 ÍÚ P ADC_SMPR1_SMP12 aÚ P ADC_SMPR1_SMP12_0 ÎÚ P ADC_SMPR1_SMP12_1 ÍÚ P ADC_SMPR1_SMP12_2 ÌÚ P ADC_SMPR1_SMP13 `Ú P ADC_SMPR1_SMP13_0 ÍÚ P ADC_SMPR1_SMP13_1 ÌÚ P ADC_SMPR1_SMP13_2 ËÚ P ADC_SMPR1_SMP14 _Ú P ADC_SMPR1_SMP14_0 ÌÚ P ADC_SMPR1_SMP14_1 ËÚ P ADC_SMPR1_SMP14_2 ÊÚ P ADC_SMPR1_SMP15 ^Ú P ADC_SMPR1_SMP15_0 ËÚ P ADC_SMPR1_SMP15_1 ÊÚ P ADC_SMPR1_SMP15_2 ÉÚ P ADC_SMPR1_SMP16 ]Ú P ADC_SMPR1_SMP16_0 ÊÚ P ADC_SMPR1_SMP16_1 ÉÚ P ADC_SMPR1_SMP16_2 ÈÚ P ADC_SMPR1_SMP17 \Ú P ADC_SMPR1_SMP17_0 ÉÚ P ADC_SMPR1_SMP17_1 ÈÚ P ADC_SMPR1_SMP17_2 ÇÚ P ADC_SMPR2_SMP0 Ú P ADC_SMPR2_SMP0_0 Ú P ADC_SMPR2_SMP0_1 Ú P ADC_SMPR2_SMP0_2 Ú P ADC_SMPR2_SMP1 Ú P ADC_SMPR2_SMP1_0 Ú P ADC_SMPR2_SMP1_1 Ú P ADC_SMPR2_SMP1_2 ÿÚ P ADC_SMPR2_SMP2 Ú P ADC_SMPR2_SMP2_0 Ú P ADC_SMPR2_SMP2_1 ÿÚ P ADC_SMPR2_SMP2_2 þÚ P ADC_SMPR2_SMP3 Ú P ADC_SMPR2_SMP3_0 ÿÚ P ADC_SMPR2_SMP3_1 þÚ P ADC_SMPR2_SMP3_2 ýÚ P ADC_SMPR2_SMP4 Ú P ADC_SMPR2_SMP4_0 þÚ P ADC_SMPR2_SMP4_1 ýÚ P ADC_SMPR2_SMP4_2 üÚ P ADC_SMPR2_SMP5 Ú P ADC_SMPR2_SMP5_0 ýÚ P ADC_SMPR2_SMP5_1 üÚ P ADC_SMPR2_SMP5_2 ûÚ P ADC_SMPR2_SMP6 Ú P ADC_SMPR2_SMP6_0 üÚ P ADC_SMPR2_SMP6_1 ûÚ P ADC_SMPR2_SMP6_2 úÚ P ADC_SMPR2_SMP7 Ú P ADC_SMPR2_SMP7_0 ûÚ P ADC_SMPR2_SMP7_1 úÚ P ADC_SMPR2_SMP7_2 ùÚ P ADC_SMPR2_SMP8 Ú P ADC_SMPR2_SMP8_0 úÚ P ADC_SMPR2_SMP8_1 ùÚ P ADC_SMPR2_SMP8_2 øÚ P ADC_SMPR2_SMP9 Ú P ADC_SMPR2_SMP9_0 ùÚ P ADC_SMPR2_SMP9_1 øÚ P ADC_SMPR2_SMP9_2 ÷Ú P ADC_JOFR1_JOFFSET1 }Ú P ADC_JOFR2_JOFFSET2 {Ú P ADC_JOFR3_JOFFSET3 yÚ P ADC_JOFR4_JOFFSET4 wÚ P ADC_HTR_HT §Ú P ADC_LTR_LT Ú P ADC_SQR1_SQ13 üÚ P ADC_SQR1_SQ13_0 iÚ P ADC_SQR1_SQ13_1 hÚ P ADC_SQR1_SQ13_2 gÚ P ADC_SQR1_SQ13_3 fÚ P ADC_SQR1_SQ13_4 eÚ P ADC_SQR1_SQ14 ûÚ P ADC_SQR1_SQ14_0 hÚ P ADC_SQR1_SQ14_1 gÚ P ADC_SQR1_SQ14_2 fÚ P ADC_SQR1_SQ14_3 eÚ P ADC_SQR1_SQ14_4 dÚ P ADC_SQR1_SQ15 úÚ P ADC_SQR1_SQ15_0 gÚ P ADC_SQR1_SQ15_1 fÚ P ADC_SQR1_SQ15_2 eÚ P ADC_SQR1_SQ15_3 dÚ P ADC_SQR1_SQ15_4 cÚ P ADC_SQR1_SQ16 ùÚ P ADC_SQR1_SQ16_0 fÚ P ADC_SQR1_SQ16_1 eÚ P ADC_SQR1_SQ16_2 dÚ P ADC_SQR1_SQ16_3 cÚ P ADC_SQR1_SQ16_4 bÚ P ADC_SQR1_L ¾Ú P
ADC_SQR1_L_0 +Ú P
ADC_SQR1_L_1 *Ú P
ADC_SQR1_L_2 )Ú P
ADC_SQR1_L_3 (Ú P
ADC_SQR2_SQ7 *Ú P ADC_SQR2_SQ7_0 Ú P ADC_SQR2_SQ7_1 Ú P ADC_SQR2_SQ7_2 Ú P ADC_SQR2_SQ7_3 Ú P ADC_SQR2_SQ7_4 Ú P
ADC_SQR2_SQ8 )Ú P ADC_SQR2_SQ8_0 Ú P ADC_SQR2_SQ8_1 Ú P ADC_SQR2_SQ8_2 Ú P ADC_SQR2_SQ8_3 Ú P ADC_SQR2_SQ8_4 Ú P
ADC_SQR2_SQ9 (Ú P ADC_SQR2_SQ9_0 Ú P ADC_SQR2_SQ9_1 Ú P ADC_SQR2_SQ9_2 Ú P ADC_SQR2_SQ9_3 Ú P ADC_SQR2_SQ9_4 Ú P ADC_SQR2_SQ10 þÚ P ADC_SQR2_SQ10_0 kÚ P ADC_SQR2_SQ10_1 jÚ P ADC_SQR2_SQ10_2 iÚ P ADC_SQR2_SQ10_3 hÚ P ADC_SQR2_SQ10_4 gÚ P ADC_SQR2_SQ11 ýÚ P ADC_SQR2_SQ11_0 jÚ P ADC_SQR2_SQ11_1 iÚ P ADC_SQR2_SQ11_2 hÚ P ADC_SQR2_SQ11_3 gÚ P ADC_SQR2_SQ11_4 fÚ P ADC_SQR2_SQ12 üÚ P ADC_SQR2_SQ12_0 iÚ P ADC_SQR2_SQ12_1 hÚ P ADC_SQR2_SQ12_2 gÚ P ADC_SQR2_SQ12_3 fÚ P ADC_SQR2_SQ12_4 eÚ P
ADC_SQR3_SQ1 /Ú P ADC_SQR3_SQ1_0 Ú P ADC_SQR3_SQ1_1 Ú P ADC_SQR3_SQ1_2 Ú P ADC_SQR3_SQ1_3 Ú P ADC_SQR3_SQ1_4 Ú P
ADC_SQR3_SQ2 .Ú P ADC_SQR3_SQ2_0 Ú P ADC_SQR3_SQ2_1 Ú P ADC_SQR3_SQ2_2 Ú P ADC_SQR3_SQ2_3 Ú P ADC_SQR3_SQ2_4 Ú P
ADC_SQR3_SQ3 -Ú P ADC_SQR3_SQ3_0 Ú P ADC_SQR3_SQ3_1 Ú P ADC_SQR3_SQ3_2 Ú P ADC_SQR3_SQ3_3 Ú P ADC_SQR3_SQ3_4 Ú P
ADC_SQR3_SQ4 ,Ú P ADC_SQR3_SQ4_0 Ú P ADC_SQR3_SQ4_1 Ú P ADC_SQR3_SQ4_2 Ú P ADC_SQR3_SQ4_3 Ú P ADC_SQR3_SQ4_4 Ú P
ADC_SQR3_SQ5 +Ú P ADC_SQR3_SQ5_0 Ú P ADC_SQR3_SQ5_1 Ú P ADC_SQR3_SQ5_2 Ú P ADC_SQR3_SQ5_3 Ú P ADC_SQR3_SQ5_4 Ú P
ADC_SQR3_SQ6 *Ú P ADC_SQR3_SQ6_0 Ú P ADC_SQR3_SQ6_1 Ú P ADC_SQR3_SQ6_2 Ú P ADC_SQR3_SQ6_3 Ú P ADC_SQR3_SQ6_4 Ú P ADC_JSQR_JSQ1 ÌÚ P ADC_JSQR_JSQ1_0 9Ú P ADC_JSQR_JSQ1_1 8Ú P ADC_JSQR_JSQ1_2 7Ú P ADC_JSQR_JSQ1_3 6Ú P ADC_JSQR_JSQ1_4 5Ú P ADC_JSQR_JSQ2 ËÚ P ADC_JSQR_JSQ2_0 8Ú P ADC_JSQR_JSQ2_1 7Ú P ADC_JSQR_JSQ2_2 6Ú P ADC_JSQR_JSQ2_3 5Ú P ADC_JSQR_JSQ2_4 4Ú P ADC_JSQR_JSQ3 ÊÚ P ADC_JSQR_JSQ3_0 7Ú P ADC_JSQR_JSQ3_1 6Ú P ADC_JSQR_JSQ3_2 5Ú P ADC_JSQR_JSQ3_3 4Ú P ADC_JSQR_JSQ3_4 3Ú P ADC_JSQR_JSQ4 ÉÚ P ADC_JSQR_JSQ4_0 6Ú P ADC_JSQR_JSQ4_1 5Ú P ADC_JSQR_JSQ4_2 4Ú P ADC_JSQR_JSQ4_3 3Ú P ADC_JSQR_JSQ4_4 2Ú P ADC_JSQR_JL YÚ P ADC_JSQR_JL_0 ÆÚ P ADC_JSQR_JL_1 ÅÚ P ADC_JDR1_JDATA ´Ú P ADC_JDR2_JDATA ³Ú P ADC_JDR3_JDATA ²Ú P ADC_JDR4_JDATA ±Ú P ADC_DR_DATA Ú P ADC_DR_ADC2DATA }Ú P DAC_CR_EN1 ØÚ P
DAC_CR_BOFF1 JÚ P DAC_CR_TEN1 Ú P
DAC_CR_TSEL1 /Ú P DAC_CR_TSEL1_0 Ú P DAC_CR_TSEL1_1 Ú P DAC_CR_TSEL1_2 Ú P
DAC_CR_WAVE1 4Ú P DAC_CR_WAVE1_0 ¡Ú P DAC_CR_WAVE1_1 Ú P
DAC_CR_MAMP1 <Ú P DAC_CR_MAMP1_0 ©Ú P DAC_CR_MAMP1_1 ¨Ú P DAC_CR_MAMP1_2 §Ú P DAC_CR_MAMP1_3 ¦Ú P DAC_CR_DMAEN1 Ú P DAC_CR_EN2 ×Ú P
DAC_CR_BOFF2 IÚ P DAC_CR_TEN2 Ú P
DAC_CR_TSEL2 .Ú P DAC_CR_TSEL2_0 Ú P DAC_CR_TSEL2_1 Ú P DAC_CR_TSEL2_2 Ú P
DAC_CR_WAVE2 3Ú P DAC_CR_WAVE2_0 Ú P DAC_CR_WAVE2_1 Ú P
DAC_CR_MAMP2 ;Ú P DAC_CR_MAMP2_0 ¨Ú P DAC_CR_MAMP2_1 §Ú P DAC_CR_MAMP2_2 ¦Ú P DAC_CR_MAMP2_3 ¥Ú P DAC_CR_DMAEN2 ÿÚ P DAC_SWTRIGR_SWTRIG1 ÜÚ P DAC_SWTRIGR_SWTRIG2 ÛÚ P DAC_DHR12R1_DACC1DHR ?Ú P DAC_DHR12L1_DACC1DHR EÚ P DAC_DHR8R1_DACC1DHR lÚ P DAC_DHR12R2_DACC2DHR =Ú P DAC_DHR12L2_DACC2DHR CÚ P DAC_DHR8R2_DACC2DHR jÚ P DAC_DHR12RD_DACC1DHR ,Ú P DAC_DHR12RD_DACC2DHR +Ú P DAC_DHR12LD_DACC1DHR 2Ú P DAC_DHR12LD_DACC2DHR 1Ú P DAC_DHR8RD_DACC1DHR YÚ P DAC_DHR8RD_DACC2DHR XÚ P DAC_DOR1_DACC1DOR ìÚ P DAC_DOR2_DACC2DOR êÚ P DAC_SR_DMAUDR1 Ú P DAC_SR_DMAUDR2 Ú P CEC_CFGR_PE uÚ P CEC_CFGR_IE |Ú P CEC_CFGR_BTEM ÞÚ P CEC_CFGR_BPEM âÚ P CEC_OAR_OA ¼Ú P
CEC_OAR_OA_0 )Ú P
CEC_OAR_OA_1 (Ú P
CEC_OAR_OA_2 'Ú P
CEC_OAR_OA_3 &Ú P CEC_PRES_PRES ´Ú P CEC_ESR_BTE gÚ P CEC_ESR_BPE kÚ P CEC_ESR_RBTFE ËÚ P CEC_ESR_SBE hÚ P
CEC_ESR_ACKE ,Ú P
CEC_ESR_LINE Ú P CEC_ESR_TBTFE ÉÚ P
CEC_CSR_TSOM ÿÚ P
CEC_CSR_TEOM
Ú P
CEC_CSR_TERR Ú P CEC_CSR_TBTRF ¾Ú P
CEC_CSR_RSOM Ú P
CEC_CSR_REOM Ú P
CEC_CSR_RERR Ú P
CEC_CSR_RBTF Ú P CEC_TXD_TXD LÚ P CEC_RXD_RXD PÚ P TIM_CR1_CEN qÚ P
TIM_CR1_UDIS Ú P TIM_CR1_URS MÚ P TIM_CR1_OPM [Ú P TIM_CR1_DIR hÚ P TIM_CR1_CMS dÚ P TIM_CR1_CMS_0 ÑÚ P TIM_CR1_CMS_1 ÐÚ P
TIM_CR1_ARPE Ú P TIM_CR1_CKD uÚ P TIM_CR1_CKD_0 âÚ P TIM_CR1_CKD_1 áÚ P
TIM_CR2_CCPC +Ú P
TIM_CR2_CCUS Ú P
TIM_CR2_CCDS 'Ú P TIM_CR2_MMS YÚ P TIM_CR2_MMS_0 ÆÚ P TIM_CR2_MMS_1 ÅÚ P TIM_CR2_MMS_2 ÄÚ P
TIM_CR2_TI1S #Ú P
TIM_CR2_OIS1 (Ú P TIM_CR2_OIS1N ØÚ P
TIM_CR2_OIS2 'Ú P TIM_CR2_OIS2N ×Ú P
TIM_CR2_OIS3 &Ú P TIM_CR2_OIS3N ÖÚ P
TIM_CR2_OIS4 %Ú P
TIM_SMCR_SMS ãÚ P TIM_SMCR_SMS_0 PÚ P TIM_SMCR_SMS_1 OÚ P TIM_SMCR_SMS_2 NÚ P TIM_SMCR_TS 1Ú P TIM_SMCR_TS_0 Ú P TIM_SMCR_TS_1 Ú P TIM_SMCR_TS_2 Ú P
TIM_SMCR_MSM éÚ P
TIM_SMCR_ETF ÷Ú P TIM_SMCR_ETF_0 dÚ P TIM_SMCR_ETF_1 cÚ P TIM_SMCR_ETF_2 bÚ P TIM_SMCR_ETF_3 aÚ P TIM_SMCR_ETPS Ú P TIM_SMCR_ETPS_0 Ú P TIM_SMCR_ETPS_1 Ú P
TIM_SMCR_ECE Ú P
TIM_SMCR_ETP íÚ P
TIM_DIER_UIE Ú P TIM_DIER_CC1IE Ú P TIM_DIER_CC2IE Ú P TIM_DIER_CC3IE Ú P TIM_DIER_CC4IE Ú P TIM_DIER_COMIE vÚ P
TIM_DIER_TIE Ú P
TIM_DIER_BIE Ú P
TIM_DIER_UDE Ú P TIM_DIER_CC1DE £Ú P TIM_DIER_CC2DE ¢Ú P TIM_DIER_CC3DE ¡Ú P TIM_DIER_CC4DE Ú P TIM_DIER_COMDE {Ú P
TIM_DIER_TDE
Ú P TIM_SR_UIF Ú P
TIM_SR_CC1IF Ú P
TIM_SR_CC2IF Ú P
TIM_SR_CC3IF Ú P
TIM_SR_CC4IF Ú P
TIM_SR_COMIF øÚ P TIM_SR_TIF Ú P TIM_SR_BIF Ú P
TIM_SR_CC1OF Ú P
TIM_SR_CC2OF Ú P
TIM_SR_CC3OF Ú P
TIM_SR_CC4OF Ú P TIM_EGR_UG Ú P
TIM_EGR_CC1G /Ú P
TIM_EGR_CC2G .Ú P
TIM_EGR_CC3G -Ú P
TIM_EGR_CC4G ,Ú P
TIM_EGR_COMG Ú P TIM_EGR_TG Ú P TIM_EGR_BG ¨Ú P TIM_CCMR1_CC1S §Ú P TIM_CCMR1_CC1S_0 Ú P TIM_CCMR1_CC1S_1 Ú P TIM_CCMR1_OC1FE aÚ P TIM_CCMR1_OC1PE WÚ P TIM_CCMR1_OC1M ¡Ú P TIM_CCMR1_OC1M_0 Ú P TIM_CCMR1_OC1M_1
Ú P TIM_CCMR1_OC1M_2 Ú P TIM_CCMR1_OC1CE dÚ P TIM_CCMR1_CC2S ¦Ú P TIM_CCMR1_CC2S_0 Ú P TIM_CCMR1_CC2S_1 Ú P TIM_CCMR1_OC2FE `Ú P TIM_CCMR1_OC2PE VÚ P TIM_CCMR1_OC2M Ú P TIM_CCMR1_OC2M_0
Ú P TIM_CCMR1_OC2M_1 Ú P TIM_CCMR1_OC2M_2 Ú P TIM_CCMR1_OC2CE cÚ P TIM_CCMR1_IC1PSC
Ú P TIM_CCMR1_IC1PSC_0 wÚ P TIM_CCMR1_IC1PSC_1 vÚ P TIM_CCMR1_IC1F ®Ú P TIM_CCMR1_IC1F_0 Ú P TIM_CCMR1_IC1F_1 Ú P TIM_CCMR1_IC1F_2 Ú P TIM_CCMR1_IC1F_3 Ú P TIM_CCMR1_IC2PSC Ú P TIM_CCMR1_IC2PSC_0 vÚ P TIM_CCMR1_IC2PSC_1 uÚ P TIM_CCMR1_IC2F Ú P TIM_CCMR1_IC2F_0 Ú P TIM_CCMR1_IC2F_1 Ú P TIM_CCMR1_IC2F_2 Ú P TIM_CCMR1_IC2F_3 Ú P TIM_CCMR2_CC3S ¤Ú P TIM_CCMR2_CC3S_0 Ú P TIM_CCMR2_CC3S_1 Ú P TIM_CCMR2_OC3FE ^Ú P TIM_CCMR2_OC3PE TÚ P TIM_CCMR2_OC3M Ú P TIM_CCMR2_OC3M_0 Ú P TIM_CCMR2_OC3M_1
Ú P TIM_CCMR2_OC3M_2 Ú P TIM_CCMR2_OC3CE aÚ P TIM_CCMR2_CC4S £Ú P TIM_CCMR2_CC4S_0 Ú P TIM_CCMR2_CC4S_1 Ú P TIM_CCMR2_OC4FE ]Ú P TIM_CCMR2_OC4PE SÚ P TIM_CCMR2_OC4M Ú P TIM_CCMR2_OC4M_0
Ú P TIM_CCMR2_OC4M_1 Ú P TIM_CCMR2_OC4M_2 Ú P TIM_CCMR2_OC4CE `Ú P TIM_CCMR2_IC3PSC Ú P TIM_CCMR2_IC3PSC_0 tÚ P TIM_CCMR2_IC3PSC_1 sÚ P TIM_CCMR2_IC3F «Ú P TIM_CCMR2_IC3F_0 Ú P TIM_CCMR2_IC3F_1 Ú P TIM_CCMR2_IC3F_2 Ú P TIM_CCMR2_IC3F_3 Ú P TIM_CCMR2_IC4PSC Ú P TIM_CCMR2_IC4PSC_0 sÚ P TIM_CCMR2_IC4PSC_1 rÚ P TIM_CCMR2_IC4F ªÚ P TIM_CCMR2_IC4F_0 Ú P TIM_CCMR2_IC4F_1 Ú P TIM_CCMR2_IC4F_2 Ú P TIM_CCMR2_IC4F_3 Ú P TIM_CCER_CC1E ðÚ P TIM_CCER_CC1P åÚ P TIM_CCER_CC1NE Ú P TIM_CCER_CC1NP Ú P TIM_CCER_CC2E ïÚ P TIM_CCER_CC2P äÚ P TIM_CCER_CC2NE Ú P TIM_CCER_CC2NP Ú P TIM_CCER_CC3E îÚ P TIM_CCER_CC3P ãÚ P TIM_CCER_CC3NE Ú P TIM_CCER_CC3NP Ú P TIM_CCER_CC4E íÚ P TIM_CCER_CC4P âÚ P TIM_CCER_CC4NP Ú P TIM_CNT_CNT CÚ P TIM_PSC_PSC AÚ P TIM_ARR_ARR CÚ P TIM_RCR_REP ?Ú P TIM_CCR1_CCR1 ÷Ú P TIM_CCR2_CCR2 õÚ P TIM_CCR3_CCR3 óÚ P TIM_CCR4_CCR4 ñÚ P
TIM_BDTR_DTG Ú P TIM_BDTR_DTG_0 mÚ P TIM_BDTR_DTG_1 lÚ P TIM_BDTR_DTG_2 kÚ P TIM_BDTR_DTG_3 jÚ P TIM_BDTR_DTG_4 iÚ P TIM_BDTR_DTG_5 hÚ P TIM_BDTR_DTG_6 gÚ P TIM_BDTR_DTG_7 fÚ P TIM_BDTR_LOCK ´Ú P TIM_BDTR_LOCK_0 !Ú P TIM_BDTR_LOCK_1 Ú P TIM_BDTR_OSSI Ú P TIM_BDTR_OSSR Ú P
TIM_BDTR_BKE
Ú P
TIM_BDTR_BKP Ú P
TIM_BDTR_AOE
Ú P
TIM_BDTR_MOE þÚ P TIM_DCR_DBA mÚ P TIM_DCR_DBA_0 ÚÚ P TIM_DCR_DBA_1 ÙÚ P TIM_DCR_DBA_2 ØÚ P TIM_DCR_DBA_3 ×Ú P TIM_DCR_DBA_4 ÖÚ P TIM_DCR_DBL bÚ P TIM_DCR_DBL_0 ÏÚ P TIM_DCR_DBL_1 ÎÚ P TIM_DCR_DBL_2 ÍÚ P TIM_DCR_DBL_3 ÌÚ P TIM_DCR_DBL_4 ËÚ P TIM_DMAR_DMAB ÑÚ P RTC_CRH_SECIE ÄÚ P RTC_CRH_ALRIE ÀÚ P
RTC_CRH_OWIE ûÚ P
RTC_CRL_SECF
Ú P
RTC_CRL_ALRF Ú P RTC_CRL_OWF AÚ P RTC_CRL_RSF BÚ P RTC_CRL_CNF VÚ P RTC_CRL_RTOFF ¨Ú P
RTC_PRLH_PRL èÚ P
RTC_PRLL_PRL äÚ P RTC_DIVH_RTC_DIV ®Ú P RTC_DIVL_RTC_DIV ªÚ P RTC_CNTH_RTC_CNT ªÚ P RTC_CNTL_RTC_CNT ¦Ú P RTC_ALRH_RTC_ALR ¶Ú P RTC_ALRL_RTC_ALR ²Ú P IWDG_KR_KEY FÚ P IWDG_PR_PR Ú P
IWDG_PR_PR_0 ÷Ú P
IWDG_PR_PR_1 öÚ P
IWDG_PR_PR_2 õÚ P IWDG_RLR_RL >Ú P IWDG_SR_PVU ,Ú P IWDG_SR_RVU *Ú P
WWDG_CR_T ÙÚ P WWDG_CR_T0 §Ú P WWDG_CR_T1 ¦Ú P WWDG_CR_T2 ¥Ú P WWDG_CR_T3 ¤Ú P WWDG_CR_T4 £Ú P WWDG_CR_T5 ¢Ú P WWDG_CR_T6 ¡Ú P
WWDG_CR_WDGA Ú P WWDG_CFR_W Ú P WWDG_CFR_W0 \Ú P WWDG_CFR_W1 [Ú P WWDG_CFR_W2 ZÚ P WWDG_CFR_W3 YÚ P WWDG_CFR_W4 XÚ P WWDG_CFR_W5 WÚ P WWDG_CFR_W6 VÚ P WWDG_CFR_WDGTB eÚ P WWDG_CFR_WDGTB0 3Ú P WWDG_CFR_WDGTB1 2Ú P
WWDG_CFR_EWI üÚ P
WWDG_SR_EWIF ìÚ P FSMC_BCR1_MBKEN QÚ P FSMC_BCR1_MUXEN 1Ú P FSMC_BCR1_MTYP vÚ P FSMC_BCR1_MTYP_0 ãÚ P FSMC_BCR1_MTYP_1 âÚ P FSMC_BCR1_MWID Ú P FSMC_BCR1_MWID_0 üÚ P FSMC_BCR1_MWID_1 ûÚ P FSMC_BCR1_FACCEN Ú P FSMC_BCR1_BURSTEN Ú P FSMC_BCR1_WAITPOL Ú P FSMC_BCR1_WRAPMOD Ú P FSMC_BCR1_WAITCFG µÚ P FSMC_BCR1_WREN Ú P FSMC_BCR1_WAITEN ôÚ P FSMC_BCR1_EXTMOD ëÚ P FSMC_BCR1_ASYNCWAIT Ú P FSMC_BCR1_CBURSTRW <Ú P FSMC_BCR2_MBKEN PÚ P FSMC_BCR2_MUXEN 0Ú P FSMC_BCR2_MTYP uÚ P FSMC_BCR2_MTYP_0 âÚ P FSMC_BCR2_MTYP_1 áÚ P FSMC_BCR2_MWID Ú P FSMC_BCR2_MWID_0 ûÚ P FSMC_BCR2_MWID_1 úÚ P FSMC_BCR2_FACCEN Ú P FSMC_BCR2_BURSTEN Ú P FSMC_BCR2_WAITPOL Ú P FSMC_BCR2_WRAPMOD Ú P FSMC_BCR2_WAITCFG ´Ú P FSMC_BCR2_WREN Ú P FSMC_BCR2_WAITEN óÚ P FSMC_BCR2_EXTMOD êÚ P FSMC_BCR2_ASYNCWAIT Ú P FSMC_BCR2_CBURSTRW ;Ú P FSMC_BCR3_MBKEN OÚ P FSMC_BCR3_MUXEN /Ú P FSMC_BCR3_MTYP tÚ P FSMC_BCR3_MTYP_0 áÚ P FSMC_BCR3_MTYP_1 àÚ P FSMC_BCR3_MWID Ú P FSMC_BCR3_MWID_0 úÚ P FSMC_BCR3_MWID_1 ùÚ P FSMC_BCR3_FACCEN Ú P FSMC_BCR3_BURSTEN Ú P FSMC_BCR3_WAITPOL Ú P FSMC_BCR3_WRAPMOD Ú P FSMC_BCR3_WAITCFG ³Ú P FSMC_BCR3_WREN Ú P FSMC_BCR3_WAITEN òÚ P FSMC_BCR3_EXTMOD éÚ P FSMC_BCR3_ASYNCWAIT Ú P FSMC_BCR3_CBURSTRW :Ú P FSMC_BCR4_MBKEN NÚ P FSMC_BCR4_MUXEN .Ú P FSMC_BCR4_MTYP sÚ P FSMC_BCR4_MTYP_0 àÚ P FSMC_BCR4_MTYP_1 ßÚ P FSMC_BCR4_MWID Ú P FSMC_BCR4_MWID_0 ùÚ P FSMC_BCR4_MWID_1 øÚ P FSMC_BCR4_FACCEN Ú P FSMC_BCR4_BURSTEN Ú P FSMC_BCR4_WAITPOL Ú P FSMC_BCR4_WRAPMOD Ú P FSMC_BCR4_WAITCFG ²Ú P FSMC_BCR4_WREN Ú P FSMC_BCR4_WAITEN ñÚ P FSMC_BCR4_EXTMOD èÚ P FSMC_BCR4_ASYNCWAIT Ú P FSMC_BCR4_CBURSTRW 9Ú P FSMC_BTR1_ADDSET öÚ P FSMC_BTR1_ADDSET_0 cÚ P FSMC_BTR1_ADDSET_1 bÚ P FSMC_BTR1_ADDSET_2 aÚ P FSMC_BTR1_ADDSET_3 `Ú P FSMC_BTR1_ADDHLD
Ú P FSMC_BTR1_ADDHLD_0 wÚ P FSMC_BTR1_ADDHLD_1 vÚ P FSMC_BTR1_ADDHLD_2 uÚ P FSMC_BTR1_ADDHLD_3 tÚ P FSMC_BTR1_DATAST êÚ P FSMC_BTR1_DATAST_0 WÚ P FSMC_BTR1_DATAST_1 VÚ P FSMC_BTR1_DATAST_2 UÚ P FSMC_BTR1_DATAST_3 TÚ P FSMC_BTR1_BUSTURN vÚ P FSMC_BTR1_BUSTURN_0 ãÚ P FSMC_BTR1_BUSTURN_1 âÚ P FSMC_BTR1_BUSTURN_2 áÚ P FSMC_BTR1_BUSTURN_3 àÚ P FSMC_BTR1_CLKDIV îÚ P FSMC_BTR1_CLKDIV_0 [Ú P FSMC_BTR1_CLKDIV_1 ZÚ P FSMC_BTR1_CLKDIV_2 YÚ P FSMC_BTR1_CLKDIV_3 XÚ P FSMC_BTR1_DATLAT ñÚ P FSMC_BTR1_DATLAT_0 ^Ú P FSMC_BTR1_DATLAT_1 ]Ú P FSMC_BTR1_DATLAT_2 \Ú P FSMC_BTR1_DATLAT_3 [Ú P FSMC_BTR1_ACCMOD Ú P FSMC_BTR1_ACCMOD_0 qÚ P FSMC_BTR1_ACCMOD_1 pÚ P FSMC_BTR2_ADDSET õÚ P FSMC_BTR2_ADDSET_0 bÚ P FSMC_BTR2_ADDSET_1 aÚ P FSMC_BTR2_ADDSET_2 `Ú P FSMC_BTR2_ADDSET_3 _Ú P FSMC_BTR2_ADDHLD Ú P FSMC_BTR2_ADDHLD_0 vÚ P FSMC_BTR2_ADDHLD_1 uÚ P FSMC_BTR2_ADDHLD_2 tÚ P FSMC_BTR2_ADDHLD_3 sÚ P FSMC_BTR2_DATAST éÚ P FSMC_BTR2_DATAST_0 VÚ P FSMC_BTR2_DATAST_1 UÚ P FSMC_BTR2_DATAST_2 TÚ P FSMC_BTR2_DATAST_3 SÚ P FSMC_BTR2_BUSTURN uÚ P FSMC_BTR2_BUSTURN_0 âÚ P FSMC_BTR2_BUSTURN_1 áÚ P FSMC_BTR2_BUSTURN_2 àÚ P FSMC_BTR2_BUSTURN_3 ßÚ P FSMC_BTR2_CLKDIV íÚ P FSMC_BTR2_CLKDIV_0 ZÚ P FSMC_BTR2_CLKDIV_1 YÚ P FSMC_BTR2_CLKDIV_2 XÚ P FSMC_BTR2_CLKDIV_3 WÚ P FSMC_BTR2_DATLAT ðÚ P FSMC_BTR2_DATLAT_0 ]Ú P FSMC_BTR2_DATLAT_1 \Ú P FSMC_BTR2_DATLAT_2 [Ú P FSMC_BTR2_DATLAT_3 ZÚ P FSMC_BTR2_ACCMOD Ú P FSMC_BTR2_ACCMOD_0 pÚ P FSMC_BTR2_ACCMOD_1 oÚ P FSMC_BTR3_ADDSET ôÚ P FSMC_BTR3_ADDSET_0 aÚ P FSMC_BTR3_ADDSET_1 `Ú P FSMC_BTR3_ADDSET_2 _Ú P FSMC_BTR3_ADDSET_3 ^Ú P FSMC_BTR3_ADDHLD Ú P FSMC_BTR3_ADDHLD_0 uÚ P FSMC_BTR3_ADDHLD_1 tÚ P FSMC_BTR3_ADDHLD_2 sÚ P FSMC_BTR3_ADDHLD_3 rÚ P FSMC_BTR3_DATAST èÚ P FSMC_BTR3_DATAST_0 UÚ P FSMC_BTR3_DATAST_1 TÚ P FSMC_BTR3_DATAST_2 SÚ P FSMC_BTR3_DATAST_3 RÚ P FSMC_BTR3_BUSTURN tÚ P FSMC_BTR3_BUSTURN_0 áÚ P FSMC_BTR3_BUSTURN_1 àÚ P FSMC_BTR3_BUSTURN_2 ßÚ P FSMC_BTR3_BUSTURN_3 ÞÚ P FSMC_BTR3_CLKDIV ìÚ P FSMC_BTR3_CLKDIV_0 YÚ P FSMC_BTR3_CLKDIV_1 XÚ P FSMC_BTR3_CLKDIV_2 WÚ P FSMC_BTR3_CLKDIV_3 VÚ P FSMC_BTR3_DATLAT ïÚ P FSMC_BTR3_DATLAT_0 \Ú P FSMC_BTR3_DATLAT_1 [Ú P FSMC_BTR3_DATLAT_2 ZÚ P FSMC_BTR3_DATLAT_3 YÚ P FSMC_BTR3_ACCMOD Ú P FSMC_BTR3_ACCMOD_0 oÚ P FSMC_BTR3_ACCMOD_1 nÚ P FSMC_BTR4_ADDSET óÚ P FSMC_BTR4_ADDSET_0 `Ú P FSMC_BTR4_ADDSET_1 _Ú P FSMC_BTR4_ADDSET_2 ^Ú P FSMC_BTR4_ADDSET_3 ]Ú P FSMC_BTR4_ADDHLD Ú P FSMC_BTR4_ADDHLD_0 tÚ P FSMC_BTR4_ADDHLD_1 sÚ P FSMC_BTR4_ADDHLD_2 rÚ P FSMC_BTR4_ADDHLD_3 qÚ P FSMC_BTR4_DATAST çÚ P FSMC_BTR4_DATAST_0 TÚ P FSMC_BTR4_DATAST_1 SÚ P FSMC_BTR4_DATAST_2 RÚ P FSMC_BTR4_DATAST_3 QÚ P FSMC_BTR4_BUSTURN sÚ P FSMC_BTR4_BUSTURN_0 àÚ P FSMC_BTR4_BUSTURN_1 ßÚ P FSMC_BTR4_BUSTURN_2 ÞÚ P FSMC_BTR4_BUSTURN_3 ÝÚ P FSMC_BTR4_CLKDIV ëÚ P FSMC_BTR4_CLKDIV_0 XÚ P FSMC_BTR4_CLKDIV_1 WÚ P FSMC_BTR4_CLKDIV_2 VÚ P FSMC_BTR4_CLKDIV_3 UÚ P FSMC_BTR4_DATLAT îÚ P FSMC_BTR4_DATLAT_0 [Ú P FSMC_BTR4_DATLAT_1 ZÚ P FSMC_BTR4_DATLAT_2 YÚ P FSMC_BTR4_DATLAT_3 XÚ P FSMC_BTR4_ACCMOD Ú P FSMC_BTR4_ACCMOD_0 nÚ P FSMC_BTR4_ACCMOD_1 mÚ P FSMC_BWTR1_ADDSET Ú P FSMC_BWTR1_ADDSET_0
Ú P FSMC_BWTR1_ADDSET_1 Ú P FSMC_BWTR1_ADDSET_2 Ú P FSMC_BWTR1_ADDSET_3 Ú P FSMC_BWTR1_ADDHLD ±Ú P FSMC_BWTR1_ADDHLD_0 Ú P FSMC_BWTR1_ADDHLD_1 Ú P FSMC_BWTR1_ADDHLD_2 Ú P FSMC_BWTR1_ADDHLD_3 Ú P FSMC_BWTR1_DATAST Ú P FSMC_BWTR1_DATAST_0 þÚ P FSMC_BWTR1_DATAST_1 ýÚ P FSMC_BWTR1_DATAST_2 üÚ P FSMC_BWTR1_DATAST_3 ûÚ P FSMC_BWTR1_CLKDIV Ú P FSMC_BWTR1_CLKDIV_0 Ú P FSMC_BWTR1_CLKDIV_1 Ú P FSMC_BWTR1_CLKDIV_2 Ú P FSMC_BWTR1_CLKDIV_3 ÿÚ P FSMC_BWTR1_DATLAT Ú P FSMC_BWTR1_DATLAT_0 Ú P FSMC_BWTR1_DATLAT_1 Ú P FSMC_BWTR1_DATLAT_2 Ú P FSMC_BWTR1_DATLAT_3 Ú P FSMC_BWTR1_ACCMOD «Ú P FSMC_BWTR1_ACCMOD_0 Ú P FSMC_BWTR1_ACCMOD_1 Ú P FSMC_BWTR2_ADDSET Ú P FSMC_BWTR2_ADDSET_0 Ú P FSMC_BWTR2_ADDSET_1 Ú P FSMC_BWTR2_ADDSET_2 Ú P FSMC_BWTR2_ADDSET_3 Ú P FSMC_BWTR2_ADDHLD °Ú P FSMC_BWTR2_ADDHLD_0 Ú P FSMC_BWTR2_ADDHLD_1 Ú P FSMC_BWTR2_ADDHLD_2 Ú P FSMC_BWTR2_ADDHLD_3 Ú P FSMC_BWTR2_DATAST Ú P FSMC_BWTR2_DATAST_0 ýÚ P FSMC_BWTR2_DATAST_1 üÚ P FSMC_BWTR2_DATAST_2 ûÚ P FSMC_BWTR2_DATAST_3 úÚ P FSMC_BWTR2_CLKDIV Ú P FSMC_BWTR2_CLKDIV_0 Ú P FSMC_BWTR2_CLKDIV_1 Ú P FSMC_BWTR2_CLKDIV_2 ÿÚ P FSMC_BWTR2_CLKDIV_3 þÚ P FSMC_BWTR2_DATLAT Ú P FSMC_BWTR2_DATLAT_0 Ú P FSMC_BWTR2_DATLAT_1 Ú P FSMC_BWTR2_DATLAT_2 Ú P FSMC_BWTR2_DATLAT_3 Ú P FSMC_BWTR2_ACCMOD ªÚ P FSMC_BWTR2_ACCMOD_0 Ú P FSMC_BWTR2_ACCMOD_1 Ú P FSMC_BWTR3_ADDSET Ú P FSMC_BWTR3_ADDSET_0 Ú P FSMC_BWTR3_ADDSET_1 Ú P FSMC_BWTR3_ADDSET_2 Ú P FSMC_BWTR3_ADDSET_3 Ú P FSMC_BWTR3_ADDHLD ¯Ú P FSMC_BWTR3_ADDHLD_0 Ú P FSMC_BWTR3_ADDHLD_1 Ú P FSMC_BWTR3_ADDHLD_2 Ú P FSMC_BWTR3_ADDHLD_3 Ú P FSMC_BWTR3_DATAST Ú P FSMC_BWTR3_DATAST_0 üÚ P FSMC_BWTR3_DATAST_1 ûÚ P FSMC_BWTR3_DATAST_2 úÚ P FSMC_BWTR3_DATAST_3 ùÚ P FSMC_BWTR3_CLKDIV Ú P FSMC_BWTR3_CLKDIV_0 Ú P FSMC_BWTR3_CLKDIV_1 ÿÚ P FSMC_BWTR3_CLKDIV_2 þÚ P FSMC_BWTR3_CLKDIV_3 ýÚ P FSMC_BWTR3_DATLAT Ú P FSMC_BWTR3_DATLAT_0 Ú P FSMC_BWTR3_DATLAT_1 Ú P FSMC_BWTR3_DATLAT_2 Ú P FSMC_BWTR3_DATLAT_3 Ú P FSMC_BWTR3_ACCMOD ©Ú P FSMC_BWTR3_ACCMOD_0 Ú P FSMC_BWTR3_ACCMOD_1 Ú P FSMC_BWTR4_ADDSET Ú P FSMC_BWTR4_ADDSET_0 Ú P FSMC_BWTR4_ADDSET_1 Ú P FSMC_BWTR4_ADDSET_2 Ú P FSMC_BWTR4_ADDSET_3 Ú P FSMC_BWTR4_ADDHLD ®Ú P FSMC_BWTR4_ADDHLD_0 Ú P FSMC_BWTR4_ADDHLD_1 Ú P FSMC_BWTR4_ADDHLD_2 Ú P FSMC_BWTR4_ADDHLD_3 Ú P FSMC_BWTR4_DATAST Ú P FSMC_BWTR4_DATAST_0 ûÚ P FSMC_BWTR4_DATAST_1 úÚ P FSMC_BWTR4_DATAST_2 ùÚ P FSMC_BWTR4_DATAST_3 øÚ P FSMC_BWTR4_CLKDIV Ú P FSMC_BWTR4_CLKDIV_0 ÿÚ P FSMC_BWTR4_CLKDIV_1 þÚ P FSMC_BWTR4_CLKDIV_2 ýÚ P FSMC_BWTR4_CLKDIV_3 üÚ P FSMC_BWTR4_DATLAT Ú P FSMC_BWTR4_DATLAT_0 Ú P FSMC_BWTR4_DATLAT_1 Ú P FSMC_BWTR4_DATLAT_2 Ú P FSMC_BWTR4_DATLAT_3 ÿÚ P FSMC_BWTR4_ACCMOD ¨Ú P FSMC_BWTR4_ACCMOD_0 Ú P FSMC_BWTR4_ACCMOD_1 Ú P FSMC_PCR2_PWAITEN Ú P FSMC_PCR2_PBKEN ?Ú P FSMC_PCR2_PTYP dÚ P FSMC_PCR2_PWID }Ú P FSMC_PCR2_PWID_0 êÚ P FSMC_PCR2_PWID_1 éÚ P FSMC_PCR2_ECCEN QÚ P FSMC_PCR2_TCLR |Ú P FSMC_PCR2_TCLR_0 éÚ P FSMC_PCR2_TCLR_1 èÚ P FSMC_PCR2_TCLR_2 çÚ P FSMC_PCR2_TCLR_3 æÚ P FSMC_PCR2_TAR ÌÚ P FSMC_PCR2_TAR_0 9Ú P FSMC_PCR2_TAR_1 8Ú P FSMC_PCR2_TAR_2 7Ú P FSMC_PCR2_TAR_3 6Ú P FSMC_PCR2_ECCPS AÚ P FSMC_PCR2_ECCPS_0 ®Ú P FSMC_PCR2_ECCPS_1 Ú P FSMC_PCR2_ECCPS_2 ¬Ú P FSMC_PCR3_PWAITEN Ú P FSMC_PCR3_PBKEN >Ú P FSMC_PCR3_PTYP cÚ P FSMC_PCR3_PWID |Ú P FSMC_PCR3_PWID_0 éÚ P FSMC_PCR3_PWID_1 èÚ P FSMC_PCR3_ECCEN PÚ P FSMC_PCR3_TCLR {Ú P FSMC_PCR3_TCLR_0 èÚ P FSMC_PCR3_TCLR_1 çÚ P FSMC_PCR3_TCLR_2 æÚ P FSMC_PCR3_TCLR_3 åÚ P FSMC_PCR3_TAR ËÚ P FSMC_PCR3_TAR_0 8Ú P FSMC_PCR3_TAR_1 7Ú P FSMC_PCR3_TAR_2 6Ú P FSMC_PCR3_TAR_3 5Ú P FSMC_PCR3_ECCPS @Ú P FSMC_PCR3_ECCPS_0 Ú P FSMC_PCR3_ECCPS_1 ¬Ú P FSMC_PCR3_ECCPS_2 «Ú P FSMC_PCR4_PWAITEN Ú P FSMC_PCR4_PBKEN =Ú P FSMC_PCR4_PTYP bÚ P FSMC_PCR4_PWID {Ú P FSMC_PCR4_PWID_0 èÚ P FSMC_PCR4_PWID_1 çÚ P FSMC_PCR4_ECCEN OÚ P FSMC_PCR4_TCLR zÚ P FSMC_PCR4_TCLR_0 çÚ P FSMC_PCR4_TCLR_1 æÚ P FSMC_PCR4_TCLR_2 åÚ P FSMC_PCR4_TCLR_3 äÚ P FSMC_PCR4_TAR ÊÚ P FSMC_PCR4_TAR_0 7Ú P FSMC_PCR4_TAR_1 6Ú P FSMC_PCR4_TAR_2 5Ú P FSMC_PCR4_TAR_3 4Ú P FSMC_PCR4_ECCPS ?Ú P FSMC_PCR4_ECCPS_0 ¬Ú P FSMC_PCR4_ECCPS_1 «Ú P FSMC_PCR4_ECCPS_2 ªÚ P
FSMC_SR2_IRS Ú P
FSMC_SR2_ILS
Ú P
FSMC_SR2_IFS Ú P FSMC_SR2_IREN ÅÚ P FSMC_SR2_ILEN ËÚ P FSMC_SR2_IFEN ÑÚ P FSMC_SR2_FEMPT uÚ P
FSMC_SR3_IRS Ú P
FSMC_SR3_ILS Ú P
FSMC_SR3_IFS Ú P FSMC_SR3_IREN ÄÚ P FSMC_SR3_ILEN ÊÚ P FSMC_SR3_IFEN ÐÚ P FSMC_SR3_FEMPT tÚ P
FSMC_SR4_IRS Ú P
FSMC_SR4_ILS Ú P
FSMC_SR4_IFS Ú P FSMC_SR4_IREN ÃÚ P FSMC_SR4_ILEN ÉÚ P FSMC_SR4_IFEN ÏÚ P FSMC_SR4_FEMPT sÚ P FSMC_PMEM2_MEMSET2 bÚ P FSMC_PMEM2_MEMSET2_0 ÏÚ P FSMC_PMEM2_MEMSET2_1 ÎÚ P FSMC_PMEM2_MEMSET2_2 ÍÚ P FSMC_PMEM2_MEMSET2_3 ÌÚ P FSMC_PMEM2_MEMSET2_4 ËÚ P FSMC_PMEM2_MEMSET2_5 ÊÚ P FSMC_PMEM2_MEMSET2_6 ÉÚ P FSMC_PMEM2_MEMSET2_7 ÈÚ P FSMC_PMEM2_MEMWAIT2 Ú P FSMC_PMEM2_MEMWAIT2_0 Ú P FSMC_PMEM2_MEMWAIT2_1 Ú P FSMC_PMEM2_MEMWAIT2_2 Ú P FSMC_PMEM2_MEMWAIT2_3 Ú P FSMC_PMEM2_MEMWAIT2_4 Ú P FSMC_PMEM2_MEMWAIT2_5 Ú P FSMC_PMEM2_MEMWAIT2_6 ~Ú P FSMC_PMEM2_MEMWAIT2_7 }Ú P FSMC_PMEM2_MEMHOLD2 %Ú P FSMC_PMEM2_MEMHOLD2_0 Ú P FSMC_PMEM2_MEMHOLD2_1 Ú P FSMC_PMEM2_MEMHOLD2_2 Ú P FSMC_PMEM2_MEMHOLD2_3 Ú P FSMC_PMEM2_MEMHOLD2_4 Ú P FSMC_PMEM2_MEMHOLD2_5 Ú P FSMC_PMEM2_MEMHOLD2_6 Ú P FSMC_PMEM2_MEMHOLD2_7 Ú P FSMC_PMEM2_MEMHIZ2 cÚ P FSMC_PMEM2_MEMHIZ2_0 ÐÚ P FSMC_PMEM2_MEMHIZ2_1 ÏÚ P FSMC_PMEM2_MEMHIZ2_2 ÎÚ P FSMC_PMEM2_MEMHIZ2_3 ÍÚ P FSMC_PMEM2_MEMHIZ2_4 ÌÚ P FSMC_PMEM2_MEMHIZ2_5 ËÚ P FSMC_PMEM2_MEMHIZ2_6 ÊÚ P FSMC_PMEM2_MEMHIZ2_7 ÉÚ P FSMC_PMEM3_MEMSET3 `Ú P FSMC_PMEM3_MEMSET3_0 ÍÚ P FSMC_PMEM3_MEMSET3_1 ÌÚ P FSMC_PMEM3_MEMSET3_2 ËÚ P FSMC_PMEM3_MEMSET3_3 ÊÚ P FSMC_PMEM3_MEMSET3_4 ÉÚ P FSMC_PMEM3_MEMSET3_5 ÈÚ P FSMC_PMEM3_MEMSET3_6 ÇÚ P FSMC_PMEM3_MEMSET3_7 ÆÚ P FSMC_PMEM3_MEMWAIT3 Ú P FSMC_PMEM3_MEMWAIT3_0 Ú P FSMC_PMEM3_MEMWAIT3_1 Ú P FSMC_PMEM3_MEMWAIT3_2 Ú P FSMC_PMEM3_MEMWAIT3_3 Ú P FSMC_PMEM3_MEMWAIT3_4 ~Ú P FSMC_PMEM3_MEMWAIT3_5 }Ú P FSMC_PMEM3_MEMWAIT3_6 |Ú P FSMC_PMEM3_MEMWAIT3_7 {Ú P FSMC_PMEM3_MEMHOLD3 #Ú P FSMC_PMEM3_MEMHOLD3_0 Ú P FSMC_PMEM3_MEMHOLD3_1 Ú P FSMC_PMEM3_MEMHOLD3_2 Ú P FSMC_PMEM3_MEMHOLD3_3 Ú P FSMC_PMEM3_MEMHOLD3_4 Ú P FSMC_PMEM3_MEMHOLD3_5 Ú P FSMC_PMEM3_MEMHOLD3_6 Ú P FSMC_PMEM3_MEMHOLD3_7 Ú P FSMC_PMEM3_MEMHIZ3 aÚ P FSMC_PMEM3_MEMHIZ3_0 ÎÚ P FSMC_PMEM3_MEMHIZ3_1 ÍÚ P FSMC_PMEM3_MEMHIZ3_2 ÌÚ P FSMC_PMEM3_MEMHIZ3_3 ËÚ P FSMC_PMEM3_MEMHIZ3_4 ÊÚ P FSMC_PMEM3_MEMHIZ3_5 ÉÚ P FSMC_PMEM3_MEMHIZ3_6 ÈÚ P FSMC_PMEM3_MEMHIZ3_7 ÇÚ P FSMC_PMEM4_MEMSET4 ^Ú P FSMC_PMEM4_MEMSET4_0 ËÚ P FSMC_PMEM4_MEMSET4_1 ÊÚ P FSMC_PMEM4_MEMSET4_2 ÉÚ P FSMC_PMEM4_MEMSET4_3 ÈÚ P FSMC_PMEM4_MEMSET4_4 ÇÚ P FSMC_PMEM4_MEMSET4_5 ÆÚ P FSMC_PMEM4_MEMSET4_6 ÅÚ P FSMC_PMEM4_MEMSET4_7 ÄÚ P FSMC_PMEM4_MEMWAIT4 Ú P FSMC_PMEM4_MEMWAIT4_0 Ú P FSMC_PMEM4_MEMWAIT4_1 Ú P FSMC_PMEM4_MEMWAIT4_2 ~Ú P FSMC_PMEM4_MEMWAIT4_3 }Ú P FSMC_PMEM4_MEMWAIT4_4 |Ú P FSMC_PMEM4_MEMWAIT4_5 {Ú P FSMC_PMEM4_MEMWAIT4_6 zÚ P FSMC_PMEM4_MEMWAIT4_7 yÚ P FSMC_PMEM4_MEMHOLD4 !Ú P FSMC_PMEM4_MEMHOLD4_0 Ú P FSMC_PMEM4_MEMHOLD4_1 Ú P FSMC_PMEM4_MEMHOLD4_2 Ú P FSMC_PMEM4_MEMHOLD4_3 Ú P FSMC_PMEM4_MEMHOLD4_4 Ú P FSMC_PMEM4_MEMHOLD4_5 Ú P FSMC_PMEM4_MEMHOLD4_6 Ú P FSMC_PMEM4_MEMHOLD4_7 Ú P FSMC_PMEM4_MEMHIZ4 _Ú P FSMC_PMEM4_MEMHIZ4_0 ÌÚ P FSMC_PMEM4_MEMHIZ4_1 ËÚ P FSMC_PMEM4_MEMHIZ4_2 ÊÚ P FSMC_PMEM4_MEMHIZ4_3 ÉÚ P FSMC_PMEM4_MEMHIZ4_4 ÈÚ P FSMC_PMEM4_MEMHIZ4_5 ÇÚ P FSMC_PMEM4_MEMHIZ4_6 ÆÚ P FSMC_PMEM4_MEMHIZ4_7 ÅÚ P FSMC_PATT2_ATTSET2 NÚ P FSMC_PATT2_ATTSET2_0 »Ú P FSMC_PATT2_ATTSET2_1 ºÚ P FSMC_PATT2_ATTSET2_2 ¹Ú P FSMC_PATT2_ATTSET2_3 ¸Ú P FSMC_PATT2_ATTSET2_4 ·Ú P FSMC_PATT2_ATTSET2_5 ¶Ú P FSMC_PATT2_ATTSET2_6 µÚ P FSMC_PATT2_ATTSET2_7 ´Ú P FSMC_PATT2_ATTWAIT2 Ú P FSMC_PATT2_ATTWAIT2_0 pÚ P FSMC_PATT2_ATTWAIT2_1 oÚ P FSMC_PATT2_ATTWAIT2_2 nÚ P FSMC_PATT2_ATTWAIT2_3 mÚ P FSMC_PATT2_ATTWAIT2_4 lÚ P FSMC_PATT2_ATTWAIT2_5 kÚ P FSMC_PATT2_ATTWAIT2_6 jÚ P FSMC_PATT2_ATTWAIT2_7 iÚ P FSMC_PATT2_ATTHOLD2 Ú P FSMC_PATT2_ATTHOLD2_0 ~Ú P FSMC_PATT2_ATTHOLD2_1 }Ú P FSMC_PATT2_ATTHOLD2_2 |Ú P FSMC_PATT2_ATTHOLD2_3 {Ú P FSMC_PATT2_ATTHOLD2_4 zÚ P FSMC_PATT2_ATTHOLD2_5 yÚ P FSMC_PATT2_ATTHOLD2_6 xÚ P FSMC_PATT2_ATTHOLD2_7 wÚ P FSMC_PATT2_ATTHIZ2 OÚ P FSMC_PATT2_ATTHIZ2_0 ¼Ú P FSMC_PATT2_ATTHIZ2_1 »Ú P FSMC_PATT2_ATTHIZ2_2 ºÚ P FSMC_PATT2_ATTHIZ2_3 ¹Ú P FSMC_PATT2_ATTHIZ2_4 ¸Ú P FSMC_PATT2_ATTHIZ2_5 ·Ú P FSMC_PATT2_ATTHIZ2_6 ¶Ú P FSMC_PATT2_ATTHIZ2_7 µÚ P FSMC_PATT3_ATTSET3 LÚ P FSMC_PATT3_ATTSET3_0 ¹Ú P FSMC_PATT3_ATTSET3_1 ¸Ú P FSMC_PATT3_ATTSET3_2 ·Ú P FSMC_PATT3_ATTSET3_3 ¶Ú P FSMC_PATT3_ATTSET3_4 µÚ P FSMC_PATT3_ATTSET3_5 ´Ú P FSMC_PATT3_ATTSET3_6 ³Ú P FSMC_PATT3_ATTSET3_7 ²Ú P FSMC_PATT3_ATTWAIT3 Ú P FSMC_PATT3_ATTWAIT3_0 nÚ P FSMC_PATT3_ATTWAIT3_1 mÚ P FSMC_PATT3_ATTWAIT3_2 lÚ P FSMC_PATT3_ATTWAIT3_3 kÚ P FSMC_PATT3_ATTWAIT3_4 jÚ P FSMC_PATT3_ATTWAIT3_5 iÚ P FSMC_PATT3_ATTWAIT3_6 hÚ P FSMC_PATT3_ATTWAIT3_7 gÚ P FSMC_PATT3_ATTHOLD3 Ú P FSMC_PATT3_ATTHOLD3_0 |Ú P FSMC_PATT3_ATTHOLD3_1 {Ú P FSMC_PATT3_ATTHOLD3_2 zÚ P FSMC_PATT3_ATTHOLD3_3 yÚ P FSMC_PATT3_ATTHOLD3_4 xÚ P FSMC_PATT3_ATTHOLD3_5 wÚ P FSMC_PATT3_ATTHOLD3_6 vÚ P FSMC_PATT3_ATTHOLD3_7 uÚ P FSMC_PATT3_ATTHIZ3 MÚ P FSMC_PATT3_ATTHIZ3_0 ºÚ P FSMC_PATT3_ATTHIZ3_1 ¹Ú P FSMC_PATT3_ATTHIZ3_2 ¸Ú P FSMC_PATT3_ATTHIZ3_3 ·Ú P FSMC_PATT3_ATTHIZ3_4 ¶Ú P FSMC_PATT3_ATTHIZ3_5 µÚ P FSMC_PATT3_ATTHIZ3_6 ´Ú P FSMC_PATT3_ATTHIZ3_7 ³Ú P FSMC_PATT4_ATTSET4 JÚ P FSMC_PATT4_ATTSET4_0 ·Ú P FSMC_PATT4_ATTSET4_1 ¶Ú P FSMC_PATT4_ATTSET4_2 µÚ P FSMC_PATT4_ATTSET4_3 ´Ú P FSMC_PATT4_ATTSET4_4 ³Ú P FSMC_PATT4_ATTSET4_5 ²Ú P FSMC_PATT4_ATTSET4_6 ±Ú P FSMC_PATT4_ATTSET4_7 °Ú P FSMC_PATT4_ATTWAIT4 ÿÚ P FSMC_PATT4_ATTWAIT4_0 lÚ P FSMC_PATT4_ATTWAIT4_1 kÚ P FSMC_PATT4_ATTWAIT4_2 jÚ P FSMC_PATT4_ATTWAIT4_3 iÚ P FSMC_PATT4_ATTWAIT4_4 hÚ P FSMC_PATT4_ATTWAIT4_5 gÚ P FSMC_PATT4_ATTWAIT4_6 fÚ P FSMC_PATT4_ATTWAIT4_7 eÚ P FSMC_PATT4_ATTHOLD4
Ú P FSMC_PATT4_ATTHOLD4_0 zÚ P FSMC_PATT4_ATTHOLD4_1 yÚ P FSMC_PATT4_ATTHOLD4_2 xÚ P FSMC_PATT4_ATTHOLD4_3 wÚ P FSMC_PATT4_ATTHOLD4_4 vÚ P FSMC_PATT4_ATTHOLD4_5 uÚ P FSMC_PATT4_ATTHOLD4_6 tÚ P FSMC_PATT4_ATTHOLD4_7 sÚ P FSMC_PATT4_ATTHIZ4 KÚ P FSMC_PATT4_ATTHIZ4_0 ¸Ú P FSMC_PATT4_ATTHIZ4_1 ·Ú P FSMC_PATT4_ATTHIZ4_2 ¶Ú P FSMC_PATT4_ATTHIZ4_3 µÚ P FSMC_PATT4_ATTHIZ4_4 ´Ú P FSMC_PATT4_ATTHIZ4_5 ³Ú P FSMC_PATT4_ATTHIZ4_6 ²Ú P FSMC_PATT4_ATTHIZ4_7 ±Ú P FSMC_PIO4_IOSET4 ðÚ P FSMC_PIO4_IOSET4_0 ]Ú P FSMC_PIO4_IOSET4_1 \Ú P FSMC_PIO4_IOSET4_2 [Ú P FSMC_PIO4_IOSET4_3 ZÚ P FSMC_PIO4_IOSET4_4 YÚ P FSMC_PIO4_IOSET4_5 XÚ P FSMC_PIO4_IOSET4_6 WÚ P FSMC_PIO4_IOSET4_7 VÚ P FSMC_PIO4_IOWAIT4 ¥Ú P FSMC_PIO4_IOWAIT4_0 Ú P FSMC_PIO4_IOWAIT4_1 Ú P FSMC_PIO4_IOWAIT4_2 Ú P FSMC_PIO4_IOWAIT4_3 Ú P FSMC_PIO4_IOWAIT4_4 Ú P FSMC_PIO4_IOWAIT4_5
Ú P FSMC_PIO4_IOWAIT4_6 Ú P FSMC_PIO4_IOWAIT4_7 Ú P FSMC_PIO4_IOHOLD4 ³Ú P FSMC_PIO4_IOHOLD4_0 Ú P FSMC_PIO4_IOHOLD4_1 Ú P FSMC_PIO4_IOHOLD4_2 Ú P FSMC_PIO4_IOHOLD4_3 Ú P FSMC_PIO4_IOHOLD4_4 Ú P FSMC_PIO4_IOHOLD4_5 Ú P FSMC_PIO4_IOHOLD4_6 Ú P FSMC_PIO4_IOHOLD4_7 Ú P FSMC_PIO4_IOHIZ4 ñÚ P FSMC_PIO4_IOHIZ4_0 ^Ú P FSMC_PIO4_IOHIZ4_1 ]Ú P FSMC_PIO4_IOHIZ4_2 \Ú P FSMC_PIO4_IOHIZ4_3 [Ú P FSMC_PIO4_IOHIZ4_4 ZÚ P FSMC_PIO4_IOHIZ4_5 YÚ P FSMC_PIO4_IOHIZ4_6 XÚ P FSMC_PIO4_IOHIZ4_7 WÚ P FSMC_ECCR2_ECC2 zÚ P FSMC_ECCR3_ECC3 xÚ P SDIO_POWER_PWRCTRL ÿÚ P SDIO_POWER_PWRCTRL_0 lÚ P SDIO_POWER_PWRCTRL_1 kÚ P SDIO_CLKCR_CLKDIV Ú P SDIO_CLKCR_CLKEN âÚ P SDIO_CLKCR_PWRSAV jÚ P SDIO_CLKCR_BYPASS {Ú P SDIO_CLKCR_WIDBUS Ú P SDIO_CLKCR_WIDBUS_0 ìÚ P SDIO_CLKCR_WIDBUS_1 ëÚ P SDIO_CLKCR_NEGEDGE \Ú P SDIO_CLKCR_HWFC_EN 1Ú P SDIO_ARG_CMDARG 8Ú P SDIO_CMD_CMDINDEX Ú P SDIO_CMD_WAITRESP yÚ P SDIO_CMD_WAITRESP_0 æÚ P SDIO_CMD_WAITRESP_1 åÚ P SDIO_CMD_WAITINT ÊÚ P SDIO_CMD_WAITPEND Ú P SDIO_CMD_CPSMEN &Ú P SDIO_CMD_SDIOSUSPEND Ú P SDIO_CMD_ENCMDCOMPL Ú P SDIO_CMD_NIEN ÆÚ P SDIO_CMD_CEATACMD ¶Ú P SDIO_RESPCMD_RESPCMD Ú P SDIO_RESP0_CARDSTATUS0 Ú P SDIO_RESP1_CARDSTATUS1 Ú P SDIO_RESP2_CARDSTATUS2 Ú P SDIO_RESP3_CARDSTATUS3 Ú P SDIO_RESP4_CARDSTATUS4 Ú P SDIO_DTIMER_DATATIME ¨Ú P SDIO_DLEN_DATALENGTH ·Ú P SDIO_DCTRL_DTEN Ú P SDIO_DCTRL_DTDIR ÎÚ P SDIO_DCTRL_DTMODE Ú P SDIO_DCTRL_DMAEN àÚ P SDIO_DCTRL_DBLOCKSIZE QÚ P SDIO_DCTRL_DBLOCKSIZE_0 ¾Ú P SDIO_DCTRL_DBLOCKSIZE_1 ½Ú P SDIO_DCTRL_DBLOCKSIZE_2 ¼Ú P SDIO_DCTRL_DBLOCKSIZE_3 »Ú P SDIO_DCTRL_RWSTART
Ú P SDIO_DCTRL_RWSTOP TÚ P SDIO_DCTRL_RWMOD ¼Ú P SDIO_DCTRL_SDIOEN Ú P SDIO_DCOUNT_DATACOUNT DÚ P SDIO_STA_CCRCFAIL Ú P SDIO_STA_DCRCFAIL Ú P SDIO_STA_CTIMEOUT jÚ P SDIO_STA_DTIMEOUT iÚ P SDIO_STA_TXUNDERR XÚ P SDIO_STA_RXOVERR Ú P SDIO_STA_CMDREND ÙÚ P SDIO_STA_CMDSENT ÈÚ P SDIO_STA_DATAEND åÚ P SDIO_STA_STBITERR eÚ P SDIO_STA_DBCKEND ëÚ P SDIO_STA_CMDACT ,Ú P SDIO_STA_TXACT VÚ P SDIO_STA_RXACT XÚ P SDIO_STA_TXFIFOHE wÚ P SDIO_STA_RXFIFOHF xÚ P SDIO_STA_TXFIFOF ÀÚ P SDIO_STA_RXFIFOF ÂÚ P SDIO_STA_TXFIFOE ÁÚ P SDIO_STA_RXFIFOE ÃÚ P SDIO_STA_TXDAVL Ú P SDIO_STA_RXDAVL Ú P SDIO_STA_SDIOIT Ú P SDIO_STA_CEATAEND Ú P SDIO_ICR_CCRCFAILC bÚ P SDIO_ICR_DCRCFAILC aÚ P SDIO_ICR_CTIMEOUTC /Ú P SDIO_ICR_DTIMEOUTC .Ú P SDIO_ICR_TXUNDERRC Ú P SDIO_ICR_RXOVERRC cÚ P SDIO_ICR_CMDRENDC Ú P SDIO_ICR_CMDSENTC Ú P SDIO_ICR_DATAENDC ªÚ P SDIO_ICR_STBITERRC *Ú P SDIO_ICR_DBCKENDC °Ú P SDIO_ICR_SDIOITC ÑÚ P SDIO_ICR_CEATAENDC dÚ P SDIO_MASK_CCRCFAILIE ÅÚ P SDIO_MASK_DCRCFAILIE ÄÚ P SDIO_MASK_CTIMEOUTIE Ú P SDIO_MASK_DTIMEOUTIE Ú P SDIO_MASK_TXUNDERRIE Ú P SDIO_MASK_RXOVERRIE ÆÚ P SDIO_MASK_CMDRENDIE Ú P SDIO_MASK_CMDSENTIE ðÚ P SDIO_MASK_DATAENDIE
Ú P SDIO_MASK_STBITERRIE Ú P SDIO_MASK_DBCKENDIE Ú P SDIO_MASK_CMDACTIE TÚ P SDIO_MASK_TXACTIE ~Ú P SDIO_MASK_RXACTIE Ú P SDIO_MASK_TXFIFOHEIE Ú P SDIO_MASK_RXFIFOHFIE Ú P SDIO_MASK_TXFIFOFIE èÚ P SDIO_MASK_RXFIFOFIE êÚ P SDIO_MASK_TXFIFOEIE éÚ P SDIO_MASK_RXFIFOEIE ëÚ P SDIO_MASK_TXDAVLIE -Ú P SDIO_MASK_RXDAVLIE /Ú P SDIO_MASK_SDIOITIE 4Ú P SDIO_MASK_CEATAENDIE ÇÚ P SDIO_FIFOCNT_FIFOCOUNT üÚ P SDIO_FIFO_FIFODATA XÚ P USB_EP0R_EA pÚ P USB_EP0R_STAT_TX ¥Ú P USB_EP0R_STAT_TX_0 Ú P USB_EP0R_STAT_TX_1 Ú P USB_EP0R_DTOG_TX ³Ú P USB_EP0R_CTR_TX úÚ P USB_EP0R_EP_KIND ÒÚ P USB_EP0R_EP_TYPE ¶Ú P USB_EP0R_EP_TYPE_0 #Ú P USB_EP0R_EP_TYPE_1 "Ú P USB_EP0R_SETUP _Ú P USB_EP0R_STAT_RX §Ú P USB_EP0R_STAT_RX_0 Ú P USB_EP0R_STAT_RX_1 Ú P USB_EP0R_DTOG_RX µÚ P USB_EP0R_CTR_RX üÚ P USB_EP1R_EA oÚ P USB_EP1R_STAT_TX ¤Ú P USB_EP1R_STAT_TX_0 Ú P USB_EP1R_STAT_TX_1 Ú P USB_EP1R_DTOG_TX ²Ú P USB_EP1R_CTR_TX ùÚ P USB_EP1R_EP_KIND ÑÚ P USB_EP1R_EP_TYPE µÚ P USB_EP1R_EP_TYPE_0 "Ú P USB_EP1R_EP_TYPE_1 !Ú P USB_EP1R_SETUP ^Ú P USB_EP1R_STAT_RX ¦Ú P USB_EP1R_STAT_RX_0 Ú P USB_EP1R_STAT_RX_1 Ú P USB_EP1R_DTOG_RX ´Ú P USB_EP1R_CTR_RX ûÚ P USB_EP2R_EA nÚ P USB_EP2R_STAT_TX £Ú P USB_EP2R_STAT_TX_0 Ú P USB_EP2R_STAT_TX_1 Ú P USB_EP2R_DTOG_TX ±Ú P USB_EP2R_CTR_TX øÚ P USB_EP2R_EP_KIND ÐÚ P USB_EP2R_EP_TYPE ´Ú P USB_EP2R_EP_TYPE_0 !Ú P USB_EP2R_EP_TYPE_1 Ú P USB_EP2R_SETUP ]Ú P USB_EP2R_STAT_RX ¥Ú P USB_EP2R_STAT_RX_0 Ú P USB_EP2R_STAT_RX_1 Ú P USB_EP2R_DTOG_RX ³Ú P USB_EP2R_CTR_RX úÚ P USB_EP3R_EA mÚ P USB_EP3R_STAT_TX ¢Ú P USB_EP3R_STAT_TX_0 Ú P USB_EP3R_STAT_TX_1 Ú P USB_EP3R_DTOG_TX °Ú P USB_EP3R_CTR_TX ÷Ú P USB_EP3R_EP_KIND ÏÚ P USB_EP3R_EP_TYPE ³Ú P USB_EP3R_EP_TYPE_0 Ú P USB_EP3R_EP_TYPE_1 Ú P USB_EP3R_SETUP \Ú P USB_EP3R_STAT_RX ¤Ú P USB_EP3R_STAT_RX_0 Ú P USB_EP3R_STAT_RX_1 Ú P USB_EP3R_DTOG_RX ²Ú P USB_EP3R_CTR_RX ùÚ P USB_EP4R_EA lÚ P USB_EP4R_STAT_TX ¡Ú P USB_EP4R_STAT_TX_0 Ú P USB_EP4R_STAT_TX_1
Ú P USB_EP4R_DTOG_TX ¯Ú P USB_EP4R_CTR_TX öÚ P USB_EP4R_EP_KIND ÎÚ P USB_EP4R_EP_TYPE ²Ú P USB_EP4R_EP_TYPE_0 Ú P USB_EP4R_EP_TYPE_1 Ú P USB_EP4R_SETUP [Ú P USB_EP4R_STAT_RX £Ú P USB_EP4R_STAT_RX_0 Ú P USB_EP4R_STAT_RX_1 Ú P USB_EP4R_DTOG_RX ±Ú P USB_EP4R_CTR_RX øÚ P USB_EP5R_EA kÚ P USB_EP5R_STAT_TX Ú P USB_EP5R_STAT_TX_0
Ú P USB_EP5R_STAT_TX_1 Ú P USB_EP5R_DTOG_TX ®Ú P USB_EP5R_CTR_TX õÚ P USB_EP5R_EP_KIND ÍÚ P USB_EP5R_EP_TYPE ±Ú P USB_EP5R_EP_TYPE_0 Ú P USB_EP5R_EP_TYPE_1 Ú P USB_EP5R_SETUP ZÚ P USB_EP5R_STAT_RX ¢Ú P USB_EP5R_STAT_RX_0 Ú P USB_EP5R_STAT_RX_1 Ú P USB_EP5R_DTOG_RX °Ú P USB_EP5R_CTR_RX ÷Ú P USB_EP6R_EA jÚ P USB_EP6R_STAT_TX Ú P USB_EP6R_STAT_TX_0 Ú P USB_EP6R_STAT_TX_1 Ú P USB_EP6R_DTOG_TX Ú P USB_EP6R_CTR_TX ôÚ P USB_EP6R_EP_KIND ÌÚ P USB_EP6R_EP_TYPE °Ú P USB_EP6R_EP_TYPE_0 Ú P USB_EP6R_EP_TYPE_1 Ú P USB_EP6R_SETUP YÚ P USB_EP6R_STAT_RX ¡Ú P USB_EP6R_STAT_RX_0 Ú P USB_EP6R_STAT_RX_1
Ú P USB_EP6R_DTOG_RX ¯Ú P USB_EP6R_CTR_RX öÚ P USB_EP7R_EA iÚ P USB_EP7R_STAT_TX Ú P USB_EP7R_STAT_TX_0 Ú P USB_EP7R_STAT_TX_1
Ú P USB_EP7R_DTOG_TX ¬Ú P USB_EP7R_CTR_TX óÚ P USB_EP7R_EP_KIND ËÚ P USB_EP7R_EP_TYPE ¯Ú P USB_EP7R_EP_TYPE_0 Ú P USB_EP7R_EP_TYPE_1 Ú P USB_EP7R_SETUP XÚ P USB_EP7R_STAT_RX Ú P USB_EP7R_STAT_RX_0
Ú P USB_EP7R_STAT_RX_1 Ú P USB_EP7R_DTOG_RX ®Ú P USB_EP7R_CTR_RX õÚ P USB_CNTR_FRES ¢Ú P USB_CNTR_PDWN Ú P USB_CNTR_LP_MODE ¬Ú P USB_CNTR_FSUSP ?Ú P USB_CNTR_RESUME ýÚ P USB_CNTR_ESOFM VÚ P USB_CNTR_SOFM Ú P USB_CNTR_RESETM þÚ P USB_CNTR_SUSPM 8Ú P USB_CNTR_WKUPM <Ú P USB_CNTR_ERRM Ú P USB_CNTR_PMAOVRM ªÚ P USB_CNTR_CTRM Ú P USB_ISTR_EP_ID DÚ P
USB_ISTR_DIR êÚ P USB_ISTR_ESOF Ú P
USB_ISTR_SOF áÚ P USB_ISTR_RESET BÚ P USB_ISTR_SUSP |Ú P USB_ISTR_WKUP Ú P
USB_ISTR_ERR àÚ P USB_ISTR_PMAOVR îÚ P
USB_ISTR_CTR àÚ P USB_FNR_FN Ú P
USB_FNR_LSOF ñÚ P USB_FNR_LCK MÚ P
USB_FNR_RXDM êÚ P
USB_FNR_RXDP çÚ P USB_DADDR_ADD áÚ P USB_DADDR_ADD0 ¯Ú P USB_DADDR_ADD1 ®Ú P USB_DADDR_ADD2 Ú P USB_DADDR_ADD3 ¬Ú P USB_DADDR_ADD4 «Ú P USB_DADDR_ADD5 ªÚ P USB_DADDR_ADD6 ©Ú P
USB_DADDR_EF !Ú P USB_BTABLE_BTABLE Ú P USB_ADDR0_TX_ADDR0_TX MÚ P USB_ADDR1_TX_ADDR1_TX KÚ P USB_ADDR2_TX_ADDR2_TX IÚ P USB_ADDR3_TX_ADDR3_TX GÚ P USB_ADDR4_TX_ADDR4_TX EÚ P USB_ADDR5_TX_ADDR5_TX CÚ P USB_ADDR6_TX_ADDR6_TX AÚ P USB_ADDR7_TX_ADDR7_TX ?Ú P USB_COUNT0_TX_COUNT0_TX mÚ P USB_COUNT1_TX_COUNT1_TX kÚ P USB_COUNT2_TX_COUNT2_TX iÚ P USB_COUNT3_TX_COUNT3_TX gÚ P USB_COUNT4_TX_COUNT4_TX eÚ P USB_COUNT5_TX_COUNT5_TX cÚ P USB_COUNT6_TX_COUNT6_TX aÚ P USB_COUNT7_TX_COUNT7_TX _Ú$ P USB_COUNT0_TX_0_COUNT0_TX_0 GÚ$ P USB_COUNT0_TX_1_COUNT0_TX_1 EÚ$ P USB_COUNT1_TX_0_COUNT1_TX_0 EÚ$ P USB_COUNT1_TX_1_COUNT1_TX_1 CÚ$ P USB_COUNT2_TX_0_COUNT2_TX_0 CÚ$ P USB_COUNT2_TX_1_COUNT2_TX_1 AÚ$ P USB_COUNT3_TX_0_COUNT3_TX_0 AÚ$ P USB_COUNT3_TX_1_COUNT3_TX_1 ?Ú$ P USB_COUNT4_TX_0_COUNT4_TX_0 ?Ú$ P USB_COUNT4_TX_1_COUNT4_TX_1 =Ú$ P USB_COUNT5_TX_0_COUNT5_TX_0 =Ú$ P USB_COUNT5_TX_1_COUNT5_TX_1 ;Ú$ P USB_COUNT6_TX_0_COUNT6_TX_0 ;Ú$ P USB_COUNT6_TX_1_COUNT6_TX_1 9Ú$ P USB_COUNT7_TX_0_COUNT7_TX_0 9Ú$ P USB_COUNT7_TX_1_COUNT7_TX_1 7Ú P USB_ADDR0_RX_ADDR0_RX QÚ P USB_ADDR1_RX_ADDR1_RX OÚ P USB_ADDR2_RX_ADDR2_RX MÚ P USB_ADDR3_RX_ADDR3_RX KÚ P USB_ADDR4_RX_ADDR4_RX IÚ P USB_ADDR5_RX_ADDR5_RX GÚ P USB_ADDR6_RX_ADDR6_RX EÚ P USB_ADDR7_RX_ADDR7_RX CÚ P USB_COUNT0_RX_COUNT0_RX qÚ P USB_COUNT0_RX_NUM_BLOCK yÚ" P USB_COUNT0_RX_NUM_BLOCK_0 æÚ" P USB_COUNT0_RX_NUM_BLOCK_1 åÚ" P USB_COUNT0_RX_NUM_BLOCK_2 äÚ" P USB_COUNT0_RX_NUM_BLOCK_3 ãÚ" P USB_COUNT0_RX_NUM_BLOCK_4 âÚ P USB_COUNT0_RX_BLSIZE pÚ P USB_COUNT1_RX_COUNT1_RX oÚ P USB_COUNT1_RX_NUM_BLOCK xÚ" P USB_COUNT1_RX_NUM_BLOCK_0 åÚ" P USB_COUNT1_RX_NUM_BLOCK_1 äÚ" P USB_COUNT1_RX_NUM_BLOCK_2 ãÚ" P USB_COUNT1_RX_NUM_BLOCK_3 âÚ" P USB_COUNT1_RX_NUM_BLOCK_4 áÚ P USB_COUNT1_RX_BLSIZE oÚ P USB_COUNT2_RX_COUNT2_RX mÚ P USB_COUNT2_RX_NUM_BLOCK wÚ" P USB_COUNT2_RX_NUM_BLOCK_0 äÚ" P USB_COUNT2_RX_NUM_BLOCK_1 ãÚ" P USB_COUNT2_RX_NUM_BLOCK_2 âÚ" P USB_COUNT2_RX_NUM_BLOCK_3 áÚ" P USB_COUNT2_RX_NUM_BLOCK_4 àÚ P USB_COUNT2_RX_BLSIZE nÚ P USB_COUNT3_RX_COUNT3_RX kÚ P USB_COUNT3_RX_NUM_BLOCK vÚ" P USB_COUNT3_RX_NUM_BLOCK_0 ãÚ" P USB_COUNT3_RX_NUM_BLOCK_1 âÚ" P USB_COUNT3_RX_NUM_BLOCK_2 áÚ" P USB_COUNT3_RX_NUM_BLOCK_3 àÚ" P USB_COUNT3_RX_NUM_BLOCK_4 ßÚ P USB_COUNT3_RX_BLSIZE mÚ P USB_COUNT4_RX_COUNT4_RX iÚ P USB_COUNT4_RX_NUM_BLOCK uÚ" P USB_COUNT4_RX_NUM_BLOCK_0 âÚ" P USB_COUNT4_RX_NUM_BLOCK_1 áÚ" P USB_COUNT4_RX_NUM_BLOCK_2 àÚ" P USB_COUNT4_RX_NUM_BLOCK_3 ßÚ" P USB_COUNT4_RX_NUM_BLOCK_4 ÞÚ P USB_COUNT4_RX_BLSIZE lÚ P USB_COUNT5_RX_COUNT5_RX gÚ P USB_COUNT5_RX_NUM_BLOCK tÚ" P USB_COUNT5_RX_NUM_BLOCK_0 áÚ" P USB_COUNT5_RX_NUM_BLOCK_1 àÚ" P USB_COUNT5_RX_NUM_BLOCK_2 ßÚ" P USB_COUNT5_RX_NUM_BLOCK_3 ÞÚ" P USB_COUNT5_RX_NUM_BLOCK_4 ÝÚ P USB_COUNT5_RX_BLSIZE kÚ P USB_COUNT6_RX_COUNT6_RX eÚ P USB_COUNT6_RX_NUM_BLOCK sÚ" P USB_COUNT6_RX_NUM_BLOCK_0 àÚ" P USB_COUNT6_RX_NUM_BLOCK_1 ßÚ" P USB_COUNT6_RX_NUM_BLOCK_2 ÞÚ" P USB_COUNT6_RX_NUM_BLOCK_3 ÝÚ" P USB_COUNT6_RX_NUM_BLOCK_4 ÜÚ P USB_COUNT6_RX_BLSIZE jÚ P USB_COUNT7_RX_COUNT7_RX cÚ P USB_COUNT7_RX_NUM_BLOCK rÚ" P USB_COUNT7_RX_NUM_BLOCK_0 ßÚ" P USB_COUNT7_RX_NUM_BLOCK_1 ÞÚ" P USB_COUNT7_RX_NUM_BLOCK_2 ÝÚ" P USB_COUNT7_RX_NUM_BLOCK_3 ÜÚ" P USB_COUNT7_RX_NUM_BLOCK_4 ÛÚ P USB_COUNT7_RX_BLSIZE iÚ$ P USB_COUNT0_RX_0_COUNT0_RX_0 KÚ$ P USB_COUNT0_RX_0_NUM_BLOCK_0 SÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_0 ÀÚ& P USB_COUNT0_RX_0_NUM_BLOCK_0_1 ¿Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_2 ¾Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_3 ½Ú& P USB_COUNT0_RX_0_NUM_BLOCK_0_4 ¼Ú! P USB_COUNT0_RX_0_BLSIZE_0 JÚ$ P USB_COUNT0_RX_1_COUNT0_RX_1 IÚ$ P USB_COUNT0_RX_1_NUM_BLOCK_1 QÚ& P USB_COUNT0_RX_1_NUM_BLOCK_1_0 ¾Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_1 ½Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_2 ¼Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_3 »Ú& P USB_COUNT0_RX_1_NUM_BLOCK_1_4 ºÚ! P USB_COUNT0_RX_1_BLSIZE_1 HÚ$ P USB_COUNT1_RX_0_COUNT1_RX_0 IÚ$ P USB_COUNT1_RX_0_NUM_BLOCK_0 RÚ& P USB_COUNT1_RX_0_NUM_BLOCK_0_0 ¿Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_1 ¾Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_2 ½Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_3 ¼Ú& P USB_COUNT1_RX_0_NUM_BLOCK_0_4 »Ú! P USB_COUNT1_RX_0_BLSIZE_0 IÚ$ P USB_COUNT1_RX_1_COUNT1_RX_1 GÚ$ P USB_COUNT1_RX_1_NUM_BLOCK_1 PÚ& P USB_COUNT1_RX_1_NUM_BLOCK_1_0 ½Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_1 ¼Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_2 »Ú& P USB_COUNT1_RX_1_NUM_BLOCK_1_3 ºÚ& P USB_COUNT1_RX_1_NUM_BLOCK_1_4 ¹Ú! P USB_COUNT1_RX_1_BLSIZE_1 GÚ$ P USB_COUNT2_RX_0_COUNT2_RX_0 GÚ$ P USB_COUNT2_RX_0_NUM_BLOCK_0 QÚ& P USB_COUNT2_RX_0_NUM_BLOCK_0_0 ¾Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_1 ½Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_2 ¼Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_3 »Ú& P USB_COUNT2_RX_0_NUM_BLOCK_0_4 ºÚ! P USB_COUNT2_RX_0_BLSIZE_0 HÚ$ P USB_COUNT2_RX_1_COUNT2_RX_1 EÚ$ P USB_COUNT2_RX_1_NUM_BLOCK_1 OÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_0 ¼Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_1 »Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_2 ºÚ& P USB_COUNT2_RX_1_NUM_BLOCK_1_3 ¹Ú& P USB_COUNT2_RX_1_NUM_BLOCK_1_4 ¸Ú! P USB_COUNT2_RX_1_BLSIZE_1 FÚ$ P USB_COUNT3_RX_0_COUNT3_RX_0 EÚ$ P USB_COUNT3_RX_0_NUM_BLOCK_0 PÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_0 ½Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_1 ¼Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_2 »Ú& P USB_COUNT3_RX_0_NUM_BLOCK_0_3 ºÚ& P USB_COUNT3_RX_0_NUM_BLOCK_0_4 ¹Ú! P USB_COUNT3_RX_0_BLSIZE_0 GÚ$ P USB_COUNT3_RX_1_COUNT3_RX_1 CÚ$ P USB_COUNT3_RX_1_NUM_BLOCK_1 NÚ& P USB_COUNT3_RX_1_NUM_BLOCK_1_0 »Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_1 ºÚ& P USB_COUNT3_RX_1_NUM_BLOCK_1_2 ¹Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_3 ¸Ú& P USB_COUNT3_RX_1_NUM_BLOCK_1_4 ·Ú! P USB_COUNT3_RX_1_BLSIZE_1 EÚ$ P USB_COUNT4_RX_0_COUNT4_RX_0 CÚ$ P USB_COUNT4_RX_0_NUM_BLOCK_0 OÚ& P USB_COUNT4_RX_0_NUM_BLOCK_0_0 ¼Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_1 »Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_2 ºÚ& P USB_COUNT4_RX_0_NUM_BLOCK_0_3 ¹Ú& P USB_COUNT4_RX_0_NUM_BLOCK_0_4 ¸Ú! P USB_COUNT4_RX_0_BLSIZE_0 FÚ$ P USB_COUNT4_RX_1_COUNT4_RX_1 AÚ$ P USB_COUNT4_RX_1_NUM_BLOCK_1 MÚ& P USB_COUNT4_RX_1_NUM_BLOCK_1_0 ºÚ& P USB_COUNT4_RX_1_NUM_BLOCK_1_1 ¹Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_2 ¸Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_3 ·Ú& P USB_COUNT4_RX_1_NUM_BLOCK_1_4 ¶Ú! P USB_COUNT4_RX_1_BLSIZE_1 DÚ$ P USB_COUNT5_RX_0_COUNT5_RX_0 AÚ$ P USB_COUNT5_RX_0_NUM_BLOCK_0 NÚ& P USB_COUNT5_RX_0_NUM_BLOCK_0_0 »Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_1 ºÚ& P USB_COUNT5_RX_0_NUM_BLOCK_0_2 ¹Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_3 ¸Ú& P USB_COUNT5_RX_0_NUM_BLOCK_0_4 ·Ú! P USB_COUNT5_RX_0_BLSIZE_0 EÚ$ P USB_COUNT5_RX_1_COUNT5_RX_1 ?Ú$ P USB_COUNT5_RX_1_NUM_BLOCK_1 LÚ& P USB_COUNT5_RX_1_NUM_BLOCK_1_0 ¹Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_1 ¸Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_2 ·Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_3 ¶Ú& P USB_COUNT5_RX_1_NUM_BLOCK_1_4 µÚ! P USB_COUNT5_RX_1_BLSIZE_1 CÚ$ P USB_COUNT6_RX_0_COUNT6_RX_0 ?Ú$ P USB_COUNT6_RX_0_NUM_BLOCK_0 MÚ& P USB_COUNT6_RX_0_NUM_BLOCK_0_0 ºÚ& P USB_COUNT6_RX_0_NUM_BLOCK_0_1 ¹Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_2 ¸Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_3 ·Ú& P USB_COUNT6_RX_0_NUM_BLOCK_0_4 ¶Ú! P USB_COUNT6_RX_0_BLSIZE_0 DÚ$ P USB_COUNT6_RX_1_COUNT6_RX_1 =Ú$ P USB_COUNT6_RX_1_NUM_BLOCK_1 KÚ& P USB_COUNT6_RX_1_NUM_BLOCK_1_0 ¸Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_1 ·Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_2 ¶Ú& P USB_COUNT6_RX_1_NUM_BLOCK_1_3 µÚ& P USB_COUNT6_RX_1_NUM_BLOCK_1_4 ´Ú! P USB_COUNT6_RX_1_BLSIZE_1 BÚ$ P USB_COUNT7_RX_0_COUNT7_RX_0 =Ú$ P USB_COUNT7_RX_0_NUM_BLOCK_0 LÚ& P USB_COUNT7_RX_0_NUM_BLOCK_0_0 ¹Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_1 ¸Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_2 ·Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_3 ¶Ú& P USB_COUNT7_RX_0_NUM_BLOCK_0_4 µÚ! P USB_COUNT7_RX_0_BLSIZE_0 CÚ$ P USB_COUNT7_RX_1_COUNT7_RX_1 ;Ú$ P USB_COUNT7_RX_1_NUM_BLOCK_1 JÚ& P USB_COUNT7_RX_1_NUM_BLOCK_1_0 ·Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_1 ¶Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_2 µÚ& P USB_COUNT7_RX_1_NUM_BLOCK_1_3 ´Ú& P USB_COUNT7_RX_1_NUM_BLOCK_1_4 ³Ú! P USB_COUNT7_RX_1_BLSIZE_1 AÚ P
CAN_MCR_INRQ Ú P CAN_MCR_SLEEP ÆÚ P
CAN_MCR_TXFP ÿÚ P
CAN_MCR_RFLM Ú P
CAN_MCR_NART Ú P
CAN_MCR_AWUM Ú P
CAN_MCR_ABOM "Ú P
CAN_MCR_TTCM Ú P CAN_MCR_RESET ¼Ú P
CAN_MSR_INAK Ú P
CAN_MSR_SLAK Ú P
CAN_MSR_ERRI ÿÚ P
CAN_MSR_WKUI ñÚ P CAN_MSR_SLAKI »Ú P CAN_MSR_TXM :Ú P CAN_MSR_RXM <Ú P
CAN_MSR_SAMP Ú P CAN_MSR_RX Ú P CAN_TSR_RQCP0 ÂÚ P CAN_TSR_TXOK0 ²Ú P CAN_TSR_ALST0 ÄÚ P CAN_TSR_TERR0 »Ú P CAN_TSR_ABRQ0 ÒÚ P CAN_TSR_RQCP1 ÁÚ P CAN_TSR_TXOK1 ±Ú P CAN_TSR_ALST1 ÃÚ P CAN_TSR_TERR1 ºÚ P CAN_TSR_ABRQ1 ÑÚ P CAN_TSR_RQCP2 ÀÚ P CAN_TSR_TXOK2 °Ú P CAN_TSR_ALST2 ÂÚ P CAN_TSR_TERR2 ¹Ú P CAN_TSR_ABRQ2 ÐÚ P
CAN_TSR_CODE Ú P CAN_TSR_TME FÚ P
CAN_TSR_TME0 Ú P
CAN_TSR_TME1 Ú P
CAN_TSR_TME2 Ú P CAN_TSR_LOW :Ú P
CAN_TSR_LOW0 Ú P
CAN_TSR_LOW1 Ú P
CAN_TSR_LOW2 Ú P CAN_RF0R_FMP0 ôÚ P CAN_RF0R_FULL0 ¢Ú P CAN_RF0R_FOVR0 Ú P CAN_RF0R_RFOM0 ¡Ú P CAN_RF1R_FMP1 òÚ P CAN_RF1R_FULL1 Ú P CAN_RF1R_FOVR1 Ú P CAN_RF1R_RFOM1 Ú P CAN_IER_TMEIE ÍÚ P CAN_IER_FMPIE0 Ú P CAN_IER_FFIE0 ÷Ú P CAN_IER_FOVIE0 Ú P CAN_IER_FMPIE1 Ú P CAN_IER_FFIE1 öÚ P CAN_IER_FOVIE1 Ú P CAN_IER_EWGIE ÐÚ P CAN_IER_EPVIE ÈÚ P CAN_IER_BOFIE ÜÚ P CAN_IER_LECIE ßÚ P CAN_IER_ERRIE ÊÚ P CAN_IER_WKUIE ¼Ú P CAN_IER_SLKIE ÉÚ P
CAN_ESR_EWGF Ú P
CAN_ESR_EPVF Ú P
CAN_ESR_BOFF Ú P CAN_ESR_LEC gÚ P CAN_ESR_LEC_0 ÔÚ P CAN_ESR_LEC_1 ÓÚ P CAN_ESR_LEC_2 ÒÚ P CAN_ESR_TEC _Ú P CAN_ESR_REC aÚ P CAN_BTR_BRP YÚ P CAN_BTR_TS1 eÚ P CAN_BTR_TS2 dÚ P CAN_BTR_SJW IÚ P
CAN_BTR_LBKM Ú P
CAN_BTR_SILM Ú P CAN_TI0R_TXRQ ³Ú P
CAN_TI0R_RTR Ú P
CAN_TI0R_IDE 2Ú P CAN_TI0R_EXID ØÚ P CAN_TI0R_STID ÎÚ P CAN_TDT0R_DLC àÚ P CAN_TDT0R_TGT ÄÚ P CAN_TDT0R_TIME Ú P CAN_TDL0R_DATA0 mÚ P CAN_TDL0R_DATA1 lÚ P CAN_TDL0R_DATA2 kÚ P CAN_TDL0R_DATA3 jÚ P CAN_TDH0R_DATA4 mÚ P CAN_TDH0R_DATA5 lÚ P CAN_TDH0R_DATA6 kÚ P CAN_TDH0R_DATA7 jÚ P CAN_TI1R_TXRQ ²Ú P
CAN_TI1R_RTR Ú P
CAN_TI1R_IDE 1Ú P CAN_TI1R_EXID ×Ú P CAN_TI1R_STID ÍÚ P CAN_TDT1R_DLC ßÚ P CAN_TDT1R_TGT ÃÚ P CAN_TDT1R_TIME Ú P CAN_TDL1R_DATA0 lÚ P CAN_TDL1R_DATA1 kÚ P CAN_TDL1R_DATA2 jÚ P CAN_TDL1R_DATA3 iÚ P CAN_TDH1R_DATA4 lÚ P CAN_TDH1R_DATA5 kÚ P CAN_TDH1R_DATA6 jÚ P CAN_TDH1R_DATA7 iÚ P CAN_TI2R_TXRQ ±Ú P
CAN_TI2R_RTR
Ú P
CAN_TI2R_IDE 0Ú P CAN_TI2R_EXID ÖÚ P CAN_TI2R_STID ÌÚ P CAN_TDT2R_DLC ÞÚ P CAN_TDT2R_TGT ÂÚ P CAN_TDT2R_TIME Ú P CAN_TDL2R_DATA0 kÚ P CAN_TDL2R_DATA1 jÚ P CAN_TDL2R_DATA2 iÚ P CAN_TDL2R_DATA3 hÚ P CAN_TDH2R_DATA4 kÚ P CAN_TDH2R_DATA5 jÚ P CAN_TDH2R_DATA6 iÚ P CAN_TDH2R_DATA7 hÚ P
CAN_RI0R_RTR Ú P
CAN_RI0R_IDE 4Ú P CAN_RI0R_EXID ÚÚ P CAN_RI0R_STID ÐÚ P CAN_RDT0R_DLC âÚ P CAN_RDT0R_FMI ÙÚ P CAN_RDT0R_TIME Ú P CAN_RDL0R_DATA0 oÚ P CAN_RDL0R_DATA1 nÚ P CAN_RDL0R_DATA2 mÚ P CAN_RDL0R_DATA3 lÚ P CAN_RDH0R_DATA4 oÚ P CAN_RDH0R_DATA5 nÚ P CAN_RDH0R_DATA6 mÚ P CAN_RDH0R_DATA7 lÚ P
CAN_RI1R_RTR
Ú P
CAN_RI1R_IDE 3Ú P CAN_RI1R_EXID ÙÚ P CAN_RI1R_STID ÏÚ P CAN_RDT1R_DLC áÚ P CAN_RDT1R_FMI ØÚ P CAN_RDT1R_TIME Ú P CAN_RDL1R_DATA0 nÚ P CAN_RDL1R_DATA1 mÚ P CAN_RDL1R_DATA2 lÚ P CAN_RDL1R_DATA3 kÚ P CAN_RDH1R_DATA4 nÚ P CAN_RDH1R_DATA5 mÚ P CAN_RDH1R_DATA6 lÚ P CAN_RDH1R_DATA7 kÚ P CAN_FMR_FINIT ÂÚ P
CAN_FM1R_FBM 8Ú P CAN_FM1R_FBM0 Ú P CAN_FM1R_FBM1 Ú P CAN_FM1R_FBM2 Ú P CAN_FM1R_FBM3 Ú P CAN_FM1R_FBM4 Ú P CAN_FM1R_FBM5 Ú P CAN_FM1R_FBM6 Ú P CAN_FM1R_FBM7 ÿÚ P CAN_FM1R_FBM8 þÚ P CAN_FM1R_FBM9 ýÚ P CAN_FM1R_FBM10 ÓÚ P CAN_FM1R_FBM11 ÒÚ P CAN_FM1R_FBM12 ÑÚ P CAN_FM1R_FBM13 ÐÚ P
CAN_FS1R_FSC +Ú P CAN_FS1R_FSC0 ùÚ P CAN_FS1R_FSC1 øÚ P CAN_FS1R_FSC2 ÷Ú P CAN_FS1R_FSC3 öÚ P CAN_FS1R_FSC4 õÚ P CAN_FS1R_FSC5 ôÚ P CAN_FS1R_FSC6 óÚ P CAN_FS1R_FSC7 òÚ P CAN_FS1R_FSC8 ñÚ P CAN_FS1R_FSC9 ðÚ P CAN_FS1R_FSC10 ÆÚ P CAN_FS1R_FSC11 ÅÚ P CAN_FS1R_FSC12 ÄÚ P CAN_FS1R_FSC13 ÃÚ P CAN_FFA1R_FFA Ú P CAN_FFA1R_FFA0 ÒÚ P CAN_FFA1R_FFA1 ÑÚ P CAN_FFA1R_FFA2 ÐÚ P CAN_FFA1R_FFA3 ÏÚ P CAN_FFA1R_FFA4 ÎÚ P CAN_FFA1R_FFA5 ÍÚ P CAN_FFA1R_FFA6 ÌÚ P CAN_FFA1R_FFA7 ËÚ P CAN_FFA1R_FFA8 ÊÚ P CAN_FFA1R_FFA9 ÉÚ P CAN_FFA1R_FFA10 Ú P CAN_FFA1R_FFA11 Ú P CAN_FFA1R_FFA12 Ú P CAN_FFA1R_FFA13 Ú P CAN_FA1R_FACT ùÚ P CAN_FA1R_FACT0 ÇÚ P CAN_FA1R_FACT1 ÆÚ P CAN_FA1R_FACT2 ÅÚ P CAN_FA1R_FACT3 ÄÚ P CAN_FA1R_FACT4 ÃÚ P CAN_FA1R_FACT5 ÂÚ P CAN_FA1R_FACT6 ÁÚ P CAN_FA1R_FACT7 ÀÚ P CAN_FA1R_FACT8 ¿Ú P CAN_FA1R_FACT9 ¾Ú P CAN_FA1R_FACT10 Ú P CAN_FA1R_FACT11 Ú P CAN_FA1R_FACT12 Ú P CAN_FA1R_FACT13 Ú P
CAN_F0R1_FB0 rÚ P
CAN_F0R1_FB1 qÚ P
CAN_F0R1_FB2 pÚ P
CAN_F0R1_FB3 oÚ P
CAN_F0R1_FB4 nÚ P
CAN_F0R1_FB5 mÚ P
CAN_F0R1_FB6 lÚ P
CAN_F0R1_FB7 kÚ P
CAN_F0R1_FB8 jÚ P
CAN_F0R1_FB9 iÚ P CAN_F0R1_FB10 ?Ú P CAN_F0R1_FB11 >Ú P CAN_F0R1_FB12 =Ú P CAN_F0R1_FB13 <Ú P CAN_F0R1_FB14 ;Ú P CAN_F0R1_FB15 :Ú P CAN_F0R1_FB16 9Ú P CAN_F0R1_FB17 8Ú P CAN_F0R1_FB18 7Ú P CAN_F0R1_FB19 6Ú P CAN_F0R1_FB20 >Ú P CAN_F0R1_FB21 =Ú P CAN_F0R1_FB22 <Ú P CAN_F0R1_FB23 ;Ú P CAN_F0R1_FB24 :Ú P CAN_F0R1_FB25 9Ú P CAN_F0R1_FB26 8Ú P CAN_F0R1_FB27 7Ú P CAN_F0R1_FB28 6Ú P CAN_F0R1_FB29 5Ú P CAN_F0R1_FB30 =Ú P CAN_F0R1_FB31 <Ú P
CAN_F1R1_FB0 qÚ P
CAN_F1R1_FB1 pÚ P
CAN_F1R1_FB2 oÚ P
CAN_F1R1_FB3 nÚ P
CAN_F1R1_FB4 mÚ P
CAN_F1R1_FB5 lÚ P
CAN_F1R1_FB6 kÚ P
CAN_F1R1_FB7 jÚ P
CAN_F1R1_FB8 iÚ P
CAN_F1R1_FB9 hÚ P CAN_F1R1_FB10 >Ú P CAN_F1R1_FB11 =Ú P CAN_F1R1_FB12 <Ú P CAN_F1R1_FB13 ;Ú P CAN_F1R1_FB14 :Ú P CAN_F1R1_FB15 9Ú P CAN_F1R1_FB16 8Ú P CAN_F1R1_FB17 7Ú P CAN_F1R1_FB18 6Ú P CAN_F1R1_FB19 5Ú P CAN_F1R1_FB20 =Ú P CAN_F1R1_FB21 <Ú P CAN_F1R1_FB22 ;Ú P CAN_F1R1_FB23 :Ú P CAN_F1R1_FB24 9Ú P CAN_F1R1_FB25 8Ú P CAN_F1R1_FB26 7Ú P CAN_F1R1_FB27 6Ú P CAN_F1R1_FB28 5Ú P CAN_F1R1_FB29 4Ú P CAN_F1R1_FB30 <Ú P CAN_F1R1_FB31 ;Ú P
CAN_F2R1_FB0 pÚ P
CAN_F2R1_FB1 oÚ P
CAN_F2R1_FB2 nÚ P
CAN_F2R1_FB3 mÚ P
CAN_F2R1_FB4 lÚ P
CAN_F2R1_FB5 kÚ P
CAN_F2R1_FB6 jÚ P
CAN_F2R1_FB7 iÚ P
CAN_F2R1_FB8 hÚ P
CAN_F2R1_FB9 gÚ P CAN_F2R1_FB10 =Ú P CAN_F2R1_FB11 <Ú P CAN_F2R1_FB12 ;Ú P CAN_F2R1_FB13 :Ú P CAN_F2R1_FB14 9Ú P CAN_F2R1_FB15 8Ú P CAN_F2R1_FB16 7Ú P CAN_F2R1_FB17 6Ú P CAN_F2R1_FB18 5Ú P CAN_F2R1_FB19 4Ú P CAN_F2R1_FB20 <Ú P CAN_F2R1_FB21 ;Ú P CAN_F2R1_FB22 :Ú P CAN_F2R1_FB23 9Ú P CAN_F2R1_FB24 8Ú P CAN_F2R1_FB25 7Ú P CAN_F2R1_FB26 6Ú P CAN_F2R1_FB27 5Ú P CAN_F2R1_FB28 4Ú P CAN_F2R1_FB29 3Ú P CAN_F2R1_FB30 ;Ú P CAN_F2R1_FB31 :Ú P
CAN_F3R1_FB0 oÚ P
CAN_F3R1_FB1 nÚ P
CAN_F3R1_FB2 mÚ P
CAN_F3R1_FB3 lÚ P
CAN_F3R1_FB4 kÚ P
CAN_F3R1_FB5 jÚ P
CAN_F3R1_FB6 iÚ P
CAN_F3R1_FB7 hÚ P
CAN_F3R1_FB8 gÚ P
CAN_F3R1_FB9 fÚ P CAN_F3R1_FB10 <Ú P CAN_F3R1_FB11 ;Ú P CAN_F3R1_FB12 :Ú P CAN_F3R1_FB13 9Ú P CAN_F3R1_FB14 8Ú P CAN_F3R1_FB15 7Ú P CAN_F3R1_FB16 6Ú P CAN_F3R1_FB17 5Ú P CAN_F3R1_FB18 4Ú P CAN_F3R1_FB19 3Ú P CAN_F3R1_FB20 ;Ú P CAN_F3R1_FB21 :Ú P CAN_F3R1_FB22 9Ú P CAN_F3R1_FB23 8Ú P CAN_F3R1_FB24 7Ú P CAN_F3R1_FB25 6Ú P CAN_F3R1_FB26 5Ú P CAN_F3R1_FB27 4Ú P CAN_F3R1_FB28 3Ú P CAN_F3R1_FB29 2Ú P CAN_F3R1_FB30 :Ú P CAN_F3R1_FB31 9Ú P
CAN_F4R1_FB0 nÚ P
CAN_F4R1_FB1 mÚ P
CAN_F4R1_FB2 lÚ P
CAN_F4R1_FB3 kÚ P
CAN_F4R1_FB4 jÚ P
CAN_F4R1_FB5 iÚ P
CAN_F4R1_FB6 hÚ P
CAN_F4R1_FB7 gÚ P
CAN_F4R1_FB8 fÚ P
CAN_F4R1_FB9 eÚ P CAN_F4R1_FB10 ;Ú P CAN_F4R1_FB11 :Ú P CAN_F4R1_FB12 9Ú P CAN_F4R1_FB13 8Ú P CAN_F4R1_FB14 7Ú P CAN_F4R1_FB15 6Ú P CAN_F4R1_FB16 5Ú P CAN_F4R1_FB17 4Ú P CAN_F4R1_FB18 3Ú P CAN_F4R1_FB19 2Ú P CAN_F4R1_FB20 :Ú P CAN_F4R1_FB21 9Ú P CAN_F4R1_FB22 8Ú P CAN_F4R1_FB23 7Ú P CAN_F4R1_FB24 6Ú P CAN_F4R1_FB25 5Ú P CAN_F4R1_FB26 4Ú P CAN_F4R1_FB27 3Ú P CAN_F4R1_FB28 2Ú P CAN_F4R1_FB29 1Ú P CAN_F4R1_FB30 9Ú P CAN_F4R1_FB31 8Ú P
CAN_F5R1_FB0 mÚ P
CAN_F5R1_FB1 lÚ P
CAN_F5R1_FB2 kÚ P
CAN_F5R1_FB3 jÚ P
CAN_F5R1_FB4 iÚ P
CAN_F5R1_FB5 hÚ P
CAN_F5R1_FB6 gÚ P
CAN_F5R1_FB7 fÚ P
CAN_F5R1_FB8 eÚ P
CAN_F5R1_FB9 dÚ P CAN_F5R1_FB10 :Ú P CAN_F5R1_FB11 9Ú P CAN_F5R1_FB12 8Ú P CAN_F5R1_FB13 7Ú P CAN_F5R1_FB14 6Ú P CAN_F5R1_FB15 5Ú P CAN_F5R1_FB16 4Ú P CAN_F5R1_FB17 3Ú P CAN_F5R1_FB18 2Ú P CAN_F5R1_FB19 1Ú P CAN_F5R1_FB20 9Ú P CAN_F5R1_FB21 8Ú P CAN_F5R1_FB22 7Ú P CAN_F5R1_FB23 6Ú P CAN_F5R1_FB24 5Ú P CAN_F5R1_FB25 4Ú P CAN_F5R1_FB26 3Ú P CAN_F5R1_FB27 2Ú P CAN_F5R1_FB28 1Ú P CAN_F5R1_FB29 0Ú P CAN_F5R1_FB30 8Ú P CAN_F5R1_FB31 7Ú P
CAN_F6R1_FB0 lÚ P
CAN_F6R1_FB1 kÚ P
CAN_F6R1_FB2 jÚ P
CAN_F6R1_FB3 iÚ P
CAN_F6R1_FB4 hÚ P
CAN_F6R1_FB5 gÚ P
CAN_F6R1_FB6 fÚ P
CAN_F6R1_FB7 eÚ P
CAN_F6R1_FB8 dÚ P
CAN_F6R1_FB9 cÚ P CAN_F6R1_FB10 9Ú P CAN_F6R1_FB11 8Ú P CAN_F6R1_FB12 7Ú P CAN_F6R1_FB13 6Ú P CAN_F6R1_FB14 5Ú P CAN_F6R1_FB15 4Ú P CAN_F6R1_FB16 3Ú P CAN_F6R1_FB17 2Ú P CAN_F6R1_FB18 1Ú P CAN_F6R1_FB19 0Ú P CAN_F6R1_FB20 8Ú P CAN_F6R1_FB21 7Ú P CAN_F6R1_FB22 6Ú P CAN_F6R1_FB23 5Ú P CAN_F6R1_FB24 4Ú P CAN_F6R1_FB25 3Ú P CAN_F6R1_FB26 2Ú P CAN_F6R1_FB27 1Ú P CAN_F6R1_FB28 0Ú P CAN_F6R1_FB29 /Ú P CAN_F6R1_FB30 7Ú P CAN_F6R1_FB31 6Ú P
CAN_F7R1_FB0 kÚ P
CAN_F7R1_FB1 jÚ P
CAN_F7R1_FB2 iÚ P
CAN_F7R1_FB3 hÚ P
CAN_F7R1_FB4 gÚ P
CAN_F7R1_FB5 fÚ P
CAN_F7R1_FB6 eÚ P
CAN_F7R1_FB7 dÚ P
CAN_F7R1_FB8 cÚ P
CAN_F7R1_FB9 bÚ P CAN_F7R1_FB10 8Ú P CAN_F7R1_FB11 7Ú P CAN_F7R1_FB12 6Ú P CAN_F7R1_FB13 5Ú P CAN_F7R1_FB14 4Ú P CAN_F7R1_FB15 3Ú P CAN_F7R1_FB16 2Ú P CAN_F7R1_FB17 1Ú P CAN_F7R1_FB18 0Ú P CAN_F7R1_FB19 /Ú P CAN_F7R1_FB20 7Ú P CAN_F7R1_FB21 6Ú P CAN_F7R1_FB22 5Ú P CAN_F7R1_FB23 4Ú P CAN_F7R1_FB24 3Ú P CAN_F7R1_FB25 2Ú P CAN_F7R1_FB26 1Ú P CAN_F7R1_FB27 0Ú P CAN_F7R1_FB28 /Ú P CAN_F7R1_FB29 .Ú P CAN_F7R1_FB30 6Ú P CAN_F7R1_FB31 5Ú P
CAN_F8R1_FB0 jÚ P
CAN_F8R1_FB1 iÚ P
CAN_F8R1_FB2 hÚ P
CAN_F8R1_FB3 gÚ P
CAN_F8R1_FB4 fÚ P
CAN_F8R1_FB5 eÚ P
CAN_F8R1_FB6 dÚ P
CAN_F8R1_FB7 cÚ P
CAN_F8R1_FB8 bÚ P
CAN_F8R1_FB9 aÚ P CAN_F8R1_FB10 7Ú P CAN_F8R1_FB11 6Ú P CAN_F8R1_FB12 5Ú P CAN_F8R1_FB13 4Ú P CAN_F8R1_FB14 3Ú P CAN_F8R1_FB15 2Ú P CAN_F8R1_FB16 1Ú P CAN_F8R1_FB17 0Ú P CAN_F8R1_FB18 /Ú P CAN_F8R1_FB19 .Ú P CAN_F8R1_FB20 6Ú P CAN_F8R1_FB21 5Ú P CAN_F8R1_FB22 4Ú P CAN_F8R1_FB23 3Ú P CAN_F8R1_FB24 2Ú P CAN_F8R1_FB25 1Ú P CAN_F8R1_FB26 0Ú P CAN_F8R1_FB27 /Ú P CAN_F8R1_FB28 .Ú P CAN_F8R1_FB29 -Ú P CAN_F8R1_FB30 5Ú P CAN_F8R1_FB31 4Ú P
CAN_F9R1_FB0 iÚ P
CAN_F9R1_FB1 hÚ P
CAN_F9R1_FB2 gÚ P
CAN_F9R1_FB3 fÚ P
CAN_F9R1_FB4 eÚ P
CAN_F9R1_FB5 dÚ P
CAN_F9R1_FB6 cÚ P
CAN_F9R1_FB7 bÚ P
CAN_F9R1_FB8 aÚ P
CAN_F9R1_FB9 `Ú P CAN_F9R1_FB10 6Ú P CAN_F9R1_FB11 5Ú P CAN_F9R1_FB12 4Ú P CAN_F9R1_FB13 3Ú P CAN_F9R1_FB14 2Ú P CAN_F9R1_FB15 1Ú P CAN_F9R1_FB16 0Ú P CAN_F9R1_FB17 /Ú P CAN_F9R1_FB18 .Ú P CAN_F9R1_FB19 -Ú P CAN_F9R1_FB20 5Ú P CAN_F9R1_FB21 4Ú P CAN_F9R1_FB22 3Ú P CAN_F9R1_FB23 2Ú P CAN_F9R1_FB24 1Ú P CAN_F9R1_FB25 0Ú P CAN_F9R1_FB26 /Ú P CAN_F9R1_FB27 .Ú P CAN_F9R1_FB28 -Ú P CAN_F9R1_FB29 ,Ú P CAN_F9R1_FB30 4Ú P CAN_F9R1_FB31 3Ú P CAN_F10R1_FB0 ?Ú P CAN_F10R1_FB1 >Ú P CAN_F10R1_FB2 =Ú P CAN_F10R1_FB3 <Ú P CAN_F10R1_FB4 ;Ú P CAN_F10R1_FB5 :Ú P CAN_F10R1_FB6 9Ú P CAN_F10R1_FB7 8Ú P CAN_F10R1_FB8 7Ú P CAN_F10R1_FB9 6Ú P CAN_F10R1_FB10 Ú P CAN_F10R1_FB11 Ú P CAN_F10R1_FB12
Ú P CAN_F10R1_FB13 Ú P CAN_F10R1_FB14 Ú P CAN_F10R1_FB15 Ú P CAN_F10R1_FB16 Ú P CAN_F10R1_FB17 Ú P CAN_F10R1_FB18 Ú P CAN_F10R1_FB19 Ú P CAN_F10R1_FB20 Ú P CAN_F10R1_FB21
Ú P CAN_F10R1_FB22 Ú P CAN_F10R1_FB23 Ú P CAN_F10R1_FB24 Ú P CAN_F10R1_FB25 Ú P CAN_F10R1_FB26 Ú P CAN_F10R1_FB27 Ú P CAN_F10R1_FB28 Ú P CAN_F10R1_FB29 Ú P CAN_F10R1_FB30
Ú P CAN_F10R1_FB31 Ú P CAN_F11R1_FB0 >Ú P CAN_F11R1_FB1 =Ú P CAN_F11R1_FB2 <Ú P CAN_F11R1_FB3 ;Ú P CAN_F11R1_FB4 :Ú P CAN_F11R1_FB5 9Ú P CAN_F11R1_FB6 8Ú P CAN_F11R1_FB7 7Ú P CAN_F11R1_FB8 6Ú P CAN_F11R1_FB9 5Ú P CAN_F11R1_FB10 Ú P CAN_F11R1_FB11
Ú P CAN_F11R1_FB12 Ú P CAN_F11R1_FB13 Ú P CAN_F11R1_FB14 Ú P CAN_F11R1_FB15 Ú P CAN_F11R1_FB16 Ú P CAN_F11R1_FB17 Ú P CAN_F11R1_FB18 Ú P CAN_F11R1_FB19 Ú P CAN_F11R1_FB20
Ú P CAN_F11R1_FB21 Ú P CAN_F11R1_FB22 Ú P CAN_F11R1_FB23 Ú P CAN_F11R1_FB24 Ú P CAN_F11R1_FB25 Ú P CAN_F11R1_FB26 Ú P CAN_F11R1_FB27 Ú P CAN_F11R1_FB28 Ú P CAN_F11R1_FB29 Ú P CAN_F11R1_FB30 Ú P CAN_F11R1_FB31 Ú P CAN_F12R1_FB0 =Ú P CAN_F12R1_FB1 <Ú P CAN_F12R1_FB2 ;Ú P CAN_F12R1_FB3 :Ú P CAN_F12R1_FB4 9Ú P CAN_F12R1_FB5 8Ú P CAN_F12R1_FB6 7Ú P CAN_F12R1_FB7 6Ú P CAN_F12R1_FB8 5Ú P CAN_F12R1_FB9 4Ú P CAN_F12R1_FB10
Ú P CAN_F12R1_FB11 Ú P CAN_F12R1_FB12 Ú P CAN_F12R1_FB13 Ú P CAN_F12R1_FB14 Ú P CAN_F12R1_FB15 Ú P CAN_F12R1_FB16 Ú P CAN_F12R1_FB17 Ú P CAN_F12R1_FB18 Ú P CAN_F12R1_FB19 Ú P CAN_F12R1_FB20 Ú P CAN_F12R1_FB21 Ú P CAN_F12R1_FB22 Ú P CAN_F12R1_FB23 Ú P CAN_F12R1_FB24 Ú P CAN_F12R1_FB25 Ú P CAN_F12R1_FB26 Ú P CAN_F12R1_FB27 Ú P CAN_F12R1_FB28 Ú P CAN_F12R1_FB29 Ú P CAN_F12R1_FB30 Ú P CAN_F12R1_FB31 Ú P CAN_F13R1_FB0 <Ú P CAN_F13R1_FB1 ;Ú P CAN_F13R1_FB2 :Ú P CAN_F13R1_FB3 9Ú P CAN_F13R1_FB4 8Ú P CAN_F13R1_FB5 7Ú P CAN_F13R1_FB6 6Ú P CAN_F13R1_FB7 5Ú P CAN_F13R1_FB8 4Ú P CAN_F13R1_FB9 3Ú P CAN_F13R1_FB10 Ú P CAN_F13R1_FB11 Ú P CAN_F13R1_FB12 Ú P CAN_F13R1_FB13 Ú P CAN_F13R1_FB14 Ú P CAN_F13R1_FB15 Ú P CAN_F13R1_FB16 Ú P CAN_F13R1_FB17 Ú P CAN_F13R1_FB18 Ú P CAN_F13R1_FB19 Ú P CAN_F13R1_FB20 Ú P CAN_F13R1_FB21 Ú P CAN_F13R1_FB22 Ú P CAN_F13R1_FB23 Ú P CAN_F13R1_FB24 Ú P CAN_F13R1_FB25 Ú P CAN_F13R1_FB26 Ú P CAN_F13R1_FB27 Ú P CAN_F13R1_FB28 Ú P CAN_F13R1_FB29 ÿÚ P CAN_F13R1_FB30 Ú P CAN_F13R1_FB31 Ú P
CAN_F0R2_FB0 qÚ P
CAN_F0R2_FB1 pÚ P
CAN_F0R2_FB2 oÚ P
CAN_F0R2_FB3 nÚ P
CAN_F0R2_FB4 mÚ P
CAN_F0R2_FB5 lÚ P
CAN_F0R2_FB6 kÚ P
CAN_F0R2_FB7 jÚ P
CAN_F0R2_FB8 iÚ P
CAN_F0R2_FB9 hÚ P CAN_F0R2_FB10 >Ú P CAN_F0R2_FB11 =Ú P CAN_F0R2_FB12 <Ú P CAN_F0R2_FB13 ;Ú P CAN_F0R2_FB14 :Ú P CAN_F0R2_FB15 9Ú P CAN_F0R2_FB16 8Ú P CAN_F0R2_FB17 7Ú P CAN_F0R2_FB18 6Ú P CAN_F0R2_FB19 5Ú P CAN_F0R2_FB20 =Ú P CAN_F0R2_FB21 <Ú P CAN_F0R2_FB22 ;Ú P CAN_F0R2_FB23 :Ú P CAN_F0R2_FB24 9Ú P CAN_F0R2_FB25 8Ú P CAN_F0R2_FB26 7Ú P CAN_F0R2_FB27 6Ú P CAN_F0R2_FB28 5Ú P CAN_F0R2_FB29 4Ú P CAN_F0R2_FB30 <Ú P CAN_F0R2_FB31 ;Ú P
CAN_F1R2_FB0 pÚ P
CAN_F1R2_FB1 oÚ P
CAN_F1R2_FB2 nÚ P
CAN_F1R2_FB3 mÚ P
CAN_F1R2_FB4 lÚ P
CAN_F1R2_FB5 kÚ P
CAN_F1R2_FB6 jÚ P
CAN_F1R2_FB7 iÚ P
CAN_F1R2_FB8 hÚ P
CAN_F1R2_FB9 gÚ P CAN_F1R2_FB10 =Ú P CAN_F1R2_FB11 <Ú P CAN_F1R2_FB12 ;Ú P CAN_F1R2_FB13 :Ú P CAN_F1R2_FB14 9Ú P CAN_F1R2_FB15 8Ú P CAN_F1R2_FB16 7Ú P CAN_F1R2_FB17 6Ú P CAN_F1R2_FB18 5Ú P CAN_F1R2_FB19 4Ú P CAN_F1R2_FB20 <Ú P CAN_F1R2_FB21 ;Ú P CAN_F1R2_FB22 :Ú P CAN_F1R2_FB23 9Ú P CAN_F1R2_FB24 8Ú P CAN_F1R2_FB25 7Ú P CAN_F1R2_FB26 6Ú P CAN_F1R2_FB27 5Ú P CAN_F1R2_FB28 4Ú P CAN_F1R2_FB29 3Ú P CAN_F1R2_FB30 ;Ú P CAN_F1R2_FB31 :Ú P
CAN_F2R2_FB0 oÚ P
CAN_F2R2_FB1 nÚ P
CAN_F2R2_FB2 mÚ P
CAN_F2R2_FB3 lÚ P
CAN_F2R2_FB4 kÚ P
CAN_F2R2_FB5 jÚ P
CAN_F2R2_FB6 iÚ P
CAN_F2R2_FB7 hÚ P
CAN_F2R2_FB8 gÚ P
CAN_F2R2_FB9 fÚ P CAN_F2R2_FB10 <Ú P CAN_F2R2_FB11 ;Ú P CAN_F2R2_FB12 :Ú P CAN_F2R2_FB13 9Ú P CAN_F2R2_FB14 8Ú P CAN_F2R2_FB15 7Ú P CAN_F2R2_FB16 6Ú P CAN_F2R2_FB17 5Ú P CAN_F2R2_FB18 4Ú P CAN_F2R2_FB19 3Ú P CAN_F2R2_FB20 ;Ú P CAN_F2R2_FB21 :Ú P CAN_F2R2_FB22 9Ú P CAN_F2R2_FB23 8Ú P CAN_F2R2_FB24 7Ú P CAN_F2R2_FB25 6Ú P CAN_F2R2_FB26 5Ú P CAN_F2R2_FB27 4Ú P CAN_F2R2_FB28 3Ú P CAN_F2R2_FB29 2Ú P CAN_F2R2_FB30 :Ú P CAN_F2R2_FB31 9Ú P
CAN_F3R2_FB0 nÚ P
CAN_F3R2_FB1 mÚ P
CAN_F3R2_FB2 lÚ P
CAN_F3R2_FB3 kÚ P
CAN_F3R2_FB4 jÚ P
CAN_F3R2_FB5 iÚ P
CAN_F3R2_FB6 hÚ P
CAN_F3R2_FB7 gÚ P
CAN_F3R2_FB8 fÚ P
CAN_F3R2_FB9 eÚ P CAN_F3R2_FB10 ;Ú P CAN_F3R2_FB11 :Ú P CAN_F3R2_FB12 9Ú P CAN_F3R2_FB13 8Ú P CAN_F3R2_FB14 7Ú P CAN_F3R2_FB15 6Ú P CAN_F3R2_FB16 5Ú P CAN_F3R2_FB17 4Ú P CAN_F3R2_FB18 3Ú P CAN_F3R2_FB19 2Ú P CAN_F3R2_FB20 :Ú P CAN_F3R2_FB21 9Ú P CAN_F3R2_FB22 8Ú P CAN_F3R2_FB23 7Ú P CAN_F3R2_FB24 6Ú P CAN_F3R2_FB25 5Ú P CAN_F3R2_FB26 4Ú P CAN_F3R2_FB27 3Ú P CAN_F3R2_FB28 2Ú P CAN_F3R2_FB29 1Ú P CAN_F3R2_FB30 9Ú P CAN_F3R2_FB31 8Ú P
CAN_F4R2_FB0 mÚ P
CAN_F4R2_FB1 lÚ P
CAN_F4R2_FB2 kÚ P
CAN_F4R2_FB3 jÚ P
CAN_F4R2_FB4 iÚ P
CAN_F4R2_FB5 hÚ P
CAN_F4R2_FB6 gÚ P
CAN_F4R2_FB7 fÚ P
CAN_F4R2_FB8 eÚ P
CAN_F4R2_FB9 dÚ P CAN_F4R2_FB10 :Ú P CAN_F4R2_FB11 9Ú P CAN_F4R2_FB12 8Ú P CAN_F4R2_FB13 7Ú P CAN_F4R2_FB14 6Ú P CAN_F4R2_FB15 5Ú P CAN_F4R2_FB16 4Ú P CAN_F4R2_FB17 3Ú P CAN_F4R2_FB18 2Ú P CAN_F4R2_FB19 1Ú P CAN_F4R2_FB20 9Ú P CAN_F4R2_FB21 8Ú P CAN_F4R2_FB22 7Ú P CAN_F4R2_FB23 6Ú P CAN_F4R2_FB24 5Ú P CAN_F4R2_FB25 4Ú P CAN_F4R2_FB26 3Ú P CAN_F4R2_FB27 2Ú P CAN_F4R2_FB28 1Ú P CAN_F4R2_FB29 0Ú P CAN_F4R2_FB30 8Ú P CAN_F4R2_FB31 7Ú P
CAN_F5R2_FB0 lÚ P
CAN_F5R2_FB1 kÚ P
CAN_F5R2_FB2 jÚ P
CAN_F5R2_FB3 iÚ P
CAN_F5R2_FB4 hÚ P
CAN_F5R2_FB5 gÚ P
CAN_F5R2_FB6 fÚ P
CAN_F5R2_FB7 eÚ P
CAN_F5R2_FB8 dÚ P
CAN_F5R2_FB9 cÚ P CAN_F5R2_FB10 9Ú P CAN_F5R2_FB11 8Ú P CAN_F5R2_FB12 7Ú P CAN_F5R2_FB13 6Ú P CAN_F5R2_FB14 5Ú P CAN_F5R2_FB15 4Ú P CAN_F5R2_FB16 3Ú P CAN_F5R2_FB17 2Ú P CAN_F5R2_FB18 1Ú P CAN_F5R2_FB19 0Ú P CAN_F5R2_FB20 8Ú P CAN_F5R2_FB21 7Ú P CAN_F5R2_FB22 6Ú P CAN_F5R2_FB23 5Ú P CAN_F5R2_FB24 4Ú P CAN_F5R2_FB25 3Ú P CAN_F5R2_FB26 2Ú P CAN_F5R2_FB27 1Ú P CAN_F5R2_FB28 0Ú P CAN_F5R2_FB29 /Ú P CAN_F5R2_FB30 7Ú P CAN_F5R2_FB31 6Ú P
CAN_F6R2_FB0 kÚ P
CAN_F6R2_FB1 jÚ P
CAN_F6R2_FB2 iÚ P
CAN_F6R2_FB3 hÚ P
CAN_F6R2_FB4 gÚ P
CAN_F6R2_FB5 fÚ P
CAN_F6R2_FB6 eÚ P
CAN_F6R2_FB7 dÚ P
CAN_F6R2_FB8 cÚ P
CAN_F6R2_FB9 bÚ P CAN_F6R2_FB10 8Ú P CAN_F6R2_FB11 7Ú P CAN_F6R2_FB12 6Ú P CAN_F6R2_FB13 5Ú P CAN_F6R2_FB14 4Ú P CAN_F6R2_FB15 3Ú P CAN_F6R2_FB16 2Ú P CAN_F6R2_FB17 1Ú P CAN_F6R2_FB18 0Ú P CAN_F6R2_FB19 /Ú P CAN_F6R2_FB20 7Ú P CAN_F6R2_FB21 6Ú P CAN_F6R2_FB22 5Ú P CAN_F6R2_FB23 4Ú P CAN_F6R2_FB24 3Ú P CAN_F6R2_FB25 2Ú P CAN_F6R2_FB26 1Ú P CAN_F6R2_FB27 0Ú P CAN_F6R2_FB28 /Ú P CAN_F6R2_FB29 .Ú P CAN_F6R2_FB30 6Ú P CAN_F6R2_FB31 5Ú P
CAN_F7R2_FB0 jÚ P
CAN_F7R2_FB1 iÚ P
CAN_F7R2_FB2 hÚ P
CAN_F7R2_FB3 gÚ P
CAN_F7R2_FB4 fÚ P
CAN_F7R2_FB5 eÚ P
CAN_F7R2_FB6 dÚ P
CAN_F7R2_FB7 cÚ P
CAN_F7R2_FB8 bÚ P
CAN_F7R2_FB9 aÚ P CAN_F7R2_FB10 7Ú P CAN_F7R2_FB11 6Ú P CAN_F7R2_FB12 5Ú P CAN_F7R2_FB13 4Ú P CAN_F7R2_FB14 3Ú P CAN_F7R2_FB15 2Ú P CAN_F7R2_FB16 1Ú P CAN_F7R2_FB17 0Ú P CAN_F7R2_FB18 /Ú P CAN_F7R2_FB19 .Ú P CAN_F7R2_FB20 6Ú P CAN_F7R2_FB21 5Ú P CAN_F7R2_FB22 4Ú P CAN_F7R2_FB23 3Ú P CAN_F7R2_FB24 2Ú P CAN_F7R2_FB25 1Ú P CAN_F7R2_FB26 0Ú P CAN_F7R2_FB27 /Ú P CAN_F7R2_FB28 .Ú P CAN_F7R2_FB29 -Ú P CAN_F7R2_FB30 5Ú P CAN_F7R2_FB31 4Ú P
CAN_F8R2_FB0 iÚ P
CAN_F8R2_FB1 hÚ P
CAN_F8R2_FB2 gÚ P
CAN_F8R2_FB3 fÚ P
CAN_F8R2_FB4 eÚ P
CAN_F8R2_FB5 dÚ P
CAN_F8R2_FB6 cÚ P
CAN_F8R2_FB7 bÚ P
CAN_F8R2_FB8 aÚ P
CAN_F8R2_FB9 `Ú P CAN_F8R2_FB10 6Ú P CAN_F8R2_FB11 5Ú P CAN_F8R2_FB12 4Ú P CAN_F8R2_FB13 3Ú P CAN_F8R2_FB14 2Ú P CAN_F8R2_FB15 1Ú P CAN_F8R2_FB16 0Ú P CAN_F8R2_FB17 /Ú P CAN_F8R2_FB18 .Ú P CAN_F8R2_FB19 -Ú P CAN_F8R2_FB20 5Ú P CAN_F8R2_FB21 4Ú P CAN_F8R2_FB22 3Ú P CAN_F8R2_FB23 2Ú P CAN_F8R2_FB24 1Ú P CAN_F8R2_FB25 0Ú P CAN_F8R2_FB26 /Ú P CAN_F8R2_FB27 .Ú P CAN_F8R2_FB28 -Ú P CAN_F8R2_FB29 ,Ú P CAN_F8R2_FB30 4Ú P CAN_F8R2_FB31 3Ú P
CAN_F9R2_FB0 hÚ P
CAN_F9R2_FB1 gÚ P
CAN_F9R2_FB2 fÚ P
CAN_F9R2_FB3 eÚ P
CAN_F9R2_FB4 dÚ P
CAN_F9R2_FB5 cÚ P
CAN_F9R2_FB6 bÚ P
CAN_F9R2_FB7 aÚ P
CAN_F9R2_FB8 `Ú P
CAN_F9R2_FB9 _Ú P CAN_F9R2_FB10 5Ú P CAN_F9R2_FB11 4Ú P CAN_F9R2_FB12 3Ú P CAN_F9R2_FB13 2Ú P CAN_F9R2_FB14 1Ú P CAN_F9R2_FB15 0Ú P CAN_F9R2_FB16 /Ú P CAN_F9R2_FB17 .Ú P CAN_F9R2_FB18 -Ú P CAN_F9R2_FB19 ,Ú P CAN_F9R2_FB20 4Ú P CAN_F9R2_FB21 3Ú P CAN_F9R2_FB22 2Ú P CAN_F9R2_FB23 1Ú P CAN_F9R2_FB24 0Ú P CAN_F9R2_FB25 /Ú P CAN_F9R2_FB26 .Ú P CAN_F9R2_FB27 -Ú P CAN_F9R2_FB28 ,Ú P CAN_F9R2_FB29 +Ú P CAN_F9R2_FB30 3Ú P CAN_F9R2_FB31 2Ú P CAN_F10R2_FB0 >Ú P CAN_F10R2_FB1 =Ú P CAN_F10R2_FB2 <Ú P CAN_F10R2_FB3 ;Ú P CAN_F10R2_FB4 :Ú P CAN_F10R2_FB5 9Ú P CAN_F10R2_FB6 8Ú P CAN_F10R2_FB7 7Ú P CAN_F10R2_FB8 6Ú P CAN_F10R2_FB9 5Ú P CAN_F10R2_FB10 Ú P CAN_F10R2_FB11
Ú P CAN_F10R2_FB12 Ú P CAN_F10R2_FB13 Ú P CAN_F10R2_FB14 Ú P CAN_F10R2_FB15 Ú P CAN_F10R2_FB16 Ú P CAN_F10R2_FB17 Ú P CAN_F10R2_FB18 Ú P CAN_F10R2_FB19 Ú P CAN_F10R2_FB20
Ú P CAN_F10R2_FB21 Ú P CAN_F10R2_FB22 Ú P CAN_F10R2_FB23 Ú P CAN_F10R2_FB24 Ú P CAN_F10R2_FB25 Ú P CAN_F10R2_FB26 Ú P CAN_F10R2_FB27 Ú P CAN_F10R2_FB28 Ú P CAN_F10R2_FB29 Ú P CAN_F10R2_FB30 Ú P CAN_F10R2_FB31 Ú P CAN_F11R2_FB0 =Ú P CAN_F11R2_FB1 <Ú P CAN_F11R2_FB2 ;Ú P CAN_F11R2_FB3 :Ú P CAN_F11R2_FB4 9Ú P CAN_F11R2_FB5 8Ú P CAN_F11R2_FB6 7Ú P CAN_F11R2_FB7 6Ú P CAN_F11R2_FB8 5Ú P CAN_F11R2_FB9 4Ú P CAN_F11R2_FB10
Ú P CAN_F11R2_FB11 Ú P CAN_F11R2_FB12 Ú P CAN_F11R2_FB13 Ú P CAN_F11R2_FB14 Ú P CAN_F11R2_FB15 Ú P CAN_F11R2_FB16 Ú P CAN_F11R2_FB17 Ú P CAN_F11R2_FB18 Ú P CAN_F11R2_FB19 Ú P CAN_F11R2_FB20 Ú P CAN_F11R2_FB21 Ú P CAN_F11R2_FB22 Ú P CAN_F11R2_FB23 Ú P CAN_F11R2_FB24 Ú P CAN_F11R2_FB25 Ú P CAN_F11R2_FB26 Ú P CAN_F11R2_FB27 Ú P CAN_F11R2_FB28 Ú P CAN_F11R2_FB29 Ú P CAN_F11R2_FB30 Ú P CAN_F11R2_FB31 Ú P CAN_F12R2_FB0 <Ú P CAN_F12R2_FB1 ;Ú P CAN_F12R2_FB2 :Ú P CAN_F12R2_FB3 9Ú P CAN_F12R2_FB4 8Ú P CAN_F12R2_FB5 7Ú P CAN_F12R2_FB6 6Ú P CAN_F12R2_FB7 5Ú P CAN_F12R2_FB8 4Ú P CAN_F12R2_FB9 3Ú P CAN_F12R2_FB10 Ú P CAN_F12R2_FB11 Ú P CAN_F12R2_FB12 Ú P CAN_F12R2_FB13 Ú P CAN_F12R2_FB14 Ú P CAN_F12R2_FB15 Ú P CAN_F12R2_FB16 Ú P CAN_F12R2_FB17 Ú P CAN_F12R2_FB18 Ú P CAN_F12R2_FB19 Ú P CAN_F12R2_FB20 Ú P CAN_F12R2_FB21 Ú P CAN_F12R2_FB22 Ú P CAN_F12R2_FB23 Ú P CAN_F12R2_FB24 Ú P CAN_F12R2_FB25 Ú P CAN_F12R2_FB26 Ú P CAN_F12R2_FB27 Ú P CAN_F12R2_FB28 Ú P CAN_F12R2_FB29 ÿÚ P CAN_F12R2_FB30 Ú P CAN_F12R2_FB31 Ú P CAN_F13R2_FB0 ;Ú P CAN_F13R2_FB1 :Ú P CAN_F13R2_FB2 9Ú P CAN_F13R2_FB3 8Ú P CAN_F13R2_FB4 7Ú P CAN_F13R2_FB5 6Ú P CAN_F13R2_FB6 5Ú P CAN_F13R2_FB7 4Ú P CAN_F13R2_FB8 3Ú P CAN_F13R2_FB9 2Ú P CAN_F13R2_FB10 Ú P CAN_F13R2_FB11 Ú P CAN_F13R2_FB12 Ú P CAN_F13R2_FB13 Ú P CAN_F13R2_FB14 Ú P CAN_F13R2_FB15 Ú P CAN_F13R2_FB16 Ú P CAN_F13R2_FB17 Ú P CAN_F13R2_FB18 Ú P CAN_F13R2_FB19 ÿÚ P CAN_F13R2_FB20 Ú P CAN_F13R2_FB21 Ú P CAN_F13R2_FB22 Ú P CAN_F13R2_FB23 Ú P CAN_F13R2_FB24 Ú P CAN_F13R2_FB25 Ú P CAN_F13R2_FB26 Ú P CAN_F13R2_FB27 Ú P CAN_F13R2_FB28 ÿÚ P CAN_F13R2_FB29 þÚ P CAN_F13R2_FB30 Ú P CAN_F13R2_FB31 Ú P
SPI_CR1_CPHA 'Ú P
SPI_CR1_CPOL Ú P
SPI_CR1_MSTR ýÚ P SPI_CR1_BR ³Ú P
SPI_CR1_BR_0 Ú P
SPI_CR1_BR_1 Ú P
SPI_CR1_BR_2 Ú P SPI_CR1_SPE ]Ú P SPI_CR1_LSBFIRST ÒÚ P SPI_CR1_SSI VÚ P SPI_CR1_SSM RÚ P SPI_CR1_RXONLY SÚ P SPI_CR1_DFF uÚ P SPI_CR1_CRCNEXT &Ú P SPI_CR1_CRCEN ÖÚ P SPI_CR1_BIDIOE Ú P SPI_CR1_BIDIMODE þÚ P SPI_CR2_RXDMAEN -Ú P SPI_CR2_TXDMAEN +Ú P
SPI_CR2_SSOE Ú P SPI_CR2_ERRIE ÉÚ P SPI_CR2_RXNEIE sÚ P SPI_CR2_TXEIE ÁÚ P SPI_SR_RXNE )Ú P SPI_SR_TXE wÚ P SPI_SR_CHSIDE ²Ú P SPI_SR_UDR }Ú P SPI_SR_CRCERR ¡Ú P SPI_SR_MODF @Ú P SPI_SR_OVR qÚ P SPI_SR_BSY zÚ P
SPI_DR_DR ãÚ P SPI_CRCPR_CRCPOLY iÚ P SPI_RXCRCR_RXCRC «Ú P SPI_TXCRCR_TXCRC §Ú P SPI_I2SCFGR_CHLEN ¥Ú P SPI_I2SCFGR_DATLEN UÚ P SPI_I2SCFGR_DATLEN_0 ÂÚ P SPI_I2SCFGR_DATLEN_1 ÁÚ P SPI_I2SCFGR_CKPOL Ú P SPI_I2SCFGR_I2SSTD TÚ P SPI_I2SCFGR_I2SSTD_0 ÁÚ P SPI_I2SCFGR_I2SSTD_1 ÀÚ P SPI_I2SCFGR_PCMSYNC îÚ P SPI_I2SCFGR_I2SCFG oÚ P SPI_I2SCFGR_I2SCFG_0 ÜÚ P SPI_I2SCFGR_I2SCFG_1 ÛÚ P SPI_I2SCFGR_I2SE þÚ P SPI_I2SCFGR_I2SMOD _Ú P SPI_I2SPR_I2SDIV àÚ P SPI_I2SPR_ODD ÀÚ P SPI_I2SPR_MCKOE $Ú P I2C_CR1_PE àÚ P I2C_CR1_SMBUS åÚ P I2C_CR1_SMBTYPE GÚ P I2C_CR1_ENARP ùÚ P I2C_CR1_ENPEC Ú P
I2C_CR1_ENGC TÚ P I2C_CR1_NOSTRETCH Ú P I2C_CR1_START áÚ P
I2C_CR1_STOP +Ú P I2C_CR1_ACK ¤Ú P I2C_CR1_POS Ú P I2C_CR1_PEC Ú P I2C_CR1_ALERT ÷Ú P I2C_CR1_SWRST ÌÚ P
I2C_CR2_FREQ BÚ P I2C_CR2_FREQ_0 ¯Ú P I2C_CR2_FREQ_1 ®Ú P I2C_CR2_FREQ_2 Ú P I2C_CR2_FREQ_3 ¬Ú P I2C_CR2_FREQ_4 «Ú P I2C_CR2_FREQ_5 ªÚ P I2C_CR2_ITERREN QÚ P I2C_CR2_ITEVTEN KÚ P I2C_CR2_ITBUFEN ]Ú P I2C_CR2_DMAEN Ú P
I2C_CR2_LAST <Ú P I2C_OAR1_ADD1_7 Ú P I2C_OAR1_ADD8_9
Ú P I2C_OAR1_ADD0 )Ú P I2C_OAR1_ADD1 (Ú P I2C_OAR1_ADD2 'Ú P I2C_OAR1_ADD3 &Ú P I2C_OAR1_ADD4 %Ú P I2C_OAR1_ADD5 $Ú P I2C_OAR1_ADD6 #Ú P I2C_OAR1_ADD7 "Ú P I2C_OAR1_ADD8 !Ú P I2C_OAR1_ADD9 Ú P I2C_OAR1_ADDMODE .Ú P I2C_OAR2_ENDUAL dÚ P I2C_OAR2_ADD2 &Ú P
I2C_DR_DR Ú P I2C_SR1_SB ÐÚ P
I2C_SR1_ADDR FÚ P I2C_SR1_BTF Ú P I2C_SR1_ADD10 5Ú P I2C_SR1_STOPF ÓÚ P
I2C_SR1_RXNE $Ú P I2C_SR1_TXE rÚ P
I2C_SR1_BERR 6Ú P
I2C_SR1_ARLO 3Ú P I2C_SR1_AF ÞÚ P I2C_SR1_OVR lÚ P I2C_SR1_PECERR Ú P I2C_SR1_TIMEOUT 4Ú P I2C_SR1_SMBALERT ÿÚ P I2C_SR2_MSL vÚ P
I2C_SR2_BUSY Ú P I2C_SR2_TRA {Ú P I2C_SR2_GENCALL dÚ P I2C_SR2_SMBDEFAULT mÚ P I2C_SR2_SMBHOST :Ú P I2C_SR2_DUALF òÚ P I2C_SR2_PEC Ú P I2C_CCR_CCR Ú P
I2C_CCR_DUTY Ú P I2C_CCR_FS ÊÚ P I2C_TRISE_TRISE #Ú P USART_SR_PE .Ú P USART_SR_FE 8Ú P USART_SR_NE 0Ú P
USART_SR_ORE ÛÚ P USART_SR_IDLE ¡Ú P USART_SR_RXNE Ú P USART_SR_TC ,Ú P
USART_SR_TXE ÐÚ P
USART_SR_LBD ïÚ P
USART_SR_CTS ×Ú P USART_DR_DR <Ú P USART_BRR_DIV_Fraction ôÚ P USART_BRR_DIV_Mantissa êÚ P USART_CR1_SBK ¾Ú P USART_CR1_RWU Ú P
USART_CR1_RE Ú P
USART_CR1_TE Ú P USART_CR1_IDLEIE ìÚ P USART_CR1_RXNEIE ÍÚ P USART_CR1_TCIE wÚ P USART_CR1_TXEIE Ú P USART_CR1_PEIE yÚ P
USART_CR1_PS ýÚ P USART_CR1_PCE ÆÚ P USART_CR1_WAKE tÚ P USART_CR1_M UÚ P
USART_CR1_UE Ú P USART_CR1_OVER8 &Ú P USART_CR2_ADD ÔÚ P USART_CR2_LBDL }Ú P USART_CR2_LBDIE 9Ú P USART_CR2_LBCL ~Ú P USART_CR2_CPHA Ú P USART_CR2_CPOL mÚ P USART_CR2_CLKEN ,Ú P USART_CR2_STOP UÚ P USART_CR2_STOP_0 ÂÚ P USART_CR2_STOP_1 ÁÚ P USART_CR2_LINEN #Ú P USART_CR3_EIE ÉÚ P USART_CR3_IREN lÚ P USART_CR3_IRLP cÚ P USART_CR3_HDSEL (Ú P USART_CR3_NACK }Ú P USART_CR3_SCEN qÚ P USART_CR3_DMAR vÚ P USART_CR3_DMAT tÚ P USART_CR3_RTSE \Ú P USART_CR3_CTSE kÚ P USART_CR3_CTSIE Ú P USART_CR3_ONEBIT ÕÚ P USART_GTPR_PSC ?Ú P USART_GTPR_PSC_0 ¬Ú P USART_GTPR_PSC_1 «Ú P USART_GTPR_PSC_2 ªÚ P USART_GTPR_PSC_3 ©Ú P USART_GTPR_PSC_4 ¨Ú P USART_GTPR_PSC_5 §Ú P USART_GTPR_PSC_6 ¦Ú P USART_GTPR_PSC_7 ¥Ú P USART_GTPR_GT Ú P DBGMCU_IDCODE_DEV_ID ÀÚ P DBGMCU_IDCODE_REV_ID ²Ú P DBGMCU_IDCODE_REV_ID_0 Ú P DBGMCU_IDCODE_REV_ID_1 Ú P DBGMCU_IDCODE_REV_ID_2 Ú P DBGMCU_IDCODE_REV_ID_3 Ú P DBGMCU_IDCODE_REV_ID_4 Ú P DBGMCU_IDCODE_REV_ID_5 Ú P DBGMCU_IDCODE_REV_ID_6 Ú P DBGMCU_IDCODE_REV_ID_7 Ú P DBGMCU_IDCODE_REV_ID_8 Ú P DBGMCU_IDCODE_REV_ID_9 Ú P DBGMCU_IDCODE_REV_ID_10 ìÚ P DBGMCU_IDCODE_REV_ID_11 ëÚ P DBGMCU_IDCODE_REV_ID_12 êÚ P DBGMCU_IDCODE_REV_ID_13 éÚ P DBGMCU_IDCODE_REV_ID_14 èÚ P DBGMCU_IDCODE_REV_ID_15 çÚ P DBGMCU_CR_DBG_SLEEP ûÚ P DBGMCU_CR_DBG_STOP 0Ú P DBGMCU_CR_DBG_STANDBY [Ú P DBGMCU_CR_TRACE_IOEN ¥Ú P DBGMCU_CR_TRACE_MODE «Ú P DBGMCU_CR_TRACE_MODE_0 Ú P DBGMCU_CR_TRACE_MODE_1 Ú P DBGMCU_CR_DBG_IWDG_STOP Ú P DBGMCU_CR_DBG_WWDG_STOP Ú P DBGMCU_CR_DBG_TIM1_STOP ¬Ú P DBGMCU_CR_DBG_TIM2_STOP «Ú P DBGMCU_CR_DBG_TIM3_STOP ªÚ P DBGMCU_CR_DBG_TIM4_STOP ©Ú P DBGMCU_CR_DBG_CAN1_STOP ÄÚ) P !DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT üÚ) P !DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ûÚ P DBGMCU_CR_DBG_TIM8_STOP ¥Ú P DBGMCU_CR_DBG_TIM5_STOP ¨Ú P DBGMCU_CR_DBG_TIM6_STOP §Ú P DBGMCU_CR_DBG_TIM7_STOP ¦Ú P DBGMCU_CR_DBG_CAN2_STOP ÃÚ! P DBGMCU_CR_DBG_TIM15_STOP uÚ! P DBGMCU_CR_DBG_TIM16_STOP tÚ! P DBGMCU_CR_DBG_TIM17_STOP sÚ! P DBGMCU_CR_DBG_TIM12_STOP xÚ! P DBGMCU_CR_DBG_TIM13_STOP wÚ! P DBGMCU_CR_DBG_TIM14_STOP vÚ P DBGMCU_CR_DBG_TIM9_STOP ¤Ú! P DBGMCU_CR_DBG_TIM10_STOP zÚ! P DBGMCU_CR_DBG_TIM11_STOP yÚ P FLASH_ACR_LATENCY Ú P FLASH_ACR_LATENCY_0 Ú P FLASH_ACR_LATENCY_1 Ú P FLASH_ACR_LATENCY_2 Ú P FLASH_ACR_HLFCYA òÚ P FLASH_ACR_PRFTBE æÚ P FLASH_ACR_PRFTBS ØÚ P FLASH_KEYR_FKEYR ÃÚ P FLASH_OPTKEYR_OPTKEYR Ú P
FLASH_SR_BSY ôÚ P FLASH_SR_PGERR ^Ú P FLASH_SR_WRPRTERR PÚ P
FLASH_SR_EOP þÚ P FLASH_CR_PG ]Ú P
FLASH_CR_PER Ú P
FLASH_CR_MER Ú P FLASH_CR_OPTPG dÚ P FLASH_CR_OPTER dÚ P FLASH_CR_STRT £Ú P FLASH_CR_LOCK ÇÚ P FLASH_CR_OPTWRE Ú P FLASH_CR_ERRIE wÚ P FLASH_CR_EOPIE |Ú P
FLASH_AR_FAR Ú P FLASH_OBR_OPTERR ÀÚ P FLASH_OBR_RDPRT Ú P FLASH_OBR_USER aÚ P FLASH_OBR_WDG_SW ±Ú P FLASH_OBR_nRST_STOP Ú P FLASH_OBR_nRST_STDBY HÚ P FLASH_OBR_BFB2 ¤Ú P FLASH_WRPR_WRP ?Ú P FLASH_RDP_RDP ¹Ú P FLASH_RDP_nRDP IÚ P FLASH_USER_USER Ú P FLASH_USER_nUSER Ú P FLASH_Data0_Data0 )Ú P FLASH_Data0_nData0 ¹Ú P FLASH_Data1_Data1 'Ú P FLASH_Data1_nData1 ·Ú P FLASH_WRP0_WRP0 /Ú P FLASH_WRP0_nWRP0 ¿Ú P FLASH_WRP1_WRP1 -Ú P FLASH_WRP1_nWRP1 ½Ú P FLASH_WRP2_WRP2 +Ú P FLASH_WRP2_nWRP2 »Ú P FLASH_WRP3_WRP3 )Ú P FLASH_WRP3_nWRP3 ¹Ú P USE_STDPERIPH_DRIVER wÚ P SET_BIT Ú P
CLEAR_BIT Ú P READ_BIT aÚ P
CLEAR_REG Ú P
WRITE_REG ñÚ P READ_REG bÚ P MODIFY_REG ²Ú 8
<unnamed> QÚ " 9CR1 2Ú " 9_resvd0 =Ú " 9CR2 1Ú " 9_resvd1 <Ú " 9SMCR ÁÚ " 9_resvd2 ;Ú " 9DIER ÒÚ " 9_resvd3 :Ú
" 9SR UÚ " 9_resvd4 9Ú " 9EGR Ú " 9_resvd5 8Ú " 9CCMR1 Ú " 9_resvd6 7Ú " 9CCMR2 Ú " 9_resvd7 6Ú " 9CCER ÙÚ " 9_resvd8 5Ú
" 9CNT Ú " 9PSC Ú " 9_resvd9 4Ú
" 9ARR Ú " 9RCR Ú " 9 _resvd10
Ú <" 9CCR äÚ " 9BDTR ÊÚ " 9 _resvd11 Ú " 9DCR Ú " 9 _resvd12 Ú " 9DMAR ÒÚ " 9 _resvd13 Ú
" 9OR YÚ " 9 _resvd14 Ú stm32_tim_t ¶Ú P STM32_TIM1 äÚ P STM32_TIM2 ãÚ P STM32_TIM3 âÚ P STM32_TIM4 áÚ P STM32_TIM5 àÚ P STM32_TIM6 ßÚ P STM32_TIM7 ÞÚ P STM32_TIM8 ÝÚ P STM32_TIM9 ÜÚ P STM32_TIM10 ²Ú P STM32_TIM11 ±Ú P STM32_TIM12 °Ú P STM32_TIM13 ¯Ú P STM32_TIM14 ®Ú P HAL_IMPLEMENTS_COUNTERS Ú P
STM32_HSICLK =Ú P
STM32_LSICLK 9Ú P STM32_PLS_MASK }Ú P STM32_PLS_LEV0 Ú P STM32_PLS_LEV1 Ú P STM32_PLS_LEV2 Ú P STM32_PLS_LEV3 Ú P STM32_PLS_LEV4 Ú P STM32_PLS_LEV5 Ú P STM32_PLS_LEV6 Ú P STM32_PLS_LEV7 Ú P STM32_HAS_RTC ÕÚ! P STM32_RTC_HAS_SUBSECONDS gÚ P STM32_RTC_IS_CALENDAR lÚ P _HAL_LLD_F103_H_ ýÚ P PLATFORM_NAME ÌÚ P STM32_SYSCLK_MAX ÕÚ P STM32_HSECLK_MAX ôÚ P STM32_HSECLK_MIN öÚ P STM32_LSECLK_MAX ðÚ P STM32_LSECLK_MIN òÚ P STM32_PLLIN_MAX 1Ú P STM32_PLLIN_MIN 3Ú P STM32_PLLOUT_MAX ÎÚ P STM32_PLLOUT_MIN ÐÚ P STM32_PCLK1_MAX UÚ P STM32_PCLK2_MAX TÚ P STM32_ADCCLK_MAX Ú P
STM32_SW_HSI Ú P
STM32_SW_HSE Ú P
STM32_SW_PLL
Ú P STM32_HPRE_DIV1 SÚ P STM32_HPRE_DIV2 RÚ P STM32_HPRE_DIV4 PÚ P STM32_HPRE_DIV8 LÚ P STM32_HPRE_DIV16 Ú P STM32_HPRE_DIV64 Ú P STM32_HPRE_DIV128 åÚ P STM32_HPRE_DIV256 ãÚ P STM32_HPRE_DIV512 èÚ P STM32_PPRE1_DIV1 Ú P STM32_PPRE1_DIV2 Ú P STM32_PPRE1_DIV4 Ú P STM32_PPRE1_DIV8 Ú P STM32_PPRE1_DIV16 àÚ P STM32_PPRE2_DIV1 Ú P STM32_PPRE2_DIV2 Ú P STM32_PPRE2_DIV4 Ú P STM32_PPRE2_DIV8 Ú P STM32_PPRE2_DIV16 ßÚ P STM32_ADCPRE_DIV2 ÎÚ P STM32_ADCPRE_DIV4 ÌÚ P STM32_ADCPRE_DIV6 ÊÚ P STM32_ADCPRE_DIV8 ÈÚ P STM32_PLLSRC_HSI àÚ P STM32_PLLSRC_HSE äÚ P STM32_PLLXTPRE_DIV1 ÿÚ P STM32_PLLXTPRE_DIV2 þÚ P STM32_USBPRE_DIV1P5 $Ú P STM32_USBPRE_DIV1 Ú P STM32_MCOSEL_NOCLOCK ÀÚ P STM32_MCOSEL_SYSCLK òÚ P STM32_MCOSEL_HSI íÚ P STM32_MCOSEL_HSE ñÚ P STM32_MCOSEL_PLLDIV2 ÌÚ P STM32_RTCSEL_MASK Ú P STM32_RTCSEL_NOCLOCK ¶Ú P STM32_RTCSEL_LSE ãÚ P STM32_RTCSEL_LSI ßÚ P STM32_RTCSEL_HSEDIV þÚ P STM32_HAS_ADC1 ÃÚ P STM32_HAS_ADC2 ÂÚ P STM32_HAS_ADC3 ÁÚ P STM32_HAS_CAN1 ¹Ú P STM32_HAS_CAN2 ¸Ú P STM32_CAN_MAX_FILTERS ZÚ P STM32_HAS_DAC öÚ P STM32_ADVANCED_DMA Ú P STM32_HAS_DMA1 ¹Ú P STM32_HAS_DMA2 ¸Ú P STM32_HAS_ETH ÝÚ P STM32_EXTI_NUM_CHANNELS ±Ú P STM32_HAS_GPIOA JÚ P STM32_HAS_GPIOB IÚ P STM32_HAS_GPIOC HÚ P STM32_HAS_GPIOD GÚ P STM32_HAS_GPIOE FÚ P STM32_HAS_GPIOF EÚ P STM32_HAS_GPIOG DÚ P STM32_HAS_GPIOH CÚ P STM32_HAS_GPIOI BÚ P STM32_HAS_I2C1 ÍÚ P STM32_I2C1_RX_DMA_MSK vÚ P STM32_I2C1_RX_DMA_CHN Ú P STM32_I2C1_TX_DMA_MSK tÚ P STM32_I2C1_TX_DMA_CHN Ú P STM32_HAS_I2C2 ÌÚ P STM32_I2C2_RX_DMA_MSK uÚ P STM32_I2C2_RX_DMA_CHN Ú P STM32_I2C2_TX_DMA_MSK sÚ P STM32_I2C2_TX_DMA_CHN
Ú P STM32_HAS_I2C3 ËÚ P STM32_I2C3_RX_DMA_MSK tÚ P STM32_I2C3_RX_DMA_CHN Ú P STM32_I2C3_TX_DMA_MSK rÚ P STM32_I2C3_TX_DMA_CHN Ú$ P STM32_RTCSEL_HAS_SUBSECONDS }Ú P STM32_HAS_SDIO Ú P STM32_HAS_SPI1 Ú P STM32_SPI1_RX_DMA_MSK HÚ P STM32_SPI1_RX_DMA_CHN ZÚ P STM32_SPI1_TX_DMA_MSK FÚ P STM32_SPI1_TX_DMA_CHN XÚ P STM32_HAS_SPI2 Ú P STM32_SPI2_RX_DMA_MSK GÚ P STM32_SPI2_RX_DMA_CHN YÚ P STM32_SPI2_TX_DMA_MSK EÚ P STM32_SPI2_TX_DMA_CHN WÚ P STM32_HAS_SPI3 Ú P STM32_SPI3_RX_DMA_MSK FÚ P STM32_SPI3_RX_DMA_CHN XÚ P STM32_SPI3_TX_DMA_MSK DÚ P STM32_SPI3_TX_DMA_CHN VÚ P STM32_HAS_TIM1 ¡Ú P STM32_HAS_TIM2 Ú P STM32_HAS_TIM3 Ú P STM32_HAS_TIM4 Ú P STM32_HAS_TIM5 Ú P STM32_HAS_TIM6 Ú P STM32_HAS_TIM7 Ú P STM32_HAS_TIM8 Ú P STM32_HAS_TIM9 Ú P STM32_HAS_TIM10 oÚ P STM32_HAS_TIM11 nÚ P STM32_HAS_TIM12 mÚ P STM32_HAS_TIM13 lÚ P STM32_HAS_TIM14 kÚ P STM32_HAS_TIM15 jÚ P STM32_HAS_TIM16 iÚ P STM32_HAS_TIM17 hÚ P STM32_HAS_TIM18 gÚ P STM32_HAS_TIM19 fÚ P STM32_HAS_USART1 øÚ P STM32_USART1_RX_DMA_MSK ¡Ú P STM32_USART1_RX_DMA_CHN ³Ú P STM32_USART1_TX_DMA_MSK Ú P STM32_USART1_TX_DMA_CHN ±Ú P STM32_HAS_USART2 ÷Ú P STM32_USART2_RX_DMA_MSK Ú P STM32_USART2_RX_DMA_CHN ²Ú P STM32_USART2_TX_DMA_MSK Ú P STM32_USART2_TX_DMA_CHN °Ú P STM32_HAS_USART3 öÚ P STM32_USART3_RX_DMA_MSK Ú P STM32_USART3_RX_DMA_CHN ±Ú P STM32_USART3_TX_DMA_MSK Ú P STM32_USART3_TX_DMA_CHN ¯Ú P STM32_HAS_UART4 JÚ P STM32_UART4_RX_DMA_MSK óÚ P STM32_UART4_RX_DMA_CHN Ú P STM32_UART4_TX_DMA_MSK ñÚ P STM32_UART4_TX_DMA_CHN Ú P STM32_HAS_UART5 IÚ P STM32_UART5_RX_DMA_MSK òÚ P STM32_UART5_RX_DMA_CHN Ú P STM32_UART5_TX_DMA_MSK ðÚ P STM32_UART5_TX_DMA_CHN Ú P STM32_HAS_USART6 óÚ P STM32_USART6_RX_DMA_MSK Ú P STM32_USART6_RX_DMA_CHN ®Ú P STM32_USART6_TX_DMA_MSK Ú P STM32_USART6_TX_DMA_CHN ¬Ú P STM32_HAS_USB ÔÚ P STM32_HAS_OTG1 ¡Ú P STM32_HAS_OTG2 Ú P WWDG_IRQHandler kÚ P PVD_IRQHandler ¼Ú P TAMPER_IRQHandler ×Ú P RTC_IRQHandler ½Ú P FLASH_IRQHandler 4Ú P RCC_IRQHandler ÎÚ P EXTI0_IRQHandler 8Ú P EXTI1_IRQHandler 7Ú P EXTI2_IRQHandler 6Ú P EXTI3_IRQHandler 5Ú P EXTI4_IRQHandler 4Ú P DMA1_Ch1_IRQHandler ^Ú P DMA1_Ch2_IRQHandler ]Ú P DMA1_Ch3_IRQHandler \Ú P DMA1_Ch4_IRQHandler [Ú P DMA1_Ch5_IRQHandler ZÚ P DMA1_Ch6_IRQHandler YÚ P DMA1_Ch7_IRQHandler XÚ P ADC1_2_IRQHandler Ú P CAN1_TX_IRQHandler Ú P USB_HP_IRQHandler ¿Ú P CAN1_RX0_IRQHandler `Ú P USB_LP_IRQHandler »Ú P CAN1_RX1_IRQHandler _Ú P CAN1_SCE_IRQHandler _Ú P EXTI9_5_IRQHandler Ú P TIM1_BRK_IRQHandler CÚ P TIM1_UP_IRQHandler Ú P TIM1_TRG_COM_IRQHandler ïÚ P TIM1_CC_IRQHandler Ú P TIM2_IRQHandler Ú P TIM3_IRQHandler Ú P TIM4_IRQHandler Ú P I2C1_EV_IRQHandler µÚ P I2C1_ER_IRQHandler ¹Ú P I2C2_EV_IRQHandler ´Ú P I2C2_ER_IRQHandler ¸Ú P SPI1_IRQHandler Ú P SPI2_IRQHandler Ú P USART1_IRQHandler àÚ P USART2_IRQHandler ßÚ P USART3_IRQHandler ÞÚ P EXTI15_10_IRQHandler :Ú P RTC_Alarm_IRQHandler eÚ P USB_FS_WKUP_IRQHandler Ú P TIM8_BRK_IRQHandler <Ú P TIM8_UP_IRQHandler xÚ P TIM8_TRG_COM_IRQHandler èÚ P TIM8_CC_IRQHandler Ú P ADC3_IRQHandler ©Ú P FSMC_IRQHandler {Ú P SDIO_IRQHandler uÚ P TIM5_IRQHandler
Ú P SPI3_IRQHandler
Ú P UART4_IRQHandler 2Ú P UART5_IRQHandler 1Ú P TIM6_IRQHandler Ú P TIM7_IRQHandler Ú P DMA2_Ch1_IRQHandler ]Ú P DMA2_Ch2_IRQHandler \Ú P DMA2_Ch3_IRQHandler [Ú P DMA2_Ch4_5_IRQHandler ÂÚ P STM32_ACTIVATE_PLL WÚ P
STM32_PLLMUL %Ú P STM32_PLLCLKIN Ú P STM32_PLLCLKOUT ;Ú P
STM32_SYSCLK "Ú P STM32_HCLK ÝÚ P STM32_PCLK1 ¢Ú P STM32_PCLK2 ¡Ú P
STM32_RTCCLK 8Ú P
STM32_ADCCLK YÚ P
STM32_USBCLK 7Ú P STM32_TIMCLK1 Ú P STM32_TIMCLK2 Ú P STM32_FLASHBITS UÚ halclock_t ÙÚ halrtcnt_t ºÚ" P hal_lld_get_counter_value OÚ& P hal_lld_get_counter_frequency Ú P _STM32_ISR_H_ ¦Ú P STM32_CAN1_TX_HANDLER ~Ú P STM32_CAN1_RX0_HANDLER NÚ P STM32_CAN1_RX1_HANDLER MÚ P STM32_CAN1_SCE_HANDLER MÚ P STM32_CAN2_TX_HANDLER }Ú P STM32_CAN2_RX0_HANDLER MÚ P STM32_CAN2_RX1_HANDLER LÚ P STM32_CAN2_SCE_HANDLER LÚ P STM32_CAN1_TX_NUMBER µÚ P STM32_CAN1_RX0_NUMBER
Ú P STM32_CAN1_RX1_NUMBER Ú P STM32_CAN1_SCE_NUMBER Ú P STM32_CAN2_TX_NUMBER ´Ú P STM32_CAN2_RX0_NUMBER Ú P STM32_CAN2_RX1_NUMBER Ú P STM32_CAN2_SCE_NUMBER Ú P STM32_OTG1_HANDLER wÚ P STM32_OTG1_NUMBER ®Ú P STM32_SDIO_HANDLER cÚ P STM32_SDIO_NUMBER Ú P STM32_TIM1_UP_HANDLER mÚ P STM32_TIM1_CC_HANDLER Ú P STM32_TIM2_HANDLER vÚ P STM32_TIM3_HANDLER uÚ P STM32_TIM4_HANDLER tÚ P STM32_TIM5_HANDLER sÚ P STM32_TIM8_UP_HANDLER fÚ P STM32_TIM8_CC_HANDLER
Ú P STM32_TIM1_UP_NUMBER ¤Ú P STM32_TIM1_CC_NUMBER ÃÚ P STM32_TIM2_NUMBER Ú P STM32_TIM3_NUMBER ¬Ú P STM32_TIM4_NUMBER «Ú P STM32_TIM5_NUMBER ªÚ P STM32_TIM8_UP_NUMBER Ú P STM32_TIM8_CC_NUMBER ¼Ú P STM32_USART1_HANDLER ÎÚ P STM32_USART2_HANDLER ÍÚ P STM32_USART3_HANDLER ÌÚ P STM32_UART4_HANDLER Ú P STM32_UART5_HANDLER Ú P STM32_USART1_NUMBER Ú P STM32_USART2_NUMBER Ú P STM32_USART3_NUMBER Ú P STM32_UART4_NUMBER WÚ P STM32_UART5_NUMBER VÚ P STM32_USB1_HP_HANDLER zÚ P STM32_USB1_LP_HANDLER vÚ P STM32_USB1_HP_NUMBER ±Ú P STM32_USB1_LP_NUMBER Ú P _STM32_DMA_H_ ÂÚ P STM32_DMA_STREAMS ¡Ú P STM32_DMA_ISR_MASK EÚ P STM32_DMA_GETCHANNEL áÚ$ P STM32_DMA_IS_VALID_PRIORITY `Ú P STM32_DMA_STREAM_ID Ú P STM32_DMA_STREAM_ID_MSK ²Ú P STM32_DMA_IS_VALID_ID aÚ P STM32_DMA_STREAM öÚ P STM32_DMA1_STREAM1 Ú P STM32_DMA1_STREAM2 Ú P STM32_DMA1_STREAM3 Ú P STM32_DMA1_STREAM4 Ú P STM32_DMA1_STREAM5 Ú P STM32_DMA1_STREAM6 Ú P STM32_DMA1_STREAM7 Ú P STM32_DMA2_STREAM1 Ú P STM32_DMA2_STREAM2 Ú P STM32_DMA2_STREAM3 Ú P STM32_DMA2_STREAM4 Ú P STM32_DMA2_STREAM5 Ú P STM32_DMA_CR_EN =Ú P STM32_DMA_CR_TEIE ¥Ú P STM32_DMA_CR_HTIE ¢Ú P STM32_DMA_CR_TCIE §Ú P STM32_DMA_CR_DIR_MASK ZÚ P STM32_DMA_CR_DIR_P2M ¹Ú P STM32_DMA_CR_DIR_M2P ¹Ú P STM32_DMA_CR_DIR_M2M ¼Ú P STM32_DMA_CR_CIRC «Ú P STM32_DMA_CR_PINC ¢Ú P STM32_DMA_CR_MINC ¥Ú P STM32_DMA_CR_PSIZE_MASK ªÚ P STM32_DMA_CR_PSIZE_BYTE ¢Ú! P STM32_DMA_CR_PSIZE_HWORD PÚ P STM32_DMA_CR_PSIZE_WORD Ú P STM32_DMA_CR_MSIZE_MASK Ú P STM32_DMA_CR_MSIZE_BYTE ¥Ú! P STM32_DMA_CR_MSIZE_HWORD SÚ P STM32_DMA_CR_MSIZE_WORD Ú P STM32_DMA_CR_SIZE_MASK üÚ P STM32_DMA_CR_PL_MASK Ú P STM32_DMA_CR_PL 4Ú P STM32_DMA_CR_DMEIE fÚ P STM32_DMA_CR_CHSEL_MASK ÆÚ P STM32_DMA_CR_CHSEL [Ú P STM32_DMA_ISR_FEIF WÚ P STM32_DMA_ISR_DMEIF
Ú P STM32_DMA_ISR_TEIF IÚ P STM32_DMA_ISR_HTIF FÚ P STM32_DMA_ISR_TCIF KÚ 8
<unnamed> QÚ " §<channel ñÚ " §<ifcr ,Ú " §<ishift ZÚ " §<
selfindex Ú " §<vector NÚ stm32_dma_stream_t ÕÚ stm32_dmaisr_t zÚ P dmaStreamSetPeripheral ÉÚ P dmaStreamSetMemory0 2Ú$ P dmaStreamSetTransactionSize ªÚ$ P dmaStreamGetTransactionSize ¶Ú P dmaStreamSetMode \Ú P dmaStreamEnable ÈÚ P dmaStreamDisable YÚ P dmaStreamClearInterrupt KÚ P dmaStartMemCopy ³Ú P dmaWaitCompletion ÈÚ < _stm32_dma_streams Ú dmaInit Ú , dmastp <Ú ,
priority MÚ
, func Ú , param ¶Ú dmaStreamAllocate Ú , dmastp <Ú dmaStreamRelease iÚ P _STM32_RCC_ gÚ P rccEnableAPB1 .Ú P rccDisableAPB1 ¿Ú P
rccResetAPB1 tÚ P rccEnableAPB2 -Ú P rccDisableAPB2 ¾Ú P
rccResetAPB2 sÚ P
rccEnableAHB iÚ P rccDisableAHB úÚ P rccResetAHB ¯Ú P rccEnableADC1 9Ú P rccDisableADC1 ÊÚ P
rccResetADC1 Ú P rccEnableBKPInterface ´Ú P rccDisableBKPInterface EÚ P rccResetBKPInterface úÚ P rccResetBKP Ú P rccEnablePWRInterface Ú P rccDisablePWRInterface )Ú P rccResetPWRInterface ÞÚ P rccEnableCAN1 /Ú P rccDisableCAN1 ÀÚ P
rccResetCAN1 uÚ P rccEnableDMA1 /Ú P rccDisableDMA1 ÀÚ P
rccResetDMA1 uÚ P rccEnableDMA2 .Ú P rccDisableDMA2 ¿Ú P
rccResetDMA2 tÚ P
rccEnableETH SÚ P rccDisableETH äÚ P rccResetETH Ú P rccEnableI2C1 CÚ P rccDisableI2C1 ÔÚ P
rccResetI2C1 Ú P rccEnableI2C2 BÚ P rccDisableI2C2 ÓÚ P
rccResetI2C2 Ú P rccEnableOTG_FS LÚ P rccDisableOTG_FS ÝÚ P rccResetOTG_FS Ú P rccEnableSDIO Ú P rccDisableSDIO Ú P
rccResetSDIO IÚ P rccEnableSPI1 Ú P rccDisableSPI1 ¦Ú P
rccResetSPI1 [Ú P rccEnableSPI2 Ú P rccDisableSPI2 ¥Ú P
rccResetSPI2 ZÚ P rccEnableSPI3 Ú P rccDisableSPI3 ¤Ú P
rccResetSPI3 YÚ P rccEnableTIM1 Ú P rccDisableTIM1 ¨Ú P
rccResetTIM1 ]Ú P rccEnableTIM2 Ú P rccDisableTIM2 §Ú P
rccResetTIM2 \Ú P rccEnableTIM3 Ú P rccDisableTIM3 ¦Ú P
rccResetTIM3 [Ú P rccEnableTIM4 Ú P rccDisableTIM4 ¥Ú P
rccResetTIM4 ZÚ P rccEnableTIM5 Ú P rccDisableTIM5 ¤Ú P
rccResetTIM5 YÚ P rccEnableTIM8 Ú P rccDisableTIM8 ¡Ú P
rccResetTIM8 VÚ P rccEnableUSART1 nÚ P rccDisableUSART1 ÿÚ P rccResetUSART1 ´Ú P rccEnableUSART2 mÚ P rccDisableUSART2 þÚ P rccResetUSART2 ³Ú P rccEnableUSART3 lÚ P rccDisableUSART3 ýÚ P rccResetUSART3 ²Ú P rccEnableUART4 ÀÚ P rccDisableUART4 QÚ P rccResetUART4 Ú P rccEnableUART5 ¿Ú P rccDisableUART5 PÚ P rccResetUART5 Ú P
rccEnableUSB JÚ P rccDisableUSB ÛÚ P rccResetUSB Ú
hal_lld_init íÚ stm32_clock_init Ú P _IO_CHANNEL_H_ ZÚ P _base_channel_methods Ú P _base_channel_data |Ú 8 BaseChannelVMT ~Ú " =write ©Ú " =read :Ú " =put Ú " =get Ú " =putt Ú " =gett "Ú " =writet 3Ú " =readt ÄÚ 8
<unnamed> QÚ " ©=vmt xÚ BaseChannel ·Ú P chnPutTimeout XÚ P chnGetTimeout qÚ P chnWrite wÚ P chnWriteTimeout Ú P chnRead Ú P chnReadTimeout Ú P
CHN_NO_ERROR õÚ P CHN_CONNECTED æÚ P CHN_DISCONNECTED Ú P CHN_INPUT_AVAILABLE ýÚ P CHN_OUTPUT_EMPTY Ú P CHN_TRANSMISSION_END Ú+ P #_base_asynchronous_channel_methods wÚ( P _base_asynchronous_channel_data ×Ú# 8 BaseAsynchronousChannelVMT ZÚ " º=write Ú " º=read Ú " º=put eÚ " º=get ~Ú " º=putt ïÚ " º=gett Ú " º=writet Ú " º=readt ªÚ 8
<unnamed> QÚ " Ã=vmt ^Ú " Ã=event Ú BaseAsynchronousChannel Ú P chnGetEventSource ÝÚ P
chnAddFlagsI ;Ú P
_IO_BLOCK_H_ ìÚ BLK_UNINIT ÚÚ BLK_STOP oÚ BLK_ACTIVE õÚ BLK_CONNECTING ÁÚ BLK_DISCONNECTING ÛÚ
BLK_READY >Ú BLK_READING µÚ BLK_WRITING Ú BLK_SYNCING Ú blkstate_t ÀÚ 8
<unnamed> QÚ
" Ô= blk_size UÚ
" Ô=blk_num ÂÚ BlockDeviceInfo Ú# P _base_block_device_methods Ú P _base_block_device_data qÚ 8 BaseBlockDeviceVMT ôÚ " Ú= is_inserted õÚ " Ú=
is_protected Ú " Ú=connect ¬Ú " Ú= disconnect fÚ " Ú=read Ú " Ú=write oÚ " Ú=sync ßÚ " Ú= get_info IÚ 8
<unnamed> QÚ " ã=vmt >Ú "" ã=state iÚ BaseBlockDevice -Ú P blkGetDriverState ãÚ P blkIsTransferring ¿Ú P blkIsInserted ~Ú P blkIsWriteProtected ûÚ P blkConnect ´Ú P blkDisconnect nÚ P blkRead Ú P blkWrite wÚ P blkSync çÚ P blkGetInfo ÒÚ P
_MMCSD_H_ àÚ P _TM_H_ ¹Ú 8 TimeMeasurement Ú TimeMeasurement ÎÚ " ó=start SÚ " ó=stop ½Ú
" ó=last ÝÚ
" ó=worst PÚ
" ó=best ãÚ P tmStartMeasurement 2Ú P tmStopMeasurement Ú tmInit gÚ , tmp zÚ
tmObjectInit Ú P _PAL_H_ {Ú P PAL_MODE_RESET lÚ P PAL_MODE_UNCONNECTED Ú P PAL_MODE_INPUT _Ú P PAL_MODE_INPUT_PULLUP Ú P PAL_MODE_INPUT_PULLDOWN yÚ P PAL_MODE_INPUT_ANALOG @Ú! P PAL_MODE_OUTPUT_PUSHPULL Ú" P PAL_MODE_OUTPUT_OPENDRAIN éÚ P PAL_LOW Ú P PAL_HIGH _Ú P _PAL_LLD_H_ 8Ú* P "PAL_MODE_STM32_ALTERNATE_PUSHPULL Ú+ P #PAL_MODE_STM32_ALTERNATE_OPENDRAIN pÚ 8
<unnamed> QÚ
" >odr ³Ú
" >crl ·Ú
" >crh »Ú stm32_gpio_setup_t ³Ú 8
<unnamed> QÚ " >PAData ÈÚ " >PBData ÇÚ " >PCData ÆÚ " >PDData ÅÚ " >PEData ÄÚ " >PFData ÃÚ " >PGData ÂÚ
PALConfig ¼Ú P PAL_IOPORTS_WIDTH ^Ú P PAL_WHOLE_PORT PÚ
ioportmask_t ÍÚ iomode_t ¡Ú ioportid_t °Ú P IOPORT1 ¯Ú P IOPORT2 ®Ú P IOPORT3 Ú P IOPORT4 ¬Ú P IOPORT5 «Ú P IOPORT6 ªÚ P IOPORT7 ©Ú P
pal_lld_init ÈÚ P pal_lld_readport Ú P pal_lld_readlatch ÊÚ P pal_lld_writeport Ú P pal_lld_setport eÚ P pal_lld_clearport ¦Ú P pal_lld_writegroup Ú P pal_lld_setgroupmode NÚ P pal_lld_writepad Ú Tpal_default_config Ú , config OÚ _pal_lld_init Ú
, port Ú
,
mask +Ú
,
mode 2Ú _pal_lld_setgroupmode
Ú 8
<unnamed> QÚ " ·>portid (Ú
" ·>mask Ú
" ·>offset AÚ IOBus 5Ú P
PAL_PORT_BIT ôÚ P PAL_GROUP_MASK [Ú P _IOBUS_DATA [Ú P IOBUS_DECL ¾Ú P palInit ìÚ P palReadPort WÚ P
palReadLatch Ú P
palWritePort ÆÚ P palSetPort ©Ú P
palClearPort êÚ P palTogglePort mÚ P
palReadGroup íÚ P palWriteGroup \Ú P palSetGroupMode ²Ú P palReadPad éÚ P palWritePad XÚ P
palSetPad ;Ú P palClearPad |Ú P
palTogglePad ÿÚ P palSetPadMode ®Ú , bus Ú palReadBus ñÚ , bus Ú
,
bits %Ú palWriteBus `Ú , bus Ú
,
mode 2Ú palSetBusMode ¶Ú P _ADC_H_ Ú P _CAN_H_ Ú P _EXT_H_ gÚ P _GPT_H_ mÚ GPT_UNINIT ÈÚ GPT_STOP ]Ú
GPT_READY ,Ú GPT_CONTINUOUS Ú GPT_ONESHOT }Ú gptstate_t ®Ú 8
GPTDriver \Ú
GPTDriver Ú gptcallback_t Ú P _GPT_LLD_H_ *Ú P STM32_GPT_USE_TIM6 9Ú P STM32_GPT_USE_TIM7 8Ú P STM32_GPT_USE_TIM9 6Ú P STM32_GPT_USE_TIM11 Ú P STM32_GPT_USE_TIM12
Ú P STM32_GPT_USE_TIM14 Ú$ P STM32_GPT_TIM6_IRQ_PRIORITY GÚ$ P STM32_GPT_TIM7_IRQ_PRIORITY FÚ$ P STM32_GPT_TIM9_IRQ_PRIORITY DÚ% P STM32_GPT_TIM11_IRQ_PRIORITY Ú% P STM32_GPT_TIM12_IRQ_PRIORITY Ú% P STM32_GPT_TIM14_IRQ_PRIORITY Ú
gptfreq_t #Ú gptcnt_t Ú 8
<unnamed> QÚ
" ô>
frequency ³Ú " ô> callback LÚ
GPTConfig ®Ú "" â>state iÚ " â>config Ú
" â>clock Ú " â>tim KÚ P gpt_lld_change_interval .Ú GPTD2 rÚ
gpt_lld_init ×Ú
, gptp Ú gpt_lld_start [Ú
, gptp Ú
gpt_lld_stop ÅÚ
, gptp Ú , period NÚ gpt_lld_start_timer ÏÚ
, gptp Ú gpt_lld_stop_timer 9Ú
, gptp Ú , interval hÚ gpt_lld_polled_delay Ú P gptChangeIntervalI Ú gptInit ûÚ
, gptp Ú gptObjectInit Ú
, gptp Ú , config OÚ gptStart Ú
, gptp Ú gptStop éÚ
, gptp Ú , interval hÚ gptStartContinuous 4Ú
, gptp Ú , interval hÚ gptStartContinuousI éÚ
, gptp Ú , interval hÚ gptChangeInterval ðÚ
, gptp Ú , interval hÚ gptStartOneShot ±Ú
, gptp Ú , interval hÚ gptStartOneShotI fÚ
, gptp Ú
gptStopTimer ÞÚ
, gptp Ú gptStopTimerI Ú
, gptp Ú , interval hÚ gptPolledDelay 2Ú P _I2C_H_ Ú P _ICU_H_ wÚ P _MAC_H_ Ú P _PWM_H_ dÚ P PWM_OUTPUT_MASK ÞÚ P PWM_OUTPUT_DISABLED ÊÚ P PWM_OUTPUT_ACTIVE_HIGH ÁÚ P PWM_OUTPUT_ACTIVE_LOW ñÚ PWM_UNINIT ¿Ú PWM_STOP TÚ
PWM_READY #Ú pwmstate_t ¥Ú 8
PWMDriver SÚ
PWMDriver Ú pwmcallback_t Ú P _PWM_LLD_H_ !Ú P
PWM_CHANNELS Ú& P PWM_COMPLEMENTARY_OUTPUT_MASK Ú* P "PWM_COMPLEMENTARY_OUTPUT_DISABLED oÚ- P %PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH fÚ, P $PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW Ú P STM32_PWM_USE_TIM9 -Ú$ P STM32_PWM_TIM9_IRQ_PRIORITY ;Ú
pwmmode_t #Ú
pwmchannel_t éÚ pwmcnt_t
Ú 8
<unnamed> QÚ
" Ä?mode Ú " Ä? callback {Ú PWMChannelConfig ÞÚ 8
<unnamed> QÚ
" È?
frequency ÞÚ " È?period 1Ú " È? callback wÚ <" È? channels Ú " È?cr2 ³Ú
PWMConfig ¥Ú "" ¶?state Ú " ¶?config DÚ " ¶?period CÚ
" ¶?clock ¾Ú " ¶?tim vÚ P pwm_lld_change_period Ú# P pwm_lld_is_channel_enabled Ú PWMD3 dÚ PWMD4 cÚ
pwm_lld_init ÎÚ
, pwmp Ú pwm_lld_start RÚ
, pwmp Ú
pwm_lld_stop ¼Ú
, pwmp Ú , channel ÿÚ , width ³Ú pwm_lld_enable_channel ÏÚ
, pwmp Ú , channel ÿÚ pwm_lld_disable_channel `Ú P PWM_FRACTION_TO_WIDTH Ú P PWM_DEGREES_TO_WIDTH pÚ P PWM_PERCENTAGE_TO_WIDTH Ú P pwmChangePeriodI eÚ P pwmEnableChannelI Ú P pwmDisableChannelI Ú P pwmIsChannelEnabledI æÚ pwmInit òÚ
, pwmp Ú pwmObjectInit Ú
, pwmp Ú , config OÚ pwmStart vÚ
, pwmp Ú pwmStop àÚ
, pwmp Ú , period NÚ pwmChangePeriod ÍÚ
, pwmp Ú , channel ÿÚ , width ³Ú pwmEnableChannel tÚ
, pwmp Ú , channel ÿÚ pwmDisableChannel Ú P _RTC_H_ oÚ P _SERIAL_H_ Ú P SD_PARITY_ERROR õÚ P SD_FRAMING_ERROR ÈÚ P SD_OVERRUN_ERROR Ú P SD_NOISE_ERROR RÚ P SD_BREAK_DETECTED Ú
SD_UNINIT Ú SD_STOP ³Ú SD_READY Ú
sdstate_t $Ú 8
SerialDriver áÚ
SerialDriver Ú P _SERIAL_LLD_H_ OÚ 8
<unnamed> QÚ
" @ sc_speed ¨Ú " @sc_cr1 µÚ " @sc_cr2 ´Ú " @sc_cr3 ³Ú
SerialConfig 3Ú P _serial_driver_data âÚ P USART_CR2_STOP1_BITS Ú P USART_CR2_STOP0P5_BITS ÿÚ P USART_CR2_STOP2_BITS Ú P USART_CR2_STOP1P5_BITS þÚ SD1 Ú SD2 Ú sd_lld_init MÚ , sdp Ú , config OÚ
sd_lld_start ÑÚ , sdp Ú sd_lld_stop ;Ú P _serial_driver_methods Ú 8 SerialDriverVMT äÚ " @write §Ú " @read 8Ú " @put }Ú " @get Ú " @putt Ú " @gett Ú " @writet 1Ú " @readt ÂÚ " @vmt Ú " @event ÃÚ "" @state ÁÚ " $@iqueue 5Ú " $@oqueue /Ú
<" @ib ôÚ
<" @ob îÚ " @usart ºÚ P sdPutWouldBlock §Ú P sdGetWouldBlock ÀÚ P sdPut ±Ú P
sdPutTimeout ¼Ú P sdGet ÊÚ P
sdGetTimeout ÕÚ P sdWrite ÛÚ P sdWriteTimeout æÚ P sdAsynchronousWrite ·Ú P sdRead lÚ P sdReadTimeout wÚ P sdAsynchronousRead HÚ sdInit qÚ , sdp Ú , inotify ÁÚ , onotify »Ú
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