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..\..\..\os\hal\include\gpt.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil D 2 éGPT_UNINIT GPT_STOP GPT_READY GPT_CONTINUOUS GPT_ONESHOT Pgptstate_t ;PGPTDriver A @O% "û "Pgptcallback_t G \
..\..\..\os\hal\platforms\STM32\gpt_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¬ t2 Pgptfreq_t ëPgptcnt_t ð*÷ frequency ¨ # callback # PGPTConfig Ï )ÏGPTDriver state é # config S# clock # tim W# ÷ "O"õ
..\..\..\os\hal\include\pwm.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil t# B ÈPWM_UNINIT PWM_STOP PWM_READY Ppwmstate_t RPPWMDriver > WOõ%õ "Ú "í Ppwmcallback_t ù ^ ô
..\..\..\os\hal\platforms\STM32\pwm_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil & B Ppwmmode_t Ppwmchannel_t ý £Ppwmcnt_t ¨* mode ¨ # callback # PPWMChannelConfig æ ¹*0 frequency # period Ó # callback #â channels Y# cr2 #, PPWMConfig "â)æPWMDriver state ` # config ê# period Ó # clock # tim î# "æ"õ
..\..\..\os\hal\include\pwm.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil B h ÈPWM_UNINIT PWM_STOP PWM_READY Ppwmstate_t RPPWMDriver J WOõ%õ "Ú "í Ppwmcallback_t ù ^
..\..\..\os\hal\platforms\STM32\pwm_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¨E Ø Ppwmmode_t Ppwmchannel_t ý £Ppwmcnt_t ¨* mode ¨ # callback ¡ # PPWMChannelConfig æ ¹*0 frequency # period Ó # callback ¡ #â channels Y# cr2 #, PPWMConfig "â)æPWMDriver state l # config ê# period Ó # clock # tim î# "æ"õ
qPWMD4 ~ 4
..\..\..\os\hal\include\gpt.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil XH ( éGPT_UNINIT GPT_STOP GPT_READY GPT_CONTINUOUS GPT_ONESHOT Pgptstate_t ;PGPTDriver ý
@O% "û "Pgptcallback_t G l
..\..\..\os\hal\platforms\STM32\gpt_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ÀH Pgptfreq_t ëPgptcnt_t ð*÷ frequency ¨ # callback Ú # PGPTConfig Ï )ÏGPTDriver state ¥ # config S# clock # tim W# ÷ "O"õ
qGPTD2 · ¤
..\..\..\os\hal\platforms\STM32\stm32.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil L
*
T CR1
# _resvd0 # CR2
# _resvd1 # SMCR
# _resvd2 #
DIER
# _resvd3 # SR
# _resvd4 # EGR
# _resvd5 # CCMR1
# _resvd6 # CCMR2
# _resvd7 # CCER
# _resvd8 #" CNT #$ PSC
#( _resvd9 #* ARR #, RCR
#0 _resvd10 #2 CCR û#4 BDTR
#D _resvd11 #F DCR
#H _resvd12 #J DMAR
#L _resvd13 #N OR
#P _resvd14 #R t t Pstm32_tim_t ¦ |
..\..\..\os\kernel\include\chthreads.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil + 4 uvoid char "¥ )Thread H p_next # p_prev # p_prio X # p_ctx # p_newer # p_older # p_name # p_state " # p_flags # p_refs 4 # p_preempt E # p_time # p_u C#$ p_waiting ? #( p_msgqueue #, p_msg i #4 p_epending #8 p_mtxlist #< p_realprio X #@ p_mpool ³ #D « "tµ "l N¯i %³ ""Ptfunc_t /ÞSü rdymsg i exitcode i wtobjp ³ ewmask ì
..\..\..\os\kernel\include\chmtx.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil \6 @ )ÜMutex m_queue # m_owner # m_next Ü # "¡ PMutex ¡ , À
..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil è> ` uvoid "© Pregarm_t ¯ ÞPstkalign_t , æ)¼extctx r0 ³ # r1 ³ # r2 ³ # r3 ³ # r12 ³ # lr_thd ³ # pc ³ # xpsr ³ # )¤intctx $ r4 ³ # r5 ³ # r6 ³ # r7 ³ # r8 ³ # r9 ³ # r10 ³ # r11 ³ # lr ³ # )¼context r13 ¼# "<
..\..\..\os\kernel\include\chlists.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ÄF ° PThread à #*Ô p_next Ô # p_prev Ô # "£ PThreadsQueue ³ _*ÿ p_next Ô # PThreadsList ì i
..\..\..\os\ports\RVCT\ARMCMx\chtypes.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 0H ü _Bool Pbool_t ¦ $Ptmode_t ý %Ptstate_t ý &Ptrefs_t ý 'Ptslices_t ý (Ptprio_t )Pmsg_t ß *Peventid_t ß +Peventmask_t ,Pflagsmask_t -Psystime_t .Pcnt_t ß / ì C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stdint.h ARM C/C++ Compiler, 5.03 [Build 24] ¼H signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t r& Pint16_t ' Pint32_t ( Pint64_t ) Puint8_t , Puint16_t ¯ - Puint32_t Á . Puint64_t Ñ / Pint_least8_t r5 Pint_least16_t 6 Pint_least32_t 7 Pint_least64_t 8 Puint_least8_t ; Puint_least16_t ¯ < Puint_least32_t Á = Puint_least64_t Ñ > Pint_fast8_t C Pint_fast16_t D Pint_fast32_t E Pint_fast64_t F Puint_fast8_t Á I Puint_fast16_t Á J Puint_fast32_t Á K Puint_fast64_t Ñ L Pintptr_t O Puintptr_t Á P Pintmax_t S Puintmax_t Ñ T È C:\Program Files\Keil\ARM\ARMCC\bin\..\include\stddef.h ARM C/C++ Compiler, 5.03 [Build 24] `P ü int unsigned int unsigned short Pptrdiff_t r#Psize_t y'Pwchar_t 4 `
..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ä Ì
ÙIRQn NonMaskableInt_IRQn rMemoryManagement_IRQn tBusFault_IRQn uUsageFault_IRQn vSVC_IRQn {DebugMonitor_IRQn |PendSV_IRQn ~SysTick_IRQn WWDG_IRQn PVD_IRQn TAMPER_STAMP_IRQn RTC_WKUP_IRQn FLASH_IRQn RCC_IRQn EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQn
DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn
DMA1_Channel4_IRQn DMA1_Channel5_IRQn DMA1_Channel6_IRQn DMA1_Channel7_IRQn ADC1_IRQn USB_HP_IRQn USB_LP_IRQn DAC_IRQn COMP_IRQn EXTI9_5_IRQn LCD_IRQn TIM9_IRQn TIM10_IRQn TIM11_IRQn TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQn I2C1_ER_IRQn I2C2_EV_IRQn !I2C2_ER_IRQn "SPI1_IRQn #SPI2_IRQn $USART1_IRQn %USART2_IRQn &USART3_IRQn 'EXTI15_10_IRQn (RTC_Alarm_IRQn )USB_FS_WKUP_IRQn *TIM6_IRQn +TIM7_IRQn , PIRQn_Type ® RESET SET PFlagStatus ë(PITStatus ë4¾DISABLE ENABLE PFunctionalState $/ïERROR SUCCESS PErrorStatus V,*¨ ` SR ¨# CR1 ¨# CR2 ¨# SMPR1 ¨# SMPR2 ¨# SMPR3 ¨# JOFR1 ¨# JOFR2 ¨# JOFR3 ¨# JOFR4 ¨#$ HTR ¨#( LTR ¨#, SQR1 ¨#0 SQR2 ¨#4 SQR3 ¨#8 SQR4 ¨#< SQR5 ¨#@ JSQR ¨#D JDR1 ¨#H JDR2 ¨#L JDR3 ¨#P JDR4 ¨#T DR ¨#X SMPR0 ¨#\ t PADC_TypeDef è*Ý CSR ¨# CCR ¨# PADC_Common_TypeDef Âî*
0 CR ¨# SR ¨# DINR ¨# DOUTR ¨# KEYR0 ¨# KEYR1 ¨# KEYR2 ¨# KEYR3 ¨# IVR0 ¨# IVR1 ¨#$ IVR2 ¨#( IVR3 ¨#, PAES_TypeDef ø*²
CSR ¨# PCOMP_TypeDef ¢* DR ¨# IDR # RESERVED0 ý # RESERVED1 # CR ¨# tý PCRC_TypeDef Ç*ï8 CR ¨# SWTRIGR ¨# DHR12R1 ¨# DHR12L1 ¨# DHR8R1 ¨# DHR12R2 ¨# DHR12L2 ¨# DHR8R2 ¨# DHR12RD ¨# DHR12LD ¨#$ DHR8RD ¨#( DOR1 ¨#, DOR2 ¨#0 SR ¨#4 PDAC_TypeDef +¯*¼ IDCODE ¨# CR ¨# APB1FZ ¨# APB2FZ ¨# PDBGMCU_TypeDef »* CCR ¨# CNDTR ¨# CPAR ¨# CMAR ¨# PDMA_Channel_TypeDef SÇ*À ISR ¨# IFCR ¨# PDMA_TypeDef ¤Í* IMR ¨# EMR ¨# RTSR ¨# FTSR ¨# SWIER ¨# PR ¨# PEXTI_TypeDef ÔÛ*â ACR ¨# PECR ¨# PDKEYR ¨# PEKEYR ¨# PRGKEYR ¨# OPTKEYR ¨# SR ¨# OBR ¨# WRPR ¨# µ RESERVED ª #$ WRPR1 ¨# WRPR2 ¨# PFLASH_TypeDef 3 ï*ä RDP ¨# USER ¨# WRP01 ¨# WRP23 ¨# WRP45 ¨# WRP67 ¨# WRP89 ¨# WRP1011 ¨# POB_TypeDef ø ÿ* CSR ¨# OTR ¨# LPOTR ¨# POPAMP_TypeDef w
*Ï Â¨ BTCR ¹
# PFSMC_Bank1_TypeDef µ
* ÷¨ BWTR î
# PFSMC_Bank1E_TypeDef ê
*Õ MEMRMP ¨# PMC ¨#ƨ EXTICR = # PSYSCFG_TypeDef À*$ CR1 # RESERVED0 # CR2 # RESERVED1 # OAR1 # RESERVED2 #
OAR2 # RESERVED3 # DR # RESERVED4 # SR1 # RESERVED5 # SR2 # RESERVED6 # CCR # RESERVED7 # TRISE # RESERVED8 #" t PI2C_TypeDef l Ú*Ê KR ¨# PR ¨# RLR ¨# SR ¨# PIWDG_TypeDef æ*´T CR ¨# FCR ¨# SR ¨# CLR ¨# RESERVED #¨¨ RAM
# PLCD_TypeDef ß õ*â CR ¨# CSR ¨# PPWR_TypeDef H
ÿ*Á 8 CR ¨# ICSCR ¨# CFGR ¨# CIR ¨# AHBRSTR ¨# APB2RSTR ¨# APB1RSTR ¨# AHBENR ¨# APB2ENR ¨# APB1ENR ¨#$ AHBLPENR ¨#( APB2LPENR ¨#, APB1LPENR ¨#0 CSR ¨#4 PRCC_TypeDef v
*· ICR ¨# ASCR1 ¨# ASCR2 ¨# HYSCR1 ¨# HYSCR2 ¨# HYSCR3 ¨# HYSCR4 ¨# PRI_TypeDef U¤*#Ð TR ¨# DR ¨# CR ¨# ISR ¨# PRER ¨# WUTR ¨# CALIBR ¨# ALRMAR ¨# ALRMBR ¨# WPR ¨#$ SSR ¨#( SHIFTR ¨#, TSTR ¨#0 TSDR ¨#4 TSSSR ¨#8 CALR ¨#< TAFCR ¨#@ ALRMASSR ¨#D ALRMBSSR ¨#H RESERVED7 #L BKP0R ¨#P BKP1R ¨#T BKP2R ¨#X BKP3R ¨#\ BKP4R ¨#` BKP5R ¨#d BKP6R ¨#h BKP7R ¨#l BKP8R ¨#p BKP9R ¨#t BKP10R ¨#x BKP11R ¨#| BKP12R ¨# BKP13R ¨# BKP14R ¨# BKP15R ¨# BKP16R ¨# BKP17R ¨# BKP18R ¨# BKP19R ¨# BKP20R ¨# BKP21R ¨#¤ BKP22R ¨#¨ BKP23R ¨#¬ BKP24R ¨#° BKP25R ¨#´ BKP26R ¨#¸ BKP27R ¨#¼ BKP28R ¨#À BKP29R ¨#Ä BKP30R ¨#È BKP31R ¨#Ì PRTC_TypeDef Êà*Ò% POWER ¨# CLKCR ¨# ARG ¨# CMD ¨# RESPCMD Ø# RESP1 Ø# RESP2 Ø# RESP3 Ø# RESP4 Ø# DTIMER ¨#$ DLEN ¨#( DCTRL ¨#, DCOUNT Ø#0 STA Ø#4 ICR ¨#8 MASK ¨#<% RESERVED0 }#@ FIFOCNT Ø#H³% RESERVED1 ¨#L FIFO ¨# tÒPSDIO_TypeDef ®ü*($ CR1 # RESERVED0 # CR2 # RESERVED1 # SR # RESERVED2 #
DR # RESERVED3 # CRCPR # RESERVED4 # RXCRCR # RESERVED5 # TXCRCR # RESERVED6 # I2SCFGR # RESERVED7 # I2SPR # RESERVED8 #" PSPI_TypeDef ñ*§,T CR1 # RESERVED0 # CR2 # RESERVED1 # SMCR # RESERVED2 #
DIER # RESERVED3 # SR # RESERVED4 # EGR # RESERVED5 # CCMR1 # RESERVED6 # CCMR2 # RESERVED7 # CCER # RESERVED8 #" CNT ¨#$ PSC #( RESERVED10 #* ARR ¨#, RESERVED12 #0 CCR1 ¨#4 CCR2 ¨#8 CCR3 ¨#< CCR4 ¨#@ RESERVED17 #D DCR #H RESERVED18 #J DMAR #L RESERVED19 #N OR #P RESERVED20 #R PTIM_TypeDef $À*. SR # RESERVED0 # DR # RESERVED1 # BRR # RESERVED2 #
CR1 # RESERVED3 # CR2 # RESERVED4 # CR3 # RESERVED5 # GTPR # RESERVED6 # PUSART_TypeDef ;Ö*Ë. CR ¨# CFR ¨# SR ¨# PWWDG_TypeDef 'á
..\..\..\os\kernel\include\chqueues.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil t% è uvoid "¤ PGenericQueue 0 Pqnotify_t 3PInputQueue ® {POutputQueue ® îO% "® "ù )GenericQueue $ q_waiting # q_counter w # q_buffer # q_top # q_wrptr # q_rdptr # q_notify  # q_link ª # "ý l
..\..\..\os\kernel\include\chevents.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ì3 ¬ PEventListener ¹ % )EventListener el_next # el_listener # el_mask # el_flags # "¤ )·EventSource es_next # PEventSource >OÔ%x "JPevhandler_t TC ð
..\..\..\os\hal\include\serial.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < uvoid " ý "© "ý )ÉSerialDriver x vmt M# event ×3 # state # iqueue Ï1 # oqueue á1 #0ý ib #T±ý ob &#d usart Q#t ¥"I"©0 SD_UNINIT SD_STOP SD_READY Psdstate_t WaPSerialDriver ¹ f )ðSerialDriverVMT NÐw %¥ %¯ %w "¹ write Ð# Nøw %¥ %³ %w "á read ø#Ni %¥ %ý " put #N·i %¥ "* get 7# Nßi %¥ %ý %µ "F putt _#Ni %¥ %µ "o gett #N¯w %¥ %¯ %w %µ " writet ¯#NÞw %¥ %³ %w %µ "Á readt Þ#
..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ø uvoid "® "wPstm32_dma_stream_t ¿Pstm32_dmaisr_t ¸ ȼ ûî q_stm32_dma_streams ò *ç channel g# ifcr s# ishift ý # selfindex ý # vector ý #
" " t "mO
%´ %
..\..\..\os\hal\include\adc.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil TK è óADC_UNINIT ADC_STOP ADC_READY ADC_ACTIVE ADC_COMPLETE ADC_ERROR Padcstate_t U Ô
..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil g L Phalclock_t ÷Phalrtcnt_t ü Ô
..\..\..\os\kernel\include\chmemcore.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ´0 uvoid "¥ N¼« %w "¯ Pmemgetfunc_t ¼ % à
..\..\..\os\kernel\include\chsem.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil : Ð )ÐSemaphore s_queue # s_cnt È # PSemaphore ¡ ) (
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil `@ *ú sc_speed # sc_cr1 # sc_cr2 # sc_cr3 # PSerialConfig ³ éqSD1 ¡5 qSD2 ¡5 t
..\..\..\os\hal\platforms\STM32L1xx\adc_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil (S \ Padcsample_t ¹Padc_channels_num_t ¾ADC_ERR_DMAFAILURE ADC_ERR_OVERFLOW Padcerror_t ß ÈPADCDriver ©ÍOÅ%E%I%w "!"¬ "3Padccallback_t M×Oó%E% "gPadcerrorcallback_t sà*è4 circular # num_channels  # end_cb Q# error_cb w# cr1 # cr2 # smpr1 # smpr2 # smpr3 # sqr1 # sqr2 #$ sqr3 #( sqr4 #, sqr5 #0 PADCConversionGroup ´* dummy # PADCConfig ¼)ÈADCDriver 4 state 9 # config L# samples I# depth w # grpp T# thread # mutex l # adc X#( dmastp d#, dmamode #0 "Hh"P"F À7 "^qADCD1 ! ,
..\keil/GPS_dekoduj.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¨ ø *-£ý UTC_time # Status_GPS ý #Òý Latitude Ç #íý
Longitude â #ý Altitude þ ## PNMEA_GPGGA
..\..\..\test\test.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ô % char uvoid "¡ *ð ¹@ % T0 ® # Î@ % T1 à #°ä@ % T2 Ù #àú@ % T3 ï #@ % T4 #À RÍtest_buffers ð wa © Áý ï buffer 5 Ø qthreads Mqtest " qu qwa yqtest_timer_done )testcase name ¥ # O¿ "» setup ¿#OÔ "Ð teardown Ô#Oì "è execute ì# ¤
..\..\..\test\test.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ´ , char " *ð ³@ % T0 ¨ # È@ % T1 ½ #°Þ@ % T2 Ó #àô@ % T3 é #@ % T4 ÿ #À RÇtest_buffers ð wa £ »ý ï buffer / )¥testcase name # Oä "` setup d#Où "u teardown y#O " execute #
..\..\..\os\kernel\include\chstreams.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil t# uvoid "¥ ý "¯ "ý *Ï vmt Ó # ó "Ï PBaseSequentialStream ¿ N)BaseSequentialStreamVMT N¦w %« %µ %w " write &# NÎw %« %¹ %w "7 read N#Nñi %« %ý "^ put q#Ni %« " get # h
..\..\..\os\hal\platforms\STM32L1xx\adc_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil `
P7 Padcsample_t ¹Padc_channels_num_t ¾ADC_ERR_DMAFAILURE ADC_ERR_OVERFLOW Padcerror_t ß ÈPADCDriver ©ÍOÅ%E%I%w "!"¬ "3Padccallback_t M×Oó%E% "gPadcerrorcallback_t sà*è4 circular # num_channels  # end_cb Q# error_cb w# cr1 # cr2 # smpr1 # smpr2 # smpr3 # sqr1 # sqr2 #$ sqr3 #( sqr4 #, sqr5 #0 PADCConversionGroup ´* dummy # PADCConfig ¼)ÈADCDriver 4 state 9 # config L# samples I# depth w # grpp T# thread # mutex l # adc X#( dmastp d#, dmamode #0 "Hh"P"F À7 "^ `
..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ´ ; uvoid "® "QPstm32_dma_stream_t î ¿Pstm32_dmaisr_t ¸ È*Á channel A# ifcr M# ishift ý # selfindex ý # vector ý #
" " t "GOß%´ %
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4! ¬> *ú sc_speed # sc_cr1 # sc_cr2 # sc_cr3 # PSerialConfig ³ é Ø
..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil D* Q *Ð set # clear # Sã W H ¯ *å( MODER e# OTYPER e# OSPEEDR e# PUPDR e# IDR e# ODR e# BSRR k# LCKR e# AFRL e# AFRH e#$ t tÐ PGPIO_TypeDef ã *ñ moder # otyper # ospeedr # pupdr # odr # afrl # afrh # Pstm32_gpio_setup_t ²*ç¨ PAData ñ# PBData ñ# PCData ñ#8 PDData ñ#T PEData ñ#p PHData ñ# PPALConfig ØPioportmask_t èPiomode_t í"oPioportid_t £õgqpal_default_config º (
..\..\..\os\hal\include\tm.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil f PTimeMeasurement ² > )£TimeMeasurement OÎ%# "Æ start Î # Oç%# "ß stop ç # last U: # worst U: # best U: # " H
..\..\..\os\kernel\include\chregistry.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil à9 |` char Pchdebug_t ¿ :*É̦ ch_identifier à # ch_zero ý # ch_size ý # ch_version # ch_ptrsize ý # ch_timesize ý # ch_threadsize ý #
cf_off_prio ý # cf_off_ctx ý # cf_off_newer ý #
cf_off_older ý # cf_off_name ý # cf_off_stklimit ý # cf_off_state ý # cf_off_flags ý # cf_off_refs ý # cf_off_preempt ý # cf_off_time ý #
..\..\..\os\kernel\include\chmempools.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil / )Æpool_header ph_next Æ # "¦ * mp_next Æ # mp_object_size w # mp_provider ,; # PMemoryPool Ê 3 $
..\..\..\os\kernel\include\chmboxes.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ä1 ` *( mb_buffer # mb_top # mb_wrptr # mb_rdptr # mb_fullsem < # mb_emptysem < # "i PMailbox ¤ 7 T
..\..\..\os\kernel\include\chheap.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 0 Ì PMemoryHeap - SÏ"ï next ¸ heap Ï "¢ *ï u ´ # size w # Rheap_header align @ h Ó )Ômemory_heap h_provider ,; # h_free ï # h_mtx l # Ð
..\..\..\os\kernel\include\chcond.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ø5 ø )ÀCondVar c_queue # PCondVar ¢ 1 ¸
..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ü] ° *Ð set # clear # Sã W H ¯ *å( MODER e# OTYPER e# OSPEEDR e# PUPDR e# IDR e# ODR e# BSRR k# LCKR e# AFRL e# AFRH e#$ t tÐ PGPIO_TypeDef ã *ñ moder # otyper # ospeedr # pupdr # odr # afrl # afrh # Pstm32_gpio_setup_t ²*ç¨ PAData ñ# PBData ñ# PCData ñ#8 PDData ñ#T PEData ñ#p PHData ñ# PPALConfig ØPioportmask_t èPiomode_t í"oPioportid_t £õ
GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil "ý $
GPS_dekoduj.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil *-ý UTC_time # Status_GPS ý #Êý Latitude ¿ #åý
Longitude Ú #ý Altitude ö ## PNMEA_GPGGA 0
..\main.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil , ô uvoid char int " " 9ç ¼dekodujPrikaz $¡ prikaz æÕý + \zp_neplatny Ê qGPGGA_informace æA > "= @ % ¦@ u ±@ % ¸
..\..\..\test\testthd.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ä T uvoid " C " ¦ ·ª Ì
..\..\..\os\kernel\include\chbsem.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 7 *· bs_sem < # PBinarySemaphore ¢ ? ¼
..\..\..\test\testsem.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ô ¼ uvoid int " C "§ ¾± Ð
..\..\..\test\testqueues.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ü
uvoid unsigned int char " C "» Á ÒÅ À
..\..\..\test\testpools.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil uvoid int " C "© ¯ À³ ¸
..\..\..\test\testmtx.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 0 4 uvoid " C " ¦ ·ª ¸
..\..\..\test\testmsg.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil P uvoid " C " ¦ ·ª ¼
..\..\..\test\testmbox.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ` ( unsigned int C "§ ¾± ¸
..\..\..\test\testheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil h uvoid " C "¡ § ¸« Ä
..\..\..\test\testevt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¬ | uvoid " ø3 ¯ C "¯ µ ƹ
..\..\..\test\testdyn.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ô à! uvoid int " 8í¿regfind $ tp a__result \ftp \found C "í ó ÷ ¤
..\..\..\os\kernel\include\chvt.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ; uvoid " "Pvtfunc_t ª NPVirtualTimer Ò S )°VirtualTimer vt_next 0# vt_prev 0# vt_time µ # vt_func ® # vt_par ¦ # "¾ *ú vt_next 0# vt_prev 0# vt_time µ # vt_systime z# tµ PVTList 4sqvtlist O£%¦
..\..\..\test\testbmk.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ä % uvoid unsigned int " 8éPmsg_loop_test $ tp a__result \n C "é ï ó
..\..\..\test\test.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil t Ø* unsigned int char uvoid int Á£ "£ Ð "« Ð áÔ "F £ "ç <
print_tokens \cp Á 9À[test_printn $ n ±£ \buf (\p Á 9Ýntest_print $ë msgp 9üytest_println $ë msgp 9
clear_tokens 8Ç_test_fail $ point a__result 8¥_test_assert $ point $ condition a__result 9¯Ïtest_wait_threads \i ± 9Ô
execute_test $utcp \i ± 9ï¬
print_line \i GE "ou"y} ü
..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4 @1 9ÐÜgpt_lld_stop_timer $ gptp 9ý
gpt_lld_serve_interrupt $ gptp Ð
..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil @
`4 9Ð1
hal_lld_backup_domain_init Ø
..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil P
6 9Ùúadc_lld_stop_conversion $H adcp
..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4 °: uvoid int "® Pdma_isr_redir_t ò YpK åÖ î¿ "Ö * dma_func K # dma_param » # P
..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil $! Ô= M "¡5 "³ "©0 9ö[
usart_init $¹ sdp $¿ config \u à 9y
usart_deinit $Ã u 9å
set_error $¹ sdp $ sr \sts Ybasepri PäYbasepri P 9Ñ
serve_interrupt $¹ sdp \u à \cr1 \sr \dr Ybasepri PÌYbasepri P àYbasepri P ôYbasepri P ¨\b i Ybasepri P §Ybasepri P ¼Ybasepri P ÐYbasepri P Ü
..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil d# \A 9Ýq
pwm_lld_serve_interrupt $ pwmp \sr è
..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil <) 8E O "¯ "æO 9èM
initgpio $ÏO gpiop $µ config ¸
..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ô) °G 9·utmObjectInit $+Q tmp Ä
..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil * I uvoid " ý "¥ "ý "¡5 "= "» è
..\..\..\os\hal\src\hal.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil * °K 8ê§halIsCounterWithin $U: start $U: end a__result \now U: (
..\..\..\os\hal\src\gpt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil $* M 9ЦgptStartContinuousI $Ò gptp $°
interval 9
ÈgptStartOneShotI $Ò gptp $°
interval 9¨ègptStopTimerI $Ò gptp ä
..\..\..\os\hal\src\adc.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4* üN 9æ´adcStartConversionI $> adcp $¨@ grpp $> samples $w depth
..\..\..\os\kernel\include\chvt.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil à2 pQ uvoid " "Pvtfunc_t ª NPVirtualTimer Ò S )°VirtualTimer vt_next 0# vt_prev 0# vt_time µ # vt_func ® # vt_par ¦ # "¾ *ú vt_next 0# vt_prev 0# vt_time µ # vt_systime z# tµ PVTList 4sO%¦
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil H6 8S <Ò"prio_insert $ tp $Ò tqp \cp " <þ-queue_insert $ tp $Ò tqp ;¸4fifo_remove $Ò tqp a__result \tp ;ò;lifo_remove $Ò tqp a__result \tp ; Bdequeue $ tp a__result "? ;àOlist_remove $ tlp a__result \tp 9Ilist_insert $ tp $ tlp ¨
..\..\..\os\kernel\src\chthreads.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil <6 ¤R uvoid "¡ ", "à 8öE _thread_init $ tp $X prio a__result 8Ú chThdCreateI $§ wsp $w size $X prio $? pf $§ arg a__result \tp 9ªçchThdExitS $i msg \tp \tlp__1 « \tp__2 ± \list_remove__3 ± °
..\..\..\os\kernel\src\chsys.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil `6 LV uvoid " ²@
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil h; ôi <Ò"prio_insert $ tp $Ò tqp \cp " ;;lifo_remove $Ò tqp a__result \tp ;ÀBdequeue $ tp a__result <åIlist_insert $ tp $etlp "? ;¥Olist_remove $etlp a__result \tp 9Ì-queue_insert $ tp $Ò tqp 84fifo_remove $Ò tqp a__result \tp x
..\..\..\os\kernel\src\chsem.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil l6 W "< "ó "à 9chSemResetI $ sp $È n \cnt È \tqp__1 £ \tp © \lifo_remove__2 © 8´²chSemWaitS i $ sp a__result i 8÷óchSemWaitTimeoutS i $ sp $µ time a__result i
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¬6 è[ <Ò"prio_insert $ tp $Ò tqp \cp " <þ-queue_insert $ tp $Ò tqp ;¸;lifo_remove $Ò tqp a__result \tp <ÝIlist_insert $ tp $]tlp "? ;Olist_remove $]tlp a__result \tp 8Ø4fifo_remove $Ò tqp a__result \tp 8Bdequeue $ tp a__result t
..\..\..\os\kernel\src\chschd.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 6 \[ uvoid " 8äJ chSchReadyI $ tp a__result \cp 9lchSchGoSleepS $" newstate \otp 9ÈÂchSchDoRescheduleAhead \otp \cp 9ô©chSchDoRescheduleBehind \otp
..\..\..\os\kernel\include\chschd.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ä6 4\ * r_queue # r_prio X # r_ctx # r_newer # r_older # r_current # PReadyList ¢ d ¨
..\..\..\os\kernel\src\chregistry.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 9 ` âQ
..\..\..\os\kernel\src\chqueues.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 8; da uvoid " "ó "à "á1 ý "¼ 8þ?qwait i $ý1 qp $µ time a__result i "Ï1 "ý
..\..\..\os\kernel\src\chmtx.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil D; f "l "ó "à 9árchMtxLockS $ mp \ctp à\tp 8ãchMtxTryLockS $ mp a__result
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil P; f " <Ð-queue_insert $ tp $¤ tqp ;;lifo_remove $¤ tqp a__result \tp <¯Ilist_insert $ tp $/tlp "? ;ïOlist_remove $/tlp a__result \tp 9"prio_insert $ tp $¤ tqp \cp 8Ù4fifo_remove $¤ tqp a__result \tp 8Bdequeue $ tp a__result `
..\..\..\os\kernel\src\chmempools.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ; <k uvoid "¢ 9ÜchPoolFreeI $\mp $¨ objp \php FT 9¥¤chPoolFree $\mp $¨ objp Ybasepri P¤Ybasepri P 8ÜbchPoolAllocI ¨ $\mp a__result ¨ \objp ¨ "T 8
..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ; øl uvoid "¡ 8ãichCoreAllocI § $w size a__result § \p § "ý óý qImage$$RW_IRAM1$$ZI$$Limit é ý qImage$$RW_IRAM2$$Base ¨
..\..\..\os\kernel\src\chmboxes.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ; <n "·U "i 8ÿchMBPostS i $ mbp $i msg $µ time a__result i \rdymsg i 8×ìchMBPostAheadS i $ mbp $i msg $µ time a__result i \rdymsg i 8ªÉchMBFetchS i $ mbp $¦ msgp $µ time a__result i \rdymsg i ´
..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¤; <q uvoid " "·V "w
..\..\..\os\kernel\src\chevents.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil H< (s "×3 ø3 "¦ 9ÛôchEvtSignalI $ tp $ mask 9±chEvtBroadcastFlagsI $ esp $ flags \elp ³3 °
..\..\..\os\kernel\src\chdynamic.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil T< Xw uvoid "¡ "T
..\..\..\os\kernel\include\chinline.h ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil l< \y " <Ð-queue_insert $ tp $¤ tqp ;;lifo_remove $¤ tqp a__result \tp ;¸Bdequeue $ tp a__result <ÝIlist_insert $ tp $]tlp "? ;Olist_remove $]tlp a__result \tp 9Ì"prio_insert $ tp $¤ tqp \cp 84fifo_remove $¤ tqp a__result \tp
..\..\..\os\kernel\src\chcond.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil `< Ðx "àW "ó "à "l 9üzchCondBroadcastI $ cp \tqp__1 ¤ \tp ª \fifo_remove__2 ª 8ɱchCondWaitS i $ cp a__result i \ctp \mp ° \msg i 8chCondWaitTimeoutS i $ cp $µ time a__result i \mp ° \msg i
..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < 8} "U 9_port_irq_epilogue Ybasepri Pô\ctxp © Ypsp P Ybasepri P °
..\..\..\boards\ST_STM32L_DISCOVERY\board.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < ô [Z GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil èo ¼p ð ?
dekoduj_zpravu_GPS èo ¼p hNMEA_retezec <[ hNMEA_delka ý Yi ý Yj ý Yk ý Yl ý Ypocet_carek ý GPS_dekoduj.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pGPGGA_informace V\ ( t ..\main.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil \h ²o p uvoid char int " " ?ùY
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pwmpcb h h , $ pwmp Ybasepri Éh h Ybasepri ?Úadccb h úh hadcp > $> buffer $w n Ybasepri Ù¨h øh Yavg_ch1 > Yavg_ch2 > Øòh øh Ybasepri >Ñ»Thread_odpal i úh ¤i ø $¡ arg ]__result i PYstav ý Ybasepri Ð i ¤i Ybasepri >äThread_GPS i ¤i jk × $¡ arg ]__result i Pý ó YinBuffer ¨{Yzacatek_retezce ¥ Ykonec_retezce ¥ Ypocet_znaku ý òý c YNMEA_zprava ç >ß±Thread1 i jk k à $¡ arg ]__result i PYseconds_counter I] k ök n(] ²k ðk 3] bA] HÖ >óÕmain ök ²o \ ]__result PÊý Yznaky ¿´á
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L ..\main.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ptp_odpal Ypwmcfg 8 Ygpt2cfg C 0w Yadcgrpcfg ¤@ 8w YUSART2_config v] lw Ysamples k] YwaThread_odpal |] YwaThread_GPS ] H YwaThread1 ] ø ..\..\..\test\testthd.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil e ,h Ì uvoid " >Þ<thread i e ,e hp ^__result i P
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sem4_execute æc e 0 Ybsem _ dYbasepri ×Nd d Ybasepri ëYbasepri P d e Ybasepri ..\..\..\test\testsem.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ysem1 < ü ptestsem1 Ó_ v ptestsem2 Ó_ v ptestsem3 Ó_ ¨v ptestsem4 Ó_ ¸v ppatternsem á_ Èv ..\..\..\test\testqueues.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil è[ ¨`
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N
queues1_setup ê[ \ >¿Sthread1 i \ \ $» p ^__result i P ?ÜZ
queues1_execute \ R^ T \i £ \n w Ybasepri Ybasepri P ®\ 6\ Ybasepri É6\ N\ Ybasepri äN\ R\ Ybasepri øYbasepri P Ybasepri P §R\ z\ Ybasepri »Ybasepri P ÏYbasepri P êz\ ¶\ Ybasepri þYbasepri P Ybasepri P ¶\ è\ Ybasepri ÈÜ\ ú\ Ybasepri ãú\ &] Ybasepri ÷Ybasepri P Ybasepri P ¦&] B] Ybasepri ÁB] Z] Ybasepri ÜZ] ª] Ybasepri ðYbasepri P Ybasepri P ª] Ä] Ybasepri ºÄ] Ö] Ybasepri ÕÖ] Ú] Ybasepri éYbasepri P ýYbasepri P Ú] ^ Ybasepri ¬Ybasepri P ÀYbasepri P Ûð] R^ Ybasepri ?ÿ¥
queues2_setup R^ h^ 4 >º ªthread2 i h^ x^ $» p ^__result i P ?ÿ±
queues2_execute x^ ¨` è \i £ \n w Ybasepri
Ybasepri P ª
z^ Â^ Ybasepri ¾
Ybasepri P Ò
Ybasepri P í
Â^ ä^ Ybasepri ¶ ä^ þ^ Yc ³ ä^ ð^ Ybasepri µ ð^ ø^ Ybasepri Ê Ybasepri P Þ Ybasepri P ù þ^ 2_ Ybasepri Ybasepri P ¡ Ybasepri P ¼ 2_ t_ Ybasepri Ð Ybasepri P ä Ybasepri P ÿ t_ ®_ Ybasepri
Ybasepri P §
Ybasepri P Â
¨_ Ò_ Ybasepri Ý
Ò_ Ü_ Ybasepri ø
Ü_ à_ Ybasepri Ybasepri P Ybasepri P »à_ l` Ybasepri ÏYbasepri P ãYbasepri P þl` ¨` Ybasepri ü ..\..\..\test\testqueues.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Yiq Ï1 ´ Yoq á1 Ø ptestqueues1 §` \v ptestqueues2 §` lv ppatternqueues µ` |v 8 ..\..\..\test\testpools.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil [ Ú[ | uvoid int " >î<null_provider © [ [ $w size ^__result © P ?B
pools1_setup [ [ ?¸G
pools1_execute [ Ú[ Ô \i ¢ Ð ..\..\..\test\testpools.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ymp1 T ¨ ptestpools1 ia Dv ppatternpools wa Tv ô ..\..\..\test\testmtx.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ÐQ [ ¬ uvoid " ?ÃT
mtx1_setup ÐQ ÖQ L >þYthread1 i ÖQ îQ , hp ^__result i P ?«a
mtx1_execute îQ R Yprio X ?Ë
mtx2_setup R R ì >thread2L i R ¸R Ì $ p ^__result i P >éthread2M i ¸R ÐR ¬ $ p ^__result i P >ÿ³thread2H i ÐR òR $ p ^__result i P ?¾
mtx2_execute òR tS ` Ytime µ ?Íñ
mtx3_setup tS S 4 >øthread3LL i S ¢S $ p ^__result i P >Æthread3L i ¢S ÚS ô $ p ^__result i P6 >thread3M i ÚS üS Ô $ p ^__result i P >¾thread3H i üS T ´ $ p ^__result i P >û©thread3HH i T 6T $ p ^__result i P ?©´
mtx3_execute 6T ÞT h Ytime µ ?ÉÕ
mtx4_setup ÞT ðT < >
Ûthread4a i ðT U $ p ^__result i P >Áäthread4b i U U ü $ p ^__result i P ?ª í
mtx4_execute U ÄW Ð Yp X Yp1 X Yp2 X Ybasepri © ^W ÄW Ybasepri ?Ê ¬
mtx5_setup ÄW ÊW ¼ ?ª
±
mtx5_execute ÊW X \b Yprio X Ybasepri ©
X X Ybasepri ?Ê
Þ
mtx6_setup X X d > äthread10 i X ¶X D hp ^__result i P ?ß í
mtx6_execute ¶X pY Yprio X Ybasepri Þ XY pY Ybasepri ?ÿ
mtx7_setup pY Y ì ?
mtx7_execute Y Z À Yprio X ?Í µ
mtx8_setup Z ,Z >
¼thread11 i ,Z XZ t hp ^__result i P* >Ç
Ëthread12 i XZ pZ T hp ^__result i P ?õ
Ó
mtx8_execute pZ [ ( Yprio X ..\..\..\test\testmtx.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Yc1 àW Ym1 l Ym2 l ptestmtx1 $b u ptestmtx2 $b °u ptestmtx3 $b Àu ptestmtx4 $b Ðu ptestmtx5 $b àu ptestmtx6 $b ðu ptestmtx7 $b v ptestmtx8 $b v ppatternmtx 2b v ..\..\..\test\testmsg.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil <Q ºQ uvoid " >Þ;thread i <Q ZQ hp ^__result i P ?C
msg1_execute ZQ ºQ ` \tp \msg i ¼ ..\..\..\test\testmsg.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ptestmsg1 àb u ppatternmsg îb u $ ..\..\..\test\testmbox.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil K 8Q ¤ unsigned int ?ËG
mbox1_setup K K Ì ?¤ L
mbox1_execute K 8Q ¬ \msg1 i Ymsg2 i h\i Ybasepri µ(L `L Ybasepri Ð`L lL Ybasepri ëlL L Ybasepri ÿYbasepri P Ybasepri P ®L ¢L Ybasepri ÂYbasepri P ÖYbasepri P ñ¢L ÀL Ybasepri
Ybasepri P Ybasepri P ´ÀL °M Ybasepri Ï°M ¼M Ybasepri ê¼M ÔM Ybasepri þYbasepri P Ybasepri P ÔM òM Ybasepri ÁYbasepri P ÕYbasepri P ðòM N Ybasepri Ybasepri P Ybasepri P ³N 0N Ybasepri Î0N ¬N Ybasepri é¬N ÞN Ybasepri ÞN ìN Ybasepri ìN O Ybasepri ³Ybasepri P ÇYbasepri P â O >O Ybasepri öYbasepri P Ybasepri P ¥>O tO Ybasepri ÀtO P Ybasepri ÛP 4P Ybasepri ö4P @P Ybasepri @P vP Ybasepri ¥ Ybasepri P ¹ Ybasepri P Ô vP P Ybasepri è Ybasepri P ü Ybasepri P
P ÈP Ybasepri «
Ybasepri P ¿
Ybasepri P Ú
ÈP âP Ybasepri î
Ybasepri P Ybasepri P âP üP Ybasepri ± Ybasepri P Å Ybasepri P à üP Q Ybasepri ô Ybasepri P Ybasepri P £ Q 6Q Ybasepri Ð ..\..\..\test\testmbox.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ymb1 ·U X ptestmbox1 £c pu ppatternmbox ±c u ..\..\..\test\testheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil I K ä uvoid " ?Å@
heap1_setup I I
?E
heap1_execute I K à \p1 ¡ \p2 ¡ \p3 ¡ Yn w hYsz w l Ô ..\..\..\test\testheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ptestheap1 ]d Xu ppatternheap kd hu Ytest_heap jV è
..\..\..\test\testevt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ØD I ô uvoid " ?ÃK
evt1_setup ØD àD Ü ?ãP
h1 àD æD È $x id ?Q
h2 æD ìD ´ $x id ?£R
h3 ìD òD $x id ?ÞU
evt1_execute òD zE C Yel1 D3 XYel2 D3 h ?þ
evt2_setup zE E / >º
thread1 i E E hp ^__result i P >õthread2 i E ´E ï $ p ^__result i P ?Ë
evt2_execute ´E 0H \m Yel1 D3 @Yel2 D3 P\target_time µ ?ë÷
evt3_setup 0H 8H î
?ü
evt3_execute 8H I ´
\m ..\..\..\test\testevt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Yes1 ×3 P Yes2 ×3 T Yevhndl e u ptestevt1 'e u ptestevt2 'e (u ptestevt3 'e 8u ppatternevt 5e Hu ..\..\..\test\testdyn.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil A D h" uvoid int " >åGthread i A A à
hp § ^__result i P
?N
dyn1_setup A $A Ì
?ÐS
dyn1_execute $A B p
Yn w dYsz w hYp1 § Yprio X ?ð
dyn2_setup B B \
?¤
dyn2_execute B òB 0
\i Yprio X ?ÄË
dyn3_setup òB þB
?Ð
dyn3_execute þB D ð Ytp Yprio X Fªçe hC C Ýnýe ef bf Üb f Ü FÙçe C ¨C Þnýe ef bf b f Fçe æC D änýe ef bf Úb f Ú F·çe D &D ånýe ef bf b f Fæçe ND hD ênýe ef bf Âb f  Fçe vD D ënýe ef bf êb f ê ..\..\..\test\testdyn.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ptestdyn1 -f Ìt ptestdyn2 -f Üt ptestdyn3 -f ìt ppatterndyn ;f üt Yheap1 jV ¸
Ymp1 T Ø
t ..\..\..\test\testbmk.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 8 ü? È% uvoid " >ó@thread1 i 8 08 $ p ^__result i PYtp Ymsg i ?Âi
bmk1_execute 08 8 à Yn FÁ h P8 z8 mn¹h eÂh bÐh 8 ?
bmk2_execute 8 9 ´ Yn F h À8 ê8 n¹h eÂh bÐh ¨ >Ïthread2 i 9 9 hp ]__result i P ?¡©
bmk3_execute 9 Ú9 t Yn F h 9 ´9 ±n¹h eÂh bÐh ò >Ëthread4 i Ú9 ú9 T $ p ^__result i P Ymsg i Yself Ybasepri ò9 ø9 Ybasepri ?²Ù
bmk4_execute ú9 : ( Ytp Yn Ybasepri û0: f: Ybasepri f: t: Ybasepri ±t: : Ybasepri ?ò
bmk5_execute : ê: ü Yn Ywap Yprio X ?²°
bmk6_execute ê: <; Ð Yn Ywap Yprio X >íÕthread3 i <; ^; ° $ p ^__result i P ?Ý
bmk7_setup ^; f; ?¸â
bmk7_execute f; < p Yn >ôthread8 i < È< P hp ^__result i P* ?¡
bmk8_execute È< t= Yn d ?
Æ
bmk9_execute t= > ì Í ý Yib Â@
Yiq Ï1 P
Yn Ybasepri
= > Ybasepri ?À
ô
tmo > > Ø $ param ?¶ ö
bmk10_execute > v> ¬ Yvt1 g t
Yvt2 g
Yn Ybasepri µ $> v> Ybasepri ?×
bmk11_setup v> ~> ? £
bmk11_execute ~> à> l Yn ?¤ Í
bmk12_setup à> æ> X ?Ð Ò
bmk12_execute æ> @? , Yn ?ó ù
bmk13_execute @? ü? è ..\..\..\test\testbmk.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ptestbmk1 Ùh Äs ptestbmk2 Ùh Ôs ptestbmk3 Ùh äs ptestbmk4 Ùh ôs ptestbmk5 Ùh t ptestbmk6 Ùh t ptestbmk7 Ùh $t ptestbmk8 Ùh 4t ptestbmk9 Ùh Dt ptestbmk10 Ùh Tt ptestbmk11 Ùh dt ptestbmk12 Ùh tt ptestbmk13 Ùh t ppatternbmk çh t Ysem1 <
Ymtx1 l ¨
8 ..\..\..\test\test.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil @0 Ä7 L, char unsigned int int uvoid " "¶ Iî j @0 0 ú nj b%j `b-j I4j 0 ¸0 Ú nGj I»Qj ¸0 æ0 ® nfj Fº4j ¼0 Ö0 {nGj ?test_emit_token æ0 þ0 htoken Ybasepri ô0 ú0 Ybasepri I·j þ0 1 n j bªj P Iÿ»j 1 "1 r nÖj nàj cðj Fþj 1 1 ¨n j eªj >¶¬_test_assert_sequence "1 ^1 . hpoint hexpected ¼ ___result h Ycp ¼ Fj *1 ,1 °n j eªj F¡j H1 P1 ³n j eªj Fµpj T1 X1 ´ >ä¸_test_assert_time_window ^1 1 hpoint hstart µ hend µ ___result J Fã»j l1 ~1 ºnÖj nàj eðj Fâj t1 ~1 ¨n j eªj ?Ätest_terminate_threads 1 1 î Yi ¯ I²k 1 º1 Î b k ?àtest_cpu_pulse º1 ê1 º hduration Ystart µ Yend µ Ynow µ >Ãõ test_wait_tick µ ê1 ø1 ^__result µ P ?â
tmr ø1 2 $À p ?Ê test_start_timer 2 ,2 f hms Yduration µ Ybasepri É 2 *2 Ybasepri >¸ºTestThread i ,2 Ä7 , hp À ^__result i P Yi ¯ Yj ¯ Ycp ¼ F¹
4j J2 ^2 ÁnGj FÓ
4j f2 z2 ÃnGj Fí
4j 2 2 ÆnGj F 4j 2 ²2 ÉnGj F¡ 4j º2 Î2 ÌnGj F» 4j Ö2 ê2 ÐnGj FÕ 4j ò2 3 ÔnGj Fï 4j 3 "3 ØnGj F Hk X3 v3 âb\k F¥ 4j x3 3 ãnGj FÒ j >3 7 änj b%j °þb-j þ Fì 4j Î3 â3 ånGj F
j æ3 $7 ænj b%j ¦b-j ¦ F³
4j "4 64 çnGj FÍ
4j >4 ø5 ènGj FQj ú5 6 énfj Fÿ
4j ú5 6 {nGj F¼#k *6 h6 ín9k dAk F»k R6 h6 ©b k FÖ4j t6 6 ï nGj F j 6 07 ð nj b%j @Æ b-j Æ F4j Æ6 Ú6 ñ nGj FÎQj ø6 7 ó ffj FÍ4j ø6 7 {nGj FQj 07 P7 ö nfj F4j 07 B7 {nGj FHk r7 7 ûb\k ² F·4j 7 ®7 ýnGj ..\..\..\test\test.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil unsigned int char " Ylocal_fail Yglobal_fail ptest_timer_done Yfailpoint Ytokp £ Ychp Õi Ypatterns uk pwa Ìi °s Ytokens_buffer ¬i pthreads ¹i ( Yvt g < ptest E P , ..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil / 00 Ä2 IÆ(l / (/ L nDl ?½VectorB0 (/ V/ FPl ,/ N/ Ánql F(l </ H/ fDl ?¹gpt_lld_init V/ d/ ?óàgpt_lld_start d/ ¸/ ì hgptp Ypsc ?¡îgpt_lld_stop ¸/ ê/ Ì hgptp ?æÈgpt_lld_start_timer ê/ 0 ¸ hgptp hinterval ô ?¬îgpt_lld_polled_delay 0 00 ¤ hgptp hinterval ô ´ ..\..\..\os\hal\platforms\STM32\gpt_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pGPTD2 û ..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 8- æ. ,5 ?ä^hal_lld_init 8- Ø- t Fã,m - Ô- t ?stm32_clock_init Ø- æ. ` ¤ ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil À) - ¤7 IÊ n À) ì) ¬ n!n ?õ9
adc_lld_serve_rx_interrupt ì) 8+ \ hadcp H hflags Ybasepri \tp È * * Ybasepri è\half w \half_index w \half w \half_index w Ybasepri P ©\tp Ä^* 8+ Ybasepri FÜ n ø) 4* ?f!n Fô n Ê* ð* K f!n ?ë[Vector88 8+ ¼+ 0 Ysr Ybasepri ·\tp Ò~+ ¼+ Ybasepri Fê n Z+ ~+ hf!n ?yadc_lld_init ¼+ à+ ?Ïadc_lld_start à+ ", ä hadcp H Îò+ , \b ?ý³adc_lld_stop ", R, Ä hadcp H ?ÏÉadc_lld_start_conversion R, - ° hadcp H Ymode Ygrpp J ?úadcSTM32EnableTSVREFE - - ?¦adcSTM32DisableTSVREFE - - ¸ ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pADCD1 iH Ô ¼ ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ð' ª) Ô; int uvoid "¹ ?írVector6C Ð' ò' Yflags ?Vector70 ò' ( ò Yflags ?ÃVector74 ( 8( Æ Yflags ?î¨Vector78 8( \( Yflags ?ºVector7C \( ( n Yflags ?ÄÌVector80 ( ¤( B Yflags ?ïÞVector84 ¤( È( Yflags ?ôdmaInit È( ô( \i ² >dmaStreamAllocate ô( z) â hdmastp o hpriority hfunc K hparam ¿ ___result J ?»ÃdmaStreamRelease z) ª) À hdmastp o ü ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil p_stm32_dma_streams o \s Ydma_streams_mask Ydma_isr_redir o @ ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil % ' ? ?ÝÉ
notify1 % ¬% H $ý1 qp ?Ñ
notify2 ¬% ¸% 4 $ý1 qp ?¡
VectorD4 ¸% È% ?¿VectorD8 È% Ø% Ü ?à÷sd_lld_init Ø% ü% ¼ ?Á¢sd_lld_start ü% n& hsdp p hconfig p FÀp <& l& Óf(p f0p b;p ?ßsd_lld_stop n& ®& hsdp p FBp v& & ânWp I±p ®& ' h nÊp bÒp bØp bâp bëp dôp \Ù' *' q dq ø ð*' 8' q dq 8' H' ,q d/q ÍH' |' @q bCq ¨µH' n' Kq dNq ¨ Ìn' r' _q dbq Î ä|' ' tq dwq Ü û' ' q dq è FÁ^p Ä& ' £nqp nyp bp ¤dp ¤À ' ' p dp à è ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ydefault_config ÿo Ps pSD1 ¡5 ¬ pSD2 ¡5 $ 4 ..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil |# % àB ?êíVectorB8 |# Ü# ä FéHr # Ô# ñnhr dsr ?Üpwm_lld_init Ü# ì# Ä ?Òpwm_lld_start ì# ú$ ¤ hpwmp Ypsc Yccer ?Úpwm_lld_stop ú$ ,% hpwmp ?ì pwm_lld_enable_channel ,% h% p hpwmp hchannel h hwidth ëJ% f% Ydier ?´¾pwm_lld_disable_channel h% % \ hpwmp hchannel h ´ ..\..\..\os\hal\platforms\STM32\pwm_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pPWMD4 r h ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil È! Z# F ?h_pal_lld_init È! ®" 0 hconfig 9s Fÿ?s ä! " |fPs f\s F?s " " }fPs f\s F¹?s " >" ~fPs f\s FÖ?s >" \" fPs f\s Fô?s \" " fPs f\s F?s " ¬" fPs f\s ?ê_pal_lld_setgroupmode ®" Z# hport ÓO hmask ¥O hmode ¼O Ymoder Yotyper Yospeedr Ypupdr Yaltr Ybit éÈ" Z# Yaltrmask Ym1 Ym2 Ym4 L ..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil H! ¸! PH ?Ã>
tm_start H! P! ¤ htmp +Q ?õJ
tm_stop P! v! htmp +Q Ynow U: It v! ! | nt ?ÎatmInit ! ¸! D Ytm £P `FÍt ! ¤! hft ¬ ..\..\..\os\hal\src\tm.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ymeasurement_offset U: ..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4 D! I uvoid " >õ7write w 4 > hip ¥ hbp Ót hn w ]__result w P >À=read w > H ð hip ¥ hbp ×t hn w ]__result w P >Cput i H R Ü hip ¥ hb ý ]__result i P >·Hget i R \ È hip ¥ ]__result i P >Mputt i \ b ´ hip ¥ hb ý htimeout µ ]__result i P >ÎRgett i b h hip ¥ htimeout µ ]__result i P >§Wwritet w h n hip ¥ hbp Ót hn w htime µ ]__result w P >ÿ\readt w n t x hip ¥ hbp ×t hn w htime µ ]__result w P ?qsdInit t x d ?å
sdObjectInit x ° D hsdp Ýt hinotify ¾1 honotify ¾1 ?ÅsdStart ° Ì $ hsdp Ýt hconfig ét Ybasepri ÄÄ Ê Ybasepri ?®sdStop Ì ü hsdp Ýt Ybasepri ô ú Ybasepri ?ÏÎsdIncomingDataI ü *! Ø hsdp Ýt hb ý > èsdRequestDataI i *! D! ¸ hsdp Ýt ^__result i PYb i ¤ ..\..\..\os\hal\src\serial.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Yvmt Y5 0s ä ..\..\..\os\hal\src\pwm.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¨ 4 ÐJ ?¸=pwmInit ¨ ¬ À ?æIpwmObjectInit ¬ ¶ ¬ hpwmp ?Ç\pwmStart ¶ Ø hpwmp hconfig ¢ Ybasepri ÆÐ Ö Ybasepri ?qpwmStop Ø ô l hpwmp Ybasepri ì ò Ybasepri ?pwmChangePeriod ô X hpwmp hperiod Ybasepri
Ybasepri ?ú¥pwmEnableChannel 8 hpwmp hchannel t hwidth Ybasepri ù Ybasepri ?æÁpwmDisableChannel 4 hpwmp hchannel t Ybasepri å, 2 Ybasepri ` ..\..\..\os\hal\src\hal.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4 TL ?¸=halInit 4 \ þ Ièu \ ~ ê n©u nµu c¿u * bÏu ?áºhalPolledDelay ~ Ô hticks U: Ystart U: Ytimeout U: Fàu ½n©u nµu e¿u bÏu P , ..\..\..\os\hal\src\gpt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ` 2 ¸M ?¸=gptInit ` d l ?æIgptObjectInit d n X hgptp Ò ?ÇWgptStart n 8 hgptp Ò hconfig G Ybasepri Æ Ybasepri ?kgptStop ¨ hgptp Ò Ybasepri ¦ Ybasepri ?gptChangeInterval ¨ ¾ hgptp Ò hinterval °
Ybasepri
¶ ¼ Ybasepri I¦tv ¾ Æ ð nv nv ?´gptStartContinuous Æ Þ Ð hgptp Ò hinterval °
Ybasepri Ö Ü Ybasepri F³tv Î Ö nv nv IÔ¬v Þ æ ¼ nÆv nÑv ?ß¹gptStartOneShot æ þ hgptp Ò hinterval °
Ybasepri ¾ö ü Ybasepri FÞ¬v î ö ¼nÆv nÑv Iùáv þ nøv ?ëÚgptStopTimer h hgptp Ò Ybasepri Ð Ybasepri Fêáv Ýnøv ?«gptPolledDelay 2 H hgptp Ò hinterval °
\ ..\..\..\os\hal\src\adc.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < \ O ?¸=adcInit < @ ?æIadcObjectInit @ V hadcp > ?ÇhadcStart V t h hadcp > hconfig @ Ybasepri Æl r Ybasepri ?|adcStop t H hadcp > Ybasepri Ybasepri IÅ w 4 n½w nÈw nÓw náw ?÷adcStartConversion ¾ hadcp > hgrpp ¨@ hsamples > hdepth w Ybasepri ʶ ¼ Ybasepri Fö w ¨ ¶ n½w nÈw nÓw náw ?êÓadcStopConversion ¾ î ô hadcp > Ybasepri ÎÜ è Ytp éè ì Ybasepri ?´îadcStopConversionI î È hadcp > ³ Ytp >adcConvert i R ¨ hadcp > hgrpp ¨@ hsamples > hdepth w ^__result i P0Ymsg i Ybasepri ÔJ P Ybasepri F w , : n½w nÈw nÓw náw ?°´adcAcquireBus R X hadcp > ?ÞÈadcReleaseBus X \ $> adcp ¤ ..\..\..\os\kernel\src\chvt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¨ 6 ¸Q uvoid " ?Ç+_vt_init ¨ º î ?EchVTSetI º ò Ú hvtp y htime µ hvtfunc x hpar ¦ Yp y ?ÅcchVTResetI ò Æ hvtp y >¥chTimeIsWithin 6 ° hstart µ hend µ ___result Ytime µ ¨ ..\..\..\os\kernel\src\chvt.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pvtlist py Ì ..\..\..\os\kernel\src\chthreads.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil @ S uvoid "¥ I×G| @ x na| nj| bu| P6 I½| x È l n¡| n©| n´| n¿| nÈ| bÐ| PNbà| F¼G| Æ ¡na| nj| eu| >È´ chThdCreateStatic È . L hwsp « hsize w hprio X hpf ? harg « ^__result PdYtp Ybasepri ã& , Ybasepri FÇ| Ô Án¡| n©| n´| n¿| nÈ| eÐ| bà| FÆG| æ ¡na| nj| eu| >ÎÒ chThdSetPriority X . Z , hnewprio X ^__result X P*Yoldprio X Ybasepri ÍP X Ybasepri >»ó chThdResume Z t htp ^__result PYbasepri ºj r Ybasepri ?chThdTerminate t ø htp Ybasepri Ybasepri ?échThdSleep ¢ Ø htime µ Ybasepri è Ybasepri ?îchThdSleepUntil ¢ À ¸ $µ time Ybasepri ¸ ¾ Ybasepri ? ½chThdYield À â Ybasepri Ú à Ybasepri IÇ ê| â " l nþ| b} ¢b} ¢b } ¢b&} ¢ ?·
ÒchThdExit " h @ hmsg i Ybasepri F¶
ê| * h Õnþ| b} êb} b } b&} >Ì chThdWait i h htp ^__result i P0Ymsg i Ybasepri ¬ Ybasepri FË h{ | ¨n|{ f
{ ..\..\..\os\kernel\src\chsys.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil $ ´V uvoid "¡ ?Ò6_idle_thread Ô $§ p ?MchSysInit Î ´ Ymainthread ã Ybasepri ?chSysTimerHandlerI Î $ Ybasepri ä " Yvtp xg ä " Yfn öf ä " Ybasepri ° ..\..\..\os\kernel\src\chsys.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil p_idle_thread_wa ã} È ä ..\..\..\os\kernel\src\chsem.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ` z X ?ÒOchSemInit ` h " hsp hn È I« h ð! nÀ nÇ dÏ bÙ bä bë ?£fchSemReset Ì Ð! hsp hn È Ybasepri èÄ Ê Ybasepri F¢« À inÀ nÇ dÏ <bÙ bä bë Iæÿ Ì ú °! n c B" Få à î ½nª n³ >chSemWait i ú 4 ! hsp ^__result i P8Ymsg i Ybasepri Û, 2 Ybasepri Fÿ , ¡n e F " ½nª n³ Iä0 4 f |! nP nW cb $" Fã H V nª n³ >²×chSemWaitTimeout i f ¨ \! hsp htime µ ^__result i P@Ymsg i Ybasepri ì ¦ Ybasepri F±0 n ÛnP nW eb F° nª n³ ?®chSemSignal ¨ Ô <! hsp Ybasepri Ì Ò Ybasepri F¼ ¼ Æ nÕ eÝ bí Ü ? ¨chSemSignalI Ô ô (! hsp ïà ô Ytp F ¼ â ì ´
nÕ eÝ bí ?þ ÇchSemAddCounterI ô " ! hsp hn È Ytqp__3 Ytp ¥ Yfifo_remove__4 ¥ >ä çchSemSignalWait i " z è hsps hspw ^__result i PVYmsg i Ybasepri R t Yctp t x Ybasepri Fà ¼ : D önÕ eÝ bí Ú Fã T b ùnª n³ ..\..\..\os\kernel\src\chschd.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil X |\ uvoid "¢ ?Ð0_scheduler_init ¨ # Iù, ¨ Æ # nE bN P b^ I¿h Æ ê p# n~ b F¾ Ò à wn. e6 bF : ?÷
wakeup ê J \# hp ¨ Ytp Ybasepri ø ( Ybasepri °B F Ybasepri FÏP " ne en Fö, & H nE eN b^ >ý¶chSchGoSleepTimeoutS i J ® $# hnewstate " htime µ ^__result i P`ìZ ª Yvt g X F´h R ¾n~ b ºF³ p x wn. e6 bF Ø Füh ¦ Ãn~ b øFû wn. e6 bF þ ?ÚchSchWakeupS ® à" hntp hmsg i Ëþ Yotp Fò, À æ änE eN b^ ¨ F, È æ
nE eN b^ ° Iã J Ì" b¸ b Fâ Çn. e6 bF ú ?ÔöchSchRescheduleS J ¸" FÓ ` ûb¸ Èb ÈFÒ b h Çn. e6 bF Ê I½ Ì Ö ¤" bí F ¦ ®n. e6 bF F¼ , ² Î ³nE eN b^ ? ãchSchDoReschedule Ö X `" FÍ
Ì à X ëbí ÈF¥
ä * ®n. e6 bF Ì FÌ
, 2 N ³nE eN b^ F ì ðb¸ Ôb ÔF î ö Çn. e6 bF Ö ¨ ..\..\..\os\kernel\src\chschd.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil prlist ` ..\..\..\os\kernel\src\chregistry.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil T È` >n chRegFirstThread T l Ì# ^__result PYtp Ybasepri d j Ybasepri >
chRegNextThread l ¬# htp ^__result P&Yntp Ybasepri Ybasepri ° ..\..\..\os\kernel\src\chregistry.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil pch_debug ¾ s ..\..\..\os\kernel\src\chqueues.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil P ôa uvoid "¤ ?XchIQInit @ ÷$ hiqp Æ hbp Ì hsize w hinfy ¾1 hlink ª ?ÚnchIQResetI @ n ×$ hiqp Æ Ytqp__1 r Ytp x Yfifo_remove__2 x >Ì
chIQPutI i n ´ ·$ hiqp Æ hb ý ___result i ®% F˼ ¦ nÕ eÝ bí >«chIQGetTimeout i ´ $ hiqp Æ htime µ ___result i % Yb ý Ybasepri âØ Ymsg i áYbasepri P ý Ybasepri FÁ Ò ´n¡ nª eµ FÀ Þ ì Dnª n³ >âÛchIQReadTimeout w ´ w$ hiqp Æ hbp Ì hn w htime µ ___result w }% Ynfy ¾1 Yr w Ybasepri çn ® Ybasepri ° Ybasepri ¤ ¬ Ybasepri Fá 8 n èn¡ nª eµ Fà V d Dnª n³ ?·chOQInit ´ Î c$ hoqp ~ hbp Ì hsize w honfy ¾1 hlink ª ? ¢chOQResetI Î þ C$ hoqp ~ Ytqp__3 r Ytp x Yfifo_remove__4 x > ÂchOQPutTimeout i þ z #$ hoqp ~ hb ý htime µ ___result i _% Ybasepri
p Ymsg i ¬
8 F Ybasepri È
p v Ybasepri F F Èn¡ nª eµ F . Dnª n³ >ÿ ächOQGetI i z ¾ $ hoqp ~ ___result i A% Yb ý Fþ ¼ ª ° ònÕ eÝ bí > chOQWriteTimeout w ¾ P à# hoqp ~ hbp hn w htime µ ___result w #% Ynfy ¾1 Yw w Ybasepri ¥
J Ybasepri À
6 L Ybasepri Û
@ H Ybasepri F Ö n¡ nª eµ F è ö Dnª n³ ..\..\..\os\kernel\src\chmtx.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ü Üf ?ÉOchMtxInit ü ®& hmp q IÔ Ø v& n b Ö § bª F§[ : X no nx b > FÆÅ 2 8 nÚ eã Fí[ t no nx b x FÅ l r nÚ eã F«Å ¢ nÚ eã FÓ[ ¦  ¦no nx b ª ?¦`chMtxLock Ø ì V& hmp q Ybasepri ¥ä ê Ybasepri Iɵ ì
B& nÑ cØ Â& >ßÇchMtxTryLock
4 .& hmp q ^__result P(Yb Ybasepri ¿, 2 Ybasepri FÞµ , ÌnÑ eØ >®úchMtxUnlock q 4 & ^__result q PTYctp Yump q Ymp q Ybasepri ëL Ytp Ynewprio X Ybasepri F j t n£ e« b» î >Ô¶chMtxUnlockS q Ô î% ^__result q PHYctp Yump q Ymp q ¬ Ò Ytp Ynewprio X FÓ º Ä Ùn£ e« b» ¾ ?
ïchMtxUnlockAll Ô Ì% Yctp Ybasepri Ytqp__4 w Ytp__5 } Yfifo_remove__6 } ï æ Yump q î ð Ytp
Ybasepri , ..\..\..\os\kernel\src\chmsg.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil x ø @j >¿DchMsgSend i x ² ' htp $i msg ^__result i P8Yctp Ybasepri ¨ ® Ybasepri F¾ Lnª n³ >Îc chMsgWait ² ä ' ^__result P0Ytp Ybasepri ¨Ü â Ybasepri Fͼ Ì Ø inÕ eÝ bí T ?®ychMsgRelease ä ø à& htp hmsg i Ybasepri ð ö Ybasepri Ø ..\..\..\os\kernel\src\chmempools.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ä
v Ðk uvoid "¦ ?õ7chPoolInit ä
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Ô' hmp T hsize w hprovider ,; I¤ î
ö
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§f¹ nÀ bÉ ?MchPoolLoadArray
2 ' hmp T hp ¬ hn w FÔ & Rfè nï dø .ó $ d < F¤ & §f¹ nÀ bÉ 8 IÄ 2 N `' n5 b< PbJ >ÚychPoolAlloc ¬ N v @' hmp T ^__result ¬ P&Yobjp ¬ Ybasepri µn t Ybasepri FÙ X n }f5 e< bJ t Ä ..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil x
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m uvoid "¥ ?Î;_core_init x
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è' ^__result w P À ..\..\..\os\kernel\src\chmemcore.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ynextmem ? Yendmem ? ..\..\..\os\kernel\src\chmboxes.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil v
Ìn ?àAchMBInit D z) hmbp 8 hbuf > hn È ?³TchMBReset D x Z) hmbp 8 Ybasepri ²p v Ybasepri IèD x ® :) n\ nd nn by P4b >©schMBPost i ® ð ) hmbp 8 hmsg i htime µ ^__result i P@Yrdymsg i Ybasepri öæ î Ybasepri F¨D ¼ æ wn\ nd nn ey b >÷®chMBPostI i ð ú( hmbp 8 hmsg i ___result i â) I¬ V Ú( n´ n¼ nÆ bÑ P4bá >ôÐchMBPostAhead i V º( hmbp 8 hmsg i htime µ ^__result i P@Yrdymsg i Ybasepri À Ybasepri Fó d Ôn´ n¼ nÆ eÑ bá È >ÇchMBPostAheadI i È ( hmbp 8 hmsg i ___result i Ä) Iüï È
z( n n n b$ P6b4 >À chMBFetch i
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Z( hmbp 8 hmsgp > htime µ ^__result i PBYrdymsg i Ybasepri :
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8( hmbp 8 hmsgp > ___result i ¦) 8 ..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ì ¤q uvoid "¢ ?ËD_heap_init Ì Þ * ?\chHeapInit Þ ò {* hheapp V hbuf ¨ hsize w Yhp ì >}chHeapAlloc ¨ ò r
[* hheapp V $w size ___result ¨ £* Yqp ì \hp ì Yfp ì ?È»chHeapFree r
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#* hp ¨ Yqp ì Yhp ì Yheapp V >¹óchHeapStatus w Ü
* hheapp V hsizep ò ^__result w P4Yqp ì Yn w Ysz w ° ..\..\..\os\kernel\src\chheap.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ydefault_heap jV @ ..\..\..\os\kernel\src\chevents.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil È ¸s ?NchEvtRegisterMask ² , hesp help ³3 hmask Ybasepri ª ® Ybasepri ?hchEvtUnregister ² Ü ~, hesp help ³3 Yp ³3 Ybasepri Ô Ú Ybasepri >
chEvtGetAndClearEvents Ü ü j, hmask ^__result P Ym Ybasepri
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chEvtAddEvents ü V, $ mask ^__result PYbasepri ö
Ybasepri I¬ F 6, n nË IÞ× F , nõ ný b Fݬ d ºn nË >ãÊ
chEvtGetAndClearFlags ¨ , help ³3 ^__result PYflags Ybasepri â ¦ Ybasepri ?äÞchEvtSignal ¨ ä â+ htp hmask Ybasepri ÃÞ â Ybasepri F㬠° Ú ãn nË ? chEvtBroadcastFlags ä > Â+ hesp hflags Ybasepri Î6 : Ybasepri F × ò 2 nõ ný b ÞF ¬ , ºn nË >ó ¢
chEvtGetAndClearFlagsI > H ®+ help ³3 ^__result PYflags ?½
´chEvtDispatch H x + hhandlers ¨ hmask Yeid x >À ×
chEvtWaitOne x ª n+ hmask ^__result P0Yctp \m Ybasepri ¿ ¨ Ybasepri >Ä ô
chEvtWaitAny ª Ø N+ hmask ^__result P,Yctp Ym Ybasepri Ã Î Ö Ybasepri >¿
chEvtWaitAll Ø .+ hmask ^__result P,Yctp Ybasepri ¾
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chEvtWaitOneTimeout J + hmask htime µ ___result â, Yctp \m Ybasepri Ö0 B Ybasepri P ñ H Ybasepri & . Ybasepri >Üâ
chEvtWaitAnyTimeout J î* hmask htime µ ___result Ä, Yctp Ym Ybasepri ¥p Ybasepri P Àb Ybasepri Ûf n Ybasepri >¢
chEvtWaitAllTimeout È Ì* hmask htime µ ___result ¦, Yctp Ybasepri ë¦ ² Ybasepri P ² Ä Ybasepri ¡¾ Æ Ybasepri à ..\..\..\os\kernel\src\chdynamic.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ¬ Äw uvoid "¥ >- chThdAddRef ¬ À T- htp ^__result PYbasepri ¸ ¾ Ybasepri ?üCchThdRelease À @- htp Yrefs 4 Ybasepri ûÐ Ybasepri >²{ chThdCreateFromHeap T - hheapp V hsize w hprio X hpf ? harg « ___result - Ywsp « Ytp Ybasepri ±J R Ybasepri >ଠchThdCreateFromMemoryPool T - hmp à hprio X hpf ? harg « ___result h- Ywsp « Ytp Ybasepri ß Ybasepri Ä ..\..\..\os\kernel\src\chcond.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ø ¨ ¨y ?Ë4chCondInit Ø Þ ¤. hcp v ?ÅBchCondSignal Þ . hcp v Ybasepri ú Ybasepri FÄ ì ò Hn± e¹ bÉ ?WchCondSignalI d. hcp v F ]n± e¹ bÉ 4 IÅ D D. n§ b® Fb¹ FbÀ F ?ËgchCondBroadcast D z $. hcp v Ybasepri r x Ybasepri FÊ N n jn§ b® vb¹ vbÀ v IªÔ z ¼ . nî bõ P>b b b F©i ª ¾n} n b ´ >þchCondWait i ¼ ä- hcp v ^__result i PJYmsg i Ybasepri Ybasepri FýÔ Æ þ nî eõ b îb b Füi Ò ð ¾n} n b ú IÜ! R Ä- nB nI bT PFbd bk FÛi 8 n} n b Ä >à âchCondWaitTimeout i R ¨ ¤- hcp v htime µ ^__result i PRYmsg i Ybasepri å ¤ Ybasepri F ! ` ænB nI eT bd bk FÁ i l n} n b ..\..\..\os\ports\common\ARMCMx\nvic.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 8 Î | unsigned int ?û'nvicEnableVector 8 x à. hn hprio Ysh © ?²5nvicDisableVector x ¬ Ì. hn Ysh © ?CnvicSetSystemHandlerPriority ¬ Î ¸. hhandler hprio Ysh © Ð ¤ ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\STM32L1xx\\vectors.s ARM Assembler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil 4 6 Ì| _unhandled_exception 4 6 ô ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < Ü} Iø' < l/ eC áT S dV d_ ÷J R l do ?(SysTickVector Þ L/ Ybasepri à Ybasepri F' Ü 0dC \÷¬ Ü S dV pd_ p ¤ ª l do h ?Õ:SVCallVector Þ ð 8/ \ctxp ! Ypsp Ybasepri ?ôq_port_init ð / ¤ ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\chcoreasm_v7m.s ARM Assembler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil < _port_switch ( _port_thread_start ( 6 _port_switch_from_isr 6 < Ô ¤ ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\cstartup.s ARM Assembler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ø Reset_Handler Ø ò __early_init ò ô ì ..\..\..\boards\ST_STM32L_DISCOVERY\board.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil Ð Ö X ?Ï0__early_init Ð Ô / ?íeboardInit Ô Ö / À ..\..\..\boards\ST_STM32L_DISCOVERY\board.c ARM C/C++ Compiler, 5.03 [Build 24] D:\GIT repositáø\ChibiOS\demos\Zkouska - STM32L152-DISCOVERY\keil ppal_default_config . pr | q
C:\Program Files\Keil\ARM\ARMCC\bin\..\include\ GPS_dekoduj.c GPS_dekoduj.h string.h l `
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} V ` } . V } . } } ( 6 } 6 Z } ä æ } æ ( } ¬ ® } ® ä } | } ¬ } : < } < | } } : } Ô â } â } } Ô } \ ^ } ^ } ( * } * \ } } " }" ( } 2 4 PX Z P Pª ¬ P Þ à P P } F } ¦ ¨ } ¨ } } } & * } * ¦ } & } } z ~ P P¢ ¦ P ö ø } ø 4 } ¶ ¸ } ¸ ö } r t } t ¶ } D F } F r } } D } ä æ } æ } ´ ¸ } ¸ ä } ª ´ } P T } T ª } } P } } ² ¶ } ¶ } } ² } h } H h } H } } $ & P2 4 P Ø Ú Pô ö P P´ ¶ P ¨ ª } ª è } j l } l ¨ } j } } ¸ ¼ Pæ è P z ~ P¦ ¨ P z ~ } ~ Ð } 0 4 } 4 z } ä æ } æ 0 } ¢ ¦ } ¦ ä } l n } n ¢ } F H } H l } * 4 } 4 F } } * } } t } @ t } } > }> @ } ´ ¸ } ¸ Ú }Ú à } ¢ ´ } J L } L ¢ } J } } } _GPS_DEKODUJ_H_ ADC_GRP1_NUM_CHANNELS 2 ADC_GRP1_BUF_DEPTH 4 #MAX_DELKA_PRIKAZU 10 &GPS_BUFFER 500 _GPS_DEKODUJ_H_ 4ALLOWED_DELAY MS2ST(5) 7TEST_QUEUES_SIZE 4 =ALLOWED_DELAY 5 4ALLOWED_DELAY MS2ST(5) 5MB_SIZE 5 1SIZE 16 4ALLOWED_DELAY MS2ST(5) _TEST_H_ DELAY_BETWEEN_TESTS 200 'TEST_NO_BENCHMARKS FALSE *MAX_THREADS 5 +MAX_TOKENS 16 4THREADS_STACK_SIZE 128 6WA_SIZE THD_WA_SIZE(THREADS_STACK_SIZE) ltest_fail(point) { _test_fail(point); return; } xtest_assert(point,condition,msg) { if (_test_assert(point, condition)) return; } test_assert_lock(point,condition,msg) { chSysLock(); if (_test_assert(point, condition)) { chSysUnlock(); return; } chSysUnlock(); } test_assert_sequence(point,expected) { if (_test_assert_sequence(point, expected)) return; } test_assert_time_window(point,start,end) { if (_test_assert_time_window(point, start, end)) return; } ! "
# $ %
&' _TEST_H_ DELAY_BETWEEN_TESTS 200 'TEST_NO_BENCHMARKS FALSE *MAX_THREADS 5 +MAX_TOKENS 16 4THREADS_STACK_SIZE 128 6WA_SIZE THD_WA_SIZE(THREADS_STACK_SIZE) ltest_fail(point) { _test_fail(point); return; } xtest_assert(point,condition,msg) { if (_test_assert(point, condition)) return; } test_assert_lock(point,condition,msg) { chSysLock(); if (_test_assert(point, condition)) { chSysUnlock(); return; } chSysUnlock(); } test_assert_sequence(point,expected) { if (_test_assert_sequence(point, expected)) return; } test_assert_time_window(point,start,end) { if (_test_assert_time_window(point, start, end)) return; } _GPT_H_ I\gptChangeIntervalI(gptp,interval) { gpt_lld_change_interval(gptp, interval); } _GPT_LLD_H_ 0STM32_GPT_USE_TIM1 FALSE TSTM32_GPT_USE_TIM5 FALSE ]STM32_GPT_USE_TIM6 FALSE fSTM32_GPT_USE_TIM7 FALSE oSTM32_GPT_USE_TIM8 FALSE xSTM32_GPT_USE_TIM9 FALSE STM32_GPT_USE_TIM11 FALSE STM32_GPT_USE_TIM12 FALSE STM32_GPT_USE_TIM14 FALSE STM32_GPT_TIM1_IRQ_PRIORITY 7 ¶STM32_GPT_TIM5_IRQ_PRIORITY 7 ½STM32_GPT_TIM6_IRQ_PRIORITY 7 ÄSTM32_GPT_TIM7_IRQ_PRIORITY 7 ËSTM32_GPT_TIM8_IRQ_PRIORITY 7 ÒSTM32_GPT_TIM9_IRQ_PRIORITY 7 ÙSTM32_GPT_TIM11_IRQ_PRIORITY 7 àSTM32_GPT_TIM12_IRQ_PRIORITY 7 çSTM32_GPT_TIM14_IRQ_PRIORITY 7 °gpt_lld_change_interval(gptp,interval) ((gptp)->tim->ARR = (uint16_t)((interval) - 1)) _ADC_LLD_H_ &ADC_CR2_EXTSEL_SRC(n) ((n) << 24) -ADC_CCR_ADCPRE_DIV1 0 .ADC_CCR_ADCPRE_DIV2 1 /ADC_CCR_ADCPRE_DIV4 2 6ADC_CHANNEL_IN0 0 7ADC_CHANNEL_IN1 1 8ADC_CHANNEL_IN2 2 9ADC_CHANNEL_IN3 3 :ADC_CHANNEL_IN4 4 ;ADC_CHANNEL_IN5 5 <ADC_CHANNEL_IN6 6 =ADC_CHANNEL_IN7 7 >ADC_CHANNEL_IN8 8 ?ADC_CHANNEL_IN9 9 @ADC_CHANNEL_IN10 10 AADC_CHANNEL_IN11 11 BADC_CHANNEL_IN12 12 CADC_CHANNEL_IN13 13 DADC_CHANNEL_IN14 14 EADC_CHANNEL_IN15 15 FADC_CHANNEL_SENSOR 16 GADC_CHANNEL_VREFINT 17 HADC_CHANNEL_IN18 18 IADC_CHANNEL_IN19 19 JADC_CHANNEL_IN20 20 KADC_CHANNEL_IN21 21 LADC_CHANNEL_IN22 22 MADC_CHANNEL_IN23 23 NADC_CHANNEL_IN24 24 OADC_CHANNEL_IN25 25 VADC_SAMPLE_4 0 WADC_SAMPLE_9 1 XADC_SAMPLE_16 2 YADC_SAMPLE_24 3 ZADC_SAMPLE_48 4 [ADC_SAMPLE_96 5 \ADC_SAMPLE_192 6 ]ADC_SAMPLE_384 7 ySTM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 ¯STM32_DMA_REQUIRED ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
ADC_SQR5_SQ1_N(n) ((n) << 0) ADC_SQR5_SQ2_N(n) ((n) << 5) ADC_SQR5_SQ3_N(n) ((n) << 10) ADC_SQR5_SQ4_N(n) ((n) << 15) ADC_SQR5_SQ5_N(n) ((n) << 20) ADC_SQR5_SQ6_N(n) ((n) << 25) ADC_SQR4_SQ7_N(n) ((n) << 0) ADC_SQR4_SQ8_N(n) ((n) << 5) ADC_SQR4_SQ9_N(n) ((n) << 10) ADC_SQR4_SQ10_N(n) ((n) << 15) ADC_SQR4_SQ11_N(n) ((n) << 20) ADC_SQR4_SQ12_N(n) ((n) << 25) ADC_SQR3_SQ13_N(n) ((n) << 0) ADC_SQR3_SQ14_N(n) ((n) << 5) ADC_SQR3_SQ15_N(n) ((n) << 10) ADC_SQR3_SQ16_N(n) ((n) << 15) ADC_SQR3_SQ17_N(n) ((n) << 20) ADC_SQR3_SQ18_N(n) ((n) << 25) ADC_SQR2_SQ19_N(n) ((n) << 0) ADC_SQR2_SQ20_N(n) ((n) << 5) ADC_SQR2_SQ21_N(n) ((n) << 10) ADC_SQR2_SQ22_N(n) ((n) << 15) ADC_SQR2_SQ23_N(n) ((n) << 20) ADC_SQR2_SQ24_N(n) ((n) << 25) ¡ADC_SQR1_SQ25_N(n) ((n) << 0) ¢ADC_SQR1_SQ26_N(n) ((n) << 5) £ADC_SQR1_SQ27_N(n) ((n) << 10) ªADC_SMPR3_SMP_AN0(n) ((n) << 0) «ADC_SMPR3_SMP_AN1(n) ((n) << 3) ¬ADC_SMPR3_SMP_AN2(n) ((n) << 6) ADC_SMPR3_SMP_AN3(n) ((n) << 9) ®ADC_SMPR3_SMP_AN4(n) ((n) << 12) ¯ADC_SMPR3_SMP_AN5(n) ((n) << 15) °ADC_SMPR3_SMP_AN6(n) ((n) << 18) ±ADC_SMPR3_SMP_AN7(n) ((n) << 21) ²ADC_SMPR3_SMP_AN8(n) ((n) << 24) ³ADC_SMPR3_SMP_AN9(n) ((n) << 27) µADC_SMPR2_SMP_AN10(n) ((n) << 0) ¶ADC_SMPR2_SMP_AN11(n) ((n) << 3) ·ADC_SMPR2_SMP_AN12(n) ((n) << 6) ¸ADC_SMPR2_SMP_AN13(n) ((n) << 9) ¹ADC_SMPR2_SMP_AN14(n) ((n) << 12) ºADC_SMPR2_SMP_AN15(n) ((n) << 15) »ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) ½ADC_SMPR2_SMP_VREF(n) ((n) << 21) ¿ADC_SMPR2_SMP_AN18(n) ((n) << 24) ÀADC_SMPR2_SMP_AN19(n) ((n) << 27) ÂADC_SMPR1_SMP_AN20(n) ((n) << 0) ÃADC_SMPR1_SMP_AN21(n) ((n) << 3) ÄADC_SMPR1_SMP_AN22(n) ((n) << 6) ÅADC_SMPR1_SMP_AN23(n) ((n) << 9) ÆADC_SMPR1_SMP_AN24(n) ((n) << 12) ÇADC_SMPR1_SMP_AN25(n) ((n) << 15) !.STM32_DMA1_STREAMS_MASK 0x0000007F 3STM32_DMA2_STREAMS_MASK 0x00000F80 8STM32_DMA_CCR_RESET_VALUE 0x00000000 _STM32_DMA_H_ 'STM32_DMA_STREAMS 7 ,STM32_DMA_ISR_MASK 0x0F 7STM32_DMA_GETCHANNEL(n,c) 0 ASTM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) JSTM32_DMA_STREAM_ID(dma,stream) ((stream) - 1) TSTM32_DMA_STREAM_ID_MSK(dma,stream) (1 << STM32_DMA_STREAM_ID(dma, stream)) `STM32_DMA_IS_VALID_ID(id,mask) (((1 << (id)) & (mask))) mSTM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) oSTM32_DMA1_STREAM1 STM32_DMA_STREAM(0) pSTM32_DMA1_STREAM2 STM32_DMA_STREAM(1) qSTM32_DMA1_STREAM3 STM32_DMA_STREAM(2) rSTM32_DMA1_STREAM4 STM32_DMA_STREAM(3) sSTM32_DMA1_STREAM5 STM32_DMA_STREAM(4) tSTM32_DMA1_STREAM6 STM32_DMA_STREAM(5) uSTM32_DMA1_STREAM7 STM32_DMA_STREAM(6) |STM32_DMA_CR_EN DMA_CCR1_EN }STM32_DMA_CR_TEIE DMA_CCR1_TEIE ~STM32_DMA_CR_HTIE DMA_CCR1_HTIE STM32_DMA_CR_TCIE DMA_CCR1_TCIE STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) STM32_DMA_CR_DIR_P2M 0 STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM STM32_DMA_CR_CIRC DMA_CCR1_CIRC
STM32_DMA_CR_PINC DMA_CCR1_PINC STM32_DMA_CR_MINC DMA_CCR1_MINC STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE STM32_DMA_CR_PSIZE_BYTE 0 STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE STM32_DMA_CR_MSIZE_BYTE 0 STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | STM32_DMA_CR_MSIZE_MASK) STM32_DMA_CR_PL_MASK DMA_CCR1_PL STM32_DMA_CR_PL(n) ((n) << 12) STM32_DMA_CR_DMEIE 0 STM32_DMA_CR_CHSEL_MASK 0 STM32_DMA_CR_CHSEL(n) 0 ¢STM32_DMA_ISR_FEIF 0 £STM32_DMA_ISR_DMEIF 0 ¤STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 ¥STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 ¦STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 ÝdmaStreamSetPeripheral(dmastp,addr) { (dmastp)->channel->CPAR = (uint32_t)(addr); } ìdmaStreamSetMemory0(dmastp,addr) { (dmastp)->channel->CMAR = (uint32_t)(addr); } ûdmaStreamSetTransactionSize(dmastp,size) { (dmastp)->channel->CNDTR = (uint32_t)(size); } dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) dmaStreamSetMode(dmastp,mode) { (dmastp)->channel->CCR = (uint32_t)(mode); } ¥dmaStreamEnable(dmastp) { (dmastp)->channel->CCR |= STM32_DMA_CR_EN; } ·dmaStreamDisable(dmastp) { (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); dmaStreamClearInterrupt(dmastp); } ÇdmaStreamClearInterrupt(dmastp) { *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; } ÞdmaStartMemCopy(dmastp,mode,src,dst,n) { dmaStreamSetPeripheral(dmastp, src); dmaStreamSetMemory0(dmastp, dst); dmaStreamSetTransactionSize(dmastp, n); dmaStreamSetMode(dmastp, (mode) | STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); } îdmaWaitCompletion(dmastp) { while ((dmastp)->channel->CNDTR > 0) ; dmaStreamDisable(dmastp); } _SERIAL_LLD_H_ KSTM32_SERIAL_USE_UART4 FALSE TSTM32_SERIAL_USE_UART5 FALSE ]STM32_SERIAL_USE_USART6 FALSE ySTM32_SERIAL_UART4_PRIORITY 12 STM32_SERIAL_UART5_PRIORITY 12 STM32_SERIAL_USART6_PRIORITY 12 î_serial_driver_data _base_asynchronous_channel_data sdstate_t state; InputQueue iqueue; OutputQueue oqueue; uint8_t ib[SERIAL_BUFFERS_SIZE]; uint8_t ob[SERIAL_BUFFERS_SIZE]; USART_TypeDef *usart;
USART_CR2_STOP1_BITS (0 << 12) USART_CR2_STOP0P5_BITS (1 << 12) USART_CR2_STOP2_BITS (2 << 12) USART_CR2_STOP1P5_BITS (3 << 12) _PWM_H_ -PWM_OUTPUT_MASK 0x0F 2PWM_OUTPUT_DISABLED 0x00 7PWM_OUTPUT_ACTIVE_HIGH 0x01 <PWM_OUTPUT_ACTIVE_LOW 0x02 `xPWM_FRACTION_TO_WIDTH(pwmp,denominator,numerator) ((uint16_t)((((uint32_t)(pwmp)->period) * (uint32_t)(numerator)) / (uint32_t)(denominator))) PWM_DEGREES_TO_WIDTH(pwmp,degrees) PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) PWM_PERCENTAGE_TO_WIDTH(pwmp,percentage) PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) °pwmChangePeriodI(pwmp,period) { (pwmp)->period = (period); pwm_lld_change_period(pwmp, period); } ÃpwmEnableChannelI(pwmp,channel,width) pwm_lld_enable_channel(pwmp, channel, width) ÔpwmDisableChannelI(pwmp,channel) pwm_lld_disable_channel(pwmp, channel) àpwmIsChannelEnabledI(pwmp,channel) pwm_lld_is_channel_enabled(pwmp, channel) _PWM_LLD_H_ %PWM_CHANNELS 4 +PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 1PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 :PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 CPWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 TSTM32_PWM_USE_ADVANCED FALSE ]STM32_PWM_USE_TIM1 FALSE STM32_PWM_USE_TIM5 FALSE STM32_PWM_USE_TIM8 FALSE STM32_PWM_USE_TIM9 FALSE STM32_PWM_TIM1_IRQ_PRIORITY 7 ¶STM32_PWM_TIM5_IRQ_PRIORITY 7 ½STM32_PWM_TIM8_IRQ_PRIORITY 7 ÅSTM32_PWM_TIM9_IRQ_PRIORITY 7 pwm_lld_change_period(pwmp,period) ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) ¢pwm_lld_is_channel_enabled(pwmp,channel) (((pwmp)->tim->CCR[channel] != 0) || (((pwmp)->tim->DIER & (2 << channel)) != 0)) #AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) &AHB_LPEN_MASK AHB_EN_MASK _PAL_LLD_H_ "PAL_MODE_RESET #PAL_MODE_UNCONNECTED $PAL_MODE_INPUT %PAL_MODE_INPUT_PULLUP &PAL_MODE_INPUT_PULLDOWN 'PAL_MODE_INPUT_ANALOG (PAL_MODE_OUTPUT_PUSHPULL )PAL_MODE_OUTPUT_OPENDRAIN /PAL_STM32_MODE_MASK (3 << 0) 0PAL_STM32_MODE_INPUT (0 << 0) 1PAL_STM32_MODE_OUTPUT (1 << 0) 2PAL_STM32_MODE_ALTERNATE (2 << 0) 3PAL_STM32_MODE_ANALOG (3 << 0) 5PAL_STM32_OTYPE_MASK (1 << 2) 6PAL_STM32_OTYPE_PUSHPULL (0 << 2) 7PAL_STM32_OTYPE_OPENDRAIN (1 << 2) 9PAL_STM32_OSPEED_MASK (3 << 3) :PAL_STM32_OSPEED_LOWEST (0 << 3) >PAL_STM32_OSPEED_MID1 (1 << 3) ?PAL_STM32_OSPEED_MID2 (2 << 3) APAL_STM32_OSPEED_HIGHEST (3 << 3) CPAL_STM32_PUDR_MASK (3 << 5) DPAL_STM32_PUDR_FLOATING (0 << 5) EPAL_STM32_PUDR_PULLUP (1 << 5) FPAL_STM32_PUDR_PULLDOWN (2 << 5) HPAL_STM32_ALTERNATE_MASK (15 << 7) IPAL_STM32_ALTERNATE(n) ((n) << 7) PPAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | PAL_STM32_ALTERNATE(n)) [PAL_MODE_RESET PAL_STM32_MODE_INPUT `PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP ePAL_MODE_INPUT PAL_STM32_MODE_INPUT jPAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | PAL_STM32_PUDR_PULLUP) pPAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | PAL_STM32_PUDR_PULLDOWN) vPAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG {PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | PAL_STM32_OTYPE_PUSHPULL) PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | PAL_STM32_OTYPE_OPENDRAIN) ÝPAL_IOPORTS_WIDTH 16 ãPAL_WHOLE_PORT ((ioportmask_t)0xFFFF) IOPORT1 GPIOA IOPORT2 GPIOB IOPORT3 GPIOC IOPORT4 GPIOD IOPORT5 GPIOE ²IOPORT8 GPIOH Æpal_lld_init(config) _pal_lld_init(config) Ôpal_lld_readport(port) ((port)->IDR) âpal_lld_readlatch(port) ((port)->ODR) îpal_lld_writeport(port,bits) ((port)->ODR = (bits)) úpal_lld_setport(port,bits) ((port)->BSRR.H.set = (uint16_t)(bits)) pal_lld_clearport(port,bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) pal_lld_writegroup(port,mask,offset,bits) ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | (((bits) & (mask)) << (offset))) ¥pal_lld_setgroupmode(port,mask,offset,mode) _pal_lld_setgroupmode(port, mask << offset, mode) ²pal_lld_writepad(port,pad,bit) pal_lld_writegroup(port, 1, pad, bit) _CHVT_H_ .S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) :MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) GUS2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) chVTDoTickI() { vtlist.vt_systime++; if (&vtlist != (VTList *)vtlist.vt_next) { VirtualTimer *vtp; --vtlist.vt_next->vt_time; while (!(vtp = vtlist.vt_next)->vt_time) { vtfunc_t fn = vtp->vt_func; vtp->vt_func = (vtfunc_t)NULL; vtp->vt_next->vt_prev = (void *)&vtlist; (&vtlist)->vt_next = vtp->vt_next; chSysUnlockFromIsr(); fn(vtp->vt_par); chSysLockFromIsr(); } } } chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) ®chVTSet(vtp,time,vtfunc,par) { chSysLock(); chVTSetI(vtp, time, vtfunc, par); chSysUnlock(); } ¼chVTReset(vtp) { chSysLock(); if (chVTIsArmedI(vtp)) chVTResetI(vtp); chSysUnlock(); } ÎchTimeNow() (vtlist.vt_systime) 9 _CHINLINE_H_ $ <Csem_insert(tp,qp) queue_insert(tp, qp) " _CHINLINE_H_ _CHSCHD_H_ $RDY_OK 0 %RDY_TIMEOUT -1 'RDY_RESET -2 /NOPRIO 0 0IDLEPRIO 1 1LOWPRIO 2 2NORMALPRIO 64 3HIGHPRIO 127 4ABSPRIO 255 ATIME_IMMEDIATE ((systime_t)0) GTIME_INFINITE ((systime_t)-1) Ofirstprio(rlp) ((rlp)->p_next->p_prio) scurrp rlist.r_current ~setcurrp(tp) (currp = (tp)) ³chSchIsRescRequiredI() (firstprio(&rlist.r_queue) > currp->p_prio) ¾chSchCanYieldS() (firstprio(&rlist.r_queue) >= currp->p_prio) ÉchSchDoYieldS() { if (chSchCanYieldS()) chSchDoRescheduleBehind(); } ×chSchPreemption() { tprio_t p1 = firstprio(&rlist.r_queue); tprio_t p2 = currp->p_prio; if (currp->p_preempt) { if (p1 > p2) chSchDoRescheduleAhead(); } else { if (p1 >= p2) chSchDoRescheduleBehind(); } } 15_offsetof(st,m) ((size_t)((char *)&((st *)0)->m - (char *)0)) _CHREGISTRY_H_ IchRegSetThreadName(p) (currp->p_name = (p)) UchRegGetThreadName(tp) ((tp)->p_name) cREG_REMOVE(tp) { (tp)->p_older->p_newer = (tp)->p_newer; (tp)->p_newer->p_older = (tp)->p_older; } nREG_INSERT(tp) { (tp)->p_newer = (Thread *)&rlist; (tp)->p_older = rlist.r_older; (tp)->p_older->p_newer = rlist.r_older = (tp); } , D _CHINLINE_H_ _CHINLINE_H_ ' / 5 )3H_LOCK(h) chMtxLock(&(h)->h_mtx) 4H_UNLOCK(h) chMtxUnlock() °LIMIT(p) (union heap_header *)((uint8_t *)(p) + sizeof(union heap_header) + (p)->h.size) = ) _CHINLINE_H_ _SERIAL_H_ *SD_PARITY_ERROR 32 +SD_FRAMING_ERROR 64 ,SD_OVERRUN_ERROR 128 -SD_NOISE_ERROR 256 .SD_BREAK_DETECTED 512 hm_serial_driver_methods _base_asynchronous_channel_methods sdPutWouldBlock(sdp) chOQIsFullI(&(sdp)->oqueue) ¦sdGetWouldBlock(sdp) chIQIsEmptyI(&(sdp)->iqueue) ²sdPut(sdp,b) chOQPut(&(sdp)->oqueue, b) ¾sdPutTimeout(sdp,b,t) chOQPutTimeout(&(sdp)->oqueue, b, t) ÊsdGet(sdp) chIQGet(&(sdp)->iqueue) ÖsdGetTimeout(sdp,t) chIQGetTimeout(&(sdp)->iqueue, t) âsdWrite(sdp,b,n) chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_INFINITE) ðsdWriteTimeout(sdp,b,n,t) chOQWriteTimeout(&(sdp)->oqueue, b, n, t) ýsdAsynchronousWrite(sdp,b,n) chOQWriteTimeout(&(sdp)->oqueue, b, n, TIME_IMMEDIATE) sdRead(sdp,b,n) chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_INFINITE) sdReadTimeout(sdp,b,n,t) chIQReadTimeout(&(sdp)->iqueue, b, n, t) ¥sdAsynchronousRead(sdp,b,n) chIQReadTimeout(&(sdp)->iqueue, b, n, TIME_IMMEDIATE) _SERIAL_LLD_H_ KSTM32_SERIAL_USE_UART4 FALSE TSTM32_SERIAL_USE_UART5 FALSE ]STM32_SERIAL_USE_USART6 FALSE ySTM32_SERIAL_UART4_PRIORITY 12 STM32_SERIAL_UART5_PRIORITY 12 STM32_SERIAL_USART6_PRIORITY 12 î_serial_driver_data _base_asynchronous_channel_data sdstate_t state; InputQueue iqueue; OutputQueue oqueue; uint8_t ib[SERIAL_BUFFERS_SIZE]; uint8_t ob[SERIAL_BUFFERS_SIZE]; USART_TypeDef *usart;
USART_CR2_STOP1_BITS (0 << 12) USART_CR2_STOP0P5_BITS (1 << 12) USART_CR2_STOP2_BITS (2 << 12) USART_CR2_STOP1P5_BITS (3 << 12) _PWM_H_ -PWM_OUTPUT_MASK 0x0F 2PWM_OUTPUT_DISABLED 0x00 7PWM_OUTPUT_ACTIVE_HIGH 0x01 <PWM_OUTPUT_ACTIVE_LOW 0x02 `xPWM_FRACTION_TO_WIDTH(pwmp,denominator,numerator) ((uint16_t)((((uint32_t)(pwmp)->period) * (uint32_t)(numerator)) / (uint32_t)(denominator))) PWM_DEGREES_TO_WIDTH(pwmp,degrees) PWM_FRACTION_TO_WIDTH(pwmp, 36000, degrees) PWM_PERCENTAGE_TO_WIDTH(pwmp,percentage) PWM_FRACTION_TO_WIDTH(pwmp, 10000, percentage) °pwmChangePeriodI(pwmp,period) { (pwmp)->period = (period); pwm_lld_change_period(pwmp, period); } ÃpwmEnableChannelI(pwmp,channel,width) pwm_lld_enable_channel(pwmp, channel, width) ÔpwmDisableChannelI(pwmp,channel) pwm_lld_disable_channel(pwmp, channel) àpwmIsChannelEnabledI(pwmp,channel) pwm_lld_is_channel_enabled(pwmp, channel) _PWM_LLD_H_ %PWM_CHANNELS 4 +PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 1PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 :PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 CPWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 TSTM32_PWM_USE_ADVANCED FALSE ]STM32_PWM_USE_TIM1 FALSE STM32_PWM_USE_TIM5 FALSE STM32_PWM_USE_TIM8 FALSE STM32_PWM_USE_TIM9 FALSE STM32_PWM_TIM1_IRQ_PRIORITY 7 ¶STM32_PWM_TIM5_IRQ_PRIORITY 7 ½STM32_PWM_TIM8_IRQ_PRIORITY 7 ÅSTM32_PWM_TIM9_IRQ_PRIORITY 7 pwm_lld_change_period(pwmp,period) ((pwmp)->tim->ARR = (uint16_t)((period) - 1)) ¢pwm_lld_is_channel_enabled(pwmp,channel) (((pwmp)->tim->CCR[channel] != 0) || (((pwmp)->tim->DIER & (2 << channel)) != 0)) _GPT_H_ I\gptChangeIntervalI(gptp,interval) { gpt_lld_change_interval(gptp, interval); } _GPT_LLD_H_ 0STM32_GPT_USE_TIM1 FALSE TSTM32_GPT_USE_TIM5 FALSE ]STM32_GPT_USE_TIM6 FALSE fSTM32_GPT_USE_TIM7 FALSE oSTM32_GPT_USE_TIM8 FALSE xSTM32_GPT_USE_TIM9 FALSE STM32_GPT_USE_TIM11 FALSE STM32_GPT_USE_TIM12 FALSE STM32_GPT_USE_TIM14 FALSE STM32_GPT_TIM1_IRQ_PRIORITY 7 ¶STM32_GPT_TIM5_IRQ_PRIORITY 7 ½STM32_GPT_TIM6_IRQ_PRIORITY 7 ÄSTM32_GPT_TIM7_IRQ_PRIORITY 7 ËSTM32_GPT_TIM8_IRQ_PRIORITY 7 ÒSTM32_GPT_TIM9_IRQ_PRIORITY 7 ÙSTM32_GPT_TIM11_IRQ_PRIORITY 7 àSTM32_GPT_TIM12_IRQ_PRIORITY 7 çSTM32_GPT_TIM14_IRQ_PRIORITY 7 °gpt_lld_change_interval(gptp,interval) ((gptp)->tim->ARR = (uint16_t)((interval) - 1)) _ADC_H_ Wi_adc_reset_i(adcp) { if ((adcp)->thread != NULL) { Thread *tp = (adcp)->thread; (adcp)->thread = NULL; tp->p_u.rdymsg = RDY_RESET; chSchReadyI(tp); } } y_adc_reset_s(adcp) { if ((adcp)->thread != NULL) { Thread *tp = (adcp)->thread; (adcp)->thread = NULL; chSchWakeupS(tp, RDY_RESET); } } _adc_wakeup_isr(adcp) { chSysLockFromIsr(); if ((adcp)->thread != NULL) { Thread *tp; tp = (adcp)->thread; (adcp)->thread = NULL; tp->p_u.rdymsg = RDY_OK; chSchReadyI(tp); } chSysUnlockFromIsr(); } _adc_timeout_isr(adcp) { chSysLockFromIsr(); if ((adcp)->thread != NULL) { Thread *tp; tp = (adcp)->thread; (adcp)->thread = NULL; tp->p_u.rdymsg = RDY_TIMEOUT; chSchReadyI(tp); } chSysUnlockFromIsr(); } º_adc_isr_half_code(adcp) { if ((adcp)->grpp->end_cb != NULL) { (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth / 2); } } Î_adc_isr_full_code(adcp) { if ((adcp)->grpp->circular) { if ((adcp)->grpp->end_cb != NULL) { if ((adcp)->depth > 1) { size_t half = (adcp)->depth / 2; size_t half_index = half * (adcp)->grpp->num_channels; (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); } else { (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); } } } else { adc_lld_stop_conversion(adcp); if ((adcp)->grpp->end_cb != NULL) { (adcp)->state = ADC_COMPLETE; if ((adcp)->depth > 1) { size_t half = (adcp)->depth / 2; size_t half_index = half * (adcp)->grpp->num_channels; (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); } else { (adcp)->grpp->end_cb(adcp, (adcp)->samples, (adcp)->depth); } if ((adcp)->state == ADC_COMPLETE) { (adcp)->state = ADC_READY; (adcp)->grpp = NULL; } } else { (adcp)->state = ADC_READY; (adcp)->grpp = NULL; } _adc_wakeup_isr(adcp); } } _adc_isr_error_code(adcp,err) { adc_lld_stop_conversion(adcp); if ((adcp)->grpp->error_cb != NULL) { (adcp)->state = ADC_ERROR; (adcp)->grpp->error_cb(adcp, err); if ((adcp)->state == ADC_ERROR) (adcp)->state = ADC_READY; } (adcp)->grpp = NULL; _adc_timeout_isr(adcp); } _ADC_LLD_H_ &ADC_CR2_EXTSEL_SRC(n) ((n) << 24) -ADC_CCR_ADCPRE_DIV1 0 .ADC_CCR_ADCPRE_DIV2 1 /ADC_CCR_ADCPRE_DIV4 2 6ADC_CHANNEL_IN0 0 7ADC_CHANNEL_IN1 1 8ADC_CHANNEL_IN2 2 9ADC_CHANNEL_IN3 3 :ADC_CHANNEL_IN4 4 ;ADC_CHANNEL_IN5 5 <ADC_CHANNEL_IN6 6 =ADC_CHANNEL_IN7 7 >ADC_CHANNEL_IN8 8 ?ADC_CHANNEL_IN9 9 @ADC_CHANNEL_IN10 10 AADC_CHANNEL_IN11 11 BADC_CHANNEL_IN12 12 CADC_CHANNEL_IN13 13 DADC_CHANNEL_IN14 14 EADC_CHANNEL_IN15 15 FADC_CHANNEL_SENSOR 16 GADC_CHANNEL_VREFINT 17 HADC_CHANNEL_IN18 18 IADC_CHANNEL_IN19 19 JADC_CHANNEL_IN20 20 KADC_CHANNEL_IN21 21 LADC_CHANNEL_IN22 22 MADC_CHANNEL_IN23 23 NADC_CHANNEL_IN24 24 OADC_CHANNEL_IN25 25 VADC_SAMPLE_4 0 WADC_SAMPLE_9 1 XADC_SAMPLE_16 2 YADC_SAMPLE_24 3 ZADC_SAMPLE_48 4 [ADC_SAMPLE_96 5 \ADC_SAMPLE_192 6 ]ADC_SAMPLE_384 7 ySTM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 ¯STM32_DMA_REQUIRED ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
ADC_SQR5_SQ1_N(n) ((n) << 0) ADC_SQR5_SQ2_N(n) ((n) << 5) ADC_SQR5_SQ3_N(n) ((n) << 10) ADC_SQR5_SQ4_N(n) ((n) << 15) ADC_SQR5_SQ5_N(n) ((n) << 20) ADC_SQR5_SQ6_N(n) ((n) << 25) ADC_SQR4_SQ7_N(n) ((n) << 0) ADC_SQR4_SQ8_N(n) ((n) << 5) ADC_SQR4_SQ9_N(n) ((n) << 10) ADC_SQR4_SQ10_N(n) ((n) << 15) ADC_SQR4_SQ11_N(n) ((n) << 20) ADC_SQR4_SQ12_N(n) ((n) << 25) ADC_SQR3_SQ13_N(n) ((n) << 0) ADC_SQR3_SQ14_N(n) ((n) << 5) ADC_SQR3_SQ15_N(n) ((n) << 10) ADC_SQR3_SQ16_N(n) ((n) << 15) ADC_SQR3_SQ17_N(n) ((n) << 20) ADC_SQR3_SQ18_N(n) ((n) << 25) ADC_SQR2_SQ19_N(n) ((n) << 0) ADC_SQR2_SQ20_N(n) ((n) << 5) ADC_SQR2_SQ21_N(n) ((n) << 10) ADC_SQR2_SQ22_N(n) ((n) << 15) ADC_SQR2_SQ23_N(n) ((n) << 20) ADC_SQR2_SQ24_N(n) ((n) << 25) ¡ADC_SQR1_SQ25_N(n) ((n) << 0) ¢ADC_SQR1_SQ26_N(n) ((n) << 5) £ADC_SQR1_SQ27_N(n) ((n) << 10) ªADC_SMPR3_SMP_AN0(n) ((n) << 0) «ADC_SMPR3_SMP_AN1(n) ((n) << 3) ¬ADC_SMPR3_SMP_AN2(n) ((n) << 6) ADC_SMPR3_SMP_AN3(n) ((n) << 9) ®ADC_SMPR3_SMP_AN4(n) ((n) << 12) ¯ADC_SMPR3_SMP_AN5(n) ((n) << 15) °ADC_SMPR3_SMP_AN6(n) ((n) << 18) ±ADC_SMPR3_SMP_AN7(n) ((n) << 21) ²ADC_SMPR3_SMP_AN8(n) ((n) << 24) ³ADC_SMPR3_SMP_AN9(n) ((n) << 27) µADC_SMPR2_SMP_AN10(n) ((n) << 0) ¶ADC_SMPR2_SMP_AN11(n) ((n) << 3) ·ADC_SMPR2_SMP_AN12(n) ((n) << 6) ¸ADC_SMPR2_SMP_AN13(n) ((n) << 9) ¹ADC_SMPR2_SMP_AN14(n) ((n) << 12) ºADC_SMPR2_SMP_AN15(n) ((n) << 15) »ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) ½ADC_SMPR2_SMP_VREF(n) ((n) << 21) ¿ADC_SMPR2_SMP_AN18(n) ((n) << 24) ÀADC_SMPR2_SMP_AN19(n) ((n) << 27) ÂADC_SMPR1_SMP_AN20(n) ((n) << 0) ÃADC_SMPR1_SMP_AN21(n) ((n) << 3) ÄADC_SMPR1_SMP_AN22(n) ((n) << 6) ÅADC_SMPR1_SMP_AN23(n) ((n) << 9) ÆADC_SMPR1_SMP_AN24(n) ((n) << 12) ÇADC_SMPR1_SMP_AN25(n) ((n) << 15) _PAL_LLD_H_ "PAL_MODE_RESET #PAL_MODE_UNCONNECTED $PAL_MODE_INPUT %PAL_MODE_INPUT_PULLUP &PAL_MODE_INPUT_PULLDOWN 'PAL_MODE_INPUT_ANALOG (PAL_MODE_OUTPUT_PUSHPULL )PAL_MODE_OUTPUT_OPENDRAIN /PAL_STM32_MODE_MASK (3 << 0) 0PAL_STM32_MODE_INPUT (0 << 0) 1PAL_STM32_MODE_OUTPUT (1 << 0) 2PAL_STM32_MODE_ALTERNATE (2 << 0) 3PAL_STM32_MODE_ANALOG (3 << 0) 5PAL_STM32_OTYPE_MASK (1 << 2) 6PAL_STM32_OTYPE_PUSHPULL (0 << 2) 7PAL_STM32_OTYPE_OPENDRAIN (1 << 2) 9PAL_STM32_OSPEED_MASK (3 << 3) :PAL_STM32_OSPEED_LOWEST (0 << 3) >PAL_STM32_OSPEED_MID1 (1 << 3) ?PAL_STM32_OSPEED_MID2 (2 << 3) APAL_STM32_OSPEED_HIGHEST (3 << 3) CPAL_STM32_PUDR_MASK (3 << 5) DPAL_STM32_PUDR_FLOATING (0 << 5) EPAL_STM32_PUDR_PULLUP (1 << 5) FPAL_STM32_PUDR_PULLDOWN (2 << 5) HPAL_STM32_ALTERNATE_MASK (15 << 7) IPAL_STM32_ALTERNATE(n) ((n) << 7) PPAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | PAL_STM32_ALTERNATE(n)) [PAL_MODE_RESET PAL_STM32_MODE_INPUT `PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP ePAL_MODE_INPUT PAL_STM32_MODE_INPUT jPAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | PAL_STM32_PUDR_PULLUP) pPAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | PAL_STM32_PUDR_PULLDOWN) vPAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG {PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | PAL_STM32_OTYPE_PUSHPULL) PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | PAL_STM32_OTYPE_OPENDRAIN) ÝPAL_IOPORTS_WIDTH 16 ãPAL_WHOLE_PORT ((ioportmask_t)0xFFFF) IOPORT1 GPIOA IOPORT2 GPIOB IOPORT3 GPIOC IOPORT4 GPIOD IOPORT5 GPIOE ²IOPORT8 GPIOH Æpal_lld_init(config) _pal_lld_init(config) Ôpal_lld_readport(port) ((port)->IDR) âpal_lld_readlatch(port) ((port)->ODR) îpal_lld_writeport(port,bits) ((port)->ODR = (bits)) úpal_lld_setport(port,bits) ((port)->BSRR.H.set = (uint16_t)(bits)) pal_lld_clearport(port,bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) pal_lld_writegroup(port,mask,offset,bits) ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | (((bits) & (mask)) << (offset))) ¥pal_lld_setgroupmode(port,mask,offset,mode) _pal_lld_setgroupmode(port, mask << offset, mode) ²pal_lld_writepad(port,pad,bit) pal_lld_writegroup(port, 1, pad, bit) _TM_H_ XtmStartMeasurement(tmp) (tmp)->start(tmp) ctmStopMeasurement(tmp) (tmp)->stop(tmp) #_HAL_LLD_H_ %.HAL_IMPLEMENTS_COUNTERS TRUE 4PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density" ;STM32_HSICLK 16000000 <STM32_LSICLK 38000 CSTM32_VOS_MASK (3 << 11) DSTM32_VOS_1P8 (1 << 11) ESTM32_VOS_1P5 (2 << 11) FSTM32_VOS_1P2 (3 << 11) HSTM32_PLS_MASK (7 << 5) ISTM32_PLS_LEV0 (0 << 5) JSTM32_PLS_LEV1 (1 << 5) KSTM32_PLS_LEV2 (2 << 5) LSTM32_PLS_LEV3 (3 << 5) MSTM32_PLS_LEV4 (4 << 5) NSTM32_PLS_LEV5 (5 << 5) OSTM32_PLS_LEV6 (6 << 5) PSTM32_PLS_LEV7 (7 << 5) WSTM32_RTCPRE_MASK (3 << 29) XSTM32_RTCPRE_DIV2 (0 << 29) YSTM32_RTCPRE_DIV4 (1 << 29) ZSTM32_RTCPRE_DIV8 (2 << 29) [STM32_RTCPRE_DIV16 (3 << 29) bSTM32_SW_MSI (0 << 0) cSTM32_SW_HSI (1 << 0) dSTM32_SW_HSE (2 << 0) eSTM32_SW_PLL (3 << 0) gSTM32_HPRE_DIV1 (0 << 4) hSTM32_HPRE_DIV2 (8 << 4) iSTM32_HPRE_DIV4 (9 << 4) jSTM32_HPRE_DIV8 (10 << 4) kSTM32_HPRE_DIV16 (11 << 4) lSTM32_HPRE_DIV64 (12 << 4) mSTM32_HPRE_DIV128 (13 << 4) nSTM32_HPRE_DIV256 (14 << 4) oSTM32_HPRE_DIV512 (15 << 4) qSTM32_PPRE1_DIV1 (0 << 8) rSTM32_PPRE1_DIV2 (4 << 8) sSTM32_PPRE1_DIV4 (5 << 8) tSTM32_PPRE1_DIV8 (6 << 8) uSTM32_PPRE1_DIV16 (7 << 8) wSTM32_PPRE2_DIV1 (0 << 11) xSTM32_PPRE2_DIV2 (4 << 11) ySTM32_PPRE2_DIV4 (5 << 11) zSTM32_PPRE2_DIV8 (6 << 11) {STM32_PPRE2_DIV16 (7 << 11) }STM32_PLLSRC_HSI (0 << 16) ~STM32_PLLSRC_HSE (1 << 16) STM32_MCOSEL_NOCLOCK (0 << 24) STM32_MCOSEL_SYSCLK (1 << 24) STM32_MCOSEL_HSI (2 << 24) STM32_MCOSEL_MSI (3 << 24) STM32_MCOSEL_HSE (4 << 24)
STM32_MCOSEL_PLL (5 << 24) STM32_MCOSEL_LSI (6 << 24) STM32_MCOSEL_LSE (7 << 24) STM32_MCOPRE_DIV1 (0 << 28) STM32_MCOPRE_DIV2 (1 << 28) STM32_MCOPRE_DIV4 (2 << 28) STM32_MCOPRE_DIV8 (3 << 28) STM32_MCOPRE_DIV16 (4 << 28) STM32_MSIRANGE_MASK (7 << 13) STM32_MSIRANGE_64K (0 << 13) STM32_MSIRANGE_128K (1 << 13) STM32_MSIRANGE_256K (2 << 13) STM32_MSIRANGE_512K (3 << 13) STM32_MSIRANGE_1M (4 << 13) STM32_MSIRANGE_2M (5 << 13) STM32_MSIRANGE_4M (6 << 13) ¢STM32_RTCSEL_MASK (3 << 16) £STM32_RTCSEL_NOCLOCK (0 << 16) ¤STM32_RTCSEL_LSE (1 << 16) ¥STM32_RTCSEL_LSI (2 << 16) ¦STM32_RTCSEL_HSEDIV (3 << 16) ²STM32_HAS_ADC1 TRUE ³STM32_HAS_ADC2 FALSE ´STM32_HAS_ADC3 FALSE µSTM32_HAS_ADC4 FALSE ¸STM32_HAS_CAN1 FALSE ¹STM32_HAS_CAN2 FALSE ºSTM32_CAN_MAX_FILTERS 0 ½STM32_HAS_DAC TRUE ÀSTM32_ADVANCED_DMA FALSE ÁSTM32_HAS_DMA1 TRUE ÂSTM32_HAS_DMA2 FALSE ÅSTM32_HAS_ETH FALSE ÈSTM32_EXTI_NUM_CHANNELS 23 ËSTM32_HAS_GPIOA TRUE ÌSTM32_HAS_GPIOB TRUE ÍSTM32_HAS_GPIOC TRUE ÎSTM32_HAS_GPIOD TRUE ÏSTM32_HAS_GPIOE TRUE ÐSTM32_HAS_GPIOF FALSE ÑSTM32_HAS_GPIOG FALSE ÒSTM32_HAS_GPIOH TRUE ÓSTM32_HAS_GPIOI FALSE ÖSTM32_HAS_I2C1 TRUE ×STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) ØSTM32_I2C1_RX_DMA_CHN 0x00000000 ÙSTM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) ÚSTM32_I2C1_TX_DMA_CHN 0x00000000 ÜSTM32_HAS_I2C2 TRUE ÝSTM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) ÞSTM32_I2C2_RX_DMA_CHN 0x00000000 ßSTM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) àSTM32_I2C2_TX_DMA_CHN 0x00000000 âSTM32_HAS_I2C3 FALSE ãSTM32_I2C3_RX_DMA_MSK 0 äSTM32_I2C3_RX_DMA_CHN 0x00000000 åSTM32_I2C3_TX_DMA_MSK 0 æSTM32_I2C3_TX_DMA_CHN 0x00000000 éSTM32_HAS_RTC TRUE êSTM32_RTC_HAS_SUBSECONDS FALSE ëSTM32_RTC_IS_CALENDAR TRUE îSTM32_HAS_SDIO TRUE ñSTM32_HAS_SPI1 TRUE òSTM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) óSTM32_SPI1_RX_DMA_CHN 0x00000000 ôSTM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) õSTM32_SPI1_TX_DMA_CHN 0x00000000 ÷STM32_HAS_SPI2 TRUE øSTM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) ùSTM32_SPI2_RX_DMA_CHN 0x00000000 úSTM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) ûSTM32_SPI2_TX_DMA_CHN 0x00000000 ýSTM32_HAS_SPI3 FALSE þSTM32_SPI3_RX_DMA_MSK 0 ÿSTM32_SPI3_RX_DMA_CHN 0x00000000 STM32_SPI3_TX_DMA_MSK 0 STM32_SPI3_TX_DMA_CHN 0x00000000 STM32_HAS_TIM1 FALSE
STM32_HAS_TIM2 TRUE STM32_HAS_TIM3 TRUE STM32_HAS_TIM4 TRUE STM32_HAS_TIM5 FALSE STM32_HAS_TIM6 TRUE STM32_HAS_TIM7 TRUE STM32_HAS_TIM8 FALSE STM32_HAS_TIM9 TRUE STM32_HAS_TIM10 TRUE STM32_HAS_TIM11 TRUE STM32_HAS_TIM12 FALSE STM32_HAS_TIM13 FALSE STM32_HAS_TIM14 FALSE STM32_HAS_TIM15 FALSE STM32_HAS_TIM16 FALSE STM32_HAS_TIM17 FALSE STM32_HAS_TIM18 FALSE STM32_HAS_TIM19 FALSE STM32_HAS_USART1 TRUE STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) STM32_USART1_RX_DMA_CHN 0x00000000 STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) STM32_USART1_TX_DMA_CHN 0x00000000 STM32_HAS_USART2 TRUE STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) ¡STM32_USART2_RX_DMA_CHN 0x00000000 ¢STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) £STM32_USART2_TX_DMA_CHN 0x00000000 ¥STM32_HAS_USART3 TRUE ¦STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) §STM32_USART3_RX_DMA_CHN 0x00000000 ¨STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) ©STM32_USART3_TX_DMA_CHN 0x00000000 «STM32_HAS_UART4 FALSE ¬STM32_UART4_RX_DMA_MSK 0 STM32_UART4_RX_DMA_CHN 0x00000000 ®STM32_UART4_TX_DMA_MSK 0 ¯STM32_UART4_TX_DMA_CHN 0x00000000 ±STM32_HAS_UART5 FALSE ²STM32_UART5_RX_DMA_MSK 0 ³STM32_UART5_RX_DMA_CHN 0x00000000 ´STM32_UART5_TX_DMA_MSK 0 µSTM32_UART5_TX_DMA_CHN 0x00000000 ·STM32_HAS_USART6 FALSE ¸STM32_USART6_RX_DMA_MSK 0 ¹STM32_USART6_RX_DMA_CHN 0x00000000 ºSTM32_USART6_TX_DMA_MSK 0 »STM32_USART6_TX_DMA_CHN 0x00000000 ¾STM32_HAS_USB TRUE ¿STM32_HAS_OTG1 FALSE ÀSTM32_HAS_OTG2 FALSE ËWWDG_IRQHandler Vector40 ÌPVD_IRQHandler Vector44 ÎTAMPER_STAMP_IRQHandler Vector48 ÐRTC_WKUP_IRQHandler Vector4C ÒFLASH_IRQHandler Vector50 ÓRCC_IRQHandler Vector54 ÔEXTI0_IRQHandler Vector58 ÕEXTI1_IRQHandler Vector5C ÖEXTI2_IRQHandler Vector60 ×EXTI3_IRQHandler Vector64 ØEXTI4_IRQHandler Vector68 ÙDMA1_Ch1_IRQHandler Vector6C ÚDMA1_Ch2_IRQHandler Vector70 ÛDMA1_Ch3_IRQHandler Vector74 ÜDMA1_Ch4_IRQHandler Vector78 ÝDMA1_Ch5_IRQHandler Vector7C ÞDMA1_Ch6_IRQHandler Vector80 ßDMA1_Ch7_IRQHandler Vector84 àADC1_IRQHandler Vector88 áUSB_HP_IRQHandler Vector8C âUSB_LP_IRQHandler Vector90 ãDAC_IRQHandler Vector94 äCOMP_IRQHandler Vector98 åEXTI9_5_IRQHandler Vector9C æTIM9_IRQHandler VectorA0 çTIM10_IRQHandler VectorA4 èTIM11_IRQHandler VectorA8 éLCD_IRQHandler VectorAC êTIM2_IRQHandler VectorB0 ëTIM3_IRQHandler VectorB4 ìTIM4_IRQHandler VectorB8 íI2C1_EV_IRQHandler VectorBC îI2C1_ER_IRQHandler VectorC0 ïI2C2_EV_IRQHandler VectorC4 ðI2C2_ER_IRQHandler VectorC8 ñSPI1_IRQHandler VectorCC òSPI2_IRQHandler VectorD0 óUSART1_IRQHandler VectorD4 ôUSART2_IRQHandler VectorD8 õUSART3_IRQHandler VectorDC öEXTI15_10_IRQHandler VectorE0 ÷RTC_Alarm_IRQHandler VectorE4 øUSB_FS_WKUP_IRQHandler VectorE8 ùTIM6_IRQHandler VectorEC úTIM7_IRQHandler VectorF0 ÃSTM32_HSECLK_MAX 32000000 ÈSTM32_SYSCLK_MAX 32000000 ÍSTM32_PLLVCO_MAX 96000000 ÒSTM32_PLLVCO_MIN 6000000 ×STM32_PCLK1_MAX 32000000 ÜSTM32_PCLK2_MAX 32000000 áSTM32_0WS_THRESHOLD 16000000 æSTM32_HSI_AVAILABLE TRUE ÁSTM32_ACTIVATE_PLL TRUE ÎSTM32_PLLMUL (2 << 18) åSTM32_PLLDIV (2 << 22) òSTM32_PLLCLKIN STM32_HSICLK ÿSTM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE) STM32_MSICLK 2100000 ²STM32_SYSCLK STM32_PLLCLKOUT ÀSTM32_HCLK (STM32_SYSCLK / 1) ÞSTM32_PCLK1 (STM32_HCLK / 1) ôSTM32_PCLK2 (STM32_HCLK / 1) STM_MCODIVCLK 0 STM_MCOCLK STM_MCODIVCLK °STM32_HSEDIVCLK (STM32_HSECLK / 2) ÁSTM_RTCCLK STM32_LSECLK ÍSTM32_ADCCLK STM32_HSICLK ÒSTM32_USBCLK (STM32_PLLVCO / 2) ØSTM32_TIMCLK1 (STM32_PCLK1 * 1) áSTM32_TIMCLK2 (STM32_PCLK2 * 1) ìSTM32_FLASHBITS1 0x00000004 íSTM32_FLASHBITS2 0x00000007 hal_lld_get_counter_value() DWT_CYCCNT hal_lld_get_counter_frequency() STM32_HCLK _STM32_DMA_H_ 'STM32_DMA_STREAMS 7 ,STM32_DMA_ISR_MASK 0x0F 7STM32_DMA_GETCHANNEL(n,c) 0 ASTM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) JSTM32_DMA_STREAM_ID(dma,stream) ((stream) - 1) TSTM32_DMA_STREAM_ID_MSK(dma,stream) (1 << STM32_DMA_STREAM_ID(dma, stream)) `STM32_DMA_IS_VALID_ID(id,mask) (((1 << (id)) & (mask))) mSTM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) oSTM32_DMA1_STREAM1 STM32_DMA_STREAM(0) pSTM32_DMA1_STREAM2 STM32_DMA_STREAM(1) qSTM32_DMA1_STREAM3 STM32_DMA_STREAM(2) rSTM32_DMA1_STREAM4 STM32_DMA_STREAM(3) sSTM32_DMA1_STREAM5 STM32_DMA_STREAM(4) tSTM32_DMA1_STREAM6 STM32_DMA_STREAM(5) uSTM32_DMA1_STREAM7 STM32_DMA_STREAM(6) |STM32_DMA_CR_EN DMA_CCR1_EN }STM32_DMA_CR_TEIE DMA_CCR1_TEIE ~STM32_DMA_CR_HTIE DMA_CCR1_HTIE STM32_DMA_CR_TCIE DMA_CCR1_TCIE STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) STM32_DMA_CR_DIR_P2M 0 STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM STM32_DMA_CR_CIRC DMA_CCR1_CIRC
STM32_DMA_CR_PINC DMA_CCR1_PINC STM32_DMA_CR_MINC DMA_CCR1_MINC STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE STM32_DMA_CR_PSIZE_BYTE 0 STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE STM32_DMA_CR_MSIZE_BYTE 0 STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | STM32_DMA_CR_MSIZE_MASK) STM32_DMA_CR_PL_MASK DMA_CCR1_PL STM32_DMA_CR_PL(n) ((n) << 12) STM32_DMA_CR_DMEIE 0 STM32_DMA_CR_CHSEL_MASK 0 STM32_DMA_CR_CHSEL(n) 0 ¢STM32_DMA_ISR_FEIF 0 £STM32_DMA_ISR_DMEIF 0 ¤STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 ¥STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 ¦STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 ÝdmaStreamSetPeripheral(dmastp,addr) { (dmastp)->channel->CPAR = (uint32_t)(addr); } ìdmaStreamSetMemory0(dmastp,addr) { (dmastp)->channel->CMAR = (uint32_t)(addr); } ûdmaStreamSetTransactionSize(dmastp,size) { (dmastp)->channel->CNDTR = (uint32_t)(size); } dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) dmaStreamSetMode(dmastp,mode) { (dmastp)->channel->CCR = (uint32_t)(mode); } ¥dmaStreamEnable(dmastp) { (dmastp)->channel->CCR |= STM32_DMA_CR_EN; } ·dmaStreamDisable(dmastp) { (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); dmaStreamClearInterrupt(dmastp); } ÇdmaStreamClearInterrupt(dmastp) { *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; } ÞdmaStartMemCopy(dmastp,mode,src,dst,n) { dmaStreamSetPeripheral(dmastp, src); dmaStreamSetMemory0(dmastp, dst); dmaStreamSetTransactionSize(dmastp, n); dmaStreamSetMode(dmastp, (mode) | STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); } îdmaWaitCompletion(dmastp) { while ((dmastp)->channel->CNDTR > 0) ; dmaStreamDisable(dmastp); } +_STM32_H_ DSTM32_TIM1 ((stm32_tim_t *)TIM1_BASE) STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) 7__STM32L1XX_H jHSE_VALUE ((uint32_t)8000000) rHSE_STARTUP_TIMEOUT ((uint16_t)0x0500) zHSI_STARTUP_TIMEOUT ((uint16_t)0x0500) ~HSI_VALUE ((uint32_t)16000000) LSI_VALUE ((uint32_t)37000) LSE_VALUE ((uint32_t)32768) __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) __STM32L1XX_STDPERIPH_VERSION_RC (0x00) __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24) |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16) |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8) |(__STM32L1XX_STDPERIPH_VERSION_RC)) ¥__CM3_REV 0x200 ¦__MPU_PRESENT 1 §__NVIC_PRIO_BITS 4 ¨__Vendor_SysTickConfig 0 IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) §__RAM_FUNC FLASH_Status ëFLASH_BASE ((uint32_t)0x08000000) ìSRAM_BASE ((uint32_t)0x20000000) íPERIPH_BASE ((uint32_t)0x40000000) ïSRAM_BB_BASE ((uint32_t)0x22000000) ðPERIPH_BB_BASE ((uint32_t)0x42000000) òFSMC_R_BASE ((uint32_t)0xA0000000) õAPB1PERIPH_BASE PERIPH_BASE öAPB2PERIPH_BASE (PERIPH_BASE + 0x10000) ÷AHBPERIPH_BASE (PERIPH_BASE + 0x20000) ùTIM2_BASE (APB1PERIPH_BASE + 0x0000) úTIM3_BASE (APB1PERIPH_BASE + 0x0400) ûTIM4_BASE (APB1PERIPH_BASE + 0x0800) üTIM5_BASE (APB1PERIPH_BASE + 0x0C00) ýTIM6_BASE (APB1PERIPH_BASE + 0x1000) þTIM7_BASE (APB1PERIPH_BASE + 0x1400) ÿLCD_BASE (APB1PERIPH_BASE + 0x2400) RTC_BASE (APB1PERIPH_BASE + 0x2800) WWDG_BASE (APB1PERIPH_BASE + 0x2C00) IWDG_BASE (APB1PERIPH_BASE + 0x3000) SPI2_BASE (APB1PERIPH_BASE + 0x3800) SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
USART2_BASE (APB1PERIPH_BASE + 0x4400) USART3_BASE (APB1PERIPH_BASE + 0x4800) UART4_BASE (APB1PERIPH_BASE + 0x4C00) UART5_BASE (APB1PERIPH_BASE + 0x5000) I2C1_BASE (APB1PERIPH_BASE + 0x5400) I2C2_BASE (APB1PERIPH_BASE + 0x5800) PWR_BASE (APB1PERIPH_BASE + 0x7000) DAC_BASE (APB1PERIPH_BASE + 0x7400) COMP_BASE (APB1PERIPH_BASE + 0x7C00) RI_BASE (APB1PERIPH_BASE + 0x7C04) OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) EXTI_BASE (APB2PERIPH_BASE + 0x0400) TIM9_BASE (APB2PERIPH_BASE + 0x0800) TIM10_BASE (APB2PERIPH_BASE + 0x0C00) TIM11_BASE (APB2PERIPH_BASE + 0x1000) ADC1_BASE (APB2PERIPH_BASE + 0x2400) ADC_BASE (APB2PERIPH_BASE + 0x2700) SDIO_BASE (APB2PERIPH_BASE + 0x2C00) SPI1_BASE (APB2PERIPH_BASE + 0x3000) USART1_BASE (APB2PERIPH_BASE + 0x3800) GPIOA_BASE (AHBPERIPH_BASE + 0x0000) GPIOB_BASE (AHBPERIPH_BASE + 0x0400) GPIOC_BASE (AHBPERIPH_BASE + 0x0800) GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) GPIOE_BASE (AHBPERIPH_BASE + 0x1000) ¡GPIOH_BASE (AHBPERIPH_BASE + 0x1400) ¢GPIOF_BASE (AHBPERIPH_BASE + 0x1800) £GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) ¤CRC_BASE (AHBPERIPH_BASE + 0x3000) ¥RCC_BASE (AHBPERIPH_BASE + 0x3800) ¨FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) ©OB_BASE ((uint32_t)0x1FF80000) «DMA1_BASE (AHBPERIPH_BASE + 0x6000) ¬DMA1_Channel1_BASE (DMA1_BASE + 0x0008) DMA1_Channel2_BASE (DMA1_BASE + 0x001C) ®DMA1_Channel3_BASE (DMA1_BASE + 0x0030) ¯DMA1_Channel4_BASE (DMA1_BASE + 0x0044) °DMA1_Channel5_BASE (DMA1_BASE + 0x0058) ±DMA1_Channel6_BASE (DMA1_BASE + 0x006C) ²DMA1_Channel7_BASE (DMA1_BASE + 0x0080) ´DMA2_BASE (AHBPERIPH_BASE + 0x6400) µDMA2_Channel1_BASE (DMA2_BASE + 0x0008) ¶DMA2_Channel2_BASE (DMA2_BASE + 0x001C) ·DMA2_Channel3_BASE (DMA2_BASE + 0x0030) ¸DMA2_Channel4_BASE (DMA2_BASE + 0x0044) ¹DMA2_Channel5_BASE (DMA2_BASE + 0x0058) »AES_BASE ((uint32_t)0x50060000) ½FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) ¾FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) ÀDBGMCU_BASE ((uint32_t)0xE0042000) ÊTIM2 ((TIM_TypeDef *) TIM2_BASE) ËTIM3 ((TIM_TypeDef *) TIM3_BASE) ÌTIM4 ((TIM_TypeDef *) TIM4_BASE) ÍTIM5 ((TIM_TypeDef *) TIM5_BASE) ÎTIM6 ((TIM_TypeDef *) TIM6_BASE) ÏTIM7 ((TIM_TypeDef *) TIM7_BASE) ÐLCD ((LCD_TypeDef *) LCD_BASE) ÑRTC ((RTC_TypeDef *) RTC_BASE) ÒWWDG ((WWDG_TypeDef *) WWDG_BASE) ÓIWDG ((IWDG_TypeDef *) IWDG_BASE) ÔSPI2 ((SPI_TypeDef *) SPI2_BASE) ÕSPI3 ((SPI_TypeDef *) SPI3_BASE) ÖUSART2 ((USART_TypeDef *) USART2_BASE) ×USART3 ((USART_TypeDef *) USART3_BASE) ØUART4 ((USART_TypeDef *) UART4_BASE) ÙUART5 ((USART_TypeDef *) UART5_BASE) ÚI2C1 ((I2C_TypeDef *) I2C1_BASE) ÛI2C2 ((I2C_TypeDef *) I2C2_BASE) ÜPWR ((PWR_TypeDef *) PWR_BASE) ÝDAC ((DAC_TypeDef *) DAC_BASE) ÞCOMP ((COMP_TypeDef *) COMP_BASE) ßRI ((RI_TypeDef *) RI_BASE) àOPAMP ((OPAMP_TypeDef *) OPAMP_BASE) áSYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) âEXTI ((EXTI_TypeDef *) EXTI_BASE) äADC1 ((ADC_TypeDef *) ADC1_BASE) åADC ((ADC_Common_TypeDef *) ADC_BASE) æSDIO ((SDIO_TypeDef *) SDIO_BASE) çTIM9 ((TIM_TypeDef *) TIM9_BASE) èTIM10 ((TIM_TypeDef *) TIM10_BASE) éTIM11 ((TIM_TypeDef *) TIM11_BASE) êSPI1 ((SPI_TypeDef *) SPI1_BASE) ëUSART1 ((USART_TypeDef *) USART1_BASE) ìDMA1 ((DMA_TypeDef *) DMA1_BASE) íDMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) îDMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) ïDMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) ðDMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) ñDMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) òDMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) óDMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) õDMA2 ((DMA_TypeDef *) DMA2_BASE) öDMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) ÷DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) øDMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) ùDMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) úDMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) üRCC ((RCC_TypeDef *) RCC_BASE) ýCRC ((CRC_TypeDef *) CRC_BASE) ÿGPIOA ((GPIO_TypeDef *) GPIOA_BASE) GPIOB ((GPIO_TypeDef *) GPIOB_BASE) GPIOC ((GPIO_TypeDef *) GPIOC_BASE) GPIOD ((GPIO_TypeDef *) GPIOD_BASE) GPIOE ((GPIO_TypeDef *) GPIOE_BASE) GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
GPIOF ((GPIO_TypeDef *) GPIOF_BASE) GPIOG ((GPIO_TypeDef *) GPIOG_BASE) FLASH ((FLASH_TypeDef *) FLASH_R_BASE) OB ((OB_TypeDef *) OB_BASE) AES ((AES_TypeDef *) AES_BASE) FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) ¨ADC_SR_AWD ((uint32_t)0x00000001) ©ADC_SR_EOC ((uint32_t)0x00000002) ªADC_SR_JEOC ((uint32_t)0x00000004) «ADC_SR_JSTRT ((uint32_t)0x00000008) ¬ADC_SR_STRT ((uint32_t)0x00000010) ADC_SR_OVR ((uint32_t)0x00000020) ®ADC_SR_ADONS ((uint32_t)0x00000040) ¯ADC_SR_RCNR ((uint32_t)0x00000100) °ADC_SR_JCNR ((uint32_t)0x00000200) ³ADC_CR1_AWDCH ((uint32_t)0x0000001F) ´ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) µADC_CR1_AWDCH_1 ((uint32_t)0x00000002) ¶ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) ·ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) ¸ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) ºADC_CR1_EOCIE ((uint32_t)0x00000020) »ADC_CR1_AWDIE ((uint32_t)0x00000040) ¼ADC_CR1_JEOCIE ((uint32_t)0x00000080) ½ADC_CR1_SCAN ((uint32_t)0x00000100) ¾ADC_CR1_AWDSGL ((uint32_t)0x00000200) ¿ADC_CR1_JAUTO ((uint32_t)0x00000400) ÀADC_CR1_DISCEN ((uint32_t)0x00000800) ÁADC_CR1_JDISCEN ((uint32_t)0x00001000) ÃADC_CR1_DISCNUM ((uint32_t)0x0000E000) ÄADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) ÅADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) ÆADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) ÈADC_CR1_PDD ((uint32_t)0x00010000) ÉADC_CR1_PDI ((uint32_t)0x00020000) ËADC_CR1_JAWDEN ((uint32_t)0x00400000) ÌADC_CR1_AWDEN ((uint32_t)0x00800000) ÎADC_CR1_RES ((uint32_t)0x03000000) ÏADC_CR1_RES_0 ((uint32_t)0x01000000) ÐADC_CR1_RES_1 ((uint32_t)0x02000000) ÒADC_CR1_OVRIE ((uint32_t)0x04000000) ÕADC_CR2_ADON ((uint32_t)0x00000001) ÖADC_CR2_CONT ((uint32_t)0x00000002) ×ADC_CR2_CFG ((uint32_t)0x00000004) ÙADC_CR2_DELS ((uint32_t)0x00000070) ÚADC_CR2_DELS_0 ((uint32_t)0x00000010) ÛADC_CR2_DELS_1 ((uint32_t)0x00000020) ÜADC_CR2_DELS_2 ((uint32_t)0x00000040) ÞADC_CR2_DMA ((uint32_t)0x00000100) ßADC_CR2_DDS ((uint32_t)0x00000200) àADC_CR2_EOCS ((uint32_t)0x00000400) áADC_CR2_ALIGN ((uint32_t)0x00000800) ãADC_CR2_JEXTSEL ((uint32_t)0x000F0000) äADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) åADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) æADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) çADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) éADC_CR2_JEXTEN ((uint32_t)0x00300000) êADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) ëADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) íADC_CR2_JSWSTART ((uint32_t)0x00400000) ïADC_CR2_EXTSEL ((uint32_t)0x0F000000) ðADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) ñADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) òADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) óADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) õADC_CR2_EXTEN ((uint32_t)0x30000000) öADC_CR2_EXTEN_0 ((uint32_t)0x10000000) ÷ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) ùADC_CR2_SWSTART ((uint32_t)0x40000000) üADC_SMPR1_SMP20 ((uint32_t)0x00000007) ýADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) þADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) ÿADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) ADC_SMPR1_SMP21 ((uint32_t)0x00000038) ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) ADC_SMPR1_SMP24 ((uint32_t)0x00007000) ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) ADC_SMPR1_SMP25 ((uint32_t)0x00038000) ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) ¡ ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) ¢ ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) ¤ ADC_SMPR1_SMP28 ((uint32_t)0x07000000) ¥ ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) ¦ ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) § ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) © ADC_SMPR1_SMP29 ((uint32_t)0x38000000) ª ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) « ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) ¬ ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) ¯ ADC_SMPR2_SMP10 ((uint32_t)0x00000007) ° ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) ± ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) ² ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) ´ ADC_SMPR2_SMP11 ((uint32_t)0x00000038) µ ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) ¶ ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) · ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) ¹ ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) º ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) » ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) ¼ ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) ¾ ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) ¿ ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) À ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) Á ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) Ã ADC_SMPR2_SMP14 ((uint32_t)0x00007000) Ä ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) Å ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) Æ ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) È ADC_SMPR2_SMP15 ((uint32_t)0x00038000) É ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) Ê ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) Ë ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) Í ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) Î ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) Ï ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) Ð ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) Ò ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) Ó ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) Ô ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) Õ ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) × ADC_SMPR2_SMP18 ((uint32_t)0x07000000) Ø ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) Ù ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) Ú ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) Ü ADC_SMPR2_SMP19 ((uint32_t)0x38000000) Ý ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) Þ ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) ß ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) â ADC_SMPR3_SMP0 ((uint32_t)0x00000007) ã ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) ä ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) å ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) ç ADC_SMPR3_SMP1 ((uint32_t)0x00000038) è ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) é ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) ê ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) ì ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) í ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) î ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) ï ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) ñ ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) ò ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) ó ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) ô ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) ö ADC_SMPR3_SMP4 ((uint32_t)0x00007000) ÷ ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) ø ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) ù ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) û ADC_SMPR3_SMP5 ((uint32_t)0x00038000) ü ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) ý ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) þ ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000)
ADC_SMPR3_SMP6 ((uint32_t)0x001C0000)
ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000)
ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000)
ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000)
ADC_SMPR3_SMP7 ((uint32_t)0x00E00000)
ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000)
ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000)
ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000)
ADC_SMPR3_SMP8 ((uint32_t)0x07000000)
ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000)
ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000)
ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000)
ADC_SMPR3_SMP9 ((uint32_t)0x38000000)
ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000)
ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000)
ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000)
ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF)
ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF)
ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF)
ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) ¡
ADC_HTR_HT ((uint32_t)0x00000FFF) ¤
ADC_LTR_LT ((uint32_t)0x00000FFF) §
ADC_SQR1_L ((uint32_t)0x00F00000) ¨
ADC_SQR1_L_0 ((uint32_t)0x00100000) ©
ADC_SQR1_L_1 ((uint32_t)0x00200000) ª
ADC_SQR1_L_2 ((uint32_t)0x00400000) «
ADC_SQR1_L_3 ((uint32_t)0x00800000)
ADC_SQR1_SQ28 ((uint32_t)0x000F8000) ®
ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) ¯
ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) °
ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) ±
ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) ²
ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) ´
ADC_SQR1_SQ27 ((uint32_t)0x00007C00) µ
ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) ¶
ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) ·
ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) ¸
ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) ¹
ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) »
ADC_SQR1_SQ26 ((uint32_t)0x000003E0) ¼
ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) ½
ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) ¾
ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) ¿
ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) À
ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) Â
ADC_SQR1_SQ25 ((uint32_t)0x0000001F) Ã
ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) Ä
ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) Å
ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) Æ
ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) Ç
ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) Ê
ADC_SQR2_SQ19 ((uint32_t)0x0000001F) Ë
ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) Ì
ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) Í
ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) Î
ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) Ï
ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) Ñ
ADC_SQR2_SQ20 ((uint32_t)0x000003E0) Ò
ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) Ó
ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) Ô
ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) Õ
ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) Ö
ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) Ø
ADC_SQR2_SQ21 ((uint32_t)0x00007C00) Ù
ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) Ú
ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) Û
ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) Ü
ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) Ý
ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) ß
ADC_SQR2_SQ22 ((uint32_t)0x000F8000) à
ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) á
ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) â
ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) ã
ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) ä
ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) æ
ADC_SQR2_SQ23 ((uint32_t)0x01F00000) ç
ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) è
ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) é
ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) ê
ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) ë
ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) í
ADC_SQR2_SQ24 ((uint32_t)0x3E000000) î
ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) ï
ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) ð
ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) ñ
ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) ò
ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) õ
ADC_SQR3_SQ13 ((uint32_t)0x0000001F) ö
ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) ÷
ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) ø
ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) ù
ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) ú
ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) ü
ADC_SQR3_SQ14 ((uint32_t)0x000003E0) ý
ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) þ
ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) ÿ
ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) ADC_SQR3_SQ15 ((uint32_t)0x00007C00) ADC_SQR3_SQ15_0 ((uint32_t)0x00000400)
ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) ADC_SQR3_SQ16 ((uint32_t)0x000F8000) ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) ADC_SQR3_SQ17 ((uint32_t)0x01F00000) ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) ADC_SQR3_SQ18 ((uint32_t)0x3E000000) ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) ADC_SQR4_SQ7 ((uint32_t)0x0000001F) ¡ ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) ¢ ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) £ ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) ¤ ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) ¥ ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) § ADC_SQR4_SQ8 ((uint32_t)0x000003E0) ¨ ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) © ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) ª ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) « ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) ¬ ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) ® ADC_SQR4_SQ9 ((uint32_t)0x00007C00) ¯ ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) ° ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) ± ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) ² ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) ³ ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) µ ADC_SQR4_SQ10 ((uint32_t)0x000F8000) ¶ ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) · ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) ¸ ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) ¹ ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) º ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) ¼ ADC_SQR4_SQ11 ((uint32_t)0x01F00000) ½ ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) ¾ ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) ¿ ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) À ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) Á ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) Ã ADC_SQR4_SQ12 ((uint32_t)0x3E000000) Ä ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) Å ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) Æ ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) Ç ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) È ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) Ë ADC_SQR5_SQ1 ((uint32_t)0x0000001F) Ì ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) Í ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) Î ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) Ï ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) Ð ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) Ò ADC_SQR5_SQ2 ((uint32_t)0x000003E0) Ó ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) Ô ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) Õ ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) Ö ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) × ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) Ù ADC_SQR5_SQ3 ((uint32_t)0x00007C00) Ú ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) Û ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) Ü ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) Ý ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) Þ ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) à ADC_SQR5_SQ4 ((uint32_t)0x000F8000) á ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) â ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) ã ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) ä ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) å ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) ç ADC_SQR5_SQ5 ((uint32_t)0x01F00000) è ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) é ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) ê ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) ë ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) ì ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) î ADC_SQR5_SQ6 ((uint32_t)0x3E000000) ï ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) ð ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) ñ ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) ò ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) ó ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) ÷ ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) ø ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) ù ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) ú ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) û ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) ü ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) þ ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) ÿ ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) ADC_JSQR_JL ((uint32_t)0x00300000) ADC_JSQR_JL_0 ((uint32_t)0x00100000) ADC_JSQR_JL_1 ((uint32_t)0x00200000) ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) ¡ ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) ¤ ADC_DR_DATA ((uint32_t)0x0000FFFF) § ADC_SMPR3_SMP30 ((uint32_t)0x00000007) ¨ ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) © ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) ª ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) ¬ ADC_SMPR3_SMP31 ((uint32_t)0x00000038) ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) ® ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) ¯ ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) ² ADC_CSR_AWD1 ((uint32_t)0x00000001) ³ ADC_CSR_EOC1 ((uint32_t)0x00000002) ´ ADC_CSR_JEOC1 ((uint32_t)0x00000004) µ ADC_CSR_JSTRT1 ((uint32_t)0x00000008) ¶ ADC_CSR_STRT1 ((uint32_t)0x00000010) · ADC_CSR_OVR1 ((uint32_t)0x00000020) ¸ ADC_CSR_ADONS1 ((uint32_t)0x00000040) » ADC_CCR_ADCPRE ((uint32_t)0x00030000) ¼ ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) ½ ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) ¾ ADC_CCR_TSVREFE ((uint32_t)0x00800000) Æ AES_CR_EN ((uint32_t)0x00000001) Ç AES_CR_DATATYPE ((uint32_t)0x00000006) È AES_CR_DATATYPE_0 ((uint32_t)0x00000002) É AES_CR_DATATYPE_1 ((uint32_t)0x00000004) Ë AES_CR_MODE ((uint32_t)0x00000018) Ì AES_CR_MODE_0 ((uint32_t)0x00000008) Í AES_CR_MODE_1 ((uint32_t)0x00000010) Ï AES_CR_CHMOD ((uint32_t)0x00000060) Ð AES_CR_CHMOD_0 ((uint32_t)0x00000020) Ñ AES_CR_CHMOD_1 ((uint32_t)0x00000040) Ó AES_CR_CCFC ((uint32_t)0x00000080) Ô AES_CR_ERRC ((uint32_t)0x00000100) Õ AES_CR_CCIE ((uint32_t)0x00000200) Ö AES_CR_ERRIE ((uint32_t)0x00000400) × AES_CR_DMAINEN ((uint32_t)0x00000800) Ø AES_CR_DMAOUTEN ((uint32_t)0x00001000) Û AES_SR_CCF ((uint32_t)0x00000001) Ü AES_SR_RDERR ((uint32_t)0x00000002) Ý AES_SR_WRERR ((uint32_t)0x00000004) à AES_DINR ((uint32_t)0x0000FFFF) ã AES_DOUTR ((uint32_t)0x0000FFFF) æ AES_KEYR0 ((uint32_t)0x0000FFFF) é AES_KEYR1 ((uint32_t)0x0000FFFF) ì AES_KEYR2 ((uint32_t)0x0000FFFF) ï AES_KEYR3 ((uint32_t)0x0000FFFF) ò AES_IVR0 ((uint32_t)0x0000FFFF) õ AES_IVR1 ((uint32_t)0x0000FFFF) ø AES_IVR2 ((uint32_t)0x0000FFFF) û AES_IVR3 ((uint32_t)0x0000FFFF)
COMP_CSR_10KPU ((uint32_t)0x00000001)
COMP_CSR_400KPU ((uint32_t)0x00000002)
COMP_CSR_10KPD ((uint32_t)0x00000004)
COMP_CSR_400KPD ((uint32_t)0x00000008)
COMP_CSR_CMP1EN ((uint32_t)0x00000010)
COMP_CSR_SW1 ((uint32_t)0x00000020)
COMP_CSR_CMP1OUT ((uint32_t)0x00000080)
COMP_CSR_SPEED ((uint32_t)0x00001000)
COMP_CSR_CMP2OUT ((uint32_t)0x00002000)
COMP_CSR_VREFOUTEN ((uint32_t)0x00010000)
COMP_CSR_WNDWE ((uint32_t)0x00020000)
COMP_CSR_INSEL ((uint32_t)0x001C0000)
COMP_CSR_INSEL_0 ((uint32_t)0x00040000)
COMP_CSR_INSEL_1 ((uint32_t)0x00080000)
COMP_CSR_INSEL_2 ((uint32_t)0x00100000)
COMP_CSR_OUTSEL ((uint32_t)0x00E00000)
COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000)
COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000)
COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000)
COMP_CSR_FCH3 ((uint32_t)0x04000000)
COMP_CSR_FCH8 ((uint32_t)0x08000000)
COMP_CSR_RCH13 ((uint32_t)0x10000000) ¡
COMP_CSR_CAIE ((uint32_t)0x20000000) ¢
COMP_CSR_CAIF ((uint32_t)0x40000000) £
COMP_CSR_TSUSP ((uint32_t)0x80000000) «
OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) ¬
OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002)
OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) ®
OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) ¯
OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) °
OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) ±
OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) ²
OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) ³
OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) ´
OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) µ
OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) ¶
OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) ·
OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) ¸
OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) ¹
OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) º
OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) »
OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) ¼
OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) ½
OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) ¾
OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) ¿
OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) À
OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) Á
OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) Â
OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) Ã
OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) Ä
OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) Å
OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) Æ
OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) Ç
OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) È
OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) É
OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) Ê
OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) Í
OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) Î
OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) Ï
OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) Ð
OPAMP_OTR_OT_USER ((uint32_t)0x80000000) Ó
OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) Ô
OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) Õ
OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) Þ
CRC_DR_DR ((uint32_t)0xFFFFFFFF) á
CRC_IDR_IDR ((uint8_t)0xFF) ä
CRC_CR_RESET ((uint32_t)0x00000001) í
DAC_CR_EN1 ((uint32_t)0x00000001) î
DAC_CR_BOFF1 ((uint32_t)0x00000002) ï
DAC_CR_TEN1 ((uint32_t)0x00000004) ñ
DAC_CR_TSEL1 ((uint32_t)0x00000038) ò
DAC_CR_TSEL1_0 ((uint32_t)0x00000008) ó
DAC_CR_TSEL1_1 ((uint32_t)0x00000010) ô
DAC_CR_TSEL1_2 ((uint32_t)0x00000020) ö
DAC_CR_WAVE1 ((uint32_t)0x000000C0) ÷
DAC_CR_WAVE1_0 ((uint32_t)0x00000040) ø
DAC_CR_WAVE1_1 ((uint32_t)0x00000080) ú
DAC_CR_MAMP1 ((uint32_t)0x00000F00) û
DAC_CR_MAMP1_0 ((uint32_t)0x00000100) ü
DAC_CR_MAMP1_1 ((uint32_t)0x00000200) ý
DAC_CR_MAMP1_2 ((uint32_t)0x00000400) þ
DAC_CR_MAMP1_3 ((uint32_t)0x00000800) DAC_CR_DMAEN1 ((uint32_t)0x00001000) DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) DAC_CR_EN2 ((uint32_t)0x00010000) DAC_CR_BOFF2 ((uint32_t)0x00020000) DAC_CR_TEN2 ((uint32_t)0x00040000) DAC_CR_TSEL2 ((uint32_t)0x00380000) DAC_CR_TSEL2_0 ((uint32_t)0x00080000) DAC_CR_TSEL2_1 ((uint32_t)0x00100000) DAC_CR_TSEL2_2 ((uint32_t)0x00200000) DAC_CR_WAVE2 ((uint32_t)0x00C00000) DAC_CR_WAVE2_0 ((uint32_t)0x00400000) DAC_CR_WAVE2_1 ((uint32_t)0x00800000) DAC_CR_MAMP2 ((uint32_t)0x0F000000) DAC_CR_MAMP2_0 ((uint32_t)0x01000000) DAC_CR_MAMP2_1 ((uint32_t)0x02000000) DAC_CR_MAMP2_2 ((uint32_t)0x04000000) DAC_CR_MAMP2_3 ((uint32_t)0x08000000) DAC_CR_DMAEN2 ((uint32_t)0x10000000) DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) ¢DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) ¥DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) ¨DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) «DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) ®DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) ¯DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) ²DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) ³DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) ¶DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) ·DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) ºDAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) ½DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) ÀDAC_SR_DMAUDR1 ((uint32_t)0x00002000) ÁDAC_SR_DMAUDR2 ((uint32_t)0x20000000) ÊDBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) ÌDBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) ÍDBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) ÎDBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) ÏDBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) ÐDBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) ÑDBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) ÒDBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) ÓDBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) ÔDBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) ÕDBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) ÖDBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) ×DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) ØDBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) ÙDBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) ÚDBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) ÛDBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) ÜDBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) ßDBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) àDBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) áDBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) âDBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) äDBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) åDBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) æDBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) êDBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) ëDBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) ìDBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) íDBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) îDBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) ïDBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) ðDBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) ñDBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) òDBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) óDBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) ôDBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) øDBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) ùDBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) úDBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) DMA_ISR_GIF1 ((uint32_t)0x00000001) DMA_ISR_TCIF1 ((uint32_t)0x00000002)
DMA_ISR_HTIF1 ((uint32_t)0x00000004) DMA_ISR_TEIF1 ((uint32_t)0x00000008) DMA_ISR_GIF2 ((uint32_t)0x00000010) DMA_ISR_TCIF2 ((uint32_t)0x00000020) DMA_ISR_HTIF2 ((uint32_t)0x00000040) DMA_ISR_TEIF2 ((uint32_t)0x00000080) DMA_ISR_GIF3 ((uint32_t)0x00000100) DMA_ISR_TCIF3 ((uint32_t)0x00000200) DMA_ISR_HTIF3 ((uint32_t)0x00000400) DMA_ISR_TEIF3 ((uint32_t)0x00000800) DMA_ISR_GIF4 ((uint32_t)0x00001000) DMA_ISR_TCIF4 ((uint32_t)0x00002000) DMA_ISR_HTIF4 ((uint32_t)0x00004000) DMA_ISR_TEIF4 ((uint32_t)0x00008000) DMA_ISR_GIF5 ((uint32_t)0x00010000) DMA_ISR_TCIF5 ((uint32_t)0x00020000) DMA_ISR_HTIF5 ((uint32_t)0x00040000) DMA_ISR_TEIF5 ((uint32_t)0x00080000) DMA_ISR_GIF6 ((uint32_t)0x00100000) DMA_ISR_TCIF6 ((uint32_t)0x00200000) DMA_ISR_HTIF6 ((uint32_t)0x00400000) DMA_ISR_TEIF6 ((uint32_t)0x00800000) DMA_ISR_GIF7 ((uint32_t)0x01000000) DMA_ISR_TCIF7 ((uint32_t)0x02000000) DMA_ISR_HTIF7 ((uint32_t)0x04000000) DMA_ISR_TEIF7 ((uint32_t)0x08000000) ¡DMA_IFCR_CGIF1 ((uint32_t)0x00000001) ¢DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) £DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) ¤DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) ¥DMA_IFCR_CGIF2 ((uint32_t)0x00000010) ¦DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) §DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) ¨DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) ©DMA_IFCR_CGIF3 ((uint32_t)0x00000100) ªDMA_IFCR_CTCIF3 ((uint32_t)0x00000200) «DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) ¬DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) DMA_IFCR_CGIF4 ((uint32_t)0x00001000) ®DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) ¯DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) °DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) ±DMA_IFCR_CGIF5 ((uint32_t)0x00010000) ²DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) ³DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) ´DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) µDMA_IFCR_CGIF6 ((uint32_t)0x00100000) ¶DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) ·DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) ¸DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) ¹DMA_IFCR_CGIF7 ((uint32_t)0x01000000) ºDMA_IFCR_CTCIF7 ((uint32_t)0x02000000) »DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) ¼DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) ¿DMA_CCR1_EN ((uint16_t)0x0001) ÀDMA_CCR1_TCIE ((uint16_t)0x0002) ÁDMA_CCR1_HTIE ((uint16_t)0x0004) ÂDMA_CCR1_TEIE ((uint16_t)0x0008) ÃDMA_CCR1_DIR ((uint16_t)0x0010) ÄDMA_CCR1_CIRC ((uint16_t)0x0020) ÅDMA_CCR1_PINC ((uint16_t)0x0040) ÆDMA_CCR1_MINC ((uint16_t)0x0080) ÈDMA_CCR1_PSIZE ((uint16_t)0x0300) ÉDMA_CCR1_PSIZE_0 ((uint16_t)0x0100) ÊDMA_CCR1_PSIZE_1 ((uint16_t)0x0200) ÌDMA_CCR1_MSIZE ((uint16_t)0x0C00) ÍDMA_CCR1_MSIZE_0 ((uint16_t)0x0400) ÎDMA_CCR1_MSIZE_1 ((uint16_t)0x0800) ÐDMA_CCR1_PL ((uint16_t)0x3000) ÑDMA_CCR1_PL_0 ((uint16_t)0x1000) ÒDMA_CCR1_PL_1 ((uint16_t)0x2000) ÔDMA_CCR1_MEM2MEM ((uint16_t)0x4000) ×DMA_CCR2_EN ((uint16_t)0x0001) ØDMA_CCR2_TCIE ((uint16_t)0x0002) ÙDMA_CCR2_HTIE ((uint16_t)0x0004) ÚDMA_CCR2_TEIE ((uint16_t)0x0008) ÛDMA_CCR2_DIR ((uint16_t)0x0010) ÜDMA_CCR2_CIRC ((uint16_t)0x0020) ÝDMA_CCR2_PINC ((uint16_t)0x0040) ÞDMA_CCR2_MINC ((uint16_t)0x0080) àDMA_CCR2_PSIZE ((uint16_t)0x0300) áDMA_CCR2_PSIZE_0 ((uint16_t)0x0100) âDMA_CCR2_PSIZE_1 ((uint16_t)0x0200) äDMA_CCR2_MSIZE ((uint16_t)0x0C00) åDMA_CCR2_MSIZE_0 ((uint16_t)0x0400) æDMA_CCR2_MSIZE_1 ((uint16_t)0x0800) èDMA_CCR2_PL ((uint16_t)0x3000) éDMA_CCR2_PL_0 ((uint16_t)0x1000) êDMA_CCR2_PL_1 ((uint16_t)0x2000) ìDMA_CCR2_MEM2MEM ((uint16_t)0x4000) ïDMA_CCR3_EN ((uint16_t)0x0001) ðDMA_CCR3_TCIE ((uint16_t)0x0002) ñDMA_CCR3_HTIE ((uint16_t)0x0004) òDMA_CCR3_TEIE ((uint16_t)0x0008) óDMA_CCR3_DIR ((uint16_t)0x0010) ôDMA_CCR3_CIRC ((uint16_t)0x0020) õDMA_CCR3_PINC ((uint16_t)0x0040) öDMA_CCR3_MINC ((uint16_t)0x0080) øDMA_CCR3_PSIZE ((uint16_t)0x0300) ùDMA_CCR3_PSIZE_0 ((uint16_t)0x0100) úDMA_CCR3_PSIZE_1 ((uint16_t)0x0200) üDMA_CCR3_MSIZE ((uint16_t)0x0C00) ýDMA_CCR3_MSIZE_0 ((uint16_t)0x0400) þDMA_CCR3_MSIZE_1 ((uint16_t)0x0800) DMA_CCR3_PL ((uint16_t)0x3000) DMA_CCR3_PL_0 ((uint16_t)0x1000) DMA_CCR3_PL_1 ((uint16_t)0x2000) DMA_CCR3_MEM2MEM ((uint16_t)0x4000) DMA_CCR4_EN ((uint16_t)0x0001) DMA_CCR4_TCIE ((uint16_t)0x0002) DMA_CCR4_HTIE ((uint16_t)0x0004) DMA_CCR4_TEIE ((uint16_t)0x0008) DMA_CCR4_DIR ((uint16_t)0x0010) DMA_CCR4_CIRC ((uint16_t)0x0020) DMA_CCR4_PINC ((uint16_t)0x0040) DMA_CCR4_MINC ((uint16_t)0x0080) DMA_CCR4_PSIZE ((uint16_t)0x0300) DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) DMA_CCR4_MSIZE ((uint16_t)0x0C00) DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) DMA_CCR4_PL ((uint16_t)0x3000) DMA_CCR4_PL_0 ((uint16_t)0x1000) DMA_CCR4_PL_1 ((uint16_t)0x2000) DMA_CCR4_MEM2MEM ((uint16_t)0x4000) DMA_CCR5_EN ((uint16_t)0x0001) DMA_CCR5_TCIE ((uint16_t)0x0002) ¡DMA_CCR5_HTIE ((uint16_t)0x0004) ¢DMA_CCR5_TEIE ((uint16_t)0x0008) £DMA_CCR5_DIR ((uint16_t)0x0010) ¤DMA_CCR5_CIRC ((uint16_t)0x0020) ¥DMA_CCR5_PINC ((uint16_t)0x0040) ¦DMA_CCR5_MINC ((uint16_t)0x0080) ¨DMA_CCR5_PSIZE ((uint16_t)0x0300) ©DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) ªDMA_CCR5_PSIZE_1 ((uint16_t)0x0200) ¬DMA_CCR5_MSIZE ((uint16_t)0x0C00) DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) ®DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) °DMA_CCR5_PL ((uint16_t)0x3000) ±DMA_CCR5_PL_0 ((uint16_t)0x1000) ²DMA_CCR5_PL_1 ((uint16_t)0x2000) ´DMA_CCR5_MEM2MEM ((uint16_t)0x4000) ·DMA_CCR6_EN ((uint16_t)0x0001) ¸DMA_CCR6_TCIE ((uint16_t)0x0002) ¹DMA_CCR6_HTIE ((uint16_t)0x0004) ºDMA_CCR6_TEIE ((uint16_t)0x0008) »DMA_CCR6_DIR ((uint16_t)0x0010) ¼DMA_CCR6_CIRC ((uint16_t)0x0020) ½DMA_CCR6_PINC ((uint16_t)0x0040) ¾DMA_CCR6_MINC ((uint16_t)0x0080) ÀDMA_CCR6_PSIZE ((uint16_t)0x0300) ÁDMA_CCR6_PSIZE_0 ((uint16_t)0x0100) ÂDMA_CCR6_PSIZE_1 ((uint16_t)0x0200) ÄDMA_CCR6_MSIZE ((uint16_t)0x0C00) ÅDMA_CCR6_MSIZE_0 ((uint16_t)0x0400) ÆDMA_CCR6_MSIZE_1 ((uint16_t)0x0800) ÈDMA_CCR6_PL ((uint16_t)0x3000) ÉDMA_CCR6_PL_0 ((uint16_t)0x1000) ÊDMA_CCR6_PL_1 ((uint16_t)0x2000) ÌDMA_CCR6_MEM2MEM ((uint16_t)0x4000) ÏDMA_CCR7_EN ((uint16_t)0x0001) ÐDMA_CCR7_TCIE ((uint16_t)0x0002) ÑDMA_CCR7_HTIE ((uint16_t)0x0004) ÒDMA_CCR7_TEIE ((uint16_t)0x0008) ÓDMA_CCR7_DIR ((uint16_t)0x0010) ÔDMA_CCR7_CIRC ((uint16_t)0x0020) ÕDMA_CCR7_PINC ((uint16_t)0x0040) ÖDMA_CCR7_MINC ((uint16_t)0x0080) ØDMA_CCR7_PSIZE , ((uint16_t)0x0300) ÙDMA_CCR7_PSIZE_0 ((uint16_t)0x0100) ÚDMA_CCR7_PSIZE_1 ((uint16_t)0x0200) ÜDMA_CCR7_MSIZE ((uint16_t)0x0C00) ÝDMA_CCR7_MSIZE_0 ((uint16_t)0x0400) ÞDMA_CCR7_MSIZE_1 ((uint16_t)0x0800) àDMA_CCR7_PL ((uint16_t)0x3000) áDMA_CCR7_PL_0 ((uint16_t)0x1000) âDMA_CCR7_PL_1 ((uint16_t)0x2000) äDMA_CCR7_MEM2MEM ((uint16_t)0x4000) çDMA_CNDTR1_NDT ((uint16_t)0xFFFF) êDMA_CNDTR2_NDT ((uint16_t)0xFFFF) íDMA_CNDTR3_NDT ((uint16_t)0xFFFF) ðDMA_CNDTR4_NDT ((uint16_t)0xFFFF) óDMA_CNDTR5_NDT ((uint16_t)0xFFFF) öDMA_CNDTR6_NDT ((uint16_t)0xFFFF) ùDMA_CNDTR7_NDT ((uint16_t)0xFFFF) üDMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) ÿDMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) £DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) ¦DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) ¯EXTI_IMR_MR0 ((uint32_t)0x00000001) °EXTI_IMR_MR1 ((uint32_t)0x00000002) ±EXTI_IMR_MR2 ((uint32_t)0x00000004) ²EXTI_IMR_MR3 ((uint32_t)0x00000008) ³EXTI_IMR_MR4 ((uint32_t)0x00000010) ´EXTI_IMR_MR5 ((uint32_t)0x00000020) µEXTI_IMR_MR6 ((uint32_t)0x00000040) ¶EXTI_IMR_MR7 ((uint32_t)0x00000080) ·EXTI_IMR_MR8 ((uint32_t)0x00000100) ¸EXTI_IMR_MR9 ((uint32_t)0x00000200) ¹EXTI_IMR_MR10 ((uint32_t)0x00000400) ºEXTI_IMR_MR11 ((uint32_t)0x00000800) »EXTI_IMR_MR12 ((uint32_t)0x00001000) ¼EXTI_IMR_MR13 ((uint32_t)0x00002000) ½EXTI_IMR_MR14 ((uint32_t)0x00004000) ¾EXTI_IMR_MR15 ((uint32_t)0x00008000) ¿EXTI_IMR_MR16 ((uint32_t)0x00010000) ÀEXTI_IMR_MR17 ((uint32_t)0x00020000) ÁEXTI_IMR_MR18 ((uint32_t)0x00040000) ÂEXTI_IMR_MR19 ((uint32_t)0x00080000) ÃEXTI_IMR_MR20 ((uint32_t)0x00100000) ÄEXTI_IMR_MR21 ((uint32_t)0x00200000) ÅEXTI_IMR_MR22 ((uint32_t)0x00400000) ÆEXTI_IMR_MR23 ((uint32_t)0x00800000) ÉEXTI_EMR_MR0 ((uint32_t)0x00000001) ÊEXTI_EMR_MR1 ((uint32_t)0x00000002) ËEXTI_EMR_MR2 ((uint32_t)0x00000004) ÌEXTI_EMR_MR3 ((uint32_t)0x00000008) ÍEXTI_EMR_MR4 ((uint32_t)0x00000010) ÎEXTI_EMR_MR5 ((uint32_t)0x00000020) ÏEXTI_EMR_MR6 ((uint32_t)0x00000040) ÐEXTI_EMR_MR7 ((uint32_t)0x00000080) ÑEXTI_EMR_MR8 ((uint32_t)0x00000100) ÒEXTI_EMR_MR9 ((uint32_t)0x00000200) ÓEXTI_EMR_MR10 ((uint32_t)0x00000400) ÔEXTI_EMR_MR11 ((uint32_t)0x00000800) ÕEXTI_EMR_MR12 ((uint32_t)0x00001000) ÖEXTI_EMR_MR13 ((uint32_t)0x00002000) ×EXTI_EMR_MR14 ((uint32_t)0x00004000) ØEXTI_EMR_MR15 ((uint32_t)0x00008000) ÙEXTI_EMR_MR16 ((uint32_t)0x00010000) ÚEXTI_EMR_MR17 ((uint32_t)0x00020000) ÛEXTI_EMR_MR18 ((uint32_t)0x00040000) ÜEXTI_EMR_MR19 ((uint32_t)0x00080000) ÝEXTI_EMR_MR20 ((uint32_t)0x00100000) ÞEXTI_EMR_MR21 ((uint32_t)0x00200000) ßEXTI_EMR_MR22 ((uint32_t)0x00400000) àEXTI_EMR_MR23 ((uint32_t)0x00800000) ãEXTI_RTSR_TR0 ((uint32_t)0x00000001) äEXTI_RTSR_TR1 ((uint32_t)0x00000002) åEXTI_RTSR_TR2 ((uint32_t)0x00000004) æEXTI_RTSR_TR3 ((uint32_t)0x00000008) çEXTI_RTSR_TR4 ((uint32_t)0x00000010) èEXTI_RTSR_TR5 ((uint32_t)0x00000020) éEXTI_RTSR_TR6 ((uint32_t)0x00000040) êEXTI_RTSR_TR7 ((uint32_t)0x00000080) ëEXTI_RTSR_TR8 ((uint32_t)0x00000100) ìEXTI_RTSR_TR9 ((uint32_t)0x00000200) íEXTI_RTSR_TR10 ((uint32_t)0x00000400) îEXTI_RTSR_TR11 ((uint32_t)0x00000800) ïEXTI_RTSR_TR12 ((uint32_t)0x00001000) ðEXTI_RTSR_TR13 ((uint32_t)0x00002000) ñEXTI_RTSR_TR14 ((uint32_t)0x00004000) òEXTI_RTSR_TR15 ((uint32_t)0x00008000) óEXTI_RTSR_TR16 ((uint32_t)0x00010000) ôEXTI_RTSR_TR17 ((uint32_t)0x00020000) õEXTI_RTSR_TR18 ((uint32_t)0x00040000) öEXTI_RTSR_TR19 ((uint32_t)0x00080000) ÷EXTI_RTSR_TR20 ((uint32_t)0x00100000) øEXTI_RTSR_TR21 ((uint32_t)0x00200000) ùEXTI_RTSR_TR22 ((uint32_t)0x00400000) úEXTI_RTSR_TR23 ((uint32_t)0x00800000) ýEXTI_FTSR_TR0 ((uint32_t)0x00000001) þEXTI_FTSR_TR1 ((uint32_t)0x00000002) ÿEXTI_FTSR_TR2 ((uint32_t)0x00000004) EXTI_FTSR_TR3 ((uint32_t)0x00000008) EXTI_FTSR_TR4 ((uint32_t)0x00000010) EXTI_FTSR_TR5 ((uint32_t)0x00000020) EXTI_FTSR_TR6 ((uint32_t)0x00000040) EXTI_FTSR_TR7 ((uint32_t)0x00000080)
EXTI_FTSR_TR8 ((uint32_t)0x00000100) EXTI_FTSR_TR9 ((uint32_t)0x00000200) EXTI_FTSR_TR10 ((uint32_t)0x00000400) EXTI_FTSR_TR11 ((uint32_t)0x00000800) EXTI_FTSR_TR12 ((uint32_t)0x00001000) EXTI_FTSR_TR13 ((uint32_t)0x00002000) EXTI_FTSR_TR14 ((uint32_t)0x00004000) EXTI_FTSR_TR15 ((uint32_t)0x00008000) EXTI_FTSR_TR16 ((uint32_t)0x00010000) EXTI_FTSR_TR17 ((uint32_t)0x00020000) EXTI_FTSR_TR18 ((uint32_t)0x00040000) EXTI_FTSR_TR19 ((uint32_t)0x00080000) EXTI_FTSR_TR20 ((uint32_t)0x00100000) EXTI_FTSR_TR21 ((uint32_t)0x00200000) EXTI_FTSR_TR22 ((uint32_t)0x00400000) EXTI_FTSR_TR23 ((uint32_t)0x00800000) EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) ¡EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) ¢EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) £EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) ¤EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) ¥EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) ¦EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) §EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) ¨EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) ©EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) ªEXTI_SWIER_SWIER19 ((uint32_t)0x00080000) «EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) ¬EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) ®EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) ±EXTI_PR_PR0 ((uint32_t)0x00000001) ²EXTI_PR_PR1 ((uint32_t)0x00000002) ³EXTI_PR_PR2 ((uint32_t)0x00000004) ´EXTI_PR_PR3 ((uint32_t)0x00000008) µEXTI_PR_PR4 ((uint32_t)0x00000010) ¶EXTI_PR_PR5 ((uint32_t)0x00000020) ·EXTI_PR_PR6 ((uint32_t)0x00000040) ¸EXTI_PR_PR7 ((uint32_t)0x00000080) ¹EXTI_PR_PR8 ((uint32_t)0x00000100) ºEXTI_PR_PR9 ((uint32_t)0x00000200) »EXTI_PR_PR10 ((uint32_t)0x00000400) ¼EXTI_PR_PR11 ((uint32_t)0x00000800) ½EXTI_PR_PR12 ((uint32_t)0x00001000) ¾EXTI_PR_PR13 ((uint32_t)0x00002000) ¿EXTI_PR_PR14 ((uint32_t)0x00004000) ÀEXTI_PR_PR15 ((uint32_t)0x00008000) ÁEXTI_PR_PR16 ((uint32_t)0x00010000) ÂEXTI_PR_PR17 ((uint32_t)0x00020000) ÃEXTI_PR_PR18 ((uint32_t)0x00040000) ÄEXTI_PR_PR19 ((uint32_t)0x00080000) ÅEXTI_PR_PR20 ((uint32_t)0x00100000) ÆEXTI_PR_PR21 ((uint32_t)0x00200000) ÇEXTI_PR_PR22 ((uint32_t)0x00400000) ÈEXTI_PR_PR23 ((uint32_t)0x00800000) ÒFLASH_ACR_LATENCY ((uint32_t)0x00000001) ÓFLASH_ACR_PRFTEN ((uint32_t)0x00000002) ÔFLASH_ACR_ACC64 ((uint32_t)0x00000004) ÕFLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) ÖFLASH_ACR_RUN_PD ((uint32_t)0x00000010) ÙFLASH_PECR_PELOCK ((uint32_t)0x00000001) ÚFLASH_PECR_PRGLOCK ((uint32_t)0x00000002) ÛFLASH_PECR_OPTLOCK ((uint32_t)0x00000004) ÜFLASH_PECR_PROG ((uint32_t)0x00000008) ÝFLASH_PECR_DATA ((uint32_t)0x00000010) ÞFLASH_PECR_FTDW ((uint32_t)0x00000100) ßFLASH_PECR_ERASE ((uint32_t)0x00000200) àFLASH_PECR_FPRG ((uint32_t)0x00000400) áFLASH_PECR_PARALLBANK ((uint32_t)0x00008000) âFLASH_PECR_EOPIE ((uint32_t)0x00010000) ãFLASH_PECR_ERRIE ((uint32_t)0x00020000) äFLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) çFLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) êFLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) íFLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) ðFLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) óFLASH_SR_BSY ((uint32_t)0x00000001) ôFLASH_SR_EOP ((uint32_t)0x00000002) õFLASH_SR_ENHV ((uint32_t)0x00000004) öFLASH_SR_READY ((uint32_t)0x00000008) øFLASH_SR_WRPERR ((uint32_t)0x00000100) ùFLASH_SR_PGAERR ((uint32_t)0x00000200) úFLASH_SR_SIZERR ((uint32_t)0x00000400) ûFLASH_SR_OPTVERR ((uint32_t)0x00000800) üFLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) ÿFLASH_OBR_RDPRT ((uint16_t)0x000000AA) FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) FLASH_OBR_USER ((uint32_t)0x00700000) FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000)
FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) FSMC_BCR1_MBKEN ((uint32_t)0x00000001) FSMC_BCR1_MUXEN ((uint32_t)0x00000002) FSMC_BCR1_MTYP ((uint32_t)0x0000000C) FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) FSMC_BCR1_MWID ((uint32_t)0x00000030) FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) FSMC_BCR1_FACCEN ((uint32_t)0x00000040) ¡FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) ¢FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) £FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) ¤FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) ¥FSMC_BCR1_WREN ((uint32_t)0x00001000) ¦FSMC_BCR1_WAITEN ((uint32_t)0x00002000) §FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) ¨FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) ©FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) ¬FSMC_BCR2_MBKEN ((uint32_t)0x00000001) FSMC_BCR2_MUXEN ((uint32_t)0x00000002) ¯FSMC_BCR2_MTYP ((uint32_t)0x0000000C) °FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) ±FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) ³FSMC_BCR2_MWID ((uint32_t)0x00000030) ´FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) µFSMC_BCR2_MWID_1 ((uint32_t)0x00000020) ·FSMC_BCR2_FACCEN ((uint32_t)0x00000040) ¸FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) ¹FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) ºFSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) »FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) ¼FSMC_BCR2_WREN ((uint32_t)0x00001000) ½FSMC_BCR2_WAITEN ((uint32_t)0x00002000) ¾FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) ¿FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) ÀFSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) ÃFSMC_BCR3_MBKEN ((uint32_t)0x00000001) ÄFSMC_BCR3_MUXEN ((uint32_t)0x00000002) ÆFSMC_BCR3_MTYP ((uint32_t)0x0000000C) ÇFSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) ÈFSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) ÊFSMC_BCR3_MWID ((uint32_t)0x00000030) ËFSMC_BCR3_MWID_0 ((uint32_t)0x00000010) ÌFSMC_BCR3_MWID_1 ((uint32_t)0x00000020) ÎFSMC_BCR3_FACCEN ((uint32_t)0x00000040) ÏFSMC_BCR3_BURSTEN ((uint32_t)0x00000100) ÐFSMC_BCR3_WAITPOL ((uint32_t)0x00000200) ÑFSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) ÒFSMC_BCR3_WAITCFG ((uint32_t)0x00000800) ÓFSMC_BCR3_WREN ((uint32_t)0x00001000) ÔFSMC_BCR3_WAITEN ((uint32_t)0x00002000) ÕFSMC_BCR3_EXTMOD ((uint32_t)0x00004000) ÖFSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) ×FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) ÚFSMC_BCR4_MBKEN ((uint32_t)0x00000001) ÛFSMC_BCR4_MUXEN ((uint32_t)0x00000002) ÝFSMC_BCR4_MTYP ((uint32_t)0x0000000C) ÞFSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) ßFSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) áFSMC_BCR4_MWID ((uint32_t)0x00000030) âFSMC_BCR4_MWID_0 ((uint32_t)0x00000010) ãFSMC_BCR4_MWID_1 ((uint32_t)0x00000020) åFSMC_BCR4_FACCEN ((uint32_t)0x00000040) æFSMC_BCR4_BURSTEN ((uint32_t)0x00000100) çFSMC_BCR4_WAITPOL ((uint32_t)0x00000200) èFSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) éFSMC_BCR4_WAITCFG ((uint32_t)0x00000800) êFSMC_BCR4_WREN ((uint32_t)0x00001000) ëFSMC_BCR4_WAITEN ((uint32_t)0x00002000) ìFSMC_BCR4_EXTMOD ((uint32_t)0x00004000) íFSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) îFSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) ñFSMC_BTR1_ADDSET ((uint32_t)0x0000000F) òFSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) óFSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) ôFSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) õFSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) ÷FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) øFSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) ùFSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) úFSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) ûFSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) ýFSMC_BTR1_DATAST ((uint32_t)0x0000FF00) þFSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) ÿFSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) ¡FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) ¢FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) £FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) ¤FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) ¦FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) §FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) ¨FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) ©FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) ªFSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) ¬FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) ®FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) ¯FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) °FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) ²FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) ³FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) ´FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) µFSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) ¶FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) ¸FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) ¹FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) ºFSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) »FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) ¼FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) ¾FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) ¿FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) ÀFSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) ÃFSMC_BTR3_ADDSET ((uint32_t)0x0000000F) ÄFSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) ÅFSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) ÆFSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) ÇFSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) ÉFSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) ÊFSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) ËFSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) ÌFSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) ÍFSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) ÏFSMC_BTR3_DATAST ((uint32_t)0x0000FF00) ÐFSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) ÑFSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) ÒFSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) ÓFSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) ÕFSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) ÖFSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) ×FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) ØFSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) ÙFSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) ÛFSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) ÜFSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) ÝFSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) ÞFSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) ßFSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) áFSMC_BTR3_DATLAT ((uint32_t)0x0F000000) âFSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) ãFSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) äFSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) åFSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) çFSMC_BTR3_ACCMOD ((uint32_t)0x30000000) èFSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) éFSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) ìFSMC_BTR4_ADDSET ((uint32_t)0x0000000F) íFSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) îFSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) ïFSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) ðFSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) òFSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) óFSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) ôFSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) õFSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) öFSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) øFSMC_BTR4_DATAST ((uint32_t)0x0000FF00) ùFSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) úFSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) ûFSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) üFSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) þFSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) ÿFSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) ¡FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) ¢FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) £FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) ¤FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) ¥FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) §FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) ¨FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) ©FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) ªFSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) «FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) ®FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) ¯FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) °FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) ±FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) ³FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) ´FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) µFSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) ¸FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) ¹FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) ºFSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) »FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) ¼FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) ¾FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) ¿FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) ÀFSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) ÁFSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) ÂFSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) ÄFSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) ÅFSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) ÆFSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) ÇFSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) ÈFSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) ÊFSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) ËFSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) ÌFSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) ÍFSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) ÎFSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) ÐFSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) ÑFSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) ÒFSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) ÓFSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) ÔFSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) ÖFSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) ×FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) ØFSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) ÛFSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) ÜFSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) ÝFSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) ÞFSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) ßFSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) áFSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) âFSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) ãFSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) äFSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) åFSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) çFSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) èFSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) éFSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) êFSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) ëFSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) íFSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) îFSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) ïFSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) ðFSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) ñFSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) óFSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) ôFSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) õFSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) öFSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) ÷FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) ùFSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) úFSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) ûFSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) þFSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) ÿFSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) ¦GPIO_MODER_MODER0 ((uint32_t)0x00000003) §GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) ¨GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) ©GPIO_MODER_MODER1 ((uint32_t)0x0000000C) ªGPIO_MODER_MODER1_0 ((uint32_t)0x00000004) «GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) ¬GPIO_MODER_MODER2 ((uint32_t)0x00000030) GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) ®GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) ¯GPIO_MODER_MODER3 ((uint32_t)0x000000C0) °GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) ±GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) ²GPIO_MODER_MODER4 ((uint32_t)0x00000300) ³GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) ´GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) µGPIO_MODER_MODER5 ((uint32_t)0x00000C00) ¶GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) ·GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) ¸GPIO_MODER_MODER6 ((uint32_t)0x00003000) ¹GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) ºGPIO_MODER_MODER6_1 ((uint32_t)0x00002000) »GPIO_MODER_MODER7 ((uint32_t)0x0000C000) ¼GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) ½GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) ¾GPIO_MODER_MODER8 ((uint32_t)0x00030000) ¿GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) ÀGPIO_MODER_MODER8_1 ((uint32_t)0x00020000) ÁGPIO_MODER_MODER9 ((uint32_t)0x000C0000) ÂGPIO_MODER_MODER9_0 ((uint32_t)0x00040000) ÃGPIO_MODER_MODER9_1 ((uint32_t)0x00080000) ÄGPIO_MODER_MODER10 ((uint32_t)0x00300000) ÅGPIO_MODER_MODER10_0 ((uint32_t)0x00100000) ÆGPIO_MODER_MODER10_1 ((uint32_t)0x00200000) ÇGPIO_MODER_MODER11 ((uint32_t)0x00C00000) ÈGPIO_MODER_MODER11_0 ((uint32_t)0x00400000) ÉGPIO_MODER_MODER11_1 ((uint32_t)0x00800000) ÊGPIO_MODER_MODER12 ((uint32_t)0x03000000) ËGPIO_MODER_MODER12_0 ((uint32_t)0x01000000) ÌGPIO_MODER_MODER12_1 ((uint32_t)0x02000000) ÍGPIO_MODER_MODER13 ((uint32_t)0x0C000000) ÎGPIO_MODER_MODER13_0 ((uint32_t)0x04000000) ÏGPIO_MODER_MODER13_1 ((uint32_t)0x08000000) ÐGPIO_MODER_MODER14 ((uint32_t)0x30000000) ÑGPIO_MODER_MODER14_0 ((uint32_t)0x10000000) ÒGPIO_MODER_MODER14_1 ((uint32_t)0x20000000) ÓGPIO_MODER_MODER15 ((uint32_t)0xC0000000) ÔGPIO_MODER_MODER15_0 ((uint32_t)0x40000000) ÕGPIO_MODER_MODER15_1 ((uint32_t)0x80000000) ØGPIO_OTYPER_OT_0 ((uint32_t)0x00000001) ÙGPIO_OTYPER_OT_1 ((uint32_t)0x00000002) ÚGPIO_OTYPER_OT_2 ((uint32_t)0x00000004) ÛGPIO_OTYPER_OT_3 ((uint32_t)0x00000008) ÜGPIO_OTYPER_OT_4 ((uint32_t)0x00000010) ÝGPIO_OTYPER_OT_5 ((uint32_t)0x00000020) ÞGPIO_OTYPER_OT_6 ((uint32_t)0x00000040) ßGPIO_OTYPER_OT_7 ((uint32_t)0x00000080) àGPIO_OTYPER_OT_8 ((uint32_t)0x00000100) áGPIO_OTYPER_OT_9 ((uint32_t)0x00000200) âGPIO_OTYPER_OT_10 ((uint32_t)0x00000400) ãGPIO_OTYPER_OT_11 ((uint32_t)0x00000800) äGPIO_OTYPER_OT_12 ((uint32_t)0x00001000) åGPIO_OTYPER_OT_13 ((uint32_t)0x00002000) æGPIO_OTYPER_OT_14 ((uint32_t)0x00004000) çGPIO_OTYPER_OT_15 ((uint32_t)0x00008000) êGPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) ëGPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) ìGPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) íGPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) îGPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) ïGPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) ðGPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) ñGPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) òGPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) óGPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) ôGPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) õGPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) öGPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) ÷GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) øGPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) ùGPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) úGPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) ûGPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) üGPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) ýGPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) þGPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) ÿGPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) ¡GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) ¢GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) £GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) ¤GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) ¥GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) ¦GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) §GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) ¨GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) ©GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) ªGPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) «GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) ¬GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) ®GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) ¯GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) °GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) ±GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) ²GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) ³GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) ´GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) µGPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) ¶GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) ·GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) ¸GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) ¹GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) ºGPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) »GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) ¼GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) ½GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) ¾GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) ¿GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) ÀGPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) ÁGPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) ÂGPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) ÃGPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) ÄGPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) ÅGPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) ÆGPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) ÇGPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) ÈGPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) ÉGPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) ÊGPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) ËGPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) ÎGPIO_IDR_IDR_0 ((uint32_t)0x00000001) ÏGPIO_IDR_IDR_1 ((uint32_t)0x00000002) ÐGPIO_IDR_IDR_2 ((uint32_t)0x00000004) ÑGPIO_IDR_IDR_3 ((uint32_t)0x00000008) ÒGPIO_IDR_IDR_4 ((uint32_t)0x00000010) ÓGPIO_IDR_IDR_5 ((uint32_t)0x00000020) ÔGPIO_IDR_IDR_6 ((uint32_t)0x00000040) ÕGPIO_IDR_IDR_7 ((uint32_t)0x00000080) ÖGPIO_IDR_IDR_8 ((uint32_t)0x00000100) ×GPIO_IDR_IDR_9 ((uint32_t)0x00000200) ØGPIO_IDR_IDR_10 ((uint32_t)0x00000400) ÙGPIO_IDR_IDR_11 ((uint32_t)0x00000800) ÚGPIO_IDR_IDR_12 ((uint32_t)0x00001000) ÛGPIO_IDR_IDR_13 ((uint32_t)0x00002000) ÜGPIO_IDR_IDR_14 ((uint32_t)0x00004000) ÝGPIO_IDR_IDR_15 ((uint32_t)0x00008000) ßGPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 àGPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 áGPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 âGPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 ãGPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 äGPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 åGPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 æGPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 çGPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 èGPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 éGPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 êGPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 ëGPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 ìGPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 íGPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 îGPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 ñGPIO_ODR_ODR_0 ((uint32_t)0x00000001) òGPIO_ODR_ODR_1 ((uint32_t)0x00000002) óGPIO_ODR_ODR_2 ((uint32_t)0x00000004) ôGPIO_ODR_ODR_3 ((uint32_t)0x00000008) õGPIO_ODR_ODR_4 ((uint32_t)0x00000010) öGPIO_ODR_ODR_5 ((uint32_t)0x00000020) ÷GPIO_ODR_ODR_6 ((uint32_t)0x00000040) øGPIO_ODR_ODR_7 ((uint32_t)0x00000080) ùGPIO_ODR_ODR_8 ((uint32_t)0x00000100) úGPIO_ODR_ODR_9 ((uint32_t)0x00000200) ûGPIO_ODR_ODR_10 ((uint32_t)0x00000400) üGPIO_ODR_ODR_11 ((uint32_t)0x00000800) ýGPIO_ODR_ODR_12 ((uint32_t)0x00001000) þGPIO_ODR_ODR_13 ((uint32_t)0x00002000) ÿGPIO_ODR_ODR_14 ((uint32_t)0x00004000) GPIO_ODR_ODR_15 ((uint32_t)0x00008000) GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 GPIO_BSRR_BS_0 ((uint32_t)0x00000001) GPIO_BSRR_BS_1 ((uint32_t)0x00000002) GPIO_BSRR_BS_2 ((uint32_t)0x00000004) GPIO_BSRR_BS_3 ((uint32_t)0x00000008) GPIO_BSRR_BS_4 ((uint32_t)0x00000010) GPIO_BSRR_BS_5 ((uint32_t)0x00000020) GPIO_BSRR_BS_6 ((uint32_t)0x00000040) GPIO_BSRR_BS_7 ((uint32_t)0x00000080) GPIO_BSRR_BS_8 ((uint32_t)0x00000100) GPIO_BSRR_BS_9 ((uint32_t)0x00000200) GPIO_BSRR_BS_10 ((uint32_t)0x00000400) GPIO_BSRR_BS_11 ((uint32_t)0x00000800) GPIO_BSRR_BS_12 ((uint32_t)0x00001000) ¡GPIO_BSRR_BS_13 ((uint32_t)0x00002000) ¢GPIO_BSRR_BS_14 ((uint32_t)0x00004000) £GPIO_BSRR_BS_15 ((uint32_t)0x00008000) ¤GPIO_BSRR_BR_0 ((uint32_t)0x00010000) ¥GPIO_BSRR_BR_1 ((uint32_t)0x00020000) ¦GPIO_BSRR_BR_2 ((uint32_t)0x00040000) §GPIO_BSRR_BR_3 ((uint32_t)0x00080000) ¨GPIO_BSRR_BR_4 ((uint32_t)0x00100000) ©GPIO_BSRR_BR_5 ((uint32_t)0x00200000) ªGPIO_BSRR_BR_6 ((uint32_t)0x00400000) «GPIO_BSRR_BR_7 ((uint32_t)0x00800000) ¬GPIO_BSRR_BR_8 ((uint32_t)0x01000000) GPIO_BSRR_BR_9 ((uint32_t)0x02000000) ®GPIO_BSRR_BR_10 ((uint32_t)0x04000000) ¯GPIO_BSRR_BR_11 ((uint32_t)0x08000000) °GPIO_BSRR_BR_12 ((uint32_t)0x10000000) ±GPIO_BSRR_BR_13 ((uint32_t)0x20000000) ²GPIO_BSRR_BR_14 ((uint32_t)0x40000000) ³GPIO_BSRR_BR_15 ((uint32_t)0x80000000) ¶GPIO_LCKR_LCK0 ((uint32_t)0x00000001) ·GPIO_LCKR_LCK1 ((uint32_t)0x00000002) ¸GPIO_LCKR_LCK2 ((uint32_t)0x00000004) ¹GPIO_LCKR_LCK3 ((uint32_t)0x00000008) ºGPIO_LCKR_LCK4 ((uint32_t)0x00000010) »GPIO_LCKR_LCK5 ((uint32_t)0x00000020) ¼GPIO_LCKR_LCK6 ((uint32_t)0x00000040) ½GPIO_LCKR_LCK7 ((uint32_t)0x00000080) ¾GPIO_LCKR_LCK8 ((uint32_t)0x00000100) ¿GPIO_LCKR_LCK9 ((uint32_t)0x00000200) ÀGPIO_LCKR_LCK10 ((uint32_t)0x00000400) ÁGPIO_LCKR_LCK11 ((uint32_t)0x00000800) ÂGPIO_LCKR_LCK12 ((uint32_t)0x00001000) ÃGPIO_LCKR_LCK13 ((uint32_t)0x00002000) ÄGPIO_LCKR_LCK14 ((uint32_t)0x00004000) ÅGPIO_LCKR_LCK15 ((uint32_t)0x00008000) ÆGPIO_LCKR_LCKK ((uint32_t)0x00010000) ÉGPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) ÊGPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) ËGPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) ÌGPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) ÍGPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) ÎGPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) ÏGPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) ÐGPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) ÓGPIO_AFRH_AFRH8 ((uint32_t)0x0000000F) ÔGPIO_AFRH_AFRH9 ((uint32_t)0x000000F0) ÕGPIO_AFRH_AFRH10 ((uint32_t)0x00000F00) ÖGPIO_AFRH_AFRH11 ((uint32_t)0x0000F000) ×GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000) ØGPIO_AFRH_AFRH13 ((uint32_t)0x00F00000) ÙGPIO_AFRH_AFRH14 ((uint32_t)0x0F000000) ÚGPIO_AFRH_AFRH15 ((uint32_t)0xF0000000) ãI2C_CR1_PE ((uint16_t)0x0001) äI2C_CR1_SMBUS ((uint16_t)0x0002) åI2C_CR1_SMBTYPE ((uint16_t)0x0008) æI2C_CR1_ENARP ((uint16_t)0x0010) çI2C_CR1_ENPEC ((uint16_t)0x0020) èI2C_CR1_ENGC ((uint16_t)0x0040) éI2C_CR1_NOSTRETCH ((uint16_t)0x0080) êI2C_CR1_START ((uint16_t)0x0100) ëI2C_CR1_STOP ((uint16_t)0x0200) ìI2C_CR1_ACK ((uint16_t)0x0400) íI2C_CR1_POS ((uint16_t)0x0800) îI2C_CR1_PEC ((uint16_t)0x1000) ïI2C_CR1_ALERT ((uint16_t)0x2000) ðI2C_CR1_SWRST ((uint16_t)0x8000) óI2C_CR2_FREQ ((uint16_t)0x003F) ôI2C_CR2_FREQ_0 ((uint16_t)0x0001) õI2C_CR2_FREQ_1 ((uint16_t)0x0002) öI2C_CR2_FREQ_2 ((uint16_t)0x0004) ÷I2C_CR2_FREQ_3 ((uint16_t)0x0008) øI2C_CR2_FREQ_4 ((uint16_t)0x0010) ùI2C_CR2_FREQ_5 ((uint16_t)0x0020) ûI2C_CR2_ITERREN ((uint16_t)0x0100) üI2C_CR2_ITEVTEN ((uint16_t)0x0200) ýI2C_CR2_ITBUFEN ((uint16_t)0x0400) þI2C_CR2_DMAEN ((uint16_t)0x0800) ÿI2C_CR2_LAST ((uint16_t)0x1000) I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
I2C_OAR1_ADD0 ((uint16_t)0x0001) I2C_OAR1_ADD1 ((uint16_t)0x0002) I2C_OAR1_ADD2 ((uint16_t)0x0004) I2C_OAR1_ADD3 ((uint16_t)0x0008) I2C_OAR1_ADD4 ((uint16_t)0x0010) I2C_OAR1_ADD5 ((uint16_t)0x0020) I2C_OAR1_ADD6 ((uint16_t)0x0040) I2C_OAR1_ADD7 ((uint16_t)0x0080) I2C_OAR1_ADD8 ((uint16_t)0x0100) I2C_OAR1_ADD9 ((uint16_t)0x0200) I2C_OAR1_ADDMODE ((uint16_t)0x8000) I2C_OAR2_ENDUAL ((uint8_t)0x01) I2C_OAR2_ADD2 ((uint8_t)0xFE) I2C_DR_DR ((uint8_t)0xFF) I2C_SR1_SB ((uint16_t)0x0001) I2C_SR1_ADDR ((uint16_t)0x0002) I2C_SR1_BTF ((uint16_t)0x0004) I2C_SR1_ADD10 ((uint16_t)0x0008) I2C_SR1_STOPF ((uint16_t)0x0010) I2C_SR1_RXNE ((uint16_t)0x0040) I2C_SR1_TXE ((uint16_t)0x0080) ¡I2C_SR1_BERR ((uint16_t)0x0100) ¢I2C_SR1_ARLO ((uint16_t)0x0200) £I2C_SR1_AF ((uint16_t)0x0400) ¤I2C_SR1_OVR ((uint16_t)0x0800) ¥I2C_SR1_PECERR ((uint16_t)0x1000) ¦I2C_SR1_TIMEOUT ((uint16_t)0x4000) §I2C_SR1_SMBALERT ((uint16_t)0x8000) ªI2C_SR2_MSL ((uint16_t)0x0001) «I2C_SR2_BUSY ((uint16_t)0x0002) ¬I2C_SR2_TRA ((uint16_t)0x0004) I2C_SR2_GENCALL ((uint16_t)0x0010) ®I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) ¯I2C_SR2_SMBHOST ((uint16_t)0x0040) °I2C_SR2_DUALF ((uint16_t)0x0080) ±I2C_SR2_PEC ((uint16_t)0xFF00) ´I2C_CCR_CCR ((uint16_t)0x0FFF) µI2C_CCR_DUTY ((uint16_t)0x4000) ¶I2C_CCR_FS ((uint16_t)0x8000) ¹I2C_TRISE_TRISE ((uint8_t)0x3F) ÂIWDG_KR_KEY ((uint16_t)0xFFFF) ÅIWDG_PR_PR ((uint8_t)0x07) ÆIWDG_PR_PR_0 ((uint8_t)0x01) ÇIWDG_PR_PR_1 ((uint8_t)0x02) ÈIWDG_PR_PR_2 ((uint8_t)0x04) ËIWDG_RLR_RL ((uint16_t)0x0FFF) ÎIWDG_SR_PVU ((uint8_t)0x01) ÏIWDG_SR_RVU ((uint8_t)0x02) ØLCD_CR_LCDEN ((uint32_t)0x00000001) ÙLCD_CR_VSEL ((uint32_t)0x00000002) ÛLCD_CR_DUTY ((uint32_t)0x0000001C) ÜLCD_CR_DUTY_0 ((uint32_t)0x00000004) ÝLCD_CR_DUTY_1 ((uint32_t)0x00000008) ÞLCD_CR_DUTY_2 ((uint32_t)0x00000010) àLCD_CR_BIAS ((uint32_t)0x00000060) áLCD_CR_BIAS_0 ((uint32_t)0x00000020) âLCD_CR_BIAS_1 ((uint32_t)0x00000040) äLCD_CR_MUX_SEG ((uint32_t)0x00000080) çLCD_FCR_HD ((uint32_t)0x00000001) èLCD_FCR_SOFIE ((uint32_t)0x00000002) éLCD_FCR_UDDIE ((uint32_t)0x00000008) ëLCD_FCR_PON ((uint32_t)0x00000070) ìLCD_FCR_PON_0 ((uint32_t)0x00000010) íLCD_FCR_PON_1 ((uint32_t)0x00000020) îLCD_FCR_PON_2 ((uint32_t)0x00000040) ðLCD_FCR_DEAD ((uint32_t)0x00000380) ñLCD_FCR_DEAD_0 ((uint32_t)0x00000080) òLCD_FCR_DEAD_1 ((uint32_t)0x00000100) óLCD_FCR_DEAD_2 ((uint32_t)0x00000200) õLCD_FCR_CC ((uint32_t)0x00001C00) öLCD_FCR_CC_0 ((uint32_t)0x00000400) ÷LCD_FCR_CC_1 ((uint32_t)0x00000800) øLCD_FCR_CC_2 ((uint32_t)0x00001000) úLCD_FCR_BLINKF ((uint32_t)0x0000E000) ûLCD_FCR_BLINKF_0 ((uint32_t)0x00002000) üLCD_FCR_BLINKF_1 ((uint32_t)0x00004000) ýLCD_FCR_BLINKF_2 ((uint32_t)0x00008000) ÿLCD_FCR_BLINK ((uint32_t)0x00030000) LCD_FCR_BLINK_0 ((uint32_t)0x00010000) LCD_FCR_BLINK_1 ((uint32_t)0x00020000) LCD_FCR_DIV ((uint32_t)0x003C0000) LCD_FCR_PS ((uint32_t)0x03C00000) LCD_SR_ENS ((uint32_t)0x00000001) LCD_SR_SOF ((uint32_t)0x00000002) LCD_SR_UDR ((uint32_t)0x00000004) LCD_SR_UDD ((uint32_t)0x00000008) LCD_SR_RDY ((uint32_t)0x00000010) LCD_SR_FCRSR ((uint32_t)0x00000020) LCD_CLR_SOFC ((uint32_t)0x00000002) LCD_CLR_UDDC ((uint32_t)0x00000008) LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) PWR_CR_LPSDSR ((uint16_t)0x0001) PWR_CR_PDDS ((uint16_t)0x0002) PWR_CR_CWUF ((uint16_t)0x0004) PWR_CR_CSBF ((uint16_t)0x0008) PWR_CR_PVDE ((uint16_t)0x0010) ¢PWR_CR_PLS ((uint16_t)0x00E0) £PWR_CR_PLS_0 ((uint16_t)0x0020) ¤PWR_CR_PLS_1 ((uint16_t)0x0040) ¥PWR_CR_PLS_2 ((uint16_t)0x0080) ¨PWR_CR_PLS_LEV0 ((uint16_t)0x0000) ©PWR_CR_PLS_LEV1 ((uint16_t)0x0020) ªPWR_CR_PLS_LEV2 ((uint16_t)0x0040) «PWR_CR_PLS_LEV3 ((uint16_t)0x0060) ¬PWR_CR_PLS_LEV4 ((uint16_t)0x0080) PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) ®PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) ¯PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) ±PWR_CR_DBP ((uint16_t)0x0100) ²PWR_CR_ULP ((uint16_t)0x0200) ³PWR_CR_FWU ((uint16_t)0x0400) µPWR_CR_VOS ((uint16_t)0x1800) ¶PWR_CR_VOS_0 ((uint16_t)0x0800) ·PWR_CR_VOS_1 ((uint16_t)0x1000) ¸PWR_CR_LPRUN ((uint16_t)0x4000) »PWR_CSR_WUF ((uint16_t)0x0001) ¼PWR_CSR_SBF ((uint16_t)0x0002) ½PWR_CSR_PVDO ((uint16_t)0x0004) ¾PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) ¿PWR_CSR_VOSF ((uint16_t)0x0010) ÀPWR_CSR_REGLPF ((uint16_t)0x0020) ÂPWR_CSR_EWUP1 ((uint16_t)0x0100) ÃPWR_CSR_EWUP2 ((uint16_t)0x0200) ÄPWR_CSR_EWUP3 ((uint16_t)0x0400) ÌRCC_CR_HSION ((uint32_t)0x00000001) ÍRCC_CR_HSIRDY ((uint32_t)0x00000002) ÏRCC_CR_MSION ((uint32_t)0x00000100) ÐRCC_CR_MSIRDY ((uint32_t)0x00000200) ÒRCC_CR_HSEON ((uint32_t)0x00010000) ÓRCC_CR_HSERDY ((uint32_t)0x00020000) ÔRCC_CR_HSEBYP ((uint32_t)0x00040000) ÖRCC_CR_PLLON ((uint32_t)0x01000000) ×RCC_CR_PLLRDY ((uint32_t)0x02000000) ØRCC_CR_CSSON ((uint32_t)0x10000000) ÚRCC_CR_RTCPRE ((uint32_t)0x60000000) ÛRCC_CR_RTCPRE_0 ((uint32_t)0x20000000) ÜRCC_CR_RTCPRE_1 ((uint32_t)0x40000000) ßRCC_ICSCR_HSICAL ((uint32_t)0x000000FF) àRCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) âRCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) ãRCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) äRCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) åRCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) æRCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) çRCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) èRCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) éRCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) êRCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) ëRCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) îRCC_CFGR_SW ((uint32_t)0x00000003) ïRCC_CFGR_SW_0 ((uint32_t)0x00000001) ðRCC_CFGR_SW_1 ((uint32_t)0x00000002) óRCC_CFGR_SW_MSI ((uint32_t)0x00000000) ôRCC_CFGR_SW_HSI ((uint32_t)0x00000001) õRCC_CFGR_SW_HSE ((uint32_t)0x00000002) öRCC_CFGR_SW_PLL ((uint32_t)0x00000003) øRCC_CFGR_SWS ((uint32_t)0x0000000C) ùRCC_CFGR_SWS_0 ((uint32_t)0x00000004) úRCC_CFGR_SWS_1 ((uint32_t)0x00000008) ýRCC_CFGR_SWS_MSI ((uint32_t)0x00000000) þRCC_CFGR_SWS_HSI ((uint32_t)0x00000004) ÿRCC_CFGR_SWS_HSE ((uint32_t)0x00000008) RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) RCC_CFGR_HPRE ((uint32_t)0x000000F0) RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) RCC_CFGR_PPRE1 ((uint32_t)0x00000700) RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) RCC_CFGR_PPRE2 ((uint32_t)0x00003800) RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) ¡RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) ¢RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) ¥RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) ¦RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) §RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) ¨RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) ©RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) ¬RCC_CFGR_PLLSRC ((uint32_t)0x00010000) ®RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) ¯RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) ²RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) ³RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) ´RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) µRCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) ¶RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) ¹RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) ºRCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) »RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) ¼RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) ½RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) ¾RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) ¿RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) ÀRCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) ÁRCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) ÄRCC_CFGR_PLLDIV ((uint32_t)0x00C00000) ÅRCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) ÆRCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) ÊRCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) ËRCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) ÌRCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) ÍRCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) ÐRCC_CFGR_MCOSEL ((uint32_t)0x07000000) ÑRCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) ÒRCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) ÓRCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) ÖRCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) ×RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) ØRCC_CFGR_MCO_HSI ((uint32_t)0x02000000) ÙRCC_CFGR_MCO_MSI ((uint32_t)0x03000000) ÚRCC_CFGR_MCO_HSE ((uint32_t)0x04000000) ÛRCC_CFGR_MCO_PLL ((uint32_t)0x05000000) ÜRCC_CFGR_MCO_LSI ((uint32_t)0x06000000) ÝRCC_CFGR_MCO_LSE ((uint32_t)0x07000000) ßRCC_CFGR_MCOPRE ((uint32_t)0x70000000) àRCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) áRCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) âRCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) åRCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) æRCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) çRCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) èRCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) éRCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) ìRCC_CIR_LSIRDYF ((uint32_t)0x00000001) íRCC_CIR_LSERDYF ((uint32_t)0x00000002) îRCC_CIR_HSIRDYF ((uint32_t)0x00000004) ïRCC_CIR_HSERDYF ((uint32_t)0x00000008) ðRCC_CIR_PLLRDYF ((uint32_t)0x00000010) ñRCC_CIR_MSIRDYF ((uint32_t)0x00000020) òRCC_CIR_LSECSS ((uint32_t)0x00000040) óRCC_CIR_CSSF ((uint32_t)0x00000080) õRCC_CIR_LSIRDYIE ((uint32_t)0x00000100) öRCC_CIR_LSERDYIE ((uint32_t)0x00000200) ÷RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) øRCC_CIR_HSERDYIE ((uint32_t)0x00000800) ùRCC_CIR_PLLRDYIE ((uint32_t)0x00001000) úRCC_CIR_MSIRDYIE ((uint32_t)0x00002000) ûRCC_CIR_LSECSSIE ((uint32_t)0x00004000) ýRCC_CIR_LSIRDYC ((uint32_t)0x00010000) þRCC_CIR_LSERDYC ((uint32_t)0x00020000) ÿRCC_CIR_HSIRDYC ((uint32_t)0x00040000) RCC_CIR_HSERDYC ((uint32_t)0x00080000) RCC_CIR_PLLRDYC ((uint32_t)0x00100000) RCC_CIR_MSIRDYC ((uint32_t)0x00200000) RCC_CIR_LSECSSC ((uint32_t)0x00400000) RCC_CIR_CSSC ((uint32_t)0x00800000) RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) ¢ RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) £ RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) ¤ RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) ¥ RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) ¦ RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) § RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) ¨ RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) © RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) ª RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) « RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) ¬ RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) ® RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) ¯ RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) ° RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) ± RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) ² RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) ³ RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) ´ RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) µ RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) ¸ RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) ¹ RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) º RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) » RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) ¼ RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) ½ RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) ¾ RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) ¿ RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) À RCC_AHBENR_CRCEN ((uint32_t)0x00001000) Á RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) Ã RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) Ä RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) Å RCC_AHBENR_AESEN ((uint32_t)0x08000000) Æ RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) Ê RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) Ë RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) Ì RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) Í RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) Î RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) Ï RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) Ð RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) Ñ RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) Õ RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) Ö RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) × RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) Ø RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) Ù RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) Ú RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) Û RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) Ü RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) Ý RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) Þ RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) ß RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) à RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) á RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) â RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) ã RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) ä RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) å RCC_APB1ENR_USBEN ((uint32_t)0x00800000) æ RCC_APB1ENR_PWREN ((uint32_t)0x10000000) ç RCC_APB1ENR_DACEN ((uint32_t)0x20000000) è RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) ë RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) ì RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) í RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) î RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) ï RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) ð RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) ñ RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) ò RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) ó RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) ô RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) ÷ RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) ø RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) ù RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) ú RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) û RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) þ RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) ÿ RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) RCC_CSR_LSION ((uint32_t)0x00000001) RCC_CSR_LSIRDY ((uint32_t)0x00000002) ¡ RCC_CSR_LSEON ((uint32_t)0x00000100) ¢ RCC_CSR_LSERDY ((uint32_t)0x00000200) £ RCC_CSR_LSEBYP ((uint32_t)0x00000400) ¤ RCC_CSR_LSECSSON ((uint32_t)0x00000800) ¥ RCC_CSR_LSECSSD ((uint32_t)0x00001000) § RCC_CSR_RTCSEL ((uint32_t)0x00030000) ¨ RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) © RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) ¬ RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) ® RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) ¯ RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) ± RCC_CSR_RTCEN ((uint32_t)0x00400000) ² RCC_CSR_RTCRST ((uint32_t)0x00800000) ´ RCC_CSR_RMVF ((uint32_t)0x01000000) µ RCC_CSR_OBLRSTF ((uint32_t)0x02000000) ¶ RCC_CSR_PINRSTF ((uint32_t)0x04000000) · RCC_CSR_PORRSTF ((uint32_t)0x08000000) ¸ RCC_CSR_SFTRSTF ((uint32_t)0x10000000) ¹ RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) º RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) » RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) Ä RTC_TR_PM ((uint32_t)0x00400000) Å RTC_TR_HT ((uint32_t)0x00300000) Æ RTC_TR_HT_0 ((uint32_t)0x00100000) Ç RTC_TR_HT_1 ((uint32_t)0x00200000) È RTC_TR_HU ((uint32_t)0x000F0000) É RTC_TR_HU_0 ((uint32_t)0x00010000) Ê RTC_TR_HU_1 ((uint32_t)0x00020000) Ë RTC_TR_HU_2 ((uint32_t)0x00040000) Ì RTC_TR_HU_3 ((uint32_t)0x00080000) Í RTC_TR_MNT ((uint32_t)0x00007000) Î RTC_TR_MNT_0 ((uint32_t)0x00001000) Ï RTC_TR_MNT_1 ((uint32_t)0x00002000) Ð RTC_TR_MNT_2 ((uint32_t)0x00004000) Ñ RTC_TR_MNU ((uint32_t)0x00000F00) Ò RTC_TR_MNU_0 ((uint32_t)0x00000100) Ó RTC_TR_MNU_1 ((uint32_t)0x00000200) Ô RTC_TR_MNU_2 ((uint32_t)0x00000400) Õ RTC_TR_MNU_3 ((uint32_t)0x00000800) Ö RTC_TR_ST ((uint32_t)0x00000070) × RTC_TR_ST_0 ((uint32_t)0x00000010) Ø RTC_TR_ST_1 ((uint32_t)0x00000020) Ù RTC_TR_ST_2 ((uint32_t)0x00000040) Ú RTC_TR_SU ((uint32_t)0x0000000F) Û RTC_TR_SU_0 ((uint32_t)0x00000001) Ü RTC_TR_SU_1 ((uint32_t)0x00000002) Ý RTC_TR_SU_2 ((uint32_t)0x00000004) Þ RTC_TR_SU_3 ((uint32_t)0x00000008) á RTC_DR_YT ((uint32_t)0x00F00000) â RTC_DR_YT_0 ((uint32_t)0x00100000) ã RTC_DR_YT_1 ((uint32_t)0x00200000) ä RTC_DR_YT_2 ((uint32_t)0x00400000) å RTC_DR_YT_3 ((uint32_t)0x00800000) æ RTC_DR_YU ((uint32_t)0x000F0000) ç RTC_DR_YU_0 ((uint32_t)0x00010000) è RTC_DR_YU_1 ((uint32_t)0x00020000) é RTC_DR_YU_2 ((uint32_t)0x00040000) ê RTC_DR_YU_3 ((uint32_t)0x00080000) ë RTC_DR_WDU ((uint32_t)0x0000E000) ì RTC_DR_WDU_0 ((uint32_t)0x00002000) í RTC_DR_WDU_1 ((uint32_t)0x00004000) î RTC_DR_WDU_2 ((uint32_t)0x00008000) ï RTC_DR_MT ((uint32_t)0x00001000) ð RTC_DR_MU ((uint32_t)0x00000F00) ñ RTC_DR_MU_0 ((uint32_t)0x00000100) ò RTC_DR_MU_1 ((uint32_t)0x00000200) ó RTC_DR_MU_2 ((uint32_t)0x00000400) ô RTC_DR_MU_3 ((uint32_t)0x00000800) õ RTC_DR_DT ((uint32_t)0x00000030) ö RTC_DR_DT_0 ((uint32_t)0x00000010) ÷ RTC_DR_DT_1 ((uint32_t)0x00000020) ø RTC_DR_DU ((uint32_t)0x0000000F) ù RTC_DR_DU_0 ((uint32_t)0x00000001) ú RTC_DR_DU_1 ((uint32_t)0x00000002) û RTC_DR_DU_2 ((uint32_t)0x00000004) ü RTC_DR_DU_3 ((uint32_t)0x00000008) ÿ RTC_CR_COE ((uint32_t)0x00800000) RTC_CR_OSEL ((uint32_t)0x00600000) RTC_CR_OSEL_0 ((uint32_t)0x00200000) RTC_CR_OSEL_1 ((uint32_t)0x00400000) RTC_CR_POL ((uint32_t)0x00100000) RTC_CR_COSEL ((uint32_t)0x00080000)
RTC_CR_BCK ((uint32_t)0x00040000) RTC_CR_SUB1H ((uint32_t)0x00020000) RTC_CR_ADD1H ((uint32_t)0x00010000) RTC_CR_TSIE ((uint32_t)0x00008000) RTC_CR_WUTIE ((uint32_t)0x00004000) RTC_CR_ALRBIE ((uint32_t)0x00002000) RTC_CR_ALRAIE ((uint32_t)0x00001000) RTC_CR_TSE ((uint32_t)0x00000800) RTC_CR_WUTE ((uint32_t)0x00000400) RTC_CR_ALRBE ((uint32_t)0x00000200) RTC_CR_ALRAE ((uint32_t)0x00000100) RTC_CR_DCE ((uint32_t)0x00000080) RTC_CR_FMT ((uint32_t)0x00000040) RTC_CR_BYPSHAD ((uint32_t)0x00000020) RTC_CR_REFCKON ((uint32_t)0x00000010) RTC_CR_TSEDGE ((uint32_t)0x00000008) RTC_CR_WUCKSEL ((uint32_t)0x00000007) RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) RTC_ISR_RECALPF ((uint32_t)0x00010000) RTC_ISR_TAMP3F ((uint32_t)0x00008000) RTC_ISR_TAMP2F ((uint32_t)0x00004000) RTC_ISR_TAMP1F ((uint32_t)0x00002000) RTC_ISR_TSOVF ((uint32_t)0x00001000) RTC_ISR_TSF ((uint32_t)0x00000800) ¡ RTC_ISR_WUTF ((uint32_t)0x00000400) ¢ RTC_ISR_ALRBF ((uint32_t)0x00000200) £ RTC_ISR_ALRAF ((uint32_t)0x00000100) ¤ RTC_ISR_INIT ((uint32_t)0x00000080) ¥ RTC_ISR_INITF ((uint32_t)0x00000040) ¦ RTC_ISR_RSF ((uint32_t)0x00000020) § RTC_ISR_INITS ((uint32_t)0x00000010) ¨ RTC_ISR_SHPF ((uint32_t)0x00000008) © RTC_ISR_WUTWF ((uint32_t)0x00000004) ª RTC_ISR_ALRBWF ((uint32_t)0x00000002) « RTC_ISR_ALRAWF ((uint32_t)0x00000001) ® RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) ¯ RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) ² RTC_WUTR_WUT ((uint32_t)0x0000FFFF) µ RTC_CALIBR_DCS ((uint32_t)0x00000080) ¶ RTC_CALIBR_DC ((uint32_t)0x0000001F) ¹ RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) º RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) » RTC_ALRMAR_DT ((uint32_t)0x30000000) ¼ RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) ½ RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) ¾ RTC_ALRMAR_DU ((uint32_t)0x0F000000) ¿ RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) À RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) Á RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) Â RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) Ã RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) Ä RTC_ALRMAR_PM ((uint32_t)0x00400000) Å RTC_ALRMAR_HT ((uint32_t)0x00300000) Æ RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) Ç RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) È RTC_ALRMAR_HU ((uint32_t)0x000F0000) É RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) Ê RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) Ë RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) Ì RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) Í RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) Î RTC_ALRMAR_MNT ((uint32_t)0x00007000) Ï RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) Ð RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) Ñ RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) Ò RTC_ALRMAR_MNU ((uint32_t)0x00000F00) Ó RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) Ô RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) Õ RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) Ö RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) × RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) Ø RTC_ALRMAR_ST ((uint32_t)0x00000070) Ù RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) Ú RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) Û RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) Ü RTC_ALRMAR_SU ((uint32_t)0x0000000F) Ý RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) Þ RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) ß RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) à RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) ã RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) ä RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) å RTC_ALRMBR_DT ((uint32_t)0x30000000) æ RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) ç RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) è RTC_ALRMBR_DU ((uint32_t)0x0F000000) é RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) ê RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) ë RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) ì RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) í RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) î RTC_ALRMBR_PM ((uint32_t)0x00400000) ï RTC_ALRMBR_HT ((uint32_t)0x00300000) ð RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) ñ RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) ò RTC_ALRMBR_HU ((uint32_t)0x000F0000) ó RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) ô RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) õ RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) ö RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) ÷ RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) ø RTC_ALRMBR_MNT ((uint32_t)0x00007000) ù RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) ú RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) û RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) ü RTC_ALRMBR_MNU ((uint32_t)0x00000F00) ý RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) þ RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) ÿ RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) RTC_ALRMBR_ST ((uint32_t)0x00000070) RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) RTC_ALRMBR_SU ((uint32_t)0x0000000F) RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) RTC_WPR_KEY ((uint32_t)0x000000FF) RTC_SSR_SS ((uint32_t)0x0000FFFF) RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) RTC_TSTR_PM ((uint32_t)0x00400000) RTC_TSTR_HT ((uint32_t)0x00300000) RTC_TSTR_HT_0 ((uint32_t)0x00100000) RTC_TSTR_HT_1 ((uint32_t)0x00200000) RTC_TSTR_HU ((uint32_t)0x000F0000) RTC_TSTR_HU_0 ((uint32_t)0x00010000) RTC_TSTR_HU_1 ((uint32_t)0x00020000) RTC_TSTR_HU_2 ((uint32_t)0x00040000) RTC_TSTR_HU_3 ((uint32_t)0x00080000) RTC_TSTR_MNT ((uint32_t)0x00007000) ¡ RTC_TSTR_MNT_0 ((uint32_t)0x00001000) ¢ RTC_TSTR_MNT_1 ((uint32_t)0x00002000) £ RTC_TSTR_MNT_2 ((uint32_t)0x00004000) ¤ RTC_TSTR_MNU ((uint32_t)0x00000F00) ¥ RTC_TSTR_MNU_0 ((uint32_t)0x00000100) ¦ RTC_TSTR_MNU_1 ((uint32_t)0x00000200) § RTC_TSTR_MNU_2 ((uint32_t)0x00000400) ¨ RTC_TSTR_MNU_3 ((uint32_t)0x00000800) © RTC_TSTR_ST ((uint32_t)0x00000070) ª RTC_TSTR_ST_0 ((uint32_t)0x00000010) « RTC_TSTR_ST_1 ((uint32_t)0x00000020) ¬ RTC_TSTR_ST_2 ((uint32_t)0x00000040) RTC_TSTR_SU ((uint32_t)0x0000000F) ® RTC_TSTR_SU_0 ((uint32_t)0x00000001) ¯ RTC_TSTR_SU_1 ((uint32_t)0x00000002) ° RTC_TSTR_SU_2 ((uint32_t)0x00000004) ± RTC_TSTR_SU_3 ((uint32_t)0x00000008) ´ RTC_TSDR_WDU ((uint32_t)0x0000E000) µ RTC_TSDR_WDU_0 ((uint32_t)0x00002000) ¶ RTC_TSDR_WDU_1 ((uint32_t)0x00004000) · RTC_TSDR_WDU_2 ((uint32_t)0x00008000) ¸ RTC_TSDR_MT ((uint32_t)0x00001000) ¹ RTC_TSDR_MU ((uint32_t)0x00000F00) º RTC_TSDR_MU_0 ((uint32_t)0x00000100) » RTC_TSDR_MU_1 ((uint32_t)0x00000200) ¼ RTC_TSDR_MU_2 ((uint32_t)0x00000400) ½ RTC_TSDR_MU_3 ((uint32_t)0x00000800) ¾ RTC_TSDR_DT ((uint32_t)0x00000030) ¿ RTC_TSDR_DT_0 ((uint32_t)0x00000010) À RTC_TSDR_DT_1 ((uint32_t)0x00000020) Á RTC_TSDR_DU ((uint32_t)0x0000000F) Â RTC_TSDR_DU_0 ((uint32_t)0x00000001) Ã RTC_TSDR_DU_1 ((uint32_t)0x00000002) Ä RTC_TSDR_DU_2 ((uint32_t)0x00000004) Å RTC_TSDR_DU_3 ((uint32_t)0x00000008) È RTC_TSSSR_SS ((uint32_t)0x0000FFFF) Ë RTC_CALR_CALP ((uint32_t)0x00008000) Ì RTC_CALR_CALW8 ((uint32_t)0x00004000) Í RTC_CALR_CALW16 ((uint32_t)0x00002000) Î RTC_CALR_CALM ((uint32_t)0x000001FF) Ï RTC_CALR_CALM_0 ((uint32_t)0x00000001) Ð RTC_CALR_CALM_1 ((uint32_t)0x00000002) Ñ RTC_CALR_CALM_2 ((uint32_t)0x00000004) Ò RTC_CALR_CALM_3 ((uint32_t)0x00000008) Ó RTC_CALR_CALM_4 ((uint32_t)0x00000010) Ô RTC_CALR_CALM_5 ((uint32_t)0x00000020) Õ RTC_CALR_CALM_6 ((uint32_t)0x00000040) Ö RTC_CALR_CALM_7 ((uint32_t)0x00000080) × RTC_CALR_CALM_8 ((uint32_t)0x00000100) Ú RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) Û RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) Ü RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) Ý RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) Þ RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) ß RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) à RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) á RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) â RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) ã RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) ä RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) å RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) æ RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) ç RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) è RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) é RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) ê RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) ë RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) ì RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) í RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) ð RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) ñ RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) ò RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) ó RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) ô RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) õ RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) ø RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) ù RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) ú RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) û RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) ü RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) ý RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) RTC_BKP0R ((uint32_t)0xFFFFFFFF) RTC_BKP1R ((uint32_t)0xFFFFFFFF) RTC_BKP2R ((uint32_t)0xFFFFFFFF) RTC_BKP3R ((uint32_t)0xFFFFFFFF) RTC_BKP4R ((uint32_t)0xFFFFFFFF) RTC_BKP5R ((uint32_t)0xFFFFFFFF) RTC_BKP6R ((uint32_t)0xFFFFFFFF) RTC_BKP7R ((uint32_t)0xFFFFFFFF) RTC_BKP8R ((uint32_t)0xFFFFFFFF) RTC_BKP9R ((uint32_t)0xFFFFFFFF) RTC_BKP10R ((uint32_t)0xFFFFFFFF) ¡ RTC_BKP11R ((uint32_t)0xFFFFFFFF) ¤ RTC_BKP12R ((uint32_t)0xFFFFFFFF) § RTC_BKP13R ((uint32_t)0xFFFFFFFF) ª RTC_BKP14R ((uint32_t)0xFFFFFFFF) RTC_BKP15R ((uint32_t)0xFFFFFFFF) ° RTC_BKP16R ((uint32_t)0xFFFFFFFF) ³ RTC_BKP17R ((uint32_t)0xFFFFFFFF) ¶ RTC_BKP18R ((uint32_t)0xFFFFFFFF) ¹ RTC_BKP19R ((uint32_t)0xFFFFFFFF) ¼ RTC_BKP20R ((uint32_t)0xFFFFFFFF) ¿ RTC_BKP21R ((uint32_t)0xFFFFFFFF) Â RTC_BKP22R ((uint32_t)0xFFFFFFFF) Å RTC_BKP23R ((uint32_t)0xFFFFFFFF) È RTC_BKP24R ((uint32_t)0xFFFFFFFF) Ë RTC_BKP25R ((uint32_t)0xFFFFFFFF) Î RTC_BKP26R ((uint32_t)0xFFFFFFFF) Ñ RTC_BKP27R ((uint32_t)0xFFFFFFFF) Ô RTC_BKP28R ((uint32_t)0xFFFFFFFF) × RTC_BKP29R ((uint32_t)0xFFFFFFFF) Ú RTC_BKP30R ((uint32_t)0xFFFFFFFF) Ý RTC_BKP31R ((uint32_t)0xFFFFFFFF) æ SDIO_POWER_PWRCTRL ((uint8_t)0x03) ç SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) è SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) ë SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) ì SDIO_CLKCR_CLKEN ((uint16_t)0x0100) í SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) î SDIO_CLKCR_BYPASS ((uint16_t)0x0400) ð SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) ñ SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) ò SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) ô SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) õ SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) ø SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) û SDIO_CMD_CMDINDEX ((uint16_t)0x003F) ý SDIO_CMD_WAITRESP ((uint16_t)0x00C0) þ SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) ÿ SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) !SDIO_CMD_WAITINT ((uint16_t)0x0100) !SDIO_CMD_WAITPEND ((uint16_t)0x0200) !SDIO_CMD_CPSMEN ((uint16_t)0x0400) !SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
!SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) !SDIO_CMD_NIEN ((uint16_t)0x2000) !SDIO_CMD_CEATACMD ((uint16_t)0x4000) !SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) !SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) !SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) !SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) !SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) !SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) !SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) !SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) ¢!SDIO_DCTRL_DTEN ((uint16_t)0x0001) £!SDIO_DCTRL_DTDIR ((uint16_t)0x0002) ¤!SDIO_DCTRL_DTMODE ((uint16_t)0x0004) ¥!SDIO_DCTRL_DMAEN ((uint16_t)0x0008) §!SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) ¨!SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) ©!SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) ª!SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) «!SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) !SDIO_DCTRL_RWSTART ((uint16_t)0x0100) ®!SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) ¯!SDIO_DCTRL_RWMOD ((uint16_t)0x0400) °!SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) ³!SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) ¶!SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) ·!SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) ¸!SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) ¹!SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) º!SDIO_STA_TXUNDERR ((uint32_t)0x00000010) »!SDIO_STA_RXOVERR ((uint32_t)0x00000020) ¼!SDIO_STA_CMDREND ((uint32_t)0x00000040) ½!SDIO_STA_CMDSENT ((uint32_t)0x00000080) ¾!SDIO_STA_DATAEND ((uint32_t)0x00000100) ¿!SDIO_STA_STBITERR ((uint32_t)0x00000200) À!SDIO_STA_DBCKEND ((uint32_t)0x00000400) Á!SDIO_STA_CMDACT ((uint32_t)0x00000800) Â!SDIO_STA_TXACT ((uint32_t)0x00001000) Ã!SDIO_STA_RXACT ((uint32_t)0x00002000) Ä!SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) Å!SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) Æ!SDIO_STA_TXFIFOF ((uint32_t)0x00010000) Ç!SDIO_STA_RXFIFOF ((uint32_t)0x00020000) È!SDIO_STA_TXFIFOE ((uint32_t)0x00040000) É!SDIO_STA_RXFIFOE ((uint32_t)0x00080000) Ê!SDIO_STA_TXDAVL ((uint32_t)0x00100000) Ë!SDIO_STA_RXDAVL ((uint32_t)0x00200000) Ì!SDIO_STA_SDIOIT ((uint32_t)0x00400000) Í!SDIO_STA_CEATAEND ((uint32_t)0x00800000) Ð!SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) Ñ!SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) Ò!SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) Ó!SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) Ô!SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) Õ!SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) Ö!SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) ×!SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) Ø!SDIO_ICR_DATAENDC ((uint32_t)0x00000100) Ù!SDIO_ICR_STBITERRC ((uint32_t)0x00000200) Ú!SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) Û!SDIO_ICR_SDIOITC ((uint32_t)0x00400000) Ü!SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) ß!SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) à!SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) á!SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) â!SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) ã!SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) ä!SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) å!SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) æ!SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) ç!SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) è!SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) é!SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) ê!SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) ë!SDIO_MASK_TXACTIE ((uint32_t)0x00001000) ì!SDIO_MASK_RXACTIE ((uint32_t)0x00002000) í!SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) î!SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) ï!SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) ð!SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) ñ!SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) ò!SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) ó!SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) ô!SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) õ!SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) ö!SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) ù!SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) ü!SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
"SPI_CR1_CPHA ((uint16_t)0x0001) "SPI_CR1_CPOL ((uint16_t)0x0002) "SPI_CR1_MSTR ((uint16_t)0x0004) "SPI_CR1_BR ((uint16_t)0x0038) "SPI_CR1_BR_0 ((uint16_t)0x0008) "SPI_CR1_BR_1 ((uint16_t)0x0010) "SPI_CR1_BR_2 ((uint16_t)0x0020) "SPI_CR1_SPE ((uint16_t)0x0040) "SPI_CR1_LSBFIRST ((uint16_t)0x0080) "SPI_CR1_SSI ((uint16_t)0x0100) "SPI_CR1_SSM ((uint16_t)0x0200) "SPI_CR1_RXONLY ((uint16_t)0x0400) "SPI_CR1_DFF ((uint16_t)0x0800) "SPI_CR1_CRCNEXT ((uint16_t)0x1000) "SPI_CR1_CRCEN ((uint16_t)0x2000) "SPI_CR1_BIDIOE ((uint16_t)0x4000) "SPI_CR1_BIDIMODE ((uint16_t)0x8000) "SPI_CR2_RXDMAEN ((uint8_t)0x01) "SPI_CR2_TXDMAEN ((uint8_t)0x02) "SPI_CR2_SSOE ((uint8_t)0x04) "SPI_CR2_FRF ((uint8_t)0x08) "SPI_CR2_ERRIE ((uint8_t)0x20) "SPI_CR2_RXNEIE ((uint8_t)0x40) "SPI_CR2_TXEIE ((uint8_t)0x80) £"SPI_SR_RXNE ((uint8_t)0x01) ¤"SPI_SR_TXE ((uint8_t)0x02) ¥"SPI_SR_CHSIDE ((uint8_t)0x04) ¦"SPI_SR_UDR ((uint8_t)0x08) §"SPI_SR_CRCERR ((uint8_t)0x10) ¨"SPI_SR_MODF ((uint8_t)0x20) ©"SPI_SR_OVR ((uint8_t)0x40) ª"SPI_SR_BSY ((uint8_t)0x80) "SPI_DR_DR ((uint16_t)0xFFFF) °"SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) ³"SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) ¶"SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) ¹"SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) »"SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) ¼"SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) ½"SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) ¿"SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) Á"SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) Â"SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) Ã"SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) Å"SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) Ç"SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) È"SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) É"SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) Ë"SPI_I2SCFGR_I2SE ((uint16_t)0x0400) Ì"SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) Ï"SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) Ð"SPI_I2SPR_ODD ((uint16_t)0x0100) Ñ"SPI_I2SPR_MCKOE ((uint16_t)0x0200) Ù"SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) Ú"SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) Û"SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) Ü"SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) Ý"SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) Þ"SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) á"SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) ä"SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) å"SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) æ"SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) ç"SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) ì"SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) í"SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) î"SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) ï"SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) ð"SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) ñ"SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) ò"SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) ó"SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) ø"SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) ù"SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) ú"SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) û"SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) ü"SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) ý"SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) þ"SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) ÿ"SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) #SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
#SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) #SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) #SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) #SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) #SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) #SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) #SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) #SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) #SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) #SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) #SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) #SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) #SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) #SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) #SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) #SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) #SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) #SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) ¡#SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) ¢#SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) £#SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) ¤#SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) ¥#SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) ¦#SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) §#SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) ¬#SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) #SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) ®#SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) ¯#SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) °#SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) ±#SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) ²#SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) ·#SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) ¸#SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) ¹#SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) º#SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) »#SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) ¼#SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) ½#SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) Â#SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) Ã#SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) Ä#SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) Å#SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) Æ#SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) Ç#SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) È#SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) Ë#SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) Ì#SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) Í#SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) Î#SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) Ó#SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) Ô#SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) Õ#SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) Ö#SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) ×#SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) Ø#SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) Ù#SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) Þ#SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) ß#SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) à#SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) á#SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) â#SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) ã#SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) ä#SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) é#SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) ê#SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) ë#SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) ì#SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) í#SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) î#SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) ï#SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) ô#SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) õ#SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) ö#SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) ÷#SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) ø#SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) ù#SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) ú#SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) ý#SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) þ#SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) ÿ#SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) $SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)
$SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) $SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) $SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) $SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) $SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) $SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) $SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) $SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) $SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) $SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) $SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) $SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) $SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) $SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) $SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) $SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) $SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) $SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) $SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) $SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) ¡$SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) ¦$SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) §$SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) ¨$SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) ©$SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) ª$SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) «$SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) ¬$SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) µ$RI_ICR_IC1Z ((uint32_t)0x0000000F) ¶$RI_ICR_IC1Z_0 ((uint32_t)0x00000001) ·$RI_ICR_IC1Z_1 ((uint32_t)0x00000002) ¸$RI_ICR_IC1Z_2 ((uint32_t)0x00000004) ¹$RI_ICR_IC1Z_3 ((uint32_t)0x00000008) »$RI_ICR_IC2Z ((uint32_t)0x000000F0) ¼$RI_ICR_IC2Z_0 ((uint32_t)0x00000010) ½$RI_ICR_IC2Z_1 ((uint32_t)0x00000020) ¾$RI_ICR_IC2Z_2 ((uint32_t)0x00000040) ¿$RI_ICR_IC2Z_3 ((uint32_t)0x00000080) Á$RI_ICR_IC3Z ((uint32_t)0x00000F00) Â$RI_ICR_IC3Z_0 ((uint32_t)0x00000100) Ã$RI_ICR_IC3Z_1 ((uint32_t)0x00000200) Ä$RI_ICR_IC3Z_2 ((uint32_t)0x00000400) Å$RI_ICR_IC3Z_3 ((uint32_t)0x00000800) Ç$RI_ICR_IC4Z ((uint32_t)0x0000F000) È$RI_ICR_IC4Z_0 ((uint32_t)0x00001000) É$RI_ICR_IC4Z_1 ((uint32_t)0x00002000) Ê$RI_ICR_IC4Z_2 ((uint32_t)0x00004000) Ë$RI_ICR_IC4Z_3 ((uint32_t)0x00008000) Í$RI_ICR_TIM ((uint32_t)0x00030000) Î$RI_ICR_TIM_0 ((uint32_t)0x00010000) Ï$RI_ICR_TIM_1 ((uint32_t)0x00020000) Ñ$RI_ICR_IC1 ((uint32_t)0x00040000) Ò$RI_ICR_IC2 ((uint32_t)0x00080000) Ó$RI_ICR_IC3 ((uint32_t)0x00100000) Ô$RI_ICR_IC4 ((uint32_t)0x00200000) ×$RI_ASCR1_CH ((uint32_t)0x03FCFFFF) Ø$RI_ASCR1_CH_0 ((uint32_t)0x00000001) Ù$RI_ASCR1_CH_1 ((uint32_t)0x00000002) Ú$RI_ASCR1_CH_2 ((uint32_t)0x00000004) Û$RI_ASCR1_CH_3 ((uint32_t)0x00000008) Ü$RI_ASCR1_CH_4 ((uint32_t)0x00000010) Ý$RI_ASCR1_CH_5 ((uint32_t)0x00000020) Þ$RI_ASCR1_CH_6 ((uint32_t)0x00000040) ß$RI_ASCR1_CH_7 ((uint32_t)0x00000080) à$RI_ASCR1_CH_8 ((uint32_t)0x00000100) á$RI_ASCR1_CH_9 ((uint32_t)0x00000200) â$RI_ASCR1_CH_10 ((uint32_t)0x00000400) ã$RI_ASCR1_CH_11 ((uint32_t)0x00000800) ä$RI_ASCR1_CH_12 ((uint32_t)0x00001000) å$RI_ASCR1_CH_13 ((uint32_t)0x00002000) æ$RI_ASCR1_CH_14 ((uint32_t)0x00004000) ç$RI_ASCR1_CH_15 ((uint32_t)0x00008000) è$RI_ASCR1_CH_31 ((uint32_t)0x00010000) é$RI_ASCR1_CH_18 ((uint32_t)0x00040000) ê$RI_ASCR1_CH_19 ((uint32_t)0x00080000) ë$RI_ASCR1_CH_20 ((uint32_t)0x00100000) ì$RI_ASCR1_CH_21 ((uint32_t)0x00200000) í$RI_ASCR1_CH_22 ((uint32_t)0x00400000) î$RI_ASCR1_CH_23 ((uint32_t)0x00800000) ï$RI_ASCR1_CH_24 ((uint32_t)0x01000000) ð$RI_ASCR1_CH_25 ((uint32_t)0x02000000) ñ$RI_ASCR1_VCOMP ((uint32_t)0x04000000) ò$RI_ASCR1_CH_27 ((uint32_t)0x00400000) ó$RI_ASCR1_CH_28 ((uint32_t)0x00800000) ô$RI_ASCR1_CH_29 ((uint32_t)0x01000000) õ$RI_ASCR1_CH_30 ((uint32_t)0x02000000) ö$RI_ASCR1_SCM ((uint32_t)0x80000000) ù$RI_ASCR2_GR10_1 ((uint32_t)0x00000001) ú$RI_ASCR2_GR10_2 ((uint32_t)0x00000002) û$RI_ASCR2_GR10_3 ((uint32_t)0x00000004) ü$RI_ASCR2_GR10_4 ((uint32_t)0x00000008) ý$RI_ASCR2_GR6_1 ((uint32_t)0x00000010) þ$RI_ASCR2_GR6_2 ((uint32_t)0x00000020) ÿ$RI_ASCR2_GR5_1 ((uint32_t)0x00000040) %RI_ASCR2_GR5_2 ((uint32_t)0x00000080) %RI_ASCR2_GR5_3 ((uint32_t)0x00000100) %RI_ASCR2_GR4_1 ((uint32_t)0x00000200) %RI_ASCR2_GR4_2 ((uint32_t)0x00000400) %RI_ASCR2_GR4_3 ((uint32_t)0x00000800)
%RI_ASCR2_GR4_4 ((uint32_t)0x00008000) %RI_ASCR2_CH0b ((uint32_t)0x00010000) %RI_ASCR2_CH1b ((uint32_t)0x00020000) %RI_ASCR2_CH2b ((uint32_t)0x00040000) %RI_ASCR2_CH3b ((uint32_t)0x00080000) %RI_ASCR2_CH6b ((uint32_t)0x00100000) %RI_ASCR2_CH7b ((uint32_t)0x00200000) %RI_ASCR2_CH8b ((uint32_t)0x00400000) %RI_ASCR2_CH9b ((uint32_t)0x00800000) %RI_ASCR2_CH10b ((uint32_t)0x01000000) %RI_ASCR2_CH11b ((uint32_t)0x02000000) %RI_ASCR2_CH12b ((uint32_t)0x04000000) %RI_ASCR2_GR6_3 ((uint32_t)0x08000000) %RI_ASCR2_GR6_4 ((uint32_t)0x10000000) %RI_ASCR2_GR5_4 ((uint32_t)0x20000000) %RI_HYSCR1_PA ((uint32_t)0x0000FFFF) %RI_HYSCR1_PA_0 ((uint32_t)0x00000001) %RI_HYSCR1_PA_1 ((uint32_t)0x00000002) %RI_HYSCR1_PA_2 ((uint32_t)0x00000004) %RI_HYSCR1_PA_3 ((uint32_t)0x00000008) %RI_HYSCR1_PA_4 ((uint32_t)0x00000010) %RI_HYSCR1_PA_5 ((uint32_t)0x00000020) %RI_HYSCR1_PA_6 ((uint32_t)0x00000040) %RI_HYSCR1_PA_7 ((uint32_t)0x00000080) %RI_HYSCR1_PA_8 ((uint32_t)0x00000100) %RI_HYSCR1_PA_9 ((uint32_t)0x00000200) ¡%RI_HYSCR1_PA_10 ((uint32_t)0x00000400) ¢%RI_HYSCR1_PA_11 ((uint32_t)0x00000800) £%RI_HYSCR1_PA_12 ((uint32_t)0x00001000) ¤%RI_HYSCR1_PA_13 ((uint32_t)0x00002000) ¥%RI_HYSCR1_PA_14 ((uint32_t)0x00004000) ¦%RI_HYSCR1_PA_15 ((uint32_t)0x00008000) ¨%RI_HYSCR1_PB ((uint32_t)0xFFFF0000) ©%RI_HYSCR1_PB_0 ((uint32_t)0x00010000) ª%RI_HYSCR1_PB_1 ((uint32_t)0x00020000) «%RI_HYSCR1_PB_2 ((uint32_t)0x00040000) ¬%RI_HYSCR1_PB_3 ((uint32_t)0x00080000) %RI_HYSCR1_PB_4 ((uint32_t)0x00100000) ®%RI_HYSCR1_PB_5 ((uint32_t)0x00200000) ¯%RI_HYSCR1_PB_6 ((uint32_t)0x00400000) °%RI_HYSCR1_PB_7 ((uint32_t)0x00800000) ±%RI_HYSCR1_PB_8 ((uint32_t)0x01000000) ²%RI_HYSCR1_PB_9 ((uint32_t)0x02000000) ³%RI_HYSCR1_PB_10 ((uint32_t)0x04000000) ´%RI_HYSCR1_PB_11 ((uint32_t)0x08000000) µ%RI_HYSCR1_PB_12 ((uint32_t)0x10000000) ¶%RI_HYSCR1_PB_13 ((uint32_t)0x20000000) ·%RI_HYSCR1_PB_14 ((uint32_t)0x40000000) ¸%RI_HYSCR1_PB_15 ((uint32_t)0x80000000) »%RI_HYSCR2_PC ((uint32_t)0x0000FFFF) ¼%RI_HYSCR2_PC_0 ((uint32_t)0x00000001) ½%RI_HYSCR2_PC_1 ((uint32_t)0x00000002) ¾%RI_HYSCR2_PC_2 ((uint32_t)0x00000004) ¿%RI_HYSCR2_PC_3 ((uint32_t)0x00000008) À%RI_HYSCR2_PC_4 ((uint32_t)0x00000010) Á%RI_HYSCR2_PC_5 ((uint32_t)0x00000020) Â%RI_HYSCR2_PC_6 ((uint32_t)0x00000040) Ã%RI_HYSCR2_PC_7 ((uint32_t)0x00000080) Ä%RI_HYSCR2_PC_8 ((uint32_t)0x00000100) Å%RI_HYSCR2_PC_9 ((uint32_t)0x00000200) Æ%RI_HYSCR2_PC_10 ((uint32_t)0x00000400) Ç%RI_HYSCR2_PC_11 ((uint32_t)0x00000800) È%RI_HYSCR2_PC_12 ((uint32_t)0x00001000) É%RI_HYSCR2_PC_13 ((uint32_t)0x00002000) Ê%RI_HYSCR2_PC_14 ((uint32_t)0x00004000) Ë%RI_HYSCR2_PC_15 ((uint32_t)0x00008000) Í%RI_HYSCR2_PD ((uint32_t)0xFFFF0000) Î%RI_HYSCR2_PD_0 ((uint32_t)0x00010000) Ï%RI_HYSCR2_PD_1 ((uint32_t)0x00020000) Ð%RI_HYSCR2_PD_2 ((uint32_t)0x00040000) Ñ%RI_HYSCR2_PD_3 ((uint32_t)0x00080000) Ò%RI_HYSCR2_PD_4 ((uint32_t)0x00100000) Ó%RI_HYSCR2_PD_5 ((uint32_t)0x00200000) Ô%RI_HYSCR2_PD_6 ((uint32_t)0x00400000) Õ%RI_HYSCR2_PD_7 ((uint32_t)0x00800000) Ö%RI_HYSCR2_PD_8 ((uint32_t)0x01000000) ×%RI_HYSCR2_PD_9 ((uint32_t)0x02000000) Ø%RI_HYSCR2_PD_10 ((uint32_t)0x04000000) Ù%RI_HYSCR2_PD_11 ((uint32_t)0x08000000) Ú%RI_HYSCR2_PD_12 ((uint32_t)0x10000000) Û%RI_HYSCR2_PD_13 ((uint32_t)0x20000000) Ü%RI_HYSCR2_PD_14 ((uint32_t)0x40000000) Ý%RI_HYSCR2_PD_15 ((uint32_t)0x80000000) à%RI_HYSCR2_PE ((uint32_t)0x0000FFFF) á%RI_HYSCR2_PE_0 ((uint32_t)0x00000001) â%RI_HYSCR2_PE_1 ((uint32_t)0x00000002) ã%RI_HYSCR2_PE_2 ((uint32_t)0x00000004) ä%RI_HYSCR2_PE_3 ((uint32_t)0x00000008) å%RI_HYSCR2_PE_4 ((uint32_t)0x00000010) æ%RI_HYSCR2_PE_5 ((uint32_t)0x00000020) ç%RI_HYSCR2_PE_6 ((uint32_t)0x00000040) è%RI_HYSCR2_PE_7 ((uint32_t)0x00000080) é%RI_HYSCR2_PE_8 ((uint32_t)0x00000100) ê%RI_HYSCR2_PE_9 ((uint32_t)0x00000200) ë%RI_HYSCR2_PE_10 ((uint32_t)0x00000400) ì%RI_HYSCR2_PE_11 ((uint32_t)0x00000800) í%RI_HYSCR2_PE_12 ((uint32_t)0x00001000) î%RI_HYSCR2_PE_13 ((uint32_t)0x00002000) ï%RI_HYSCR2_PE_14 ((uint32_t)0x00004000) ð%RI_HYSCR2_PE_15 ((uint32_t)0x00008000) ò%RI_HYSCR3_PF ((uint32_t)0xFFFF0000) ó%RI_HYSCR3_PF_0 ((uint32_t)0x00010000) ô%RI_HYSCR3_PF_1 ((uint32_t)0x00020000) õ%RI_HYSCR3_PF_2 ((uint32_t)0x00040000) ö%RI_HYSCR3_PF_3 ((uint32_t)0x00080000) ÷%RI_HYSCR3_PF_4 ((uint32_t)0x00100000) ø%RI_HYSCR3_PF_5 ((uint32_t)0x00200000) ù%RI_HYSCR3_PF_6 ((uint32_t)0x00400000) ú%RI_HYSCR3_PF_7 ((uint32_t)0x00800000) û%RI_HYSCR3_PF_8 ((uint32_t)0x01000000) ü%RI_HYSCR3_PF_9 ((uint32_t)0x02000000) ý%RI_HYSCR3_PF_10 ((uint32_t)0x04000000) þ%RI_HYSCR3_PF_11 ((uint32_t)0x08000000) ÿ%RI_HYSCR3_PF_12 ((uint32_t)0x10000000) &RI_HYSCR3_PF_13 ((uint32_t)0x20000000) &RI_HYSCR3_PF_14 ((uint32_t)0x40000000) &RI_HYSCR3_PF_15 ((uint32_t)0x80000000)
&RI_HYSCR4_PG ((uint32_t)0x0000FFFF) &RI_HYSCR4_PG_0 ((uint32_t)0x00000001) &RI_HYSCR4_PG_1 ((uint32_t)0x00000002) &RI_HYSCR4_PG_2 ((uint32_t)0x00000004) &RI_HYSCR4_PG_3 ((uint32_t)0x00000008) &RI_HYSCR4_PG_4 ((uint32_t)0x00000010) &RI_HYSCR4_PG_5 ((uint32_t)0x00000020) &RI_HYSCR4_PG_6 ((uint32_t)0x00000040) &RI_HYSCR4_PG_7 ((uint32_t)0x00000080) &RI_HYSCR4_PG_8 ((uint32_t)0x00000100) &RI_HYSCR4_PG_9 ((uint32_t)0x00000200) &RI_HYSCR4_PG_10 ((uint32_t)0x00000400) &RI_HYSCR4_PG_11 ((uint32_t)0x00000800) &RI_HYSCR4_PG_12 ((uint32_t)0x00001000) &RI_HYSCR4_PG_13 ((uint32_t)0x00002000) &RI_HYSCR4_PG_14 ((uint32_t)0x00004000) &RI_HYSCR4_PG_15 ((uint32_t)0x00008000) &TIM_CR1_CEN ((uint16_t)0x0001) &TIM_CR1_UDIS ((uint16_t)0x0002) &TIM_CR1_URS ((uint16_t)0x0004) ¡&TIM_CR1_OPM ((uint16_t)0x0008) ¢&TIM_CR1_DIR ((uint16_t)0x0010) ¤&TIM_CR1_CMS ((uint16_t)0x0060) ¥&TIM_CR1_CMS_0 ((uint16_t)0x0020) ¦&TIM_CR1_CMS_1 ((uint16_t)0x0040) ¨&TIM_CR1_ARPE ((uint16_t)0x0080) ª&TIM_CR1_CKD ((uint16_t)0x0300) «&TIM_CR1_CKD_0 ((uint16_t)0x0100) ¬&TIM_CR1_CKD_1 ((uint16_t)0x0200) ¯&TIM_CR2_CCDS ((uint16_t)0x0008) ±&TIM_CR2_MMS ((uint16_t)0x0070) ²&TIM_CR2_MMS_0 ((uint16_t)0x0010) ³&TIM_CR2_MMS_1 ((uint16_t)0x0020) ´&TIM_CR2_MMS_2 ((uint16_t)0x0040) ¶&TIM_CR2_TI1S ((uint16_t)0x0080) ¹&TIM_SMCR_SMS ((uint16_t)0x0007) º&TIM_SMCR_SMS_0 ((uint16_t)0x0001) »&TIM_SMCR_SMS_1 ((uint16_t)0x0002) ¼&TIM_SMCR_SMS_2 ((uint16_t)0x0004) ¾&TIM_SMCR_OCCS ((uint16_t)0x0008) À&TIM_SMCR_TS ((uint16_t)0x0070) Á&TIM_SMCR_TS_0 ((uint16_t)0x0010) Â&TIM_SMCR_TS_1 ((uint16_t)0x0020) Ã&TIM_SMCR_TS_2 ((uint16_t)0x0040) Å&TIM_SMCR_MSM ((uint16_t)0x0080) Ç&TIM_SMCR_ETF ((uint16_t)0x0F00) È&TIM_SMCR_ETF_0 ((uint16_t)0x0100) É&TIM_SMCR_ETF_1 ((uint16_t)0x0200) Ê&TIM_SMCR_ETF_2 ((uint16_t)0x0400) Ë&TIM_SMCR_ETF_3 ((uint16_t)0x0800) Í&TIM_SMCR_ETPS ((uint16_t)0x3000) Î&TIM_SMCR_ETPS_0 ((uint16_t)0x1000) Ï&TIM_SMCR_ETPS_1 ((uint16_t)0x2000) Ñ&TIM_SMCR_ECE ((uint16_t)0x4000) Ò&TIM_SMCR_ETP ((uint16_t)0x8000) Õ&TIM_DIER_UIE ((uint16_t)0x0001) Ö&TIM_DIER_CC1IE ((uint16_t)0x0002) ×&TIM_DIER_CC2IE ((uint16_t)0x0004) Ø&TIM_DIER_CC3IE ((uint16_t)0x0008) Ù&TIM_DIER_CC4IE ((uint16_t)0x0010) Ú&TIM_DIER_TIE ((uint16_t)0x0040) Û&TIM_DIER_UDE ((uint16_t)0x0100) Ü&TIM_DIER_CC1DE ((uint16_t)0x0200) Ý&TIM_DIER_CC2DE ((uint16_t)0x0400) Þ&TIM_DIER_CC3DE ((uint16_t)0x0800) ß&TIM_DIER_CC4DE ((uint16_t)0x1000) à&TIM_DIER_TDE ((uint16_t)0x4000) ã&TIM_SR_UIF ((uint16_t)0x0001) ä&TIM_SR_CC1IF ((uint16_t)0x0002) å&TIM_SR_CC2IF ((uint16_t)0x0004) æ&TIM_SR_CC3IF ((uint16_t)0x0008) ç&TIM_SR_CC4IF ((uint16_t)0x0010) è&TIM_SR_TIF ((uint16_t)0x0040) é&TIM_SR_CC1OF ((uint16_t)0x0200) ê&TIM_SR_CC2OF ((uint16_t)0x0400) ë&TIM_SR_CC3OF ((uint16_t)0x0800) ì&TIM_SR_CC4OF ((uint16_t)0x1000) ï&TIM_EGR_UG ((uint8_t)0x01) ð&TIM_EGR_CC1G ((uint8_t)0x02) ñ&TIM_EGR_CC2G ((uint8_t)0x04) ò&TIM_EGR_CC3G ((uint8_t)0x08) ó&TIM_EGR_CC4G ((uint8_t)0x10) ô&TIM_EGR_TG ((uint8_t)0x40) ÷&TIM_CCMR1_CC1S ((uint16_t)0x0003) ø&TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) ù&TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) û&TIM_CCMR1_OC1FE ((uint16_t)0x0004) ü&TIM_CCMR1_OC1PE ((uint16_t)0x0008) þ&TIM_CCMR1_OC1M ((uint16_t)0x0070) ÿ&TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 'TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 'TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 'TIM_CCMR1_OC1CE ((uint16_t)0x0080)
'TIM_CCMR1_CC2S ((uint16_t)0x0300) 'TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 'TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 'TIM_CCMR1_OC2FE ((uint16_t)0x0400) 'TIM_CCMR1_OC2PE ((uint16_t)0x0800) 'TIM_CCMR1_OC2M ((uint16_t)0x7000) 'TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 'TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 'TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 'TIM_CCMR1_OC2CE ((uint16_t)0x8000) 'TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 'TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 'TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 'TIM_CCMR1_IC1F ((uint16_t)0x00F0) 'TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 'TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 'TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 'TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 'TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 'TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) ¡'TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) £'TIM_CCMR1_IC2F ((uint16_t)0xF000) ¤'TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) ¥'TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) ¦'TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) §'TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) ª'TIM_CCMR2_CC3S ((uint16_t)0x0003) «'TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) ¬'TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) ®'TIM_CCMR2_OC3FE ((uint16_t)0x0004) ¯'TIM_CCMR2_OC3PE ((uint16_t)0x0008) ±'TIM_CCMR2_OC3M ((uint16_t)0x0070) ²'TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) ³'TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) ´'TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) ¶'TIM_CCMR2_OC3CE ((uint16_t)0x0080) ¸'TIM_CCMR2_CC4S ((uint16_t)0x0300) ¹'TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) º'TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) ¼'TIM_CCMR2_OC4FE ((uint16_t)0x0400) ½'TIM_CCMR2_OC4PE ((uint16_t)0x0800) ¿'TIM_CCMR2_OC4M ((uint16_t)0x7000) À'TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) Á'TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) Â'TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) Ä'TIM_CCMR2_OC4CE ((uint16_t)0x8000) È'TIM_CCMR2_IC3PSC ((uint16_t)0x000C) É'TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) Ê'TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) Ì'TIM_CCMR2_IC3F ((uint16_t)0x00F0) Í'TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) Î'TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) Ï'TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) Ð'TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) Ò'TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) Ó'TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) Ô'TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) Ö'TIM_CCMR2_IC4F ((uint16_t)0xF000) ×'TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) Ø'TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) Ù'TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) Ú'TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) Ý'TIM_CCER_CC1E ((uint16_t)0x0001) Þ'TIM_CCER_CC1P ((uint16_t)0x0002) ß'TIM_CCER_CC1NP ((uint16_t)0x0008) à'TIM_CCER_CC2E ((uint16_t)0x0010) á'TIM_CCER_CC2P ((uint16_t)0x0020) â'TIM_CCER_CC2NP ((uint16_t)0x0080) ã'TIM_CCER_CC3E ((uint16_t)0x0100) ä'TIM_CCER_CC3P ((uint16_t)0x0200) å'TIM_CCER_CC3NP ((uint16_t)0x0800) æ'TIM_CCER_CC4E ((uint16_t)0x1000) ç'TIM_CCER_CC4P ((uint16_t)0x2000) è'TIM_CCER_CC4NP ((uint16_t)0x8000) ë'TIM_CNT_CNT ((uint16_t)0xFFFF) î'TIM_PSC_PSC ((uint16_t)0xFFFF) ñ'TIM_ARR_ARR ((uint16_t)0xFFFF) ô'TIM_CCR1_CCR1 ((uint16_t)0xFFFF) ÷'TIM_CCR2_CCR2 ((uint16_t)0xFFFF) ú'TIM_CCR3_CCR3 ((uint16_t)0xFFFF) ý'TIM_CCR4_CCR4 ((uint16_t)0xFFFF) (TIM_DCR_DBA ((uint16_t)0x001F) (TIM_DCR_DBA_0 ((uint16_t)0x0001) (TIM_DCR_DBA_1 ((uint16_t)0x0002) (TIM_DCR_DBA_2 ((uint16_t)0x0004) (TIM_DCR_DBA_3 ((uint16_t)0x0008)
(TIM_DCR_DBA_4 ((uint16_t)0x0010) (TIM_DCR_DBL ((uint16_t)0x1F00) (TIM_DCR_DBL_0 ((uint16_t)0x0100) (TIM_DCR_DBL_1 ((uint16_t)0x0200) (TIM_DCR_DBL_2 ((uint16_t)0x0400) (TIM_DCR_DBL_3 ((uint16_t)0x0800) (TIM_DCR_DBL_4 ((uint16_t)0x1000) (TIM_DMAR_DMAB ((uint16_t)0xFFFF) (TIM_OR_TI1RMP ((uint16_t)0x0003) (TIM_OR_TI1RMP_0 ((uint16_t)0x0001) (TIM_OR_TI1RMP_1 ((uint16_t)0x0002) (USART_SR_PE ((uint16_t)0x0001) (USART_SR_FE ((uint16_t)0x0002) (USART_SR_NE ((uint16_t)0x0004) (USART_SR_ORE ((uint16_t)0x0008) ¡(USART_SR_IDLE ((uint16_t)0x0010) ¢(USART_SR_RXNE ((uint16_t)0x0020) £(USART_SR_TC ((uint16_t)0x0040) ¤(USART_SR_TXE ((uint16_t)0x0080) ¥(USART_SR_LBD ((uint16_t)0x0100) ¦(USART_SR_CTS ((uint16_t)0x0200) ©(USART_DR_DR ((uint16_t)0x01FF) ¬(USART_BRR_DIV_FRACTION ((uint16_t)0x000F) (USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) °(USART_CR1_SBK ((uint16_t)0x0001) ±(USART_CR1_RWU ((uint16_t)0x0002) ²(USART_CR1_RE ((uint16_t)0x0004) ³(USART_CR1_TE ((uint16_t)0x0008) ´(USART_CR1_IDLEIE ((uint16_t)0x0010) µ(USART_CR1_RXNEIE ((uint16_t)0x0020) ¶(USART_CR1_TCIE ((uint16_t)0x0040) ·(USART_CR1_TXEIE ((uint16_t)0x0080) ¸(USART_CR1_PEIE ((uint16_t)0x0100) ¹(USART_CR1_PS ((uint16_t)0x0200) º(USART_CR1_PCE ((uint16_t)0x0400) »(USART_CR1_WAKE ((uint16_t)0x0800) ¼(USART_CR1_M ((uint16_t)0x1000) ½(USART_CR1_UE ((uint16_t)0x2000) ¾(USART_CR1_OVER8 ((uint16_t)0x8000) Á(USART_CR2_ADD ((uint16_t)0x000F) Â(USART_CR2_LBDL ((uint16_t)0x0020) Ã(USART_CR2_LBDIE ((uint16_t)0x0040) Ä(USART_CR2_LBCL ((uint16_t)0x0100) Å(USART_CR2_CPHA ((uint16_t)0x0200) Æ(USART_CR2_CPOL ((uint16_t)0x0400) Ç(USART_CR2_CLKEN ((uint16_t)0x0800) É(USART_CR2_STOP ((uint16_t)0x3000) Ê(USART_CR2_STOP_0 ((uint16_t)0x1000) Ë(USART_CR2_STOP_1 ((uint16_t)0x2000) Í(USART_CR2_LINEN ((uint16_t)0x4000) Ð(USART_CR3_EIE ((uint16_t)0x0001) Ñ(USART_CR3_IREN ((uint16_t)0x0002) Ò(USART_CR3_IRLP ((uint16_t)0x0004) Ó(USART_CR3_HDSEL ((uint16_t)0x0008) Ô(USART_CR3_NACK ((uint16_t)0x0010) Õ(USART_CR3_SCEN ((uint16_t)0x0020) Ö(USART_CR3_DMAR ((uint16_t)0x0040) ×(USART_CR3_DMAT ((uint16_t)0x0080) Ø(USART_CR3_RTSE ((uint16_t)0x0100) Ù(USART_CR3_CTSE ((uint16_t)0x0200) Ú(USART_CR3_CTSIE ((uint16_t)0x0400) Û(USART_CR3_ONEBIT ((uint16_t)0x0800) Þ(USART_GTPR_PSC ((uint16_t)0x00FF) ß(USART_GTPR_PSC_0 ((uint16_t)0x0001) à(USART_GTPR_PSC_1 ((uint16_t)0x0002) á(USART_GTPR_PSC_2 ((uint16_t)0x0004) â(USART_GTPR_PSC_3 ((uint16_t)0x0008) ã(USART_GTPR_PSC_4 ((uint16_t)0x0010) ä(USART_GTPR_PSC_5 ((uint16_t)0x0020) å(USART_GTPR_PSC_6 ((uint16_t)0x0040) æ(USART_GTPR_PSC_7 ((uint16_t)0x0080) è(USART_GTPR_GT ((uint16_t)0xFF00) ò(USB_EP0R_EA ((uint16_t)0x000F) ô(USB_EP0R_STAT_TX ((uint16_t)0x0030) õ(USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) ö(USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) ø(USB_EP0R_DTOG_TX ((uint16_t)0x0040) ù(USB_EP0R_CTR_TX ((uint16_t)0x0080) ú(USB_EP0R_EP_KIND ((uint16_t)0x0100) ü(USB_EP0R_EP_TYPE ((uint16_t)0x0600) ý(USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) þ(USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) )USB_EP0R_SETUP ((uint16_t)0x0800) )USB_EP0R_STAT_RX ((uint16_t)0x3000) )USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) )USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) )USB_EP0R_DTOG_RX ((uint16_t)0x4000) )USB_EP0R_CTR_RX ((uint16_t)0x8000) )USB_EP1R_EA ((uint16_t)0x000F) )USB_EP1R_STAT_TX ((uint16_t)0x0030) )USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) )USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) )USB_EP1R_DTOG_TX ((uint16_t)0x0040) )USB_EP1R_CTR_TX ((uint16_t)0x0080) )USB_EP1R_EP_KIND ((uint16_t)0x0100) )USB_EP1R_EP_TYPE ((uint16_t)0x0600) )USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) )USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) )USB_EP1R_SETUP ((uint16_t)0x0800) )USB_EP1R_STAT_RX ((uint16_t)0x3000) )USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) )USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) )USB_EP1R_DTOG_RX ((uint16_t)0x4000) )USB_EP1R_CTR_RX ((uint16_t)0x8000) ¢)USB_EP2R_EA ((uint16_t)0x000F) ¤)USB_EP2R_STAT_TX ((uint16_t)0x0030) ¥)USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) ¦)USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) ¨)USB_EP2R_DTOG_TX ((uint16_t)0x0040) ©)USB_EP2R_CTR_TX ((uint16_t)0x0080) ª)USB_EP2R_EP_KIND ((uint16_t)0x0100) ¬)USB_EP2R_EP_TYPE ((uint16_t)0x0600) )USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) ®)USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) °)USB_EP2R_SETUP ((uint16_t)0x0800) ²)USB_EP2R_STAT_RX ((uint16_t)0x3000) ³)USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) ´)USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) ¶)USB_EP2R_DTOG_RX ((uint16_t)0x4000) ·)USB_EP2R_CTR_RX ((uint16_t)0x8000) º)USB_EP3R_EA ((uint16_t)0x000F) ¼)USB_EP3R_STAT_TX ((uint16_t)0x0030) ½)USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) ¾)USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) À)USB_EP3R_DTOG_TX ((uint16_t)0x0040) Á)USB_EP3R_CTR_TX ((uint16_t)0x0080) Â)USB_EP3R_EP_KIND ((uint16_t)0x0100) Ä)USB_EP3R_EP_TYPE ((uint16_t)0x0600) Å)USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) Æ)USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) È)USB_EP3R_SETUP ((uint16_t)0x0800) Ê)USB_EP3R_STAT_RX ((uint16_t)0x3000) Ë)USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) Ì)USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) Î)USB_EP3R_DTOG_RX ((uint16_t)0x4000) Ï)USB_EP3R_CTR_RX ((uint16_t)0x8000) Ò)USB_EP4R_EA ((uint16_t)0x000F) Ô)USB_EP4R_STAT_TX ((uint16_t)0x0030) Õ)USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) Ö)USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) Ø)USB_EP4R_DTOG_TX ((uint16_t)0x0040) Ù)USB_EP4R_CTR_TX ((uint16_t)0x0080) Ú)USB_EP4R_EP_KIND ((uint16_t)0x0100) Ü)USB_EP4R_EP_TYPE ((uint16_t)0x0600) Ý)USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) Þ)USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) à)USB_EP4R_SETUP ((uint16_t)0x0800) â)USB_EP4R_STAT_RX ((uint16_t)0x3000) ã)USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) ä)USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) æ)USB_EP4R_DTOG_RX ((uint16_t)0x4000) ç)USB_EP4R_CTR_RX ((uint16_t)0x8000) ê)USB_EP5R_EA ((uint16_t)0x000F) ì)USB_EP5R_STAT_TX ((uint16_t)0x0030) í)USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) î)USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) ð)USB_EP5R_DTOG_TX ((uint16_t)0x0040) ñ)USB_EP5R_CTR_TX ((uint16_t)0x0080) ò)USB_EP5R_EP_KIND ((uint16_t)0x0100) ô)USB_EP5R_EP_TYPE ((uint16_t)0x0600) õ)USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) ö)USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) ø)USB_EP5R_SETUP ((uint16_t)0x0800) ú)USB_EP5R_STAT_RX ((uint16_t)0x3000) û)USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) ü)USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) þ)USB_EP5R_DTOG_RX ((uint16_t)0x4000) ÿ)USB_EP5R_CTR_RX ((uint16_t)0x8000) *USB_EP6R_EA ((uint16_t)0x000F) *USB_EP6R_STAT_TX ((uint16_t)0x0030)
*USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) *USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) *USB_EP6R_DTOG_TX ((uint16_t)0x0040) *USB_EP6R_CTR_TX ((uint16_t)0x0080) *USB_EP6R_EP_KIND ((uint16_t)0x0100) *USB_EP6R_EP_TYPE ((uint16_t)0x0600) *USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) *USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) *USB_EP6R_SETUP ((uint16_t)0x0800) *USB_EP6R_STAT_RX ((uint16_t)0x3000) *USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) *USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) *USB_EP6R_DTOG_RX ((uint16_t)0x4000) *USB_EP6R_CTR_RX ((uint16_t)0x8000) *USB_EP7R_EA ((uint16_t)0x000F) *USB_EP7R_STAT_TX ((uint16_t)0x0030) *USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) *USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) *USB_EP7R_DTOG_TX ((uint16_t)0x0040) ¡*USB_EP7R_CTR_TX ((uint16_t)0x0080) ¢*USB_EP7R_EP_KIND ((uint16_t)0x0100) ¤*USB_EP7R_EP_TYPE ((uint16_t)0x0600) ¥*USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) ¦*USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) ¨*USB_EP7R_SETUP ((uint16_t)0x0800) ª*USB_EP7R_STAT_RX ((uint16_t)0x3000) «*USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) ¬*USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) ®*USB_EP7R_DTOG_RX ((uint16_t)0x4000) ¯*USB_EP7R_CTR_RX ((uint16_t)0x8000) ³*USB_CNTR_FRES ((uint16_t)0x0001) ´*USB_CNTR_PDWN ((uint16_t)0x0002) µ*USB_CNTR_LP_MODE ((uint16_t)0x0004) ¶*USB_CNTR_FSUSP ((uint16_t)0x0008) ·*USB_CNTR_RESUME ((uint16_t)0x0010) ¸*USB_CNTR_ESOFM ((uint16_t)0x0100) ¹*USB_CNTR_SOFM ((uint16_t)0x0200) º*USB_CNTR_RESETM ((uint16_t)0x0400) »*USB_CNTR_SUSPM ((uint16_t)0x0800) ¼*USB_CNTR_WKUPM ((uint16_t)0x1000) ½*USB_CNTR_ERRM ((uint16_t)0x2000) ¾*USB_CNTR_PMAOVRM ((uint16_t)0x4000) ¿*USB_CNTR_CTRM ((uint16_t)0x8000) Â*USB_ISTR_EP_ID ((uint16_t)0x000F) Ã*USB_ISTR_DIR ((uint16_t)0x0010) Ä*USB_ISTR_ESOF ((uint16_t)0x0100) Å*USB_ISTR_SOF ((uint16_t)0x0200) Æ*USB_ISTR_RESET ((uint16_t)0x0400) Ç*USB_ISTR_SUSP ((uint16_t)0x0800) È*USB_ISTR_WKUP ((uint16_t)0x1000) É*USB_ISTR_ERR ((uint16_t)0x2000) Ê*USB_ISTR_PMAOVR ((uint16_t)0x4000) Ë*USB_ISTR_CTR ((uint16_t)0x8000) Î*USB_FNR_FN ((uint16_t)0x07FF) Ï*USB_FNR_LSOF ((uint16_t)0x1800) Ð*USB_FNR_LCK ((uint16_t)0x2000) Ñ*USB_FNR_RXDM ((uint16_t)0x4000) Ò*USB_FNR_RXDP ((uint16_t)0x8000) Õ*USB_DADDR_ADD ((uint8_t)0x7F) Ö*USB_DADDR_ADD0 ((uint8_t)0x01) ×*USB_DADDR_ADD1 ((uint8_t)0x02) Ø*USB_DADDR_ADD2 ((uint8_t)0x04) Ù*USB_DADDR_ADD3 ((uint8_t)0x08) Ú*USB_DADDR_ADD4 ((uint8_t)0x10) Û*USB_DADDR_ADD5 ((uint8_t)0x20) Ü*USB_DADDR_ADD6 ((uint8_t)0x40) Þ*USB_DADDR_EF ((uint8_t)0x80) á*USB_BTABLE_BTABLE ((uint16_t)0xFFF8) å*USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) è*USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) ë*USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) î*USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) ñ*USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) ô*USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) ÷*USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) ú*USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) ÿ*USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) +USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF)
+USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) +USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) +USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) +USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) +USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) +USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) +USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) +USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) +USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) ¢+USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) ¥+USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) ¨+USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) «+USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) ®+USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) ±+USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) ´+USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) ·+USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) º+USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) ½+USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) À+USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) Ã+USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) Æ+USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) Ë+USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) Î+USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) Ñ+USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) Ô+USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) ×+USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) Ú+USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) Ý+USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) à+USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) å+USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) ç+USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) è+USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) é+USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ê+USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ë+USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ì+USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) î+USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) ñ+USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) ó+USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) ô+USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) õ+USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ö+USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ÷+USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ø+USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ú+USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) ý+USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) ÿ+USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) ,USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ,USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ,USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ,USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ,USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ,USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) ,USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) ,USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) ,USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ,USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ,USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ,USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ,USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ,USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) ,USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) ,USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) ,USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ,USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ,USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ,USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ,USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ,USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) ¡,USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) £,USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) ¤,USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ¥,USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ¦,USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) §,USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ¨,USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ª,USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) ,USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) ¯,USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) °,USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ±,USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ²,USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ³,USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ´,USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ¶,USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) ¹,USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) »,USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) ¼,USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ½,USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ¾,USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ¿,USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) À,USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Â,USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) Ç,USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) É,USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Ê,USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Ë,USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Ì,USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Í,USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) Î,USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) Ð,USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) Ó,USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) Õ,USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Ö,USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ×,USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Ø,USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Ù,USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ú,USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Ü,USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ß,USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) á,USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) â,USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) ã,USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ä,USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) å,USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) æ,USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) è,USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ë,USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) í,USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) î,USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ï,USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ð,USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ñ,USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ò,USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ô,USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ÷,USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) ù,USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ú,USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) û,USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ü,USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ý,USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) þ,USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) -USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) -USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000)
-USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) -USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) -USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) -USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) -USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) -USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) -USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) -USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) -USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) -USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) -USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) -USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) -USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) -USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) -USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) -USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) -USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) -USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) -USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) -USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ¡-USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¢-USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ¤-USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) §-USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) ©-USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ª-USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) «-USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ¬-USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) -USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) ®-USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) °-USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ³-USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) µ-USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) ¶-USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ·-USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ¸-USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ¹-USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) º-USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ¼-USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ¿-USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) Á-USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Â-USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Ã-USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Ä-USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Å-USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) Æ-USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) È-USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) Ë-USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) Í-USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Î-USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Ï-USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Ð-USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Ñ-USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ò-USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Ô-USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ×-USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) Ù-USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Ú-USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Û-USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Ü-USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Ý-USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) Þ-USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) à-USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ã-USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) å-USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) æ-USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ç-USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) è-USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) é-USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ê-USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ì-USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ï-USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) ñ-USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ò-USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) ó-USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ô-USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) õ-USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) ö-USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ø-USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) û-USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) ý-USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) þ-USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ÿ-USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) .USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) .USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) .USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) .USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) .WWDG_CR_T ((uint8_t)0x7F) .WWDG_CR_T0 ((uint8_t)0x01) .WWDG_CR_T1 ((uint8_t)0x02) .WWDG_CR_T2 ((uint8_t)0x04) .WWDG_CR_T3 ((uint8_t)0x08) .WWDG_CR_T4 ((uint8_t)0x10) .WWDG_CR_T5 ((uint8_t)0x20) .WWDG_CR_T6 ((uint8_t)0x40) .WWDG_CR_WDGA ((uint8_t)0x80) .WWDG_CFR_W ((uint16_t)0x007F) .WWDG_CFR_W0 ((uint16_t)0x0001) .WWDG_CFR_W1 ((uint16_t)0x0002) .WWDG_CFR_W2 ((uint16_t)0x0004) .WWDG_CFR_W3 ((uint16_t)0x0008) .WWDG_CFR_W4 ((uint16_t)0x0010) .WWDG_CFR_W5 ((uint16_t)0x0020) .WWDG_CFR_W6 ((uint16_t)0x0040) ¢.WWDG_CFR_WDGTB ((uint16_t)0x0180) £.WWDG_CFR_WDGTB0 ((uint16_t)0x0080) ¤.WWDG_CFR_WDGTB1 ((uint16_t)0x0100) ¦.WWDG_CFR_EWI ((uint16_t)0x0200) ©.WWDG_SR_EWIF ((uint8_t)0x01) ².SysTick_CTRL_ENABLE ((uint32_t)0x00000001) ³.SysTick_CTRL_TICKINT ((uint32_t)0x00000002) ´.SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) µ.SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) ¸.SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) ».SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) ¾.SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) ¿.SysTick_CALIB_SKEW ((uint32_t)0x40000000) À.SysTick_CALIB_NOREF ((uint32_t)0x80000000) É.NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) Ê.NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) Ë.NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) Ì.NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) Í.NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) Î.NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) Ï.NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) Ð.NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) Ñ.NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) Ò.NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) Ó.NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) Ô.NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) Õ.NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) Ö.NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) ×.NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) Ø.NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) Ù.NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) Ú.NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) Û.NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) Ü.NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) Ý.NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) Þ.NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) ß.NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) à.NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) á.NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) â.NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) ã.NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) ä.NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) å.NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) æ.NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) ç.NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) è.NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) é.NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) ì.NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) í.NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) î.NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) ï.NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) ð.NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) ñ.NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) ò.NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) ó.NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) ô.NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) õ.NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) ö.NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) ÷.NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) ø.NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) ù.NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) ú.NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) û.NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) ü.NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) ý.NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) þ.NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) ÿ.NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000)
/NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) ¡/NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) ¢/NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) £/NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) ¤/NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) ¥/NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) ¦/NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) §/NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) ¨/NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) ©/NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) ª/NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) «/NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) ¬/NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) ®/NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) ¯/NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) ²/NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) ³/NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) ´/NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) µ/NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) ¶/NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) ·/NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) ¸/NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) ¹/NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) º/NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) »/NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) ¼/NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) ½/NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) ¾/NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) ¿/NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) À/NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) Á/NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) Â/NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) Ã/NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) Ä/NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) Å/NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) Æ/NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) Ç/NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) È/NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) É/NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) Ê/NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) Ë/NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) Ì/NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) Í/NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) Î/NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) Ï/NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) Ð/NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) Ñ/NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) Ò/NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) Õ/NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) Ö/NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) ×/NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) Ø/NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) Ù/NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) Ú/NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) Û/NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) Ü/NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) Ý/NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) Þ/NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) ß/NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) à/NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) á/NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) â/NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) ã/NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) ä/NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) å/NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) æ/NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) ç/NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) è/NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) é/NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) ê/NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) ë/NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) ì/NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) í/NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) î/NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) ï/NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) ð/NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) ñ/NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) ò/NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) ó/NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) ô/NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) õ/NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) ø/NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) ù/NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) ú/NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) û/NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) þ/NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) ÿ/NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) 0NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) 0NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) 0NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF)
0NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) 0NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) 0NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) 0NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) 0NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) 0NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) 0NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) 0NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) 0NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) 0NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) 0NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) 0NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) 0NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) 0NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) 0NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) 0NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) 0NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) 0NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) 0NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) ¢0NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) £0NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) ¤0NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) ¥0NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) ¨0SCB_CPUID_REVISION ((uint32_t)0x0000000F) ©0SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) ª0SCB_CPUID_Constant ((uint32_t)0x000F0000) «0SCB_CPUID_VARIANT ((uint32_t)0x00F00000) ¬0SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) ¯0SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) °0SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) ±0SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) ²0SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) ³0SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) ´0SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) µ0SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) ¶0SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) ·0SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) ¸0SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) »0SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) ¼0SCB_VTOR_TBLBASE ((uint32_t)0x20000000) ¿0SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) À0SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) Á0SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) Ã0SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) Ä0SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) Å0SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) Æ0SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) É0SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) Ê0SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) Ë0SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) Ì0SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) Í0SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) Î0SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) Ï0SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) Ð0SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) Ò0SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) Ó0SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) Ö0SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) ×0SCB_SCR_SLEEPDEEP ((uint8_t)0x04) Ø0SCB_SCR_SEVONPEND ((uint8_t)0x10) Û0SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) Ü0SCB_CCR_USERSETMPEND ((uint16_t)0x0002) Ý0SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) Þ0SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) ß0SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) à0SCB_CCR_STKALIGN ((uint16_t)0x0200) ã0SCB_SHPR_PRI_N ((uint32_t)0x000000FF) ä0SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) å0SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) æ0SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) é0SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) ê0SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) ë0SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) ì0SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) í0SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) î0SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) ï0SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) ð0SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) ñ0SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) ò0SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) ó0SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) ô0SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) õ0SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) ö0SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) ú0SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) û0SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) ü0SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) ý0SCB_CFSR_MSTKERR ((uint32_t)0x00000010) þ0SCB_CFSR_MMARVALID ((uint32_t)0x00000080) 1SCB_CFSR_IBUSERR ((uint32_t)0x00000100) 1SCB_CFSR_PRECISERR ((uint32_t)0x00000200) 1SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) 1SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) 1SCB_CFSR_STKERR ((uint32_t)0x00001000)
1SCB_CFSR_BFARVALID ((uint32_t)0x00008000) 1SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) 1SCB_CFSR_INVSTATE ((uint32_t)0x00020000) 1SCB_CFSR_INVPC ((uint32_t)0x00040000) 1SCB_CFSR_NOCP ((uint32_t)0x00080000) 1SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) 1SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) 1SCB_HFSR_VECTTBL ((uint32_t)0x00000002) 1SCB_HFSR_FORCED ((uint32_t)0x40000000) 1SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) 1SCB_DFSR_HALTED ((uint8_t)0x01) 1SCB_DFSR_BKPT ((uint8_t)0x02) 1SCB_DFSR_DWTTRAP ((uint8_t)0x04) 1SCB_DFSR_VCATCH ((uint8_t)0x08) 1SCB_DFSR_EXTERNAL ((uint8_t)0x10) 1SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 1SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) ¡1SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) ²1SET_BIT(REG,BIT) ((REG) |= (BIT)) ´1CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) ¶1READ_BIT(REG,BIT) ((REG) & (BIT)) ¸1CLEAR_REG(REG) ((REG) = (0x0)) º1WRITE_REG(REG,VAL) ((REG) = (VAL)) ¼1READ_REG(REG) ((REG)) ¾1MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) (_CHSTREAMS_H_ -_base_sequential_stream_methods size_t (*write)(void *instance, const uint8_t *bp, size_t n); size_t (*read)(void *instance, uint8_t *bp, size_t n); msg_t (*put)(void *instance, uint8_t b); msg_t (*get)(void *instance); <_base_sequential_stream_data achSequentialStreamWrite(ip,bp,n) ((ip)->vmt->write(ip, bp, n)) pchSequentialStreamRead(ip,bp,n) ((ip)->vmt->read(ip, bp, n)) chSequentialStreamPut(ip,b) ((ip)->vmt->put(ip, b)) chSequentialStreamGet(ip) ((ip)->vmt->get(ip)) _CHQUEUES_H_ &Q_OK RDY_OK 'Q_TIMEOUT RDY_TIMEOUT (Q_RESET RDY_RESET )Q_EMPTY -3 *Q_FULL -4 VchQSizeI(qp) ((size_t)((qp)->q_top - (qp)->q_buffer)) bchQSpaceI(qp) ((qp)->q_counter) mchQGetLink(qp) ((qp)->q_link) chIQGetFullI(iqp) chQSpaceI(iqp) chIQGetEmptyI(iqp) (chQSizeI(iqp) - chQSpaceI(iqp)) ¡chIQIsEmptyI(iqp) ((bool_t)(chQSpaceI(iqp) <= 0)) chIQIsFullI(iqp) ((bool_t)(((iqp)->q_wrptr == (iqp)->q_rdptr) && ((iqp)->q_counter != 0))) ¼chIQGet(iqp) chIQGetTimeout(iqp, TIME_INFINITE) Ê_INPUTQUEUE_DATA(name,buffer,size,inotify,link) { _THREADSQUEUE_DATA(name), 0, (uint8_t *)(buffer), (uint8_t *)(buffer) + (size), (uint8_t *)(buffer), (uint8_t *)(buffer), (inotify), (link) } àINPUTQUEUE_DECL(name,buffer,size,inotify,link) InputQueue name = _INPUTQUEUE_DATA(name, buffer, size, inotify, link) ýchOQGetFullI(oqp) (chQSizeI(oqp) - chQSpaceI(oqp)) chOQGetEmptyI(oqp) chQSpaceI(oqp) chOQIsEmptyI(oqp) ((bool_t)(((oqp)->q_wrptr == (oqp)->q_rdptr) && ((oqp)->q_counter != 0))) ¡chOQIsFullI(oqp) ((bool_t)(chQSpaceI(oqp) <= 0)) ±chOQPut(oqp,b) chOQPutTimeout(oqp, b, TIME_INFINITE) ¿_OUTPUTQUEUE_DATA(name,buffer,size,onotify,link) { _THREADSQUEUE_DATA(name), (size), (uint8_t *)(buffer), (uint8_t *)(buffer) + (size), (uint8_t *)(buffer), (uint8_t *)(buffer), (onotify), (link) } ÕOUTPUTQUEUE_DECL(name,buffer,size,onotify,link) OutputQueue name = _OUTPUTQUEUE_DATA(name, buffer, size, onotify, link) _CHTHREADS_H_ $THD_STATE_READY 0 %THD_STATE_CURRENT 1 &THD_STATE_SUSPENDED 2 'THD_STATE_WTSEM 3 (THD_STATE_WTMTX 4 )THD_STATE_WTCOND 5 +THD_STATE_SLEEPING 6 -THD_STATE_WTEXIT 7 .THD_STATE_WTOREVT 8 /THD_STATE_WTANDEVT 9 0THD_STATE_SNDMSGQ 10 1THD_STATE_SNDMSG 11 3THD_STATE_WTMSG 12 4THD_STATE_WTQUEUE 13 5THD_STATE_FINAL 14 <THD_STATE_NAMES "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", "FINAL" FTHD_MEM_MODE_MASK 3 GTHD_MEM_MODE_STATIC 0 HTHD_MEM_MODE_HEAP 1 JTHD_MEM_MODE_MEMPOOL 2 LTHD_TERMINATE 4 êchThdSelf() currp òchThdGetPriority() (currp->p_prio) þchThdGetTicks(tp) ((tp)->p_time) chThdLS() (void *)(currp + 1) chThdTerminated(tp) ((tp)->p_state == THD_STATE_FINAL) chThdShouldTerminate() (currp->p_flags & THD_TERMINATE) ¦chThdResumeI(tp) chSchReadyI(tp) ´chThdSleepS(time) chSchGoSleepTimeoutS(THD_STATE_SLEEPING, time) ÀchThdSleepSeconds(sec) chThdSleep(S2ST(sec)) ÍchThdSleepMilliseconds(msec) chThdSleep(MS2ST(msec)) ÚchThdSleepMicroseconds(usec) chThdSleep(US2ST(usec)) _CHMEMPOOLS_H_ >_MEMORYPOOL_DATA(name,size,provider) {NULL, size, provider} KMEMORYPOOL_DECL(name,size,provider) MemoryPool name = _MEMORYPOOL_DATA(name, size, provider) achPoolAdd(mp,objp) chPoolFree(mp, objp) rchPoolAddI(mp,objp) chPoolFreeI(mp, objp) _CHHEAP_H_ _CHMEMCORE_H_ -MEM_ALIGN_SIZE sizeof(stkalign_t) 2MEM_ALIGN_MASK (MEM_ALIGN_SIZE - 1) 7MEM_ALIGN_PREV(p) ((size_t)(p) & ~MEM_ALIGN_MASK) <MEM_ALIGN_NEXT(p) MEM_ALIGN_PREV((size_t)(p) + MEM_ALIGN_MASK) BMEM_IS_ALIGNED(p) (((size_t)(p) & MEM_ALIGN_MASK) == 0) _CHMBOXES_H_ VchMBSizeI(mbp) ((mbp)->mb_top - (mbp)->mb_buffer) echMBGetFreeCountI(mbp) chSemGetCounterI(&(mbp)->mb_emptysem) schMBGetUsedCountI(mbp) chSemGetCounterI(&(mbp)->mb_fullsem) ~chMBPeekI(mbp) (*(mbp)->mb_rdptr) _MAILBOX_DATA(name,buffer,size) { (msg_t *)(buffer), (msg_t *)(buffer) + size, (msg_t *)(buffer), (msg_t *)(buffer), _SEMAPHORE_DATA(name.mb_fullsem, 0), _SEMAPHORE_DATA(name.mb_emptysem, size), } MAILBOX_DECL(name,buffer,size) Mailbox name = _MAILBOX_DATA(name, buffer, size) !_CHEVENTS_H_ K_EVENTSOURCE_DATA(name) {(void *)(&name)} TEVENTSOURCE_DECL(name) EventSource name = _EVENTSOURCE_DATA(name) YALL_EVENTS ((eventmask_t)-1) ^EVENT_MASK(eid) ((eventmask_t)(1 << (eid))) schEvtRegister(esp,elp,eid) chEvtRegisterMask(esp, elp, EVENT_MASK(eid)) chEvtInit(esp) ((esp)->es_next = (EventListener *)(void *)(esp)) chEvtIsListeningI(esp) ((void *)(esp) != (void *)(esp)->es_next) chEvtBroadcast(esp) chEvtBroadcastFlags(esp, 0) ¢chEvtBroadcastI(esp) chEvtBroadcastFlagsI(esp, 0) !_CHCOND_H_ L_CONDVAR_DATA(name) {_THREADSQUEUE_DATA(name.c_queue)} UCONDVAR_DECL(name) CondVar name = _CONDVAR_DATA(name) _CHMTX_H_ D_MUTEX_DATA(name) {_THREADSQUEUE_DATA(name.m_queue), NULL, NULL} MMUTEX_DECL(name) Mutex name = _MUTEX_DATA(name) YchMtxQueueNotEmptyS(mp) notempty(&(mp)->m_queue) 4_CHBSEM_H_ I_BSEMAPHORE_DATA(name,taken) {_SEMAPHORE_DATA(name.bs_sem, ((taken) ? 0 : 1))} TBSEMAPHORE_DECL(name,taken) BinarySemaphore name = _BSEMAPHORE_DATA(name, taken) fchBSemInit(bsp,taken) chSemInit(&(bsp)->bs_sem, (taken) ? 0 : 1) tchBSemWait(bsp) chSemWait(&(bsp)->bs_sem) chBSemWaitS(bsp) chSemWaitS(&(bsp)->bs_sem) chBSemWaitTimeout(bsp,time) chSemWaitTimeout(&(bsp)->bs_sem, (time)) ¬chBSemWaitTimeoutS(bsp,time) chSemWaitTimeoutS(&(bsp)->bs_sem, (time)) ¼chBSemReset(bsp,taken) chSemReset(&(bsp)->bs_sem, (taken) ? 0 : 1) ÍchBSemResetI(bsp,taken) chSemResetI(&(bsp)->bs_sem, (taken) ? 0 : 1) ÖchBSemSignal(bsp) { chSysLock(); chBSemSignalI((bsp)); chSchRescheduleS(); chSysUnlock(); } åchBSemSignalI(bsp) { if ((bsp)->bs_sem.s_cnt < 1) chSemSignalI(&(bsp)->bs_sem); } ôchBSemGetStateI(bsp) ((bsp)->bs_sem.s_cnt > 0 ? FALSE : TRUE) _CHSEM_H_ H_SEMAPHORE_DATA(name,n) {_THREADSQUEUE_DATA(name.s_queue), n} SSEMAPHORE_DECL(name,n) Semaphore name = _SEMAPHORE_DATA(name, n) _chSemFastWaitI(sp) ((sp)->s_cnt--) hchSemFastSignalI(sp) ((sp)->s_cnt++) ochSemGetCounterI(sp) ((sp)->s_cnt) _CHVT_H_ .S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY)) :MS2ST(msec) ((systime_t)(((((msec) - 1L) * CH_FREQUENCY) / 1000L) + 1L)) GUS2ST(usec) ((systime_t)(((((usec) - 1L) * CH_FREQUENCY) / 1000000L) + 1L)) chVTDoTickI() { vtlist.vt_systime++; if (&vtlist != (VTList *)vtlist.vt_next) { VirtualTimer *vtp; --vtlist.vt_next->vt_time; while (!(vtp = vtlist.vt_next)->vt_time) { vtfunc_t fn = vtp->vt_func; vtp->vt_func = (vtfunc_t)NULL; vtp->vt_next->vt_prev = (void *)&vtlist; (&vtlist)->vt_next = vtp->vt_next; chSysUnlockFromIsr(); fn(vtp->vt_par); chSysLockFromIsr(); } } } chVTIsArmedI(vtp) ((vtp)->vt_func != NULL) ®chVTSet(vtp,time,vtfunc,par) { chSysLock(); chVTSetI(vtp, time, vtfunc, par); chSysUnlock(); } ¼chVTReset(vtp) { chSysLock(); if (chVTIsArmedI(vtp)) chVTResetI(vtp); chSysUnlock(); } ÎchTimeNow() (vtlist.vt_systime) _CHCORE_V7M_H_ 'CORTEX_BASEPRI_DISABLED 0 ;PORT_IDLE_THREAD_STACK_SIZE 16 HPORT_INT_REQUIRED_STACK 32 OCORTEX_ENABLE_WFI_IDLE FALSE XCORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) cCORTEX_USE_FPU CORTEX_HAS_FPU oCORTEX_SIMPLIFIED_PRIORITY FALSE zCORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) CORTEX_VTOR_INIT 0x00000000 CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1) CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY) ¬CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL ¶CH_ARCHITECTURE_ARM_v7M »CH_ARCHITECTURE_NAME "ARMv7-M" ÀCH_CORE_VARIANT_NAME "Cortex-M3" ÐCH_PORT_INFO "Advanced kernel mode" ¹SETUP_CONTEXT(workspace,wsize,pf,arg) { tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + wsize - sizeof(struct intctx)); tp->p_ctx.r13->r4 = (regarm_t)pf; tp->p_ctx.r13->r5 = (regarm_t)arg; tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; } ÅSTACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) ÊTHD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + sizeof(struct intctx) + sizeof(struct extctx) + (n) + (PORT_INT_REQUIRED_STACK)) ÔWORKING_AREA(s,n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] ÛPORT_IRQ_PROLOGUE() âPORT_IRQ_EPILOGUE() _port_irq_epilogue() éPORT_IRQ_HANDLER(id) void id(void) ðPORT_FAST_IRQ_HANDLER(id) void id(void) õport_init() _port_init() þport_lock() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_KERNEL; } port_unlock() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_DISABLED; } port_lock_from_isr() port_lock() ¥port_unlock_from_isr() port_unlock() port_disable() __disable_irq() µport_suspend() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_KERNEL; } Âport_enable() { register uint32_t basepri __asm("basepri"); basepri = CORTEX_BASEPRI_DISABLED; __enable_irq(); } Öport_wait_for_interrupt() äport_switch(ntp,otp) _port_switch(ntp, otp) !_CHLISTS_H_ *queue_init(tqp) ((tqp)->p_next = (tqp)->p_prev = (Thread *)(tqp)); 1list_init(tlp) ((tlp)->p_next = (Thread *)(tlp)) 9isempty(p) ((p)->p_next == (Thread *)(p)) Anotempty(p) ((p)->p_next != (Thread *)(p)) J_THREADSQUEUE_DATA(name) {(Thread *)&name, (Thread *)&name} STHREADSQUEUE_DECL(name) ThreadsQueue name = _THREADSQUEUE_DATA(name) _CHTYPES_H_ !"4INLINE __inline :ROMCONST const @PACK_STRUCT_STRUCT EPACK_STRUCT_BEGIN __packed KPACK_STRUCT_END __stdint_h __ARMCLIB_VERSION 5030024 __STDINT_DECLS __CLIBNS __CLIBNS \INT8_MIN -128 ]INT16_MIN -32768 ^INT32_MIN (~0x7fffffff) _INT64_MIN __ESCAPE__(~0x7fffffffffffffffll) bINT8_MAX 127 cINT16_MAX 32767 dINT32_MAX 2147483647 eINT64_MAX __ESCAPE__(9223372036854775807ll) hUINT8_MAX 255 iUINT16_MAX 65535 jUINT32_MAX 4294967295u kUINT64_MAX __ESCAPE__(18446744073709551615ull) pINT_LEAST8_MIN -128 qINT_LEAST16_MIN -32768 rINT_LEAST32_MIN (~0x7fffffff) sINT_LEAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) vINT_LEAST8_MAX 127 wINT_LEAST16_MAX 32767 xINT_LEAST32_MAX 2147483647 yINT_LEAST64_MAX __ESCAPE__(9223372036854775807ll) |UINT_LEAST8_MAX 255 }UINT_LEAST16_MAX 65535 ~UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull) INT_FAST8_MIN (~0x7fffffff)
INT_FAST16_MIN (~0x7fffffff) INT_FAST32_MIN (~0x7fffffff) INT_FAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) INT_FAST8_MAX 2147483647 INT_FAST16_MAX 2147483647 INT_FAST32_MAX 2147483647 INT_FAST64_MAX __ESCAPE__(9223372036854775807ll) UINT_FAST8_MAX 4294967295u UINT_FAST16_MAX 4294967295u UINT_FAST32_MAX 4294967295u UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull) INTPTR_MIN (~0x7fffffff) INTPTR_MAX 2147483647 UINTPTR_MAX 4294967295u £INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ¦INTMAX_MAX __ESCAPE__(9223372036854775807ll) ©UINTMAX_MAX __ESCAPE__(18446744073709551615ull) ®PTRDIFF_MIN (~0x7fffffff) ¯PTRDIFF_MAX 2147483647 ²SIG_ATOMIC_MIN (~0x7fffffff) ³SIG_ATOMIC_MAX 2147483647 ¶SIZE_MAX 4294967295u »WCHAR_MIN ¼WCHAR_MAX ÂWCHAR_MIN 0 ÃWCHAR_MAX 65535 ÇWINT_MIN (~0x7fffffff) ÈWINT_MAX 2147483647 ÏINT8_C(x) (x) ÐINT16_C(x) (x) ÑINT32_C(x) (x) ÒINT64_C(x) __ESCAPE__(x##ll) ÔUINT8_C(x) (x##u) ÕUINT16_C(x) (x##u) ÖUINT32_C(x) (x##u) ×UINT64_C(x) __ESCAPE__(x##ull) ÚINTMAX_C(x) __ESCAPE__(x##ll) ÛUINTMAX_C(x) __ESCAPE__(x##ull) __stddef_h __ARMCLIB_VERSION 5030024 __STDDEF_DECLS __CLIBNS __CLIBNS GNULL HNULL 0 Loffsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb))) % 8 dekoduj_zpravu_GPS " P ¤ GPGGA_informace 4 l\ 4 ¥ dekodujPrikaz ç GPGGA_informace ô x main l P tp_odpal Q Ì testthd1 ¤ testthd2 º testthd3 Ð testthd4 æ patternthd Q X¥ testsem1 µ testsem2 Ë testsem3 á testsem4 ÷ patternsem @ ð ¯ testqueues1 È testqueues2 á patternqueues . ,° Ô testpools1 ¸ patternpools
ø· » testmtx1 Ñ testmtx2 ç testmtx3 ý testmtx4 testmtx5 ) testmtx6 ? testmtx7 U testmtx8 k patternmtx * º À testmsg1 ¤ patternmsg , |Á Ô testmbox1 ¶ patternmbox , hÃ Ø testheap1 ¦ patternheap D ØÆ Á testevt1 × testevt2 í testevt3 patternevt D Ë testdyn1 ¤ testdyn2 º testdyn3 Ð patterndyn > üA X threads f test wa test_timer_done Ì x ! thread4 Ê Ò ì testbmk1 ¤ testbmk2 º testbmk3 Ð testbmk4 æ testbmk5 ü testbmk6 testbmk7 ( testbmk8 > testbmk9 T testbmk10 k testbmk11 testbmk12 testbmk13 ° patternbmk t ôh test_printn @ test_print ] test_println _test_fail Ç _test_assert
test_wait_threads ¾ Ô < ; test_emit_token ÿ _test_assert_sequence ¶ _test_assert_time_window d test_terminate_threads ² test_cpu_pulse test_wait_tick b test_start_timer Ê TestThread > ¼Ü Ö test_timer_done ; wa e threads test % k ¨ gpt_lld_stop_timer \Þ 0 Æ VectorB0 gpt_lld_init 9 gpt_lld_start s gpt_lld_stop ¡ gpt_lld_start_timer æ gpt_lld_polled_delay à ¸ GPTD2 4 Dá ° hal_lld_init ä stm32_clock_init * Tm Ü ¬ adc_lld_stop_conversion ¡ Pâ ¨ õ Vector88 k adc_lld_init adc_lld_start Ï adc_lld_stop ý adc_lld_start_conversion O adcSTM32EnableTSVREFE z adcSTM32DisableTSVREFE øå ¼ ¤ ADCD1 ´æ À à Vector6C í Vector70 Vector74 C Vector78 n Vector7C Vector80 Ä Vector84 ï dmaInit dmaStreamAllocate dmaStreamRelease % té ¦ _stm32_dma_streams Y tê D VectorD4 ! VectorD8 ? sd_lld_init ` sd_lld_start Á sd_lld_stop ¸í ì Æ SD1 × SD2 ¤î 8 ¬ VectorB8 ê pwm_lld_init pwm_lld_start R pwm_lld_stop pwm_lld_enable_channel ì pwm_lld_disable_channel Üð ¸ PWMD4 : ñ l ³ _pal_lld_init _pal_lld_setgroupmode ls ¼ tmObjectInit ô P tmInit h ö ¤ ÿ sdInit sdObjectInit e sdStart Å sdStop sdIncomingDataI O sdRequestDataI Lû è pwmInit ¸ pwmObjectInit æ pwmStart G pwmStop pwmChangePeriod pwmEnableChannel z pwmDisableChannel % ðt ì halIsCounterWithin - 4þ d halInit è halPolledDelay M Üu , gptStartContinuousI Ð gptStartOneShotI gptStopTimerI ª ÿ 0 gptInit ¸ gptObjectInit æ gptStart G gptStop gptChangeInterval & gptStartContinuous Ô gptStartOneShot y gptStopTimer ë gptPolledDelay & w è adcStartConversionI ¼ È ` adcInit ¸ adcObjectInit æ adcStart G adcStop Å adcStartConversion w adcStopConversion ê adcStopConversionI 4 adcConvert adcAcquireBus 0 adcReleaseBus % ,M Ü ¾ pal_default_config J ( ¨ ª _vt_init Ç chVTSetI chVTResetI E chTimeIsWithin Ð ¬ vtlist ? { ¬ · _thread_init ö chThdCreateI Z chThdExitS ª |
Ð = chThdCreateStatic H chThdSetPriority Î chThdResume ; chThdTerminate chThdSleep é chThdSleepUntil C chThdYield Ç chThdExit 7 chThdWait D L « _idle_thread Ò chSysInit chSysTimerHandlerI " ä ´ _idle_thread_wa C ü | ¯ chSemResetI chSemWaitS 4 chSemWaitTimeoutS è ¡ chSemInit
chSemReset æ chSemWait ä chSemWaitTimeout ² chSemSignal . chSemSignalI chSemAddCounterI þ chSemSignalWait g x ¨ chSchReadyI ä chSchGoSleepS chSchDoRescheduleAhead H chSchDoRescheduleBehind w ¬ _scheduler_init ÷ chSchGoSleepTimeoutS ý chSchWakeupS ã chSchRescheduleS ½ chSchDoReschedule ¬ rlist 7 È ¦ chRegFirstThread chRegNextThread ` ´ ch_debug ¯ ! $ ® chIQInit chIQResetI Z chIQPutI Ì chIQGetTimeout  chIQReadTimeout â chOQInit 7 chOQResetI chOQPutTimeout chOQGetI ÿ chOQWriteTimeout / Ô ¯ chMtxLockS á chMtxTryLockS o 8( ¡ chMtxInit Ô chMtxLock I chMtxTryLock ß chMtxUnlock ® chMtxUnlockS T chMtxUnlockAll ; H- 0 ¡ chMsgSend ? chMsgWait Î chMsgRelease > ø d ¬ chPoolFreeI Ü chPoolFree % chPoolAllocI A x/ Ü ° chPoolInit } chPoolLoadArray D chPoolAlloc X \ < « chCoreAllocI ó Image$$RW_IRAM1$$ZI$$Limit Image$$RW_IRAM2$$Base > T2 È ¯ _core_init ö chCoreAlloc chCoreStatus > ¬ ¬ chMBPostS ÿ chMBPostAheadS W chMBFetchS à4 ¤ chMBInit à chMBReset h chMBPost ) chMBPostI ¬ chMBPostAhead t chMBPostAheadI ü chMBFetch À chMBFetchI \ ô9 < ¬ _heap_init Ë chHeapInit chHeapAlloc chHeapFree È chHeapStatus 8 ü ° chEvtSignalI Û chEvtBroadcastFlagsI P ä< $ ¤ chEvtRegisterMask chEvtUnregister chEvtGetAndClearEvents chEvtAddEvents Þ chEvtGetAndClearFlags c chEvtSignal ä chEvtBroadcastFlags chEvtGetAndClearFlagsI ó chEvtDispatch = chEvtWaitOne À chEvtWaitAny D chEvtWaitAll ¿ chEvtWaitOneTimeout chEvtWaitAnyTimeout \ chEvtWaitAllTimeout e F ä ¯ chThdAddRef chThdRelease | chThdCreateFromHeap 2 chThdCreateFromMemoryPool J Ø ¶ chCondBroadcastI ü chCondWaitS I chCondWaitTimeoutS y ìH È ¢ chCondInit Ë chCondSignal E chCondSignalI Å chCondBroadcast ª chCondWait Ü chCondWaitTimeout Z ´M ¹ nvicEnableVector û nvicDisableVector 2 nvicSetSystemHandlerPriority % x ¯ _port_irq_epilogue @ P ø ø SysTickVector SVCallVector Õ _port_init (< , SD1 SD2 ¸ ô PWMD4 ô p ] GPTD2 T= x h ADCD1 % 7 û _stm32_dma_streams Hf ¨ vtlist - äS ð ® __early_init Ï boardInit % ÔT Ä ¢ pal_default_config
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/ Ìt / Üt / ìt %/ üt 0/ u 9/ (u B/ 8u K/ Hu V/ Xu `/ hu l/ pu v/ u / u / u / u / °u ¨/ Àu ±/ Ðu º/ àu Ã/ ðu Ì/ v Õ/ v Þ/ v $ é/ Dv ô/ Tv 0 \v
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0 | 0 <| ®0 ¾0 Ç0 ` Í0 È À Ý0 ä0 ê0 ¬ x î0 $ x ò0 Ô 4 ø0 þ0 ( 1 P ð 1 ( - 1 X 61 X C1 X ^1 X l1 @ $d.realdata $t $d ..\\..\\..\\boards\\ST_STM32L_DISCOVERY\\board.c ..\..\..\boards\ST_STM32L_DISCOVERY\board.c .text .constdata ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\cstartup.s MSTACK CSTACK proc_stack_mem HEAP Heap_Mem ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\chcoreasm_v7m.s ..\..\..\os\ports\RVCT\ARMCMx\chcore.c ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c ..\\..\\..\\os\\ports\\RVCT\\ARMCMx\\STM32L1xx\\vectors.s RESET ..\..\..\os\ports\common\ARMCMx\nvic.c ..\..\..\os\kernel\src\chcond.c ..\..\..\os\kernel\src\chdebug.c ..\..\..\os\kernel\src\chdynamic.c ..\..\..\os\kernel\src\chevents.c ..\..\..\os\kernel\src\chheap.c .bss default_heap ..\..\..\os\kernel\src\chlists.c ..\..\..\os\kernel\src\chmboxes.c ..\..\..\os\kernel\src\chmemcore.c .data nextmem endmem ..\..\..\os\kernel\src\chmempools.c ..\..\..\os\kernel\src\chmsg.c ..\..\..\os\kernel\src\chmtx.c ..\..\..\os\kernel\src\chqueues.c ..\..\..\os\kernel\src\chregistry.c ..\..\..\os\kernel\src\chschd.c wakeup ..\..\..\os\kernel\src\chsem.c ..\..\..\os\kernel\src\chsys.c mainthread ..\..\..\os\kernel\src\chthreads.c ..\..\..\os\kernel\src\chvt.c ..\\..\\..\\os\\hal\\src\\usb.c ..\..\..\os\hal\src\usb.c ..\\..\\..\\os\\hal\\src\\adc.c ..\..\..\os\hal\src\adc.c ..\\..\\..\\os\\hal\\src\\can.c ..\..\..\os\hal\src\can.c ..\\..\\..\\os\\hal\\src\\ext.c ..\..\..\os\hal\src\ext.c ..\\..\\..\\os\\hal\\src\\gpt.c ..\..\..\os\hal\src\gpt.c ..\\..\\..\\os\\hal\\src\\hal.c ..\..\..\os\hal\src\hal.c ..\\..\\..\\os\\hal\\src\\i2c.c ..\..\..\os\hal\src\i2c.c ..\\..\\..\\os\\hal\\src\\icu.c ..\..\..\os\hal\src\icu.c ..\\..\\..\\os\\hal\\src\\mac.c ..\..\..\os\hal\src\mac.c ..\\..\\..\\os\\hal\\src\\mmc_spi.c ..\..\..\os\hal\src\mmc_spi.c ..\\..\\..\\os\\hal\\src\\pal.c ..\..\..\os\hal\src\pal.c ..\\..\\..\\os\\hal\\src\\pwm.c ..\..\..\os\hal\src\pwm.c ..\\..\\..\\os\\hal\\src\\rtc.c ..\..\..\os\hal\src\rtc.c ..\\..\\..\\os\\hal\\src\\sdc.c ..\..\..\os\hal\src\sdc.c ..\\..\\..\\os\\hal\\src\\serial.c ..\..\..\os\hal\src\serial.c write read put get putt gett writet readt vmt ..\\..\\..\\os\\hal\\src\\serial_usb.c ..\..\..\os\hal\src\serial_usb.c ..\\..\\..\\os\\hal\\src\\spi.c ..\..\..\os\hal\src\spi.c ..\\..\\..\\os\\hal\\src\\tm.c ..\..\..\os\hal\src\tm.c tm_start tm_stop measurement_offset ..\\..\\..\\os\\hal\\src\\uart.c ..\..\..\os\hal\src\uart.c ..\\..\\..\\os\\hal\\platforms\\STM32\\GPIOv2\\pal_lld.c ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c ..\\..\\..\\os\\hal\\platforms\\STM32\\mac_lld.c ..\..\..\os\hal\platforms\STM32\mac_lld.c ..\\..\\..\\os\\hal\\platforms\\STM32\\pwm_lld.c ..\..\..\os\hal\platforms\STM32\pwm_lld.c ..\\..\\..\\os\\hal\\platforms\\STM32\\USARTv1\\serial_lld.c ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c notify1 notify2 serve_interrupt default_config ..\\..\\..\\os\\hal\\platforms\\STM32L1xx\\stm32_dma.c ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c dma_isr_redir dma_streams_mask ..\\..\\..\\os\\hal\\platforms\\STM32L1xx\\adc_lld.c ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c adc_lld_serve_rx_interrupt ..\\..\\..\\os\\hal\\platforms\\STM32L1xx\\hal_lld.c ..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c ..\\..\\..\\os\\hal\\platforms\\STM32\\gpt_lld.c ..\..\..\os\hal\platforms\STM32\gpt_lld.c ..\\..\\..\\test\\test.c ..\..\..\test\test.c tmr tokens_buffer vt local_fail global_fail failpoint tokp chp patterns ..\..\..\test\testbmk.c thread1 bmk1_execute bmk2_execute thread2 bmk3_execute bmk4_execute bmk5_execute bmk6_execute thread3 bmk7_setup bmk7_execute thread8 bmk8_execute bmk9_execute tmo bmk10_execute bmk11_setup bmk11_execute bmk12_setup bmk12_execute bmk13_execute ib iq vt1 vt2 sem1 mtx1 .conststring ..\..\..\test\testdyn.c thread dyn1_setup dyn1_execute dyn2_setup dyn2_execute dyn3_setup dyn3_execute heap1 mp1 ..\..\..\test\testevt.c evt1_setup h1 h2 h3 evt1_execute evt2_setup evt2_execute evt3_setup evt3_execute evhndl es1 es2 ..\..\..\test\testheap.c heap1_setup heap1_execute test_heap ..\..\..\test\testmbox.c mbox1_setup mbox1_execute mb1 ..\..\..\test\testmsg.c msg1_execute ..\..\..\test\testmtx.c mtx1_setup mtx1_execute mtx2_setup thread2L thread2M thread2H mtx2_execute mtx3_setup thread3LL thread3L thread3M thread3H thread3HH mtx3_execute mtx4_setup thread4a thread4b mtx4_execute mtx5_setup mtx5_execute mtx6_setup thread10 mtx6_execute mtx7_setup mtx7_execute mtx8_setup thread11 thread12 mtx8_execute c1 m1 m2 ..\..\..\test\testpools.c null_provider pools1_setup pools1_execute ..\..\..\test\testqueues.c notify queues1_setup queues1_execute queues2_setup queues2_execute oq ..\..\..\test\testsem.c sem1_setup sem1_execute sem2_setup sem2_execute sem3_setup sem3_execute thread4 sem4_execute ..\..\..\test\testthd.c thd1_execute thd2_execute thd3_execute thd4_execute ..\\main.c ..\main.c gpt2cb pwmpcb adccb Thread_odpal Thread_GPS Thread1 samples waThread_odpal waThread_GPS waThread1 gpt2cfg adcgrpcfg USART2_config seconds_counter pwmcfg GPS_dekoduj.c kom_uziv.c dc.s ../clib/string.c ../clib/memcpset.s ../clib/heapaux.c ../clib/angel/startup.s !!!main ../clib/angel/kernel.s .ARM.Collect$$rtentry$$00000000 .ARM.Collect$$rtentry$$00000002 .ARM.Collect$$rtentry$$00000009 .ARM.Collect$$rtentry$$0000000A .ARM.Collect$$rtentry$$0000000C .ARM.Collect$$rtentry$$0000000D .ARM.Collect$$rtentry$$00000005 .ARM.Collect$$rtentry$$00002716 __lit__00000000 ../clib/angel/sys.s ../clib/stdlib.c ../clib/angel/boardlib.s ../clib/libinit.s .ARM.Collect$$libinit$$00000000 .ARM.Collect$$rtexit$$00000000 .ARM.Collect$$libinit$$00000002 .ARM.Collect$$libinit$$00000008 .ARM.Collect$$libinit$$0000000A .ARM.Collect$$libinit$$0000000C .ARM.Collect$$libinit$$0000000F .ARM.Collect$$libinit$$00000011 .ARM.Collect$$libinit$$00000013 .ARM.Collect$$libinit$$00000015 .ARM.Collect$$libinit$$00000017 .ARM.Collect$$libinit$$00000019 .ARM.Collect$$libinit$$0000001B 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BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 __ARM_use_no_argv __Vectors __main __scatterload __scatterload_rt2 __scatterload_rt2_thumb_only __scatterload_null __decompress __decompress1 __scatterload_zeroinit __rt_lib_init __rt_lib_init_alloca_1 __rt_lib_init_argv_1 __rt_lib_init_atexit_1 __rt_lib_init_clock_1 __rt_lib_init_cpp_1 __rt_lib_init_exceptions_1 __rt_lib_init_fp_1 __rt_lib_init_fp_trap_1 __rt_lib_init_getenv_1 __rt_lib_init_heap_1 __rt_lib_init_lc_collate_1 __rt_lib_init_lc_ctype_1 __rt_lib_init_lc_monetary_1 __rt_lib_init_lc_numeric_1 __rt_lib_init_lc_time_1 __rt_lib_init_rand_1 __rt_lib_init_return __rt_lib_init_signal_1 __rt_lib_init_stdio_1 __rt_lib_init_user_alloc_1 __rt_lib_shutdown __rt_lib_shutdown_fp_trap_1 __rt_lib_shutdown_heap_1 __rt_lib_shutdown_return __rt_lib_shutdown_signal_1 __rt_lib_shutdown_stdio_1 __rt_lib_shutdown_user_alloc_1 __rt_entry __rt_entry_presh_1 __rt_entry_sh __rt_entry_li __rt_entry_postsh_1 __rt_entry_main __rt_entry_postli_1 __rt_exit __rt_exit_ls __rt_exit_prels_1 __rt_exit_exit __early_init boardInit Reset_Handler __user_initial_stackheap _port_switch _port_thread_start _port_switch_from_isr _port_exit_from_isr _port_irq_epilogue SysTickVector SVCallVector _port_init BusFaultVector DebugMonitorVector HardFaultVector MemManageVector NMIVector PendSVVector UsageFaultVector Vector1C Vector20 Vector24 Vector28 Vector34 Vector40 Vector44 Vector48 Vector4C Vector50 Vector54 Vector58 Vector5C Vector60 Vector64 Vector68 Vector8C Vector90 Vector94 Vector98 Vector9C VectorA0 VectorA4 VectorA8 VectorAC VectorB4 VectorBC VectorC0 VectorC4 VectorC8 VectorCC VectorD0 VectorDC VectorE0 VectorE4 VectorE8 VectorEC VectorF0 _unhandled_exception nvicEnableVector nvicDisableVector nvicSetSystemHandlerPriority chCondInit chCondSignal chCondSignalI chCondBroadcastI chCondBroadcast chCondWaitS chCondWait chCondWaitTimeoutS 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chSchReadyI chSchGoSleepS chSchGoSleepTimeoutS chSchWakeupS chSchDoRescheduleAhead chSchRescheduleS chSchDoRescheduleBehind chSchDoReschedule chSemInit chSemResetI chSemReset chSemWaitS chSemWait chSemWaitTimeoutS chSemWaitTimeout chSemSignal chSemSignalI chSemAddCounterI chSemSignalWait _idle_thread chSysInit chSysTimerHandlerI _thread_init chThdCreateI chThdCreateStatic chThdSetPriority chThdResume chThdTerminate chThdSleep chThdSleepUntil chThdYield chThdExitS chThdExit chThdWait _vt_init chVTSetI chVTResetI chTimeIsWithin adcInit adcObjectInit adcStart adcStop adcStartConversionI adcStartConversion adcStopConversion adcStopConversionI adcConvert adcAcquireBus adcReleaseBus gptInit gptObjectInit gptStart gptStop gptChangeInterval gptStartContinuousI gptStartContinuous gptStartOneShotI gptStartOneShot gptStopTimerI gptStopTimer gptPolledDelay halInit halIsCounterWithin halPolledDelay pwmInit pwmObjectInit pwmStart pwmStop pwmChangePeriod pwmEnableChannel pwmDisableChannel sdInit sdObjectInit sdStart sdStop sdIncomingDataI sdRequestDataI tmObjectInit tmInit _pal_lld_init _pal_lld_setgroupmode VectorB8 pwm_lld_init pwm_lld_start pwm_lld_stop pwm_lld_enable_channel pwm_lld_disable_channel VectorD4 VectorD8 sd_lld_init sd_lld_start sd_lld_stop Vector6C Vector70 Vector74 Vector78 Vector7C Vector80 Vector84 dmaInit dmaStreamAllocate dmaStreamRelease adc_lld_stop_conversion Vector88 adc_lld_init adc_lld_start adc_lld_stop adc_lld_start_conversion adcSTM32EnableTSVREFE adcSTM32DisableTSVREFE hal_lld_init stm32_clock_init gpt_lld_stop_timer VectorB0 gpt_lld_init gpt_lld_start gpt_lld_stop gpt_lld_start_timer gpt_lld_polled_delay test_printn test_print test_println test_emit_token _test_fail _test_assert _test_assert_sequence _test_assert_time_window test_terminate_threads test_wait_threads test_cpu_pulse test_wait_tick test_start_timer TestThread dekodujPrikaz main dekoduj_zpravu_GPS strstr strncpy strcmp __use_two_region_memory __rt_heap_escrow$2region __rt_heap_expand$2region __aeabi_memclr __rt_memclr _memset __aeabi_memclr4 __aeabi_memclr8 __rt_memclr_w _memset_w exit _sys_exit __I$use$semihosting __use_no_semihosting_swi __semihosting_library_function pal_default_config ch_debug _stm32_dma_streams wa testbmk1 testbmk2 testbmk3 testbmk4 testbmk5 testbmk6 testbmk7 testbmk8 testbmk9 testbmk10 testbmk11 testbmk12 testbmk13 patternbmk testdyn1 testdyn2 testdyn3 patterndyn testevt1 testevt2 testevt3 patternevt testheap1 patternheap testmbox1 patternmbox testmsg1 patternmsg testmtx1 testmtx2 testmtx3 testmtx4 testmtx5 testmtx6 testmtx7 testmtx8 patternmtx testpools1 patternpools testqueues1 testqueues2 patternqueues testsem1 testsem2 testsem3 testsem4 patternsem testthd1 testthd2 testthd3 testthd4 patternthd Region$$Table$$Base Region$$Table$$Limit test_timer_done tp_odpal rlist _idle_thread_wa vtlist PWMD4 SD1 SD2 ADCD1 GPTD2 threads test GPGGA_informace __main_thread_stack_base__ __initial_sp Image$$RW_IRAM1$$ZI$$Limit __initial_msp Image$$RW_IRAM2$$Base @ARM ARM Linker, 5.03 [Build 24]
ArmLink --strict --callgraph --map --symbols --xref --cpu=Cortex-M3 --fpu=SoftVFP --list=.\lst\ch.map --output=.\obj\ch.axf --scatter=.\obj\ch.sct --info=summarysizes,sizes,totals,unused,veneers
C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\c_w.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\fz_ws.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\h_w.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\m_ws.l C:\Program Files\Keil\ARM\ARMCC\bin\..\lib\armlib\vfpsupport.l Input Comments: board.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\board.o --vfemode=force
Input Comments: p3a20-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p3a20-2 board.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\board.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\board.crf cstartup.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\cstartup.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program chcoreasm_v7m.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\chcoreasm_v7m.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program chcore.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcore.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcore.crf chcore_v7m.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcore_v7m.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcore_v7m.crf vectors.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpreproc --cpu=Cortex-M3 --apcs=interwork --depend=.\obj\vectors.d -I..\ -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program nvic.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\nvic.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\nvic.crf chcond.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chcond.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chcond.crf chdebug.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chdebug.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chdebug.crf chdynamic.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chdynamic.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chdynamic.crf chevents.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chevents.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chevents.crf chheap.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chheap.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chheap.crf chlists.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chlists.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chlists.crf chmboxes.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmboxes.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmboxes.crf chmemcore.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmemcore.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmemcore.crf chmempools.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmempools.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmempools.crf chmsg.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmsg.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmsg.crf chmtx.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chmtx.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chmtx.crf chsem.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chsem.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chsem.crf chsys.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chsys.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chsys.crf gps_dekoduj.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gps_dekoduj.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gps_dekoduj.crf chqueues.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chqueues.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chqueues.crf chregistry.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chregistry.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chregistry.crf chschd.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chschd.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chschd.crf chthreads.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chthreads.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chthreads.crf chvt.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\chvt.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\chvt.crf usb.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\usb.o --vfemode=force
Input Comments: p5ee4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p5ee4-2 usb.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\usb.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\usb.crf adc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\adc.o --vfemode=force
Input Comments: p3fb8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p3fb8-2 adc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\adc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\adc.crf can.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\can.o --vfemode=force
Input Comments: p2c48-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2c48-2 can.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\can.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\can.crf ext.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\ext.o --vfemode=force
Input Comments: p14dc-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p14dc-2 ext.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\ext.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\ext.crf gpt.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\gpt.o --vfemode=force
Input Comments: p55e8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p55e8-2 gpt.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gpt.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gpt.crf hal.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\hal.o --vfemode=force
Input Comments: p4894-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4894-2 hal.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\hal.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\hal.crf i2c.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\i2c.o --vfemode=force
Input Comments: p1ef8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p1ef8-2 i2c.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\i2c.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\i2c.crf icu.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\icu.o --vfemode=force
Input Comments: p2bfc-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2bfc-2 icu.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\icu.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\icu.crf mac.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mac.o --vfemode=force
Input Comments: p2ce0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2ce0-2 mac.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mac.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mac.crf mmc_spi.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mmc_spi.o --vfemode=force
Input Comments: p4e28-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4e28-2 mmc_spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mmc_spi.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mmc_spi.crf pal.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pal.o --vfemode=force
Input Comments: p5524-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p5524-2 pal.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pal.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pal.crf pwm.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pwm.o --vfemode=force
Input Comments: p5224-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p5224-2 pwm.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pwm.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pwm.crf rtc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\rtc.o --vfemode=force
Input Comments: p58b8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p58b8-2 rtc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\rtc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\rtc.crf sdc.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\sdc.o --vfemode=force
Input Comments: p4ffc-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4ffc-2 sdc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\sdc.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\sdc.crf serial.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial.o --vfemode=force
Input Comments: p2bd8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2bd8-2 serial.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial.crf serial_usb.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial_usb.o --vfemode=force
Input Comments: p30b8-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p30b8-2 serial_usb.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial_usb.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial_usb.crf spi.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\spi.o --vfemode=force
Input Comments: p4110-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4110-2 spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\spi.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\spi.crf tm.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\tm.o --vfemode=force
Input Comments: p4c74-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4c74-2 tm.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\tm.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\tm.crf uart.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\uart.o --vfemode=force
Input Comments: p3184-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p3184-2 uart.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\uart.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\uart.crf pal_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pal_lld.o --vfemode=force
Input Comments: p1d4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p1d4-2 pal_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pal_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pal_lld.crf mac_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\mac_lld.o --vfemode=force
Input Comments: p25fc-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p25fc-2 mac_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\mac_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\mac_lld.crf pwm_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\pwm_lld.o --vfemode=force
Input Comments: p3710-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p3710-2 pwm_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\pwm_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\pwm_lld.crf serial_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\serial_lld.o --vfemode=force
Input Comments: p4594-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4594-2 serial_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\serial_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\serial_lld.crf stm32_dma.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\stm32_dma.o --vfemode=force
Input Comments: p34a4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p34a4-2 stm32_dma.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\stm32_dma.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\stm32_dma.crf adc_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\adc_lld.o --vfemode=force
Input Comments: p2004-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2004-2 adc_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\adc_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\adc_lld.crf hal_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\hal_lld.o --vfemode=force
Input Comments: p2408-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p2408-2 hal_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\hal_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\hal_lld.crf gpt_lld.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\gpt_lld.o --vfemode=force
Input Comments: p4340-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p4340-2 gpt_lld.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\gpt_lld.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\gpt_lld.crf test.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\test.o --vfemode=force
Input Comments: p3dc0-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p3dc0-2 test.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\test.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\test.crf testbmk.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testbmk.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testbmk.crf testdyn.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testdyn.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testdyn.crf testevt.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testevt.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testevt.crf testheap.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testheap.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testheap.crf testmbox.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testmbox.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testmbox.crf testmsg.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testmsg.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testmsg.crf testmtx.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testmtx.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testmtx.crf testpools.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testpools.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testpools.crf testqueues.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testqueues.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testqueues.crf testsem.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testsem.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testsem.crf testthd.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\testthd.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\testthd.crf main.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=.\obj\main.o --vfemode=force
Input Comments: p1cc4-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\Zbynek\AppData\Local\Temp\p1cc4-2 main.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\main.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\main.crf kom_uziv.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=.\obj\kom_uziv.d --cpu=Cortex-M3 --apcs=interwork -O3 -Otime -I..\ -I..\..\..\os\kernel\include -I..\..\..\os\ports\common\ARMCMx -I..\..\..\os\ports\common\ARMCMx\CMSIS\include -I..\..\..\os\ports\RVCT\ARMCMx -I..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx -I..\..\..\os\hal\include -I..\..\..\os\hal\platforms\STM32 -I..\..\..\os\hal\platforms\STM32\GPIOv2 -I..\..\..\os\hal\platforms\STM32\SPIv1 -I..\..\..\os\hal\platforms\STM32\USARTv1 -I..\..\..\os\hal\platforms\STM32L1xx -I..\..\..\boards\ST_STM32L_DISCOVERY -I..\..\..\test -I"C:\Program Files\Keil\ARM\RV31\INC" -I"C:\Program Files\Keil\ARM\CMSIS\Include" -I"C:\Program Files\Keil\ARM\Inc\ST\STM32L1xx" -D__EVAL -D__heap_base__=Image$$RW_IRAM1$$ZI$$Limit -D__heap_end__=Image$$RW_IRAM2$$Base --omf_browse=.\obj\kom_uziv.crf argv_veneer.o ARM Linker, 5.03 [Build 24]
armlink --partial --no_add_relocs_to_undefined --no_execstack --no_generate_mapping_symbols --diag_suppress=6642 --cpu=7-M --fpu=None --no_unaligned_access --output=argv_veneer.o --vfemode=force --branchpatch=m3-ldrd
Input Comments: ER_IROM1 RW_IRAM1 RW_IRAM2 .debug_abbrev .debug_frame .debug_info .debug_line .debug_loc .debug_macinfo .debug_pubnames .symtab .strtab .note .comment .shstrtab 4 Ð| 4 <|
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