Subversion Repositories – MLAB

(root)/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp @ 3164

Rev 3091

SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true