/********************************************************************************* @file system_stm32f10x.c* @author MCD Application Team* @version V3.1.2* @date 09/28/2009* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.******************************************************************************** THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.** <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>*******************************************************************************//** @addtogroup CMSIS* @{*//** @addtogroup stm32f10x_system* @{*//** @addtogroup STM32F10x_System_Private_Includes* @{*/#include "stm32f10x.h"/*** @}*//** @addtogroup STM32F10x_System_Private_TypesDefinitions* @{*//*** @}*//** @addtogroup STM32F10x_System_Private_Defines* @{*//*!< Uncomment the line corresponding to the desired System clock (SYSCLK)frequency (after reset the HSI is used as SYSCLK source)IMPORTANT NOTE:==============1. After each device reset the HSI is used as System clock source.2. Please make sure that the selected System clock doesn't exceed your device'smaximum frequency.3. If none of the define below is enabled, the HSI is used as System clocksource.4. The System clock configuration functions provided within this file assume that:- For Low, Medium and High density devices an external 8MHz crystal isused to drive the System clock.- For Connectivity line devices an external 25MHz crystal is used to drivethe System clock.If you are using different crystal you have to adapt those functions accordingly.*//* #define SYSCLK_FREQ_HSE HSE_Value *//* #define SYSCLK_FREQ_24MHz 24000000 *//* #define SYSCLK_FREQ_36MHz 36000000 *//* #define SYSCLK_FREQ_48MHz 48000000 *//* #define SYSCLK_FREQ_56MHz 56000000 */#define SYSCLK_FREQ_72MHz 72000000/*!< Uncomment the following line if you need to use external SRAM mountedon STM3210E-EVAL board (STM32 High density devices) as data memory */#ifdef STM32F10X_HD/* #define DATA_IN_ExtSRAM */#endif /* STM32F10X_HD *//*** @}*//** @addtogroup STM32F10x_System_Private_Macros* @{*//*** @}*//** @addtogroup STM32F10x_System_Private_Variables* @{*//******************************************************************************** Clock Definitions*******************************************************************************/#ifdef SYSCLK_FREQ_HSEconst uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */#elif defined SYSCLK_FREQ_24MHzconst uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */#elif defined SYSCLK_FREQ_36MHzconst uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */#elif defined SYSCLK_FREQ_48MHzconst uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */#elif defined SYSCLK_FREQ_56MHzconst uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */#elif defined SYSCLK_FREQ_72MHzconst uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */#else /*!< HSI Selected as System Clock source */const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */#endif/*** @}*//** @addtogroup STM32F10x_System_Private_FunctionPrototypes* @{*/static void SetSysClock(void);#ifdef SYSCLK_FREQ_HSEstatic void SetSysClockToHSE(void);#elif defined SYSCLK_FREQ_24MHzstatic void SetSysClockTo24(void);#elif defined SYSCLK_FREQ_36MHzstatic void SetSysClockTo36(void);#elif defined SYSCLK_FREQ_48MHzstatic void SetSysClockTo48(void);#elif defined SYSCLK_FREQ_56MHzstatic void SetSysClockTo56(void);#elif defined SYSCLK_FREQ_72MHzstatic void SetSysClockTo72(void);#endif/*** @}*//** @addtogroup STM32F10x_System_Private_Functions* @{*//*** @brief Setup the microcontroller system* Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.* @note This function should be used only after reset.* @param None* @retval None*/void SystemInit (void){/* Reset the RCC clock configuration to the default reset state(for debug purpose) *//* Set HSION bit */RCC->CR |= (uint32_t)0x00000001;/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */#ifndef STM32F10X_CLRCC->CFGR &= (uint32_t)0xF8FF0000;#elseRCC->CFGR &= (uint32_t)0xF0FF0000;#endif /* STM32F10X_CL *//* Reset HSEON, CSSON and PLLON bits */RCC->CR &= (uint32_t)0xFEF6FFFF;/* Reset HSEBYP bit */RCC->CR &= (uint32_t)0xFFFBFFFF;/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */RCC->CFGR &= (uint32_t)0xFF80FFFF;#ifndef STM32F10X_CL/* Disable all interrupts and clear pending bits */RCC->CIR = 0x009F0000;#else/* Reset PLL2ON and PLL3ON bits */RCC->CR &= (uint32_t)0xEBFFFFFF;/* Disable all interrupts and clear pending bits */RCC->CIR = 0x00FF0000;/* Reset CFGR2 register */RCC->CFGR2 = 0x00000000;#endif /* STM32F10X_CL *//* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers *//* Configure the Flash Latency cycles and enable prefetch buffer */SetSysClock();}/*** @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.* @param None* @retval None*/static void SetSysClock(void){#ifdef SYSCLK_FREQ_HSESetSysClockToHSE();#elif defined SYSCLK_FREQ_24MHzSetSysClockTo24();#elif defined SYSCLK_FREQ_36MHzSetSysClockTo36();#elif defined SYSCLK_FREQ_48MHzSetSysClockTo48();#elif defined SYSCLK_FREQ_56MHzSetSysClockTo56();#elif defined SYSCLK_FREQ_72MHzSetSysClockTo72();#endif/* If none of the define above is enabled, the HSI is used as System clocksource (default after reset) */}/*** @brief Setup the external memory controller. Called in startup_stm32f10x.s* before jump to __main* @param None* @retval None*/#ifdef DATA_IN_ExtSRAM/*** @brief Setup the external memory controller.* Called in startup_stm32f10x_xx.s/.c before jump to main.* This function configures the external SRAM mounted on STM3210E-EVAL* board (STM32 High density devices). This SRAM will be used as program* data memory (including heap and stack).* @param None* @retval None*/void SystemInit_ExtMemCtl(void){/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank isrequired, then adjust the Register Addresses *//* Enable FSMC clock */RCC->AHBENR = 0x00000114;/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */RCC->APB2ENR = 0x000001E0;/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*//*---------------- SRAM Address lines configuration -------------------------*//*---------------- NOE and NWE configuration --------------------------------*//*---------------- NE3 configuration ----------------------------------------*//*---------------- NBL0, NBL1 configuration ---------------------------------*/GPIOD->CRL = 0x44BB44BB;GPIOD->CRH = 0xBBBBBBBB;GPIOE->CRL = 0xB44444BB;GPIOE->CRH = 0xBBBBBBBB;GPIOF->CRL = 0x44BBBBBB;GPIOF->CRH = 0xBBBB4444;GPIOG->CRL = 0x44BBBBBB;GPIOG->CRH = 0x44444B44;/*---------------- FSMC Configuration ---------------------------------------*//*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/FSMC_Bank1->BTCR[4] = 0x00001011;FSMC_Bank1->BTCR[5] = 0x00000200;}#endif /* DATA_IN_ExtSRAM */#ifdef SYSCLK_FREQ_HSE/*** @brief Selects HSE as System clock source and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockToHSE(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 0 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);#ifndef STM32F10X_CLFLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;#elseif (HSE_Value <= 24000000){FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;}else{FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;}#endif /* STM32F10X_CL *//* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;/* Select HSE as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;/* Wait till HSE is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#elif defined SYSCLK_FREQ_24MHz/*** @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockTo24(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 0 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;#ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |RCC_CFGR_PLLMULL6);/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}#else/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);#endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till PLL is ready */while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;/* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#elif defined SYSCLK_FREQ_36MHz/*** @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockTo36(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 1 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;#ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |RCC_CFGR_PLLMULL9);/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}#else/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);#endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till PLL is ready */while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;/* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#elif defined SYSCLK_FREQ_48MHz/*** @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockTo48(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 1 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK/2 */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;#ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |RCC_CFGR_PLLMULL6);#else/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);#endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till PLL is ready */while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;/* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#elif defined SYSCLK_FREQ_56MHz/*** @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockTo56(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 2 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK/2 */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;#ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |RCC_CFGR_PLLMULL7);#else/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);#endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till PLL is ready */while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;/* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#elif defined SYSCLK_FREQ_72MHz/*** @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2* and PCLK1 prescalers.* @note This function should be used only after reset.* @param None* @retval None*/static void SetSysClockTo72(void){__IO uint32_t StartUpCounter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*//* Enable HSE */RCC->CR |= ((uint32_t)RCC_CR_HSEON);/* Wait till HSE is ready and if Time out is reached exit */do{HSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCounter++;} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));if ((RCC->CR & RCC_CR_HSERDY) != RESET){HSEStatus = (uint32_t)0x01;}else{HSEStatus = (uint32_t)0x00;}if (HSEStatus == (uint32_t)0x01){/* Enable Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTBE;/* Flash 2 wait state */FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;/* HCLK = SYSCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;/* PCLK1 = HCLK/2 */RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;#ifdef STM32F10X_CL/* Configure PLLs ------------------------------------------------------*//* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz *//* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);/* Enable PLL2 */RCC->CR |= RCC_CR_PLL2ON;/* Wait till PLL2 is ready */while((RCC->CR & RCC_CR_PLL2RDY) == 0){}/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |RCC_CFGR_PLLMULL9);#else/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |RCC_CFGR_PLLMULL));RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);#endif /* STM32F10X_CL *//* Enable PLL */RCC->CR |= RCC_CR_PLLON;/* Wait till PLL is ready */while((RCC->CR & RCC_CR_PLLRDY) == 0){}/* Select PLL as system clock source */RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;/* Wait till PLL is used as system clock source */while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}}else{ /* If HSE fails to start-up, the application will have wrong clockconfiguration. User can add here some code to deal with this error *//* Go to infinite loop */while (1){}}}#endif/*** @}*//*** @}*//*** @}*//******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/