EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991

Document file for gal3.eqn
Device: 16V8

$LABELS 20 nc D7 D6 D5 D4 D3 D2 D1 D0 GND nc CLOCK DATA nc RES nc VCCON VPPON
 DQ VCC


Pin   Label               Type
---   -----               ----
2     D7                  com input
3     D6                  com input
4     D5                  com input
5     D4                  com input
6     D3                  com input
7     D2                  com input
8     D1                  com input
9     D0                  com input
10    GND                 ground pin
12    CLOCK               pos,trst,com output
13    DATA                pos,trst,com feedback
15    RES                 pos,trst,com output
17    VCCON               pos,trst,com output
18    VPPON               pos,trst,com output
19    DQ                  pos,trst,com output
20    VCC                 power pin

EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991

Device Utilization:

No of dedicated inputs used               :  8/10 (80.0%)
No of dedicated outputs used              :  2/2  (100.0%)
No of feedbacks used as dedicated outputs :  3/6  (50.0%)
No of feedbacks used                      :  1/6  (16.7%)

                ------------------------------------------
                Pin   Label                 Terms Usage
                ------------------------------------------
                19    DQ                    2/8   (25.0%)
                18    VPPON                 2/8   (25.0%)
                17    VCCON                 2/8   (25.0%)
                15    RES                   2/8   (25.0%)
                13    DATA                  3/8   (37.5%)
                12    CLOCK                 3/8   (37.5%)
                ------------------------------------------
                Total                      12/64  (18.8%)
                ------------------------------------------

EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991

                            Chip diagram (DIP)

                             ._____    _____.
                             |     \__/     |
                             |  1        20 | VCC
                          D7 |  2        19 | DQ
                          D6 |  3        18 | VPPON
                          D5 |  4        17 | VCCON
                          D4 |  5        16 | 
                          D3 |  6        15 | RES
                          D2 |  7        14 | 
                          D1 |  8        13 | DATA
                          D0 |  9        12 | CLOCK
                         GND | 10        11 | 
                             |______________|