!PADS-POWERPCB-V2005.2-BASIC! DESIGN DATABASE ASCII FILE 1.0
*PCB* GENERAL PARAMETERS OF THE PCB DESIGN
UNITS 0 2=Inches 1=Metric 0=Mils
USERGRID 3810000 3810000 Space between USER grid points
MAXIMUMLAYER 2 Maximum routing layer
WORKLEVEL 1 Level items will be created on
DISPLAYLEVEL 1 toggle for displaying working level last
LAYERPAIR 1 2 Layer pair used to route connection
VIAMODE T Type of via to use when routing between layers
LINEWIDTH 381000 Width items will be created with
TEXTSIZE 3810000 381000 Height and LineWidth text will be created with
JOBTIME 5 Amount of time spent on this PCB design
DOTGRID 38100000 38100000 Space between graphic dots
SCALE 12.175 Scale of window expansion
ORIGIN 381000000 381000000 User defined origin location
WINDOWCENTER 1146454798 1105042753 Point defining the center of the window
BACKUPTIME 20 Number of minutes between database backups
REAL WIDTH 381000 Widths greater then this are displayed real size
ALLSIGONOFF 1 All signal nets displayed on/off
REFNAMESIZE 3810000 381000 Height and LineWidth used by part ref. names
HIGHLIGHT 0 Highlight nets flag
JOBNAME REL8SW01A.pcb
CONCOL 1
FBGCOL 1 0
HATCHGRID 381000 Copper pour hatching grid
TEARDROP 2713690 Teardrop tracks
THERLINEWID 571500 Copper pour thermal line width
PSVIAGRID 952500 952500 Push & Shove Via Grid
PADFILLWID 381000 CAM finger pad fill width
THERSMDWID 381000 Copper pour thermal line width for SMD
MINHATAREA 0 Minimum hatch area
HATCHMODE 0 Hatch generation mode
HATCHDISP 0 Hatch display flag
DRILLHOLE 228600 Drill hole checking spacing
MITRERADII 0.5 1.0 1.5 2.0 2.5 3.0 3.5
MITRETYPE 1 Mitring type
HATCHRAD 0.500000 Hatch outline smoothing radius
MITREANG 180 180 180 180 180 180 90
HATCHANG 0 Hatch angle
THERFLAGS 0 Copper pour thermal line flags
DRLOVERSIZE 114300 Drill oversize for plated holes
PLANERAD 0.000000 Plane outline smoothing radius
PLANEFLAGS OUTLINE THERMALS Y Y Y N N Y Y Y N N Y Y N Y Y N N N Plane and Test Points flags
COMPHEIGHT 0 Board Top Component Height Restriction
KPTHATCHGRID 3810000 Copper pour hatching grid
BOTCMPHEIGHT 0 Board Bottom Component Height Restriction
FANOUTGRID 952500 952500 Fanout grid
FANOUTLENGTH 9525000 Maximum fanout length
ROUTERFLAGS 83879441 Autorouter specific flags
VERIFYFLAGS 1861 Verify Design flags
FABCHKFLAGS 3967 Fabrication checks flags
ATMAXSIZE 114300 Acid Traps Maximum Size
ATMAXANGLE 161999820 Acid Traps Maximum Angle
SLMINCOPPER 114300 Slivers Minimum Copper
SLMINMASK 114300 Slivers Minimum Mask
STMINCLEAR 5 Starved Thermal Minimum Clearance
STMINSPOKES 4 Starved Thermal Minimum Spokes
TPMINWIDTH 114300 Minimum Trace Width
TPMINSIZE 114300 Mimimum Pad Size
SSMINGAP 114300 Silk Screen Over Pads Minimum Gap
SBMINGAP 114300 Solder Bridges Minimum Gap
SBLAYER 1 Solder Bridges Layer
ARPTOM 114300 Pad To Mask Annular Ring
ARPTOMLAYER 1 Pad To Mask Annular Ring Layer
ARDTOM 114300 Drill To Mask Annular Ring
ARDTOMLAYER 1 Drill To Mask Annular Ring Layer
ARDTOP 114300 Drill To Pad Annular Ring
ARDTOPLAYER 0 Drill To Pad Annular Ring Layer
PLNSEPGAP 228600 Plane separation gap
IDFSHAPELAY 0 IDF shapes layer
TEARDROPDATA 90 90
*REUSE*
*REMARK* TYPE TYPENAME
*REMARK* TIMESTAMP SECONDS
*REMARK* PART NAMING PARTNAMING
*REMARK* PART NAME
*REMARK* NET NAMING NETNAMING
*REMARK* NET MERGE NAME
*REMARK* REUSE INSTANCENM PARTNAMING NETNAMING X Y ORI GLUED
*TEXT* FREE TEXT
*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST .REUSE. INSTANCENM
*REMARK* FONTSTYLE FONTFACE
*LINES* LINES ITEMS
*REMARK* NAME TYPE XLOC YLOC PIECES TEXT SIGSTR
*REMARK* .REUSE. INSTANCE RSIGNAL
*REMARK* PIECETYPE CORNERS WIDTHHGHT LEVEL RESTRICTIONS
*REMARK* XLOC YLOC BEGINANGLE DELTAANGLE
*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST
*CLUSTER* ITEMS
*REMARK* NAME XLOC YLOC PARENTID CLUSTERID CHILD_NUM ATTRIBUTE ATT2 BROID
*VIA* ITEMS
*REMARK* NAME DRILL STACKLINES [DRILL START] [DRILL END]
*REMARK* LEVEL SIZE SHAPE [INNER DIAMETER]
JMPVIA_AAAAA 1409700 3
-2 2095500 R
-1 2667000 R
0 2095500 R
STANDARDVIA 1409700 3
-2 2095500 R
-1 2095500 R
0 2095500 R
*PARTDECAL* ITEMS
*REMARK* NAME UNITS ORIX ORIY PIECES TERMINALS STACKS TEXT LABELS
*REMARK* PIECETYPE CORNERS WIDTHHGHT LEVEL RESTRICTIONS
*REMARK* PIECETYPE CORNERS WIDTH LEVEL PINNUM
*REMARK* XLOC YLOC BEGINANGLE DELTAANGLE
*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST
*REMARK* VISIBLE XLOC YLOC ORI LEVEL HEIGTH WIDTH MIRRORED HJUST VJUST RIGHTREADING
*REMARK* FONTSTYLE FONTFACE
*REMARK* T XLOC YLOC NMXLOC NMYLOC
*REMARK* PAD PIN STACKLINES
*REMARK* LEVEL SIZE SHAPE IDIA DRILL [PLATED]
*REMARK* LEVEL SIZE SHAPE FINORI FINLENGTH FINOFFSET DRILL [PLATED]
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A C
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RL7.1 RL1.1
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691591200 735044250 65 457200 1792 THERMAL
*SIGNAL* N01853 0 -2
U1.1 J11.1
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J11.2 J11.1
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*SIGNAL* N01894 0 -2
U1.2 J11.3
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J11.4 J11.3
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*SIGNAL* N01935 0 -2
U1.3 J11.5
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J11.6 J11.5
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*SIGNAL* N01976 0 -2
U1.4 J11.7
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J11.8 J11.7
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*SIGNAL* N02017 0 -2
U1.5 J11.10
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J11.10 J11.9
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*SIGNAL* N02058 0 -2
U1.6 J11.12
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J11.12 J11.11
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*SIGNAL* N02099 0 -2
U1.7 J11.14
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J11.14 J11.13
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*SIGNAL* N02140 0 -2
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J11.16 J11.15
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*SIGNAL* N03066 0 -2
RL1.2 U1.18
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*SIGNAL* N03225 0 -2
RL2.2 U1.17
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*SIGNAL* N03399 0 -2
RL3.2 U1.16
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*SIGNAL* N03870 0 -2
RL7.2 U1.12
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*SIGNAL* N04098 0 -2
RL6.2 U1.13
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*SIGNAL* N04420 0 -2
RL5.2 U1.14
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*SIGNAL* N04844 0 -2
RL7.4 RL1.4
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RL6.4 RL1.4
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RL5.4 RL1.4
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RL4.4 RL1.4
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RL2.4 RL1.4
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RL3.4 RL1.4
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RL1.4 RL8.4
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J9.2 RL1.4
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*SIGNAL* N06819 0 -2
J1.1 RL1.3
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*SIGNAL* N06937 0 -2
J2.1 RL2.3
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*SIGNAL* N07058 0 -2
J3.1 RL3.3
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*SIGNAL* N07182 0 -2
J4.1 RL4.3
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*SIGNAL* N07309 0 -2
J5.1 RL5.3
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*SIGNAL* N07439 0 -2
J6.1 RL6.3
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*SIGNAL* N07572 0 -2
J7.1 RL7.3
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*TESTPOINT*
*MISC* MISCELLANEOUS PARAMETERS
*REMARK* PARENT_KEYWORD PARENT_VALUE
*REMARK* [ {
*REMARK* CHILD_KEYWORD CHILD_VALUE
*REMARK* [ CHILD_KEYWORD CHILD_VALUE
*REMARK* [ {
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
*REMARK* } ]]
*REMARK* } ]
DFT_CONFIGURATION PARENT
{
UNITS MILS
PROBING_STRATEGY PARENT
{
PROBE_TOP_SIDE NO
PROBE_VIAS YES
PROBE_NO_CONNECT NO
}
DFT_RULES PARENT
{
PROBE 100
{
DRILL_SIZE 69
ENABLE NO
}
PROBE 75
{
DRILL_SIZE 43
ENABLE NO
}
PROBE 50
{
DRILL_SIZE 25
ENABLE YES
}
MIN_VIA_SIZE 25
MIN_PAD_SIZE 25
PIN_TO_PIN 6
PIN_TO_BOARD 6
PIN_TO_COMPONENT 6
}
DIF_FILE PARENT
{
VIA_PREFIX VIA
TP_PART_TYPE TP100
TP_PART_TYPE TP150
TP_PREFIX TP
TP_PREFIX PN_TP
TP_PREFIX TP_SMD
TH_PART_TYPE MTHOLE1
TH_PART_TYPE MTHOLE2
TH_PREFIX TH
TH_PREFIX MH
NC_NET N.C.
INCLUDE_TP YES
}
RETURN_OPTIONS PARENT
{
AUTO_RETURN YES
ADD_TP_VIAS_ON_RETURN YES
ADD_MULTIPLE_FOR_POWERNET NO
TP_VIA_TYPE STANDARDVIA
PPCB_NOT_CONNECTED_NET_NAME NOT_CONNECTED
}
}
LAYER DATA
{
LAYER 0
{
LAYER_THICKNESS 0
DIELECTRIC 3.300000
}
LAYER 1
{
LAYER_NAME Top
LAYER_TYPE ROUTING
PLANE NONE
ROUTING_DIRECTION HORIZONTAL
ASSOCIATED_SILK_SCREEN Silkscreen Top
ASSOCIATED_PASTE_MASK Paste Mask Top
ASSOCIATED_SOLDER_MASK Solder Mask Top
ASSOCIATED_ASSEMBLY Assembly Drawing Top
COMPONENT Y
ROUTABLE Y
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 3
VIA 3
PAD 3
COPPER 3
2DLINE 3
TEXT 3
ERROR 5
TOPCOMPONENT 1
BOTTOMCOMPONENT 0
REFDES 1
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 381000
COPPER_THICKNESS 51435
DIELECTRIC 4.300000
COST 0
}
LAYER 2
{
LAYER_NAME Bottom
LAYER_TYPE ROUTING
PLANE NONE
ROUTING_DIRECTION VERTICAL
ASSOCIATED_SILK_SCREEN Silkscreen Bottom
ASSOCIATED_PASTE_MASK Paste Mask Bottom
ASSOCIATED_SOLDER_MASK Solder Mask Bottom
ASSOCIATED_ASSEMBLY Assembly Drawing Bottom
COMPONENT Y
ROUTABLE Y
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 11
VIA 11
PAD 11
COPPER 11
2DLINE 11
TEXT 11
ERROR 13
TOPCOMPONENT 0
BOTTOMCOMPONENT 14
REFDES 14
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 51435
DIELECTRIC 3.300000
COST 0
}
LAYER 3
{
LAYER_NAME Layer_3
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 4
{
LAYER_NAME Layer_4
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 5
{
LAYER_NAME Layer_5
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 6
{
LAYER_NAME Layer_6
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 7
{
LAYER_NAME Layer_7
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 8
{
LAYER_NAME Layer_8
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 9
{
LAYER_NAME Layer_9
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 10
{
LAYER_NAME Layer_10
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 11
{
LAYER_NAME Layer_11
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 12
{
LAYER_NAME Layer_12
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 13
{
LAYER_NAME Layer_13
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 14
{
LAYER_NAME Layer_14
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 15
{
LAYER_NAME Layer_15
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 16
{
LAYER_NAME Layer_16
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 17
{
LAYER_NAME Layer_17
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 18
{
LAYER_NAME Layer_18
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 19
{
LAYER_NAME Layer_19
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 20
{
LAYER_NAME Layer_20
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 21
{
LAYER_NAME Solder Mask Top
LAYER_TYPE SOLDER_MASK
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 22
{
LAYER_NAME Paste Mask Bottom
LAYER_TYPE PASTE_MASK
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 23
{
LAYER_NAME Paste Mask Top
LAYER_TYPE PASTE_MASK
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 24
{
LAYER_NAME Drill Drawing
LAYER_TYPE DRILL
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 5
TEXT 5
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 25
{
LAYER_NAME Layer_25
LAYER_TYPE UNASSIGNED
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 26
{
LAYER_NAME Silkscreen Top
LAYER_TYPE SILK_SCREEN
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 27
{
LAYER_NAME Assembly Drawing Top
LAYER_TYPE ASSEMBLY
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 28
{
LAYER_NAME Solder Mask Bottom
LAYER_TYPE SOLDER_MASK
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 29
{
LAYER_NAME Silkscreen Bottom
LAYER_TYPE SILK_SCREEN
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
LAYER 30
{
LAYER_NAME Assembly Drawing Bottom
LAYER_TYPE ASSEMBLY
PLANE NONE
ROUTING_DIRECTION NO_PREFERENCE
VISIBLE Y
SELECTABLE Y
ENABLED Y
COLORS :
{
ROUTE 0
VIA 0
PAD 0
COPPER 0
2DLINE 0
TEXT 0
ERROR 0
TOPCOMPONENT 0
BOTTOMCOMPONENT 0
REFDES 0
PARTTYPE 0
ATTRIBUTE 0
KEEPOUT 0
}
LAYER_THICKNESS 0
COPPER_THICKNESS 0
DIELECTRIC 0.000000
COST 0
}
}
SELECTABILITY DATA
{
PARTS Y
PINS Y
TRACES Y
VIAS Y
TACKS Y
UNROUTED Y
EDGES Y
NODES Y
SHAPES Y
DIMENSIONS Y
TEXT Y
AREA_PARTS Y
AREA_PINS Y
AREA_TRACES Y
AREA_VIAS Y
AREA_TACKS Y
AREA_UNROUTED Y
AREA_EDGES Y
AREA_NODES Y
AREA_SHAPES Y
AREA_DIMENSIONS Y
AREA_TEXT Y
}
VISIBILITY DATA
{
PADS Y
TRACKS Y
VIAS Y
COPPER Y
LINES Y
TEXT Y
ERRORS Y
CLUSTER Y
TOP_COMPONENT Y
BOTTOM_COMPONENT Y
PLANE_THERMAL Y
REFDES Y
PARTTYPES Y
ATTRIBUTES Y
KEEPOUTS Y
SELECTION_COLOR 15
HIGHLIGHT_COLOR 14
FIXED_COLOR 3
FONT_FACE <Romansim Stroke Font>
{
}
}
*MISC* MISCELLANEOUS PARAMETERS
*REMARK* PARENT_KEYWORD PARENT_VALUE
*REMARK* [ {
*REMARK* CHILD_KEYWORD CHILD_VALUE
*REMARK* [ CHILD_KEYWORD CHILD_VALUE
*REMARK* [ {
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
*REMARK* } ]]
*REMARK* } ]
RULES_SECTION PARENT
{
NET_CLASS DATA
GROUP DATA
DESIGN RULES
{
RULE_SET (1)
{
FOR :
{
DEFAULT :
}
AGAINST :
{
DEFAULT :
}
LAYER 0
CLEARANCE_RULE :
{
TRACK_TO_TRACK 228600
VIA_TO_TRACK 228600
VIA_TO_VIA 228600
PAD_TO_TRACK 228600
PAD_TO_VIA 228600
PAD_TO_PAD 228600
SMD_TO_TRACK 228600
SMD_TO_VIA 228600
SMD_TO_PAD 228600
SMD_TO_SMD 228600
COPPER_TO_TRACK 228600
COPPER_TO_VIA 228600
COPPER_TO_PAD 228600
COPPER_TO_SMD 228600
COPPER_TO_COPPER 228600
TEXT_TO_TRACK 228600
TEXT_TO_VIA 228600
TEXT_TO_PAD 228600
TEXT_TO_SMD 228600
OUTLINE_TO_TRACK 228600
OUTLINE_TO_VIA 228600
OUTLINE_TO_PAD 228600
OUTLINE_TO_SMD 228600
OUTLINE_TO_COPPER 228600
DRILL_TO_TRACK 228600
DRILL_TO_VIA 228600
DRILL_TO_PAD 228600
DRILL_TO_SMD 228600
DRILL_TO_COPPER 228600
SAME_NET_SMD_TO_VIA 228600
SAME_NET_SMD_TO_CRN 228600
SAME_NET_VIA_TO_VIA 228600
SAME_NET_PAD_TO_CRN 228600
MIN_TRACK_WIDTH 457200
REC_TRACK_WIDTH 457200
MAX_TRACK_WIDTH 457200
DRILL_TO_DRILL 228600
BODY_TO_BODY 228600
SAME_NET_TRACK_TO_CRN 0
}
}
RULE_SET (2)
{
FOR :
{
DEFAULT :
}
AGAINST :
{
DEFAULT :
}
LAYER 0
HIGH_SPEED_RULE :
{
MIN_LENGTH 0
MAX_LENGTH 1904999936
STUB_LENGTH 0
PARALLEL_LENGTH 38100000
PARALLEL_GAP 7620000
TANDEM_LENGTH 38100000
TANDEM_GAP 7620000
MIN_DELAY 0.000000
MAX_DELAY 10.000000
MIN_CAPACITANCE 0.000000
MAX_CAPACITANCE 10.000000
MIN_IMPEDANCE 50.000000
MAX_IMPEDANCE 150.000000
SHIELD_NET *
SHIELD_GAP 7620000
MATCH_LENGTH_TOLERANCE 7620000
}
}
RULE_SET (3)
{
FOR :
{
DEFAULT :
}
AGAINST :
{
DEFAULT :
}
LAYER 0
ROUTE_RULE :
{
LENGTH_MINIMIZATION_TYPE 1
VIA_SHARE Y
TRACE_SHARE Y
AUTO_ROUTE Y
RIPUP Y
SHOVE Y
ROUTE_PRIORITY 3
MAX_NUMBER_OF_VIAS -1
VALID_LAYER 1
VALID_LAYER 2
VALID_VIA_TYPE STANDARDVIA
}
}
}
}
*MISC* MISCELLANEOUS PARAMETERS
*REMARK* PARENT_KEYWORD PARENT_VALUE
*REMARK* [ {
*REMARK* CHILD_KEYWORD CHILD_VALUE
*REMARK* [ CHILD_KEYWORD CHILD_VALUE
*REMARK* [ {
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
*REMARK* } ]]
*REMARK* } ]
CAM_SECTION PARENT
{
CAM_VERSION V2005.0
CAM_DOC_LIST PARENT
{
}
CAM_AUGMENT_ON_THE_FLY Y
CAM_DRILL_SYMBOL_TABLE_EXTENDED PARENT
{
MARKER_SIZE 3048000
MARKER_LINE_WIDTH 381000
MARKER_CHAR_HEIGHT 1905000
CHART_TEXT_HEIGHT 4572000
CHART_LINE_WIDTH 381000
SIZE_VALUES_SORTING_ORDER 0
QUANTITY_VALUES_SORTING_ORDER 0
PLATED_VALUES_SORTING_ORDER 0
DEFAULT_TOLERANCE +/-0.0
DRILL_UNIT 0
}
}
*MISC* MISCELLANEOUS PARAMETERS
*REMARK* PARENT_KEYWORD PARENT_VALUE
*REMARK* [ {
*REMARK* CHILD_KEYWORD CHILD_VALUE
*REMARK* [ CHILD_KEYWORD CHILD_VALUE
*REMARK* [ {
*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...]
*REMARK* } ]]
*REMARK* } ]
*MISC* MISCELLANEOUS PARAMETERS
ATTRIBUTES DICTIONARY
{
ATTRIBUTE Rules.Fanout.Alignment
{
TYPE LIST N
{
Aligned
Alternate
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Alignment.Multi-Row
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Direction
{
TYPE LIST N
{
Inside
Outside
Both Sides
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.ViaSpacing
{
TYPE LIST N
{
Use Grid
1 Trace
2 Trace
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Sharing.Pin
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Sharing.SMD
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Sharing.Via
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Sharing.Trace
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Nets.Plane
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Nets.Signal
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Nets.UnusedPins
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Length.Unlimited
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.Length.Maximum
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.AlignmentBGA
{
TYPE LIST N
{
Quadrant
Diagonal
X-pattern
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.DirectionBGA
{
TYPE LIST N
{
45
135
225
315
Clockwise
Counterclockwise
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Fanout.DirectionBGAstaggered
{
TYPE LIST N
{
Horizontal
Vertical
}
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.PadEntry.Side
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.PadEntry.Corner
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.PadEntry.AnyAngle
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.PadEntry.Soft
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.ViaAtSMD
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.ViaAtSMD.FitInside
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.ViaAtSMD.Center
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.ViaAtSMD.Ends
{
TYPE BOOLEAN
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Trace.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Via.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Via.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Pad.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Pad.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Pad.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.SMD.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.SMD.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.SMD.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.SMD.SMD
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Copper.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Copper.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Copper.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Copper.SMD
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Text.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Text.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Text.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Text.SMD
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Board.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Board.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Board.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Board.SMD
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Drill.Trace
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Drill.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Drill.Pad
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Clearance.Drill.SMD
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.SameNet.SMD.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.SameNet.SMD.Crn
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.SameNet.Via.Via
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.SameNet.Pad.Crn
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.SameNet.Trace.Crn
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Width.Minimum
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 9525000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Width.Recommended
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 9525000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Rules.Width.Maximum
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 9525000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Value
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE Tolerance
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE Part Number
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM N
HIDDEN N
}
ATTRIBUTE Description
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE DECAL
ECO_REGISTRATION Y
READONLY N
SYSTEM N
HIDDEN N
}
ATTRIBUTE Cost
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM N
HIDDEN N
}
ATTRIBUTE Manufacturer #1
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM N
HIDDEN N
}
ATTRIBUTE Manufacturer #2
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM N
HIDDEN N
}
ATTRIBUTE ASSEMBLY_OPTIONS
{
TYPE FREETEXT N
INHERITANCE PCB
INHERITANCE PART
INHERITANCE JUMPER
ECO_REGISTRATION Y
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE PowerGround
{
TYPE BOOLEAN
INHERITANCE NET NETCLASS PCB
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE Voltage
{
TYPE QUANTITY
QUANTITY Voltage
ABBR V
UNIT Volt
MIN -100kV
MAX 100kV
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE Geometry.Height
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 952500000dbunit
INHERITANCE PCB
INHERITANCE PART PARTTYPE DECAL
ECO_REGISTRATION N
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE DFT.Nail Count Per Net
{
TYPE INTEGER
MIN 0
MAX 1000
INHERITANCE NET NETCLASS PCB
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE DFT.Nail Diameter
{
TYPE FREETEXT N
INHERITANCE PIN
INHERITANCE VIA
ECO_REGISTRATION N
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE DFT.Nail Number
{
TYPE FREETEXT N
INHERITANCE PIN
INHERITANCE VIA
ECO_REGISTRATION N
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE DFT.Probe to Trace Clearance
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Probe to Pad Clearance
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 38100000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Generate Test Points
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Allow Stubs
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Stub Length
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Use Via Grid
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Grid X-Coordinate
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Grid Y-Coordinate
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Preserve Test Points
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Insert Test Point Vias
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DFT.Probe Pins
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE HyperLynx.Model
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Model File
{
TYPE FREETEXT N
INHERITANCE PART PARTTYPE
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Sim Direction
{
TYPE LIST N
{
SIM_BOTH
SIM_IN
SIM_OUT
}
INHERITANCE PIN
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Frequency
{
TYPE QUANTITY
QUANTITY Frequency
ABBR Hz
UNIT Hertz
MIN 0Hz
MAX 1000GHz
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Duty Cycle
{
TYPE QUANTITY
QUANTITY
ABBR %
UNIT percent
MIN 0%
MAX 100%
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Signal Type
{
TYPE LIST N
{
Address
Analog High Speed
Analog Low Speed
Clock
Data
Do Not Analyze
Power Supply
Strobe
}
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Default IC.Model
{
TYPE FREETEXT N
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Default IC.Model File
{
TYPE FREETEXT N
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE HyperLynx.Default IC.Model Pin
{
TYPE FREETEXT N
INHERITANCE NET NETCLASS
ECO_REGISTRATION Y
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE Strategy.Fanout.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Fanout.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Patterns.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Route.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Optimize.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Miters.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.TestPoint.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Center.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.Pass
{
TYPE LIST N
{
No
Yes
Done
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.Protect
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.Pause
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.Intensity
{
TYPE LIST N
{
Low
Medium
High
}
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.PlanePriority
{
TYPE INTEGER
MIN 0
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.Priority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PART
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.DiffPairPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET
INHERITANCE PINPAIR
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Strategy.Tune.MLGPriority
{
TYPE INTEGER
MIN 0
INHERITANCE NET NETCLASS PCB
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.FormatId
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.ChipLength
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.ChipWidth
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.ChipHeight
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBRules.MinLength
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBRules.MaxLength
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBRules.WToWDistance
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBRules.WBtoPad
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBRules.MaxAngle
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.SBPCount
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.SBP1
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.CBPCount
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.CBP1
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WBCount
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.WB1
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.SBPGuideCount
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.SBPGuide1
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE DIE.CBPAssignment1
{
TYPE FREETEXT N
INHERITANCE DECAL
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Marker_Shape
{
TYPE FREETEXT N
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Text_NumberPrecision
{
TYPE FREETEXT N
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Text_AngularPrecision
{
TYPE FREETEXT N
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Text_Suffix
{
TYPE FREETEXT N
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Text_Layer
{
TYPE INTEGER
MIN 0
MAX 250
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Line_Layer
{
TYPE INTEGER
MIN 0
MAX 250
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE AutoDimensioning.Preview_Type
{
TYPE INTEGER
MIN 1
MAX 5
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Placement.Grid.Use
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Placement.Grid.X
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Placement.Grid.Y
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 76200000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Accordion.Amplitude.Min
{
TYPE INTEGER
MIN 3
MAX 30
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Accordion.Gap.Min
{
TYPE INTEGER
MIN 1
MAX 10
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Routing.MaxChannelWidth
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN 0dbunit
MAX 381000000dbunit
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Routing.SoftLengthRrules
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Routing.MeanderBeforeTune
{
TYPE BOOLEAN
INHERITANCE PCB
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE MatchLength.Name
{
TYPE FREETEXT N
INHERITANCE NET NETCLASS
INHERITANCE PINPAIR GROUP
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Planning.Scheduled
{
TYPE BOOLEAN
INHERITANCE NET
ECO_REGISTRATION Y
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Library.Timestamp
{
TYPE FREETEXT N
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE Design.Timestamp
{
TYPE FREETEXT N
ECO_REGISTRATION N
READONLY Y
SYSTEM Y
HIDDEN Y
}
ATTRIBUTE CAM.Solder mask.Adjust
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN -9525000dbunit
MAX 9525000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
INHERITANCE VIA
ECO_REGISTRATION N
READONLY N
SYSTEM Y
HIDDEN N
}
ATTRIBUTE CAM.Paste mask.Adjust
{
TYPE QUANTITY
QUANTITY Size/Dimension
ABBR
UNIT
MIN -9525000dbunit
MAX 9525000dbunit
INHERITANCE PCB
INHERITANCE PART DECAL
INHERITANCE VIA
ECO_REGISTRATION N
READONLY N
SYSTEM Y
HIDDEN N
}
}
ATTRIBUTE VALUES
{
PART C1
{
Value 100UF/25V
}
PART D1
{
Value 1N4007
}
PART J1
{
Value ARK210/2
}
PART J10
{
Value JUMP2X4
}
PART J11
{
Value JUMP2X8
}
PART J2
{
Value ARK210/2
}
PART J3
{
Value ARK210/2
}
PART J4
{
Value ARK210/2
}
PART J5
{
Value ARK210/2
}
PART J6
{
Value ARK210/2
}
PART J7
{
Value ARK210/2
}
PART J8
{
Value ARK210/2
}
PART J9
{
Value ARK210/2
}
PART RL1
{
Value RELAY_FTR-F3
}
PART RL2
{
Value RELAY_FTR-F3
}
PART RL3
{
Value RELAY_FTR-F3
}
PART RL4
{
Value RELAY_FTR-F3
}
PART RL5
{
Value RELAY_FTR-F3
}
PART RL6
{
Value RELAY_FTR-F3
}
PART RL7
{
Value RELAY_FTR-F3
}
PART RL8
{
Value RELAY_FTR-F3
}
PART U1
{
Value DIP18_300
}
DECAL ELYTA
{
Description elektrolyt SMD velikost A
Geometry.Height 1.8 mm
}
DECAL ELYTB
{
Description elektrolyt SMD velikost B
Geometry.Height 2 mm
}
DECAL ELYTC
{
Description elektrolyt SMD velikost C
Geometry.Height 2.8 mm
}
DECAL ELYTD
{
Description elektrolyt SMD velikost D
Geometry.Height 3 mm
}
DECAL CE020X5
{
Description Elyt prumer 5mm, roztec 2.032mm - 80 mils
Geometry.Height 12 mm
}
DECAL CE025X6
{
Description Elyt prumer 6.3mm, roztec 2.54mm - 100 mils
Geometry.Height 12 mm
}
DECAL CE035X8
{
Description Elyt prumer 8 mm, roztec3.505 mm - 138 mils
Geometry.Height 12 mm
}
DECAL CE050X10
{
Description Elyt prumer 10mm, roztec 5.08mm - 200 mils
Geometry.Height 17 mm
}
DECAL CE050X13
{
Description Elyt prumer 13mm, roztec 5.08mm - 200 mils
Geometry.Height 27 mm
}
DECAL CE075X16
{
Description Elyt prumer 16mm, roztec 7.5mm - 300 mils
Geometry.Height 26 mm
}
DECAL CE075X18
{
Description Elyt prumer 18mm, roztec 7.5mm - 300 mils
Geometry.Height 43 mm
}
DECAL CE020X5/L
{
Description Elyt prumer 5mm na lezato, roztec 2.032mm - 80 mils
Geometry.Height 5.5 mm
}
DECAL CE025X6/L
{
Description Elyt prumer 6.3mm na lezato, roztec 2.54mm - 100 mils
Geometry.Height 6.5 mm
}
DECAL CE035X8/L
{
Description Elyt prumer 8 mm na lezato, roztec3.505 mm - 138 mils
Geometry.Height 8.5 mm
}
DECAL CE050X10/L
{
Description Elyt prumer 10mm na lezato, roztec 5.08mm - 200 mils
Geometry.Height 10.5 mm
}
DECAL SOD87
{
Description dioda SMD v pouzdre SOD87
Geometry.Height 1.8 mm
}
DECAL DO201
{
Description usm. dioda nad 1A roztec 13.97mm, 550mils
Geometry.Height 10mm
}
DECAL DO41
{
Description usm. dioda do 1A roztec 8.89mm, 350mils
Geometry.Height 3.5mm
}
DECAL MELF
{
Description dioda SMD v pouzdre MELF
Geometry.Height 3 mm
}
DECAL MINIMELF
{
Description dioda SMD v pouzdre MINIMELF
Geometry.Height 1.8 mm
}
DECAL DO35
{
Description vseob. dioda roztec 6.35mm, 250mils
Geometry.Height 3.5mm
}
DECAL DS040
{
Description dioda nastojato, roztec 3.81 mm ,150 mils
Geometry.Height 15mm
}
DECAL TO220AC
{
Description diodove pouzdro TO220AC
Geometry.Height 20mm
}
DECAL TO220AB
{
Description diodove pouzdro TO220AB
Geometry.Height 20mm
}
DECAL SMA
{
Description SMD dioda v pouzdre SMA
Geometry.Height 2.5mm
}
DECAL SMB
{
Description SMD dioda v pouzdre SMB
Geometry.Height 2.5mm
}
DECAL SMC
{
Description SMD dioda v pouzdre SMC
Geometry.Height 2.8mm
}
DECAL ARK210/2
{
Description svorkovnice se dvema piny, roztec 5.08 mm - 200 mils
Geometry.Height 13 mm
}
DECAL JUMP2X4
{
Description dvourady hrebinek 2x4 piny
Geometry.Height 10 mm
}
DECAL JUMP2X8
{
Description dvourady hrebinek 2x8 pinu
Geometry.Height 10 mm
}
DECAL RELAY_FTR-F3
{
Description Rele Fujitsu-Siemens 1x spinaci kontakt
Geometry.Height 15.5 mm
}
DECAL DIP18_300
{
Description pouzdro DIP18 roztec 7.62 mm - 300 mils
Geometry.Height 6 mm
}
PARTTYPE C-ELYT
{
Description ruzne druhy elektrolytickych kondenzatoru
}
PARTTYPE D
{
Description ruzne druhy diod
}
PCB DEFAULT
{
Accordion.Amplitude.Min 3
Accordion.Gap.Min 1
AutoDimensioning.Line_Layer 24
AutoDimensioning.Marker_Shape YYNNNY
AutoDimensioning.Preview_Type 1
AutoDimensioning.Text_AngularPrecision 0 0 0
AutoDimensioning.Text_Layer 24
AutoDimensioning.Text_NumberPrecision 0 1 2
AutoDimensioning.Text_Suffix mil##mm##"
"DFT.Allow Stubs" Yes
"DFT.Generate Test Points" No
"DFT.Grid X-Coordinate" 952500dbunit
"DFT.Grid Y-Coordinate" 952500dbunit
"DFT.Insert Test Point Vias" No
"DFT.Preserve Test Points" No
"DFT.Probe Pins" Yes
"DFT.Probe to Pad Clearance" 228600dbunit
"DFT.Probe to Trace Clearance" 228600dbunit
"DFT.Stub Length" 19050000dbunit
"DFT.Use Via Grid" Yes
Placement.Grid.Use No
Placement.Grid.X 3810000dbunit
Placement.Grid.Y 3810000dbunit
Routing.MaxChannelWidth 3810000dbunit
Routing.MeanderBeforeTune No
Routing.SoftLengthRrules Yes
Rules.ViaAtSMD No
Rules.Fanout.Length.Maximum 9525000dbunit
Rules.Fanout.Length.Unlimited Yes
Rules.Fanout.Nets.Plane Yes
Rules.Fanout.Nets.Signal No
Rules.Fanout.Nets.UnusedPins No
Rules.Fanout.Sharing.Pin Yes
Rules.Fanout.Sharing.SMD Yes
Rules.Fanout.Sharing.Trace No
Rules.Fanout.Sharing.Via Yes
Rules.PadEntry.AnyAngle Yes
Rules.PadEntry.Corner Yes
Rules.PadEntry.Side Yes
Rules.PadEntry.Soft Yes
Rules.ViaAtSMD.Center Yes
Rules.ViaAtSMD.Ends Yes
Rules.ViaAtSMD.FitInside Yes
}
}
*END* OF ASCII OUTPUT FILE