Subversion Repositories – MLAB

(root)/Modules/Translators/SPIDIFF01A/SCH_PCB/SPIDIFF01A.kicad_pcb @ 4791

Rev 4772

(kicad_pcb (version 20160815) (host pcbnew 4.1.0-alpha+201609050731+7118~50~ubuntu16.04.1-product)

  (general
    (links 132)
    (no_connects 0)
    (area 0 0 0 0)
    (thickness 1.6)
    (drawings 0)
    (tracks 0)
    (zones 0)
    (modules 0)
    (nets 1)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.25)
    (user_trace_width 0.25)
    (user_trace_width 0.3)
    (user_trace_width 0.4)
    (user_trace_width 0.5)
    (user_trace_width 0.6)
    (user_trace_width 0.7)
    (user_trace_width 0.8)
    (user_trace_width 0.9)
    (trace_clearance 0.2)
    (zone_clearance 0.2)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.1)
    (via_size 0.89)
    (via_drill 0.5)
    (via_min_size 0.7)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.127)
    (uvias_allowed no)
    (uvia_min_size 0.3)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.5 1.5)
    (pad_drill 0.6)
    (pad_to_mask_clearance 0.12)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFF7F)
    (pcbplotparams
      (layerselection 0x010e0_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.300000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory ../CAM_PROFI/))
  )

  (net 0 "")

  (net_class Default "Toto je výchozí třída sítě."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.89)
    (via_drill 0.5)
    (uvia_dia 0.3)
    (uvia_drill 0.127)
    (diff_pair_gap 0.25)
    (diff_pair_width 0.2)
    (add_net /EN)
    (add_net /INT)
    (add_net /PIDENT)
    (add_net /READY)
    (add_net /VDD1)
    (add_net /VDD2)
    (add_net /VddA)
    (add_net /VddB)
    (add_net GND)
    (add_net "Net-(C8-Pad1)")
    (add_net "Net-(J14-Pad2)")
    (add_net "Net-(J2-Pad10)")
    (add_net "Net-(J2-Pad12)")
    (add_net SCL)
    (add_net SDA)
    (add_net VCC)
    (add_net VDD)
  )

  (net_class dif ""
    (clearance 0.2)
    (trace_width 0.4)
    (via_dia 0.89)
    (via_drill 0.5)
    (uvia_dia 0.3)
    (uvia_drill 0.127)
    (diff_pair_gap 0.25)
    (diff_pair_width 0.2)
    (add_net /INT+)
    (add_net /INT-)
    (add_net /SCL+)
    (add_net /SCL-)
    (add_net /SDA+)
    (add_net /SDA-)
  )

)