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_DATAINPUTQUEUE_DECLchOQGetFullIchOQGetEmptyIchOQIsEmptyIchOQIsFullIchOQPut_OUTPUTQUEUE_DATAOUTPUTQUEUE_DECLchstreams.h_CHSTREAMS_H__base_sequential_stream_methods_base_sequential_stream_datachSequentialStreamWritechSequentialStreamReadchSequentialStreamPutchSequentialStreamGetchfiles.h_CHFILES_H_FILE_OKFILE_ERROR_base_file_stream_methods_base_file_stream_datachFileStreamClosechFileStreamGetErrorchFileStreamGetSizechFileStreamGetPositionchFileStreamSeekchdebug.h_CHDEBUG_H_CH_DBG_ENABLED__QUOTE_THISCH_TRACE_BUFFER_SIZECH_STACK_FILL_VALUECH_THREAD_FILL_VALUEdbg_enter_lockdbg_leave_lockdbg_check_disabledbg_check_suspenddbg_check_enabledbg_check_lockdbg_check_unlockdbg_check_lock_from_isrdbg_check_unlock_from_isrdbg_check_enter_isrdbg_check_leave_isrchDbgCheckClassIchDbgCheckClassSdbg_tracechDbgCheckchDbgAssertchDbgPanichal.h_HAL_H_board.h_BOARD_H_BOARD_ST_STM32L_DISCOVERYBOARD_NAMESTM32_LSECLKSTM32_HSECLKSTM32_HSE_BYPASSSTM32L1XX_MDGPIOA_BUTTONGPIOA_PIN1GPIOA_PIN2GPIOA_PIN3GPIOA_PIN4GPIOA_PIN5GPIOA_PIN6GPIOA_PIN7GPIOA_PIN8GPIOA_PIN9GPIOA_PIN10GPIOA_PIN11GPIOA_PIN12GPIOA_JTAG_TMSGPIOA_JTAG_TCKGPIOA_JTAG_TDIGPIOB_PIN0GPIOB_PIN1GPIOB_BOOT1GPIOB_JTAG_TDOGPIOB_JTAG_TRSTGPIOB_PIN5GPIOB_LED4GPIOB_LED3GPIOB_PIN8GPIOB_PIN9GPIOB_PIN10GPIOB_PIN11GPIOB_PIN12GPIOB_PIN13GPIOB_PIN14GPIOB_PIN15GPIOC_PIN0GPIOC_PIN1GPIOC_PIN2GPIOC_PIN3GPIOC_PIN4GPIOC_PIN5GPIOC_PIN6GPIOC_PIN7GPIOC_PIN8GPIOC_PIN9GPIOC_PIN10GPIOC_PIN11GPIOC_PIN12GPIOC_PIN13GPIOC_OSC32_INGPIOC_OSC32_OUTGPIOD_PIN0GPIOD_PIN1GPIOD_PIN2GPIOD_PIN3GPIOD_PIN4GPIOD_PIN5GPIOD_PIN6GPIOD_PIN7GPIOD_PIN8GPIOD_PIN9GPIOD_PIN10GPIOD_PIN11GPIOD_PIN12GPIOD_PIN13GPIOD_PIN14GPIOD_PIN15GPIOE_PIN0GPIOE_PIN1GPIOE_PIN2GPIOE_PIN3GPIOE_PIN4GPIOE_PIN5GPIOE_PIN6GPIOE_PIN7GPIOE_PIN8GPIOE_PIN9GPIOE_PIN10GPIOE_PIN11GPIOE_PIN12GPIOE_PIN13GPIOE_PIN14GPIOE_PIN15GPIOH_OSC_INGPIOH_OSC_OUTGPIOH_PIN2GPIOH_PIN3GPIOH_PIN4GPIOH_PIN5GPIOH_PIN6GPIOH_PIN7GPIOH_PIN8GPIOH_PIN9GPIOH_PIN10GPIOH_PIN11GPIOH_PIN12GPIOH_PIN13GPIOH_PIN14GPIOH_PIN15PIN_MODE_INPUTPIN_MODE_OUTPUTPIN_MODE_ALTERNATEPIN_MODE_ANALOGPIN_ODR_LOWPIN_ODR_HIGHPIN_OTYPE_PUSHPULLPIN_OTYPE_OPENDRAINPIN_OSPEED_400KPIN_OSPEED_2MPIN_OSPEED_10MPIN_OSPEED_40MPIN_PUPDR_FLOATINGPIN_PUPDR_PULLUPPIN_PUPDR_PULLDOWNPIN_AFIO_AFVAL_GPIOA_MODERVAL_GPIOA_OTYPERVAL_GPIOA_OSPEEDRVAL_GPIOA_PUPDRVAL_GPIOA_ODRVAL_GPIOA_AFRLVAL_GPIOA_AFRHVAL_GPIOB_MODERVAL_GPIOB_OTYPERVAL_GPIOB_OSPEEDRVAL_GPIOB_PUPDRVAL_GPIOB_ODRVAL_GPIOB_AFRLVAL_GPIOB_AFRHVAL_GPIOC_MODERVAL_GPIOC_OTYPERVAL_GPIOC_OSPEEDRVAL_GPIOC_PUPDRVAL_GPIOC_ODRVAL_GPIOC_AFRLVAL_GPIOC_AFRHVAL_GPIOD_MODERVAL_GPIOD_OTYPERVAL_GPIOD_OSPEEDRVAL_GPIOD_PUPDRVAL_GPIOD_ODRVAL_GPIOD_AFRLVAL_GPIOD_AFRHVAL_GPIOE_MODERVAL_GPIOE_OTYPERVAL_GPIOE_OSPEEDRVAL_GPIOE_PUPDRVAL_GPIOE_ODRVAL_GPIOE_AFRLVAL_GPIOE_AFRHVAL_GPIOH_MODERVAL_GPIOH_OTYPERVAL_GPIOH_OSPEEDRVAL_GPIOH_PUPDRVAL_GPIOH_ODRVAL_GPIOH_AFRLVAL_GPIOH_AFRHhalconf.h_HALCONF_H_mcuconf.hSTM32L1xx_MCUCONFSTM32_NO_INITSTM32_HSI_ENABLEDSTM32_LSI_ENABLEDSTM32_HSE_ENABLEDSTM32_LSE_ENABLEDSTM32_ADC_CLOCK_ENABLEDSTM32_USB_CLOCK_ENABLEDSTM32_MSIRANGESTM32_SWSTM32_PLLSRCSTM32_PLLMUL_VALUESTM32_PLLDIV_VALUESTM32_HPRESTM32_PPRE1STM32_PPRE2STM32_MCOSELSTM32_MCOPRESTM32_RTCSELSTM32_RTCPRESTM32_VOSSTM32_PVD_ENABLESTM32_PLSSTM32_ADC_USE_ADC1STM32_ADC_ADC1_DMA_PRIORITYSTM32_ADC_IRQ_PRIORITYSTM32_ADC_ADC1_DMA_IRQ_PRIORITYSTM32_EXT_EXTI0_IRQ_PRIORITYSTM32_EXT_EXTI1_IRQ_PRIORITYSTM32_EXT_EXTI2_IRQ_PRIORITYSTM32_EXT_EXTI3_IRQ_PRIORITYSTM32_EXT_EXTI4_IRQ_PRIORITYSTM32_EXT_EXTI5_9_IRQ_PRIORITYSTM32_EXT_EXTI10_15_IRQ_PRIORITYSTM32_EXT_EXTI16_IRQ_PRIORITYSTM32_EXT_EXTI17_IRQ_PRIORITYSTM32_EXT_EXTI18_IRQ_PRIORITYSTM32_EXT_EXTI19_IRQ_PRIORITYSTM32_EXT_EXTI20_IRQ_PRIORITYSTM32_EXT_EXTI21_22_IRQ_PRIORITYSTM32_GPT_USE_TIM2STM32_GPT_USE_TIM3STM32_GPT_USE_TIM4STM32_GPT_TIM2_IRQ_PRIORITYSTM32_GPT_TIM3_IRQ_PRIORITYSTM32_GPT_TIM4_IRQ_PRIORITYSTM32_I2C_USE_I2C1STM32_I2C_USE_I2C2STM32_I2C_I2C1_IRQ_PRIORITYSTM32_I2C_I2C2_IRQ_PRIORITYSTM32_I2C_I2C1_DMA_PRIORITYSTM32_I2C_I2C2_DMA_PRIORITYSTM32_I2C_I2C1_DMA_ERROR_HOOKSTM32_I2C_I2C2_DMA_ERROR_HOOKSTM32_ICU_USE_TIM2STM32_ICU_USE_TIM3STM32_ICU_USE_TIM4STM32_ICU_TIM2_IRQ_PRIORITYSTM32_ICU_TIM3_IRQ_PRIORITYSTM32_ICU_TIM4_IRQ_PRIORITYSTM32_PWM_USE_TIM2STM32_PWM_USE_TIM3STM32_PWM_USE_TIM4STM32_PWM_TIM2_IRQ_PRIORITYSTM32_PWM_TIM3_IRQ_PRIORITYSTM32_PWM_TIM4_IRQ_PRIORITYSTM32_SERIAL_USE_USART1STM32_SERIAL_USE_USART2STM32_SERIAL_USE_USART3STM32_SERIAL_USART1_PRIORITYSTM32_SERIAL_USART2_PRIORITYSTM32_SERIAL_USART3_PRIORITYSTM32_SPI_USE_SPI1STM32_SPI_USE_SPI2STM32_SPI_SPI1_DMA_PRIORITYSTM32_SPI_SPI2_DMA_PRIORITYSTM32_SPI_SPI1_IRQ_PRIORITYSTM32_SPI_SPI2_IRQ_PRIORITYSTM32_SPI_DMA_ERROR_HOOKSTM32_UART_USE_USART1STM32_UART_USE_USART2STM32_UART_USE_USART3STM32_UART_USART1_IRQ_PRIORITYSTM32_UART_USART2_IRQ_PRIORITYSTM32_UART_USART3_IRQ_PRIORITYSTM32_UART_USART1_DMA_PRIORITYSTM32_UART_USART2_DMA_PRIORITYSTM32_UART_USART3_DMA_PRIORITYSTM32_UART_DMA_ERROR_HOOKSTM32_USB_USE_USB1STM32_USB_LOW_POWER_ON_SUSPENDSTM32_USB_USB1_HP_IRQ_PRIORITYSTM32_USB_USB1_LP_IRQ_PRIORITYHAL_USE_TMHAL_USE_PALHAL_USE_ADCHAL_USE_CANHAL_USE_EXTHAL_USE_GPTHAL_USE_I2CHAL_USE_ICUHAL_USE_MACHAL_USE_MMC_SPIHAL_USE_PWMHAL_USE_RTCHAL_USE_SDCHAL_USE_SERIALHAL_USE_SERIAL_USBHAL_USE_SPIHAL_USE_UARTHAL_USE_USBADC_USE_WAITADC_USE_MUTUAL_EXCLUSIONCAN_USE_SLEEP_MODEI2C_USE_MUTUAL_EXCLUSIONMAC_USE_ZERO_COPYMAC_USE_EVENTSMMC_NICE_WAITINGSDC_INIT_RETRYSDC_MMC_SUPPORTSDC_NICE_WAITINGSERIAL_DEFAULT_BITRATESERIAL_BUFFERS_SIZESPI_USE_WAITSPI_USE_MUTUAL_EXCLUSIONhal_lld.h_HAL_LLD_H_stm32.h_STM32_H_stm32l1xx.h__STM32L1XX_HHSE_VALUEHSE_STARTUP_TIMEOUTHSI_STARTUP_TIMEOUTHSI_VALUELSI_VALUELSE_VALUE__STM32L1XX_STDPERIPH_VERSION_MAIN__STM32L1XX_STDPERIPH_VERSION_SUB1__STM32L1XX_STDPERIPH_VERSION_SUB2__STM32L1XX_STDPERIPH_VERSION_RC__STM32L1XX_STDPERIPH_VERSION__CM3_REV__MPU_PRESENT__NVIC_PRIO_BITS__Vendor_SysTickConfigcore_cm3.h__CORE_CM3_H_GENERIC__CM3_CMSIS_VERSION_MAIN__CM3_CMSIS_VERSION_SUB__CM3_CMSIS_VERSION__CORTEX_M__ASM__INLINE__STATIC_INLINE__FPU_USEDcore_cmInstr.h__CORE_CMINSTR_Hcmsis_iar.h__CMSIS_IAR_H____CORE____ARM6M____enable_irq__disable_irq__NOP__VER____BKPT__LDREXW__STREXW__enable_fault_irq__disable_fault_irqcore_cmFunc.h__CORE_CMFUNC_H__CORE_CM3_H_DEPENDANT__I__O__IONVIC_STIR_INTID_PosNVIC_STIR_INTID_MskSCB_CPUID_IMPLEMENTER_PosSCB_CPUID_IMPLEMENTER_MskSCB_CPUID_VARIANT_PosSCB_CPUID_VARIANT_MskSCB_CPUID_ARCHITECTURE_PosSCB_CPUID_ARCHITECTURE_MskSCB_CPUID_PARTNO_PosSCB_CPUID_PARTNO_MskSCB_CPUID_REVISION_PosSCB_CPUID_REVISION_MskSCB_ICSR_NMIPENDSET_PosSCB_ICSR_NMIPENDSET_MskSCB_ICSR_PENDSVSET_PosSCB_ICSR_PENDSVSET_MskSCB_ICSR_PENDSVCLR_PosSCB_ICSR_PENDSVCLR_MskSCB_ICSR_PENDSTSET_PosSCB_ICSR_PENDSTSET_MskSCB_ICSR_PENDSTCLR_PosSCB_ICSR_PENDSTCLR_MskSCB_ICSR_ISRPREEMPT_PosSCB_ICSR_ISRPREEMPT_MskSCB_ICSR_ISRPENDING_PosSCB_ICSR_ISRPENDING_MskSCB_ICSR_VECTPENDING_PosSCB_ICSR_VECTPENDING_MskSCB_ICSR_RETTOBASE_PosSCB_ICSR_RETTOBASE_MskSCB_ICSR_VECTACTIVE_PosSCB_ICSR_VECTACTIVE_MskSCB_VTOR_TBLBASE_PosSCB_VTOR_TBLBASE_MskSCB_VTOR_TBLOFF_PosSCB_VTOR_TBLOFF_MskSCB_AIRCR_VECTKEY_PosSCB_AIRCR_VECTKEY_MskSCB_AIRCR_VECTKEYSTAT_PosSCB_AIRCR_VECTKEYSTAT_MskSCB_AIRCR_ENDIANESS_PosSCB_AIRCR_ENDIANESS_MskSCB_AIRCR_PRIGROUP_PosSCB_AIRCR_PRIGROUP_MskSCB_AIRCR_SYSRESETREQ_PosSCB_AIRCR_SYSRESETREQ_MskSCB_AIRCR_VECTCLRACTIVE_PosSCB_AIRCR_VECTCLRACTIVE_MskSCB_AIRCR_VECTRESET_PosSCB_AIRCR_VECTRESET_MskSCB_SCR_SEVONPEND_PosSCB_SCR_SEVONPEND_MskSCB_SCR_SLEEPDEEP_PosSCB_SCR_SLEEPDEEP_MskSCB_SCR_SLEEPONEXIT_PosSCB_SCR_SLEEPONEXIT_MskSCB_CCR_STKALIGN_PosSCB_CCR_STKALIGN_MskSCB_CCR_BFHFNMIGN_PosSCB_CCR_BFHFNMIGN_MskSCB_CCR_DIV_0_TRP_PosSCB_CCR_DIV_0_TRP_MskSCB_CCR_UNALIGN_TRP_PosSCB_CCR_UNALIGN_TRP_MskSCB_CCR_USERSETMPEND_PosSCB_CCR_USERSETMPEND_MskSCB_CCR_NONBASETHRDENA_PosSCB_CCR_NONBASETHRDENA_MskSCB_SHCSR_USGFAULTENA_PosSCB_SHCSR_USGFAULTENA_MskSCB_SHCSR_BUSFAULTENA_PosSCB_SHCSR_BUSFAULTENA_MskSCB_SHCSR_MEMFAULTENA_PosSCB_SHCSR_MEMFAULTENA_MskSCB_SHCSR_SVCALLPENDED_PosSCB_SHCSR_SVCALLPENDED_MskSCB_SHCSR_BUSFAULTPENDED_PosSCB_SHCSR_BUSFAULTPENDED_MskSCB_SHCSR_MEMFAULTPENDED_PosSCB_SHCSR_MEMFAULTPENDED_MskSCB_SHCSR_USGFAULTPENDED_PosSCB_SHCSR_USGFAULTPENDED_MskSCB_SHCSR_SYSTICKACT_PosSCB_SHCSR_SYSTICKACT_MskSCB_SHCSR_PENDSVACT_PosSCB_SHCSR_PENDSVACT_MskSCB_SHCSR_MONITORACT_PosSCB_SHCSR_MONITORACT_MskSCB_SHCSR_SVCALLACT_PosSCB_SHCSR_SVCALLACT_MskSCB_SHCSR_USGFAULTACT_PosSCB_SHCSR_USGFAULTACT_MskSCB_SHCSR_BUSFAULTACT_PosSCB_SHCSR_BUSFAULTACT_MskSCB_SHCSR_MEMFAULTACT_PosSCB_SHCSR_MEMFAULTACT_MskSCB_CFSR_USGFAULTSR_PosSCB_CFSR_USGFAULTSR_MskSCB_CFSR_BUSFAULTSR_PosSCB_CFSR_BUSFAULTSR_MskSCB_CFSR_MEMFAULTSR_PosSCB_CFSR_MEMFAULTSR_MskSCB_HFSR_DEBUGEVT_PosSCB_HFSR_DEBUGEVT_MskSCB_HFSR_FORCED_PosSCB_HFSR_FORCED_MskSCB_HFSR_VECTTBL_PosSCB_HFSR_VECTTBL_MskSCB_DFSR_EXTERNAL_PosSCB_DFSR_EXTERNAL_MskSCB_DFSR_VCATCH_PosSCB_DFSR_VCATCH_MskSCB_DFSR_DWTTRAP_PosSCB_DFSR_DWTTRAP_MskSCB_DFSR_BKPT_PosSCB_DFSR_BKPT_MskSCB_DFSR_HALTED_PosSCB_DFSR_HALTED_MskSCnSCB_ICTR_INTLINESNUM_PosSCnSCB_ICTR_INTLINESNUM_MskSCnSCB_ACTLR_DISFOLD_PosSCnSCB_ACTLR_DISFOLD_MskSCnSCB_ACTLR_DISDEFWBUF_PosSCnSCB_ACTLR_DISDEFWBUF_MskSCnSCB_ACTLR_DISMCYCINT_PosSCnSCB_ACTLR_DISMCYCINT_MskSysTick_CTRL_COUNTFLAG_PosSysTick_CTRL_COUNTFLAG_MskSysTick_CTRL_CLKSOURCE_PosSysTick_CTRL_CLKSOURCE_MskSysTick_CTRL_TICKINT_PosSysTick_CTRL_TICKINT_MskSysTick_CTRL_ENABLE_PosSysTick_CTRL_ENABLE_MskSysTick_LOAD_RELOAD_PosSysTick_LOAD_RELOAD_MskSysTick_VAL_CURRENT_PosSysTick_VAL_CURRENT_MskSysTick_CALIB_NOREF_PosSysTick_CALIB_NOREF_MskSysTick_CALIB_SKEW_PosSysTick_CALIB_SKEW_MskSysTick_CALIB_TENMS_PosSysTick_CALIB_TENMS_MskITM_TPR_PRIVMASK_PosITM_TPR_PRIVMASK_MskITM_TCR_BUSY_PosITM_TCR_BUSY_MskITM_TCR_TraceBusID_PosITM_TCR_TraceBusID_MskITM_TCR_GTSFREQ_PosITM_TCR_GTSFREQ_MskITM_TCR_TSPrescale_PosITM_TCR_TSPrescale_MskITM_TCR_SWOENA_PosITM_TCR_SWOENA_MskITM_TCR_DWTENA_PosITM_TCR_DWTENA_MskITM_TCR_SYNCENA_PosITM_TCR_SYNCENA_MskITM_TCR_TSENA_PosITM_TCR_TSENA_MskITM_TCR_ITMENA_PosITM_TCR_ITMENA_MskITM_IWR_ATVALIDM_PosITM_IWR_ATVALIDM_MskITM_IRR_ATREADYM_PosITM_IRR_ATREADYM_MskITM_IMCR_INTEGRATION_PosITM_IMCR_INTEGRATION_MskITM_LSR_ByteAcc_PosITM_LSR_ByteAcc_MskITM_LSR_Access_PosITM_LSR_Access_MskITM_LSR_Present_PosITM_LSR_Present_MskDWT_CTRL_NUMCOMP_PosDWT_CTRL_NUMCOMP_MskDWT_CTRL_NOTRCPKT_PosDWT_CTRL_NOTRCPKT_MskDWT_CTRL_NOEXTTRIG_PosDWT_CTRL_NOEXTTRIG_MskDWT_CTRL_NOCYCCNT_PosDWT_CTRL_NOCYCCNT_MskDWT_CTRL_NOPRFCNT_PosDWT_CTRL_NOPRFCNT_MskDWT_CTRL_CYCEVTENA_PosDWT_CTRL_CYCEVTENA_MskDWT_CTRL_FOLDEVTENA_PosDWT_CTRL_FOLDEVTENA_MskDWT_CTRL_LSUEVTENA_PosDWT_CTRL_LSUEVTENA_MskDWT_CTRL_SLEEPEVTENA_PosDWT_CTRL_SLEEPEVTENA_MskDWT_CTRL_EXCEVTENA_PosDWT_CTRL_EXCEVTENA_MskDWT_CTRL_CPIEVTENA_PosDWT_CTRL_CPIEVTENA_MskDWT_CTRL_EXCTRCENA_PosDWT_CTRL_EXCTRCENA_MskDWT_CTRL_PCSAMPLENA_PosDWT_CTRL_PCSAMPLENA_MskDWT_CTRL_SYNCTAP_PosDWT_CTRL_SYNCTAP_MskDWT_CTRL_CYCTAP_PosDWT_CTRL_CYCTAP_MskDWT_CTRL_POSTINIT_PosDWT_CTRL_POSTINIT_MskDWT_CTRL_POSTPRESET_PosDWT_CTRL_POSTPRESET_MskDWT_CTRL_CYCCNTENA_PosDWT_CTRL_CYCCNTENA_MskDWT_CPICNT_CPICNT_PosDWT_CPICNT_CPICNT_MskDWT_EXCCNT_EXCCNT_PosDWT_EXCCNT_EXCCNT_MskDWT_SLEEPCNT_SLEEPCNT_PosDWT_SLEEPCNT_SLEEPCNT_MskDWT_LSUCNT_LSUCNT_PosDWT_LSUCNT_LSUCNT_MskDWT_FOLDCNT_FOLDCNT_PosDWT_FOLDCNT_FOLDCNT_MskDWT_MASK_MASK_PosDWT_MASK_MASK_MskDWT_FUNCTION_MATCHED_PosDWT_FUNCTION_MATCHED_MskDWT_FUNCTION_DATAVADDR1_PosDWT_FUNCTION_DATAVADDR1_MskDWT_FUNCTION_DATAVADDR0_PosDWT_FUNCTION_DATAVADDR0_MskDWT_FUNCTION_DATAVSIZE_PosDWT_FUNCTION_DATAVSIZE_MskDWT_FUNCTION_LNK1ENA_PosDWT_FUNCTION_LNK1ENA_MskDWT_FUNCTION_DATAVMATCH_PosDWT_FUNCTION_DATAVMATCH_MskDWT_FUNCTION_CYCMATCH_PosDWT_FUNCTION_CYCMATCH_MskDWT_FUNCTION_EMITRANGE_PosDWT_FUNCTION_EMITRANGE_MskDWT_FUNCTION_FUNCTION_PosDWT_FUNCTION_FUNCTION_MskTPI_ACPR_PRESCALER_PosTPI_ACPR_PRESCALER_MskTPI_SPPR_TXMODE_PosTPI_SPPR_TXMODE_MskTPI_FFSR_FtNonStop_PosTPI_FFSR_FtNonStop_MskTPI_FFSR_TCPresent_PosTPI_FFSR_TCPresent_MskTPI_FFSR_FtStopped_PosTPI_FFSR_FtStopped_MskTPI_FFSR_FlInProg_PosTPI_FFSR_FlInProg_MskTPI_FFCR_TrigIn_PosTPI_FFCR_TrigIn_MskTPI_FFCR_EnFCont_PosTPI_FFCR_EnFCont_MskTPI_TRIGGER_TRIGGER_PosTPI_TRIGGER_TRIGGER_MskTPI_FIFO0_ITM_ATVALID_PosTPI_FIFO0_ITM_ATVALID_MskTPI_FIFO0_ITM_bytecount_PosTPI_FIFO0_ITM_bytecount_MskTPI_FIFO0_ETM_ATVALID_PosTPI_FIFO0_ETM_ATVALID_MskTPI_FIFO0_ETM_bytecount_PosTPI_FIFO0_ETM_bytecount_MskTPI_FIFO0_ETM2_PosTPI_FIFO0_ETM2_MskTPI_FIFO0_ETM1_PosTPI_FIFO0_ETM1_MskTPI_FIFO0_ETM0_PosTPI_FIFO0_ETM0_MskTPI_ITATBCTR2_ATREADY_PosTPI_ITATBCTR2_ATREADY_MskTPI_FIFO1_ITM_ATVALID_PosTPI_FIFO1_ITM_ATVALID_MskTPI_FIFO1_ITM_bytecount_PosTPI_FIFO1_ITM_bytecount_MskTPI_FIFO1_ETM_ATVALID_PosTPI_FIFO1_ETM_ATVALID_MskTPI_FIFO1_ETM_bytecount_PosTPI_FIFO1_ETM_bytecount_MskTPI_FIFO1_ITM2_PosTPI_FIFO1_ITM2_MskTPI_FIFO1_ITM1_PosTPI_FIFO1_ITM1_MskTPI_FIFO1_ITM0_PosTPI_FIFO1_ITM0_MskTPI_ITATBCTR0_ATREADY_PosTPI_ITATBCTR0_ATREADY_MskTPI_ITCTRL_Mode_PosTPI_ITCTRL_Mode_MskTPI_DEVID_NRZVALID_PosTPI_DEVID_NRZVALID_MskTPI_DEVID_MANCVALID_PosTPI_DEVID_MANCVALID_MskTPI_DEVID_PTINVALID_PosTPI_DEVID_PTINVALID_MskTPI_DEVID_MinBufSz_PosTPI_DEVID_MinBufSz_MskTPI_DEVID_AsynClkIn_PosTPI_DEVID_AsynClkIn_MskTPI_DEVID_NrTraceInput_PosTPI_DEVID_NrTraceInput_MskTPI_DEVTYPE_SubType_PosTPI_DEVTYPE_SubType_MskTPI_DEVTYPE_MajorType_PosTPI_DEVTYPE_MajorType_MskMPU_TYPE_IREGION_PosMPU_TYPE_IREGION_MskMPU_TYPE_DREGION_PosMPU_TYPE_DREGION_MskMPU_TYPE_SEPARATE_PosMPU_TYPE_SEPARATE_MskMPU_CTRL_PRIVDEFENA_PosMPU_CTRL_PRIVDEFENA_MskMPU_CTRL_HFNMIENA_PosMPU_CTRL_HFNMIENA_MskMPU_CTRL_ENABLE_PosMPU_CTRL_ENABLE_MskMPU_RNR_REGION_PosMPU_RNR_REGION_MskMPU_RBAR_ADDR_PosMPU_RBAR_ADDR_MskMPU_RBAR_VALID_PosMPU_RBAR_VALID_MskMPU_RBAR_REGION_PosMPU_RBAR_REGION_MskMPU_RASR_ATTRS_PosMPU_RASR_ATTRS_MskMPU_RASR_XN_PosMPU_RASR_XN_MskMPU_RASR_AP_PosMPU_RASR_AP_MskMPU_RASR_TEX_PosMPU_RASR_TEX_MskMPU_RASR_S_PosMPU_RASR_S_MskMPU_RASR_C_PosMPU_RASR_C_MskMPU_RASR_B_PosMPU_RASR_B_MskMPU_RASR_SRD_PosMPU_RASR_SRD_MskMPU_RASR_SIZE_PosMPU_RASR_SIZE_MskMPU_RASR_ENABLE_PosMPU_RASR_ENABLE_MskCoreDebug_DHCSR_DBGKEY_PosCoreDebug_DHCSR_DBGKEY_MskCoreDebug_DHCSR_S_RESET_ST_PosCoreDebug_DHCSR_S_RESET_ST_MskCoreDebug_DHCSR_S_RETIRE_ST_PosCoreDebug_DHCSR_S_RETIRE_ST_MskCoreDebug_DHCSR_S_LOCKUP_PosCoreDebug_DHCSR_S_LOCKUP_MskCoreDebug_DHCSR_S_SLEEP_PosCoreDebug_DHCSR_S_SLEEP_MskCoreDebug_DHCSR_S_HALT_PosCoreDebug_DHCSR_S_HALT_MskCoreDebug_DHCSR_S_REGRDY_PosCoreDebug_DHCSR_S_REGRDY_MskCoreDebug_DHCSR_C_SNAPSTALL_PosCoreDebug_DHCSR_C_SNAPSTALL_MskCoreDebug_DHCSR_C_MASKINTS_PosCoreDebug_DHCSR_C_MASKINTS_MskCoreDebug_DHCSR_C_STEP_PosCoreDebug_DHCSR_C_STEP_MskCoreDebug_DHCSR_C_HALT_PosCoreDebug_DHCSR_C_HALT_MskCoreDebug_DHCSR_C_DEBUGEN_PosCoreDebug_DHCSR_C_DEBUGEN_MskCoreDebug_DCRSR_REGWnR_PosCoreDebug_DCRSR_REGWnR_MskCoreDebug_DCRSR_REGSEL_PosCoreDebug_DCRSR_REGSEL_MskCoreDebug_DEMCR_TRCENA_PosCoreDebug_DEMCR_TRCENA_MskCoreDebug_DEMCR_MON_REQ_PosCoreDebug_DEMCR_MON_REQ_MskCoreDebug_DEMCR_MON_STEP_PosCoreDebug_DEMCR_MON_STEP_MskCoreDebug_DEMCR_MON_PEND_PosCoreDebug_DEMCR_MON_PEND_MskCoreDebug_DEMCR_MON_EN_PosCoreDebug_DEMCR_MON_EN_MskCoreDebug_DEMCR_VC_HARDERR_PosCoreDebug_DEMCR_VC_HARDERR_MskCoreDebug_DEMCR_VC_INTERR_PosCoreDebug_DEMCR_VC_INTERR_MskCoreDebug_DEMCR_VC_BUSERR_PosCoreDebug_DEMCR_VC_BUSERR_MskCoreDebug_DEMCR_VC_STATERR_PosCoreDebug_DEMCR_VC_STATERR_MskCoreDebug_DEMCR_VC_CHKERR_PosCoreDebug_DEMCR_VC_CHKERR_MskCoreDebug_DEMCR_VC_NOCPERR_PosCoreDebug_DEMCR_VC_NOCPERR_MskCoreDebug_DEMCR_VC_MMERR_PosCoreDebug_DEMCR_VC_MMERR_MskCoreDebug_DEMCR_VC_CORERESET_PosCoreDebug_DEMCR_VC_CORERESET_MskSCS_BASEITM_BASEDWT_BASETPI_BASECoreDebug_BASESysTick_BASENVIC_BASESCB_BASESCnSCBSCBSysTickNVICITMDWTTPICoreDebugMPU_BASEMPUITM_RXBUFFER_EMPTYIS_FUNCTIONAL_STATE__RAM_FUNCFLASH_BASESRAM_BASEPERIPH_BASESRAM_BB_BASEPERIPH_BB_BASEFSMC_R_BASEAPB1PERIPH_BASEAPB2PERIPH_BASEAHBPERIPH_BASETIM2_BASETIM3_BASETIM4_BASETIM5_BASETIM6_BASETIM7_BASELCD_BASERTC_BASEWWDG_BASEIWDG_BASESPI2_BASESPI3_BASEUSART2_BASEUSART3_BASEUART4_BASEUART5_BASEI2C1_BASEI2C2_BASEPWR_BASEDAC_BASECOMP_BASERI_BASEOPAMP_BASESYSCFG_BASEEXTI_BASETIM9_BASETIM10_BASETIM11_BASEADC1_BASEADC_BASESDIO_BASESPI1_BASEUSART1_BASEGPIOA_BASEGPIOB_BASEGPIOC_BASEGPIOD_BASEGPIOE_BASEGPIOH_BASEGPIOF_BASEGPIOG_BASECRC_BASERCC_BASEFLASH_R_BASEOB_BASEDMA1_BASEDMA1_Channel1_BASEDMA1_Channel2_BASEDMA1_Channel3_BASEDMA1_Channel4_BASEDMA1_Channel5_BASEDMA1_Channel6_BASEDMA1_Channel7_BASEDMA2_BASEDMA2_Channel1_BASEDMA2_Channel2_BASEDMA2_Channel3_BASEDMA2_Channel4_BASEDMA2_Channel5_BASEAES_BASEFSMC_Bank1_R_BASEFSMC_Bank1E_R_BASEDBGMCU_BASETIM2TIM3TIM4TIM5TIM6TIM7LCDRTCWWDGIWDGSPI2SPI3USART2USART3UART4UART5I2C1I2C2PWRDACCOMPRIOPAMPSYSCFGEXTIADC1ADCSDIOTIM9TIM10TIM11SPI1USART1DMA1DMA1_Channel1DMA1_Channel2DMA1_Channel3DMA1_Channel4DMA1_Channel5DMA1_Channel6DMA1_Channel7DMA2DMA2_Channel1DMA2_Channel2DMA2_Channel3DMA2_Channel4DMA2_Channel5RCCCRCGPIOAGPIOBGPIOCGPIODGPIOEGPIOHGPIOFGPIOGFLASHOBAESFSMC_Bank1FSMC_Bank1EDBGMCUADC_SR_AWDADC_SR_EOCADC_SR_JEOCADC_SR_JSTRTADC_SR_STRTADC_SR_OVRADC_SR_ADONSADC_SR_RCNRADC_SR_JCNRADC_CR1_AWDCHADC_CR1_AWDCH_0ADC_CR1_AWDCH_1ADC_CR1_AWDCH_2ADC_CR1_AWDCH_3ADC_CR1_AWDCH_4ADC_CR1_EOCIEADC_CR1_AWDIEADC_CR1_JEOCIEADC_CR1_SCANADC_CR1_AWDSGLADC_CR1_JAUTOADC_CR1_DISCENADC_CR1_JDISCENADC_CR1_DISCNUMADC_CR1_DISCNUM_0ADC_CR1_DISCNUM_1ADC_CR1_DISCNUM_2ADC_CR1_PDDADC_CR1_PDIADC_CR1_JAWDENADC_CR1_AWDENADC_CR1_RESADC_CR1_RES_0ADC_CR1_RES_1ADC_CR1_OVRIEADC_CR2_ADONADC_CR2_CONTADC_CR2_CFGADC_CR2_DELSADC_CR2_DELS_0ADC_CR2_DELS_1ADC_CR2_DELS_2ADC_CR2_DMAADC_CR2_DDSADC_CR2_EOCSADC_CR2_ALIGNADC_CR2_JEXTSELADC_CR2_JEXTSEL_0ADC_CR2_JEXTSEL_1ADC_CR2_JEXTSEL_2ADC_CR2_JEXTSEL_3ADC_CR2_JEXTENADC_CR2_JEXTEN_0ADC_CR2_JEXTEN_1ADC_CR2_JSWSTARTADC_CR2_EXTSELADC_CR2_EXTSEL_0ADC_CR2_EXTSEL_1ADC_CR2_EXTSEL_2ADC_CR2_EXTSEL_3ADC_CR2_EXTENADC_CR2_EXTEN_0ADC_CR2_EXTEN_1ADC_CR2_SWSTARTADC_SMPR1_SMP20ADC_SMPR1_SMP20_0ADC_SMPR1_SMP20_1ADC_SMPR1_SMP20_2ADC_SMPR1_SMP21ADC_SMPR1_SMP21_0ADC_SMPR1_SMP21_1ADC_SMPR1_SMP21_2ADC_SMPR1_SMP22ADC_SMPR1_SMP22_0ADC_SMPR1_SMP22_1ADC_SMPR1_SMP22_2ADC_SMPR1_SMP23ADC_SMPR1_SMP23_0ADC_SMPR1_SMP23_1ADC_SMPR1_SMP23_2ADC_SMPR1_SMP24ADC_SMPR1_SMP24_0ADC_SMPR1_SMP24_1ADC_SMPR1_SMP24_2ADC_SMPR1_SMP25ADC_SMPR1_SMP25_0ADC_SMPR1_SMP25_1ADC_SMPR1_SMP25_2ADC_SMPR1_SMP26ADC_SMPR1_SMP26_0ADC_SMPR1_SMP26_1ADC_SMPR1_SMP26_2ADC_SMPR1_SMP27ADC_SMPR1_SMP27_0ADC_SMPR1_SMP27_1ADC_SMPR1_SMP27_2ADC_SMPR1_SMP28ADC_SMPR1_SMP28_0ADC_SMPR1_SMP28_1ADC_SMPR1_SMP28_2ADC_SMPR1_SMP29ADC_SMPR1_SMP29_0ADC_SMPR1_SMP29_1ADC_SMPR1_SMP29_2ADC_SMPR2_SMP10ADC_SMPR2_SMP10_0ADC_SMPR2_SMP10_1ADC_SMPR2_SMP10_2ADC_SMPR2_SMP11ADC_SMPR2_SMP11_0ADC_SMPR2_SMP11_1ADC_SMPR2_SMP11_2ADC_SMPR2_SMP12ADC_SMPR2_SMP12_0ADC_SMPR2_SMP12_1ADC_SMPR2_SMP12_2ADC_SMPR2_SMP13ADC_SMPR2_SMP13_0ADC_SMPR2_SMP13_1ADC_SMPR2_SMP13_2ADC_SMPR2_SMP14ADC_SMPR2_SMP14_0ADC_SMPR2_SMP14_1ADC_SMPR2_SMP14_2ADC_SMPR2_SMP15ADC_SMPR2_SMP15_0ADC_SMPR2_SMP15_1ADC_SMPR2_SMP15_2ADC_SMPR2_SMP16ADC_SMPR2_SMP16_0ADC_SMPR2_SMP16_1ADC_SMPR2_SMP16_2ADC_SMPR2_SMP17ADC_SMPR2_SMP17_0ADC_SMPR2_SMP17_1ADC_SMPR2_SMP17_2ADC_SMPR2_SMP18ADC_SMPR2_SMP18_0ADC_SMPR2_SMP18_1ADC_SMPR2_SMP18_2ADC_SMPR2_SMP19ADC_SMPR2_SMP19_0ADC_SMPR2_SMP19_1ADC_SMPR2_SMP19_2ADC_SMPR3_SMP0ADC_SMPR3_SMP0_0ADC_SMPR3_SMP0_1ADC_SMPR3_SMP0_2ADC_SMPR3_SMP1ADC_SMPR3_SMP1_0ADC_SMPR3_SMP1_1ADC_SMPR3_SMP1_2ADC_SMPR3_SMP2ADC_SMPR3_SMP2_0ADC_SMPR3_SMP2_1ADC_SMPR3_SMP2_2ADC_SMPR3_SMP3ADC_SMPR3_SMP3_0ADC_SMPR3_SMP3_1ADC_SMPR3_SMP3_2ADC_SMPR3_SMP4ADC_SMPR3_SMP4_0ADC_SMPR3_SMP4_1ADC_SMPR3_SMP4_2ADC_SMPR3_SMP5ADC_SMPR3_SMP5_0ADC_SMPR3_SMP5_1ADC_SMPR3_SMP5_2ADC_SMPR3_SMP6ADC_SMPR3_SMP6_0ADC_SMPR3_SMP6_1ADC_SMPR3_SMP6_2ADC_SMPR3_SMP7ADC_SMPR3_SMP7_0ADC_SMPR3_SMP7_1ADC_SMPR3_SMP7_2ADC_SMPR3_SMP8ADC_SMPR3_SMP8_0ADC_SMPR3_SMP8_1ADC_SMPR3_SMP8_2ADC_SMPR3_SMP9ADC_SMPR3_SMP9_0ADC_SMPR3_SMP9_1ADC_SMPR3_SMP9_2ADC_JOFR1_JOFFSET1ADC_JOFR2_JOFFSET2ADC_JOFR3_JOFFSET3ADC_JOFR4_JOFFSET4ADC_HTR_HTADC_LTR_LTADC_SQR1_LADC_SQR1_L_0ADC_SQR1_L_1ADC_SQR1_L_2ADC_SQR1_L_3ADC_SQR1_SQ28ADC_SQR1_SQ28_0ADC_SQR1_SQ28_1ADC_SQR1_SQ28_2ADC_SQR1_SQ28_3ADC_SQR1_SQ28_4ADC_SQR1_SQ27ADC_SQR1_SQ27_0ADC_SQR1_SQ27_1ADC_SQR1_SQ27_2ADC_SQR1_SQ27_3ADC_SQR1_SQ27_4ADC_SQR1_SQ26ADC_SQR1_SQ26_0ADC_SQR1_SQ26_1ADC_SQR1_SQ26_2ADC_SQR1_SQ26_3ADC_SQR1_SQ26_4ADC_SQR1_SQ25ADC_SQR1_SQ25_0ADC_SQR1_SQ25_1ADC_SQR1_SQ25_2ADC_SQR1_SQ25_3ADC_SQR1_SQ25_4ADC_SQR2_SQ19ADC_SQR2_SQ19_0ADC_SQR2_SQ19_1ADC_SQR2_SQ19_2ADC_SQR2_SQ19_3ADC_SQR2_SQ19_4ADC_SQR2_SQ20ADC_SQR2_SQ20_0ADC_SQR2_SQ20_1ADC_SQR2_SQ20_2ADC_SQR2_SQ20_3ADC_SQR2_SQ20_4ADC_SQR2_SQ21ADC_SQR2_SQ21_0ADC_SQR2_SQ21_1ADC_SQR2_SQ21_2ADC_SQR2_SQ21_3ADC_SQR2_SQ21_4ADC_SQR2_SQ22ADC_SQR2_SQ22_0ADC_SQR2_SQ22_1ADC_SQR2_SQ22_2ADC_SQR2_SQ22_3ADC_SQR2_SQ22_4ADC_SQR2_SQ23ADC_SQR2_SQ23_0ADC_SQR2_SQ23_1ADC_SQR2_SQ23_2ADC_SQR2_SQ23_3ADC_SQR2_SQ23_4ADC_SQR2_SQ24ADC_SQR2_SQ24_0ADC_SQR2_SQ24_1ADC_SQR2_SQ24_2ADC_SQR2_SQ24_3ADC_SQR2_SQ24_4ADC_SQR3_SQ13ADC_SQR3_SQ13_0ADC_SQR3_SQ13_1ADC_SQR3_SQ13_2ADC_SQR3_SQ13_3ADC_SQR3_SQ13_4ADC_SQR3_SQ14ADC_SQR3_SQ14_0ADC_SQR3_SQ14_1ADC_SQR3_SQ14_2ADC_SQR3_SQ14_3ADC_SQR3_SQ14_4ADC_SQR3_SQ15ADC_SQR3_SQ15_0ADC_SQR3_SQ15_1ADC_SQR3_SQ15_2ADC_SQR3_SQ15_3ADC_SQR3_SQ15_4ADC_SQR3_SQ16ADC_SQR3_SQ16_0ADC_SQR3_SQ16_1ADC_SQR3_SQ16_2ADC_SQR3_SQ16_3ADC_SQR3_SQ16_4ADC_SQR3_SQ17ADC_SQR3_SQ17_0ADC_SQR3_SQ17_1ADC_SQR3_SQ17_2ADC_SQR3_SQ17_3ADC_SQR3_SQ17_4ADC_SQR3_SQ18ADC_SQR3_SQ18_0ADC_SQR3_SQ18_1ADC_SQR3_SQ18_2ADC_SQR3_SQ18_3ADC_SQR3_SQ18_4ADC_SQR4_SQ7ADC_SQR4_SQ7_0ADC_SQR4_SQ7_1ADC_SQR4_SQ7_2ADC_SQR4_SQ7_3ADC_SQR4_SQ7_4ADC_SQR4_SQ8ADC_SQR4_SQ8_0ADC_SQR4_SQ8_1ADC_SQR4_SQ8_2ADC_SQR4_SQ8_3ADC_SQR4_SQ8_4ADC_SQR4_SQ9ADC_SQR4_SQ9_0ADC_SQR4_SQ9_1ADC_SQR4_SQ9_2ADC_SQR4_SQ9_3ADC_SQR4_SQ9_4ADC_SQR4_SQ10ADC_SQR4_SQ10_0ADC_SQR4_SQ10_1ADC_SQR4_SQ10_2ADC_SQR4_SQ10_3ADC_SQR4_SQ10_4ADC_SQR4_SQ11ADC_SQR4_SQ11_0ADC_SQR4_SQ11_1ADC_SQR4_SQ11_2ADC_SQR4_SQ11_3ADC_SQR4_SQ11_4ADC_SQR4_SQ12ADC_SQR4_SQ12_0ADC_SQR4_SQ12_1ADC_SQR4_SQ12_2ADC_SQR4_SQ12_3ADC_SQR4_SQ12_4ADC_SQR5_SQ1ADC_SQR5_SQ1_0ADC_SQR5_SQ1_1ADC_SQR5_SQ1_2ADC_SQR5_SQ1_3ADC_SQR5_SQ1_4ADC_SQR5_SQ2ADC_SQR5_SQ2_0ADC_SQR5_SQ2_1ADC_SQR5_SQ2_2ADC_SQR5_SQ2_3ADC_SQR5_SQ2_4ADC_SQR5_SQ3ADC_SQR5_SQ3_0ADC_SQR5_SQ3_1ADC_SQR5_SQ3_2ADC_SQR5_SQ3_3ADC_SQR5_SQ3_4ADC_SQR5_SQ4ADC_SQR5_SQ4_0ADC_SQR5_SQ4_1ADC_SQR5_SQ4_2ADC_SQR5_SQ4_3ADC_SQR5_SQ4_4ADC_SQR5_SQ5ADC_SQR5_SQ5_0ADC_SQR5_SQ5_1ADC_SQR5_SQ5_2ADC_SQR5_SQ5_3ADC_SQR5_SQ5_4ADC_SQR5_SQ6ADC_SQR5_SQ6_0ADC_SQR5_SQ6_1ADC_SQR5_SQ6_2ADC_SQR5_SQ6_3ADC_SQR5_SQ6_4ADC_JSQR_JSQ1ADC_JSQR_JSQ1_0ADC_JSQR_JSQ1_1ADC_JSQR_JSQ1_2ADC_JSQR_JSQ1_3ADC_JSQR_JSQ1_4ADC_JSQR_JSQ2ADC_JSQR_JSQ2_0ADC_JSQR_JSQ2_1ADC_JSQR_JSQ2_2ADC_JSQR_JSQ2_3ADC_JSQR_JSQ2_4ADC_JSQR_JSQ3ADC_JSQR_JSQ3_0ADC_JSQR_JSQ3_1ADC_JSQR_JSQ3_2ADC_JSQR_JSQ3_3ADC_JSQR_JSQ3_4ADC_JSQR_JSQ4ADC_JSQR_JSQ4_0ADC_JSQR_JSQ4_1ADC_JSQR_JSQ4_2ADC_JSQR_JSQ4_3ADC_JSQR_JSQ4_4ADC_JSQR_JLADC_JSQR_JL_0ADC_JSQR_JL_1ADC_JDR1_JDATAADC_JDR2_JDATAADC_JDR3_JDATAADC_JDR4_JDATAADC_DR_DATAADC_SMPR3_SMP30ADC_SMPR3_SMP30_0ADC_SMPR3_SMP30_1ADC_SMPR3_SMP30_2ADC_SMPR3_SMP31ADC_SMPR3_SMP31_0ADC_SMPR3_SMP31_1ADC_SMPR3_SMP31_2ADC_CSR_AWD1ADC_CSR_EOC1ADC_CSR_JEOC1ADC_CSR_JSTRT1ADC_CSR_STRT1ADC_CSR_OVR1ADC_CSR_ADONS1ADC_CCR_ADCPREADC_CCR_ADCPRE_0ADC_CCR_ADCPRE_1ADC_CCR_TSVREFEAES_CR_ENAES_CR_DATATYPEAES_CR_DATATYPE_0AES_CR_DATATYPE_1AES_CR_MODEAES_CR_MODE_0AES_CR_MODE_1AES_CR_CHMODAES_CR_CHMOD_0AES_CR_CHMOD_1AES_CR_CCFCAES_CR_ERRCAES_CR_CCIEAES_CR_ERRIEAES_CR_DMAINENAES_CR_DMAOUTENAES_SR_CCFAES_SR_RDERRAES_SR_WRERRAES_DINRAES_DOUTRAES_KEYR0AES_KEYR1AES_KEYR2AES_KEYR3AES_IVR0AES_IVR1AES_IVR2AES_IVR3COMP_CSR_10KPUCOMP_CSR_400KPUCOMP_CSR_10KPDCOMP_CSR_400KPDCOMP_CSR_CMP1ENCOMP_CSR_SW1COMP_CSR_CMP1OUTCOMP_CSR_SPEEDCOMP_CSR_CMP2OUTCOMP_CSR_VREFOUTENCOMP_CSR_WNDWECOMP_CSR_INSELCOMP_CSR_INSEL_0COMP_CSR_INSEL_1COMP_CSR_INSEL_2COMP_CSR_OUTSELCOMP_CSR_OUTSEL_0COMP_CSR_OUTSEL_1COMP_CSR_OUTSEL_2COMP_CSR_FCH3COMP_CSR_FCH8COMP_CSR_RCH13COMP_CSR_CAIECOMP_CSR_CAIFCOMP_CSR_TSUSPOPAMP_CSR_OPA1PDOPAMP_CSR_S3SEL1OPAMP_CSR_S4SEL1OPAMP_CSR_S5SEL1OPAMP_CSR_S6SEL1OPAMP_CSR_OPA1CAL_LOPAMP_CSR_OPA1CAL_HOPAMP_CSR_OPA1LPMOPAMP_CSR_OPA2PDOPAMP_CSR_S3SEL2OPAMP_CSR_S4SEL2OPAMP_CSR_S5SEL2OPAMP_CSR_S6SEL2OPAMP_CSR_OPA2CAL_LOPAMP_CSR_OPA2CAL_HOPAMP_CSR_OPA2LPMOPAMP_CSR_OPA3PDOPAMP_CSR_S3SEL3OPAMP_CSR_S4SEL3OPAMP_CSR_S5SEL3OPAMP_CSR_S6SEL3OPAMP_CSR_OPA3CAL_LOPAMP_CSR_OPA3CAL_HOPAMP_CSR_OPA3LPMOPAMP_CSR_ANAWSEL1OPAMP_CSR_ANAWSEL2OPAMP_CSR_ANAWSEL3OPAMP_CSR_S7SEL2OPAMP_CSR_AOP_RANGEOPAMP_CSR_OPA1CALOUTOPAMP_CSR_OPA2CALOUTOPAMP_CSR_OPA3CALOUTOPAMP_OTR_AO1_OPT_OFFSET_TRIMOPAMP_OTR_AO2_OPT_OFFSET_TRIMOPAMP_OTR_AO3_OPT_OFFSET_TRIMOPAMP_OTR_OT_USEROPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LPOPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LPOPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LPCRC_DR_DRCRC_IDR_IDRCRC_CR_RESETDAC_CR_EN1DAC_CR_BOFF1DAC_CR_TEN1DAC_CR_TSEL1DAC_CR_TSEL1_0DAC_CR_TSEL1_1DAC_CR_TSEL1_2DAC_CR_WAVE1DAC_CR_WAVE1_0DAC_CR_WAVE1_1DAC_CR_MAMP1DAC_CR_MAMP1_0DAC_CR_MAMP1_1DAC_CR_MAMP1_2DAC_CR_MAMP1_3DAC_CR_DMAEN1DAC_CR_DMAUDRIE1DAC_CR_EN2DAC_CR_BOFF2DAC_CR_TEN2DAC_CR_TSEL2DAC_CR_TSEL2_0DAC_CR_TSEL2_1DAC_CR_TSEL2_2DAC_CR_WAVE2DAC_CR_WAVE2_0DAC_CR_WAVE2_1DAC_CR_MAMP2DAC_CR_MAMP2_0DAC_CR_MAMP2_1DAC_CR_MAMP2_2DAC_CR_MAMP2_3DAC_CR_DMAEN2DAC_CR_DMAUDRIE2DAC_SWTRIGR_SWTRIG1DAC_SWTRIGR_SWTRIG2DAC_DHR12R1_DACC1DHRDAC_DHR12L1_DACC1DHRDAC_DHR8R1_DACC1DHRDAC_DHR12R2_DACC2DHRDAC_DHR12L2_DACC2DHRDAC_DHR8R2_DACC2DHRDAC_DHR12RD_DACC1DHRDAC_DHR12RD_DACC2DHRDAC_DHR12LD_DACC1DHRDAC_DHR12LD_DACC2DHRDAC_DHR8RD_DACC1DHRDAC_DHR8RD_DACC2DHRDAC_DOR1_DACC1DORDAC_DOR2_DACC2DORDAC_SR_DMAUDR1DAC_SR_DMAUDR2DBGMCU_IDCODE_DEV_IDDBGMCU_IDCODE_REV_IDDBGMCU_IDCODE_REV_ID_0DBGMCU_IDCODE_REV_ID_1DBGMCU_IDCODE_REV_ID_2DBGMCU_IDCODE_REV_ID_3DBGMCU_IDCODE_REV_ID_4DBGMCU_IDCODE_REV_ID_5DBGMCU_IDCODE_REV_ID_6DBGMCU_IDCODE_REV_ID_7DBGMCU_IDCODE_REV_ID_8DBGMCU_IDCODE_REV_ID_9DBGMCU_IDCODE_REV_ID_10DBGMCU_IDCODE_REV_ID_11DBGMCU_IDCODE_REV_ID_12DBGMCU_IDCODE_REV_ID_13DBGMCU_IDCODE_REV_ID_14DBGMCU_IDCODE_REV_ID_15DBGMCU_CR_DBG_SLEEPDBGMCU_CR_DBG_STOPDBGMCU_CR_DBG_STANDBYDBGMCU_CR_TRACE_IOENDBGMCU_CR_TRACE_MODEDBGMCU_CR_TRACE_MODE_0DBGMCU_CR_TRACE_MODE_1DBGMCU_APB1_FZ_DBG_TIM2_STOPDBGMCU_APB1_FZ_DBG_TIM3_STOPDBGMCU_APB1_FZ_DBG_TIM4_STOPDBGMCU_APB1_FZ_DBG_TIM5_STOPDBGMCU_APB1_FZ_DBG_TIM6_STOPDBGMCU_APB1_FZ_DBG_TIM7_STOPDBGMCU_APB1_FZ_DBG_RTC_STOPDBGMCU_APB1_FZ_DBG_WWDG_STOPDBGMCU_APB1_FZ_DBG_IWDG_STOPDBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUTDBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUTDBGMCU_APB2_FZ_DBG_TIM9_STOPDBGMCU_APB2_FZ_DBG_TIM10_STOPDBGMCU_APB2_FZ_DBG_TIM11_STOPDMA_ISR_GIF1DMA_ISR_TCIF1DMA_ISR_HTIF1DMA_ISR_TEIF1DMA_ISR_GIF2DMA_ISR_TCIF2DMA_ISR_HTIF2DMA_ISR_TEIF2DMA_ISR_GIF3DMA_ISR_TCIF3DMA_ISR_HTIF3DMA_ISR_TEIF3DMA_ISR_GIF4DMA_ISR_TCIF4DMA_ISR_HTIF4DMA_ISR_TEIF4DMA_ISR_GIF5DMA_ISR_TCIF5DMA_ISR_HTIF5DMA_ISR_TEIF5DMA_ISR_GIF6DMA_ISR_TCIF6DMA_ISR_HTIF6DMA_ISR_TEIF6DMA_ISR_GIF7DMA_ISR_TCIF7DMA_ISR_HTIF7DMA_ISR_TEIF7DMA_IFCR_CGIF1DMA_IFCR_CTCIF1DMA_IFCR_CHTIF1DMA_IFCR_CTEIF1DMA_IFCR_CGIF2DMA_IFCR_CTCIF2DMA_IFCR_CHTIF2DMA_IFCR_CTEIF2DMA_IFCR_CGIF3DMA_IFCR_CTCIF3DMA_IFCR_CHTIF3DMA_IFCR_CTEIF3DMA_IFCR_CGIF4DMA_IFCR_CTCIF4DMA_IFCR_CHTIF4DMA_IFCR_CTEIF4DMA_IFCR_CGIF5DMA_IFCR_CTCIF5DMA_IFCR_CHTIF5DMA_IFCR_CTEIF5DMA_IFCR_CGIF6DMA_IFCR_CTCIF6DMA_IFCR_CHTIF6DMA_IFCR_CTEIF6DMA_IFCR_CGIF7DMA_IFCR_CTCIF7DMA_IFCR_CHTIF7DMA_IFCR_CTEIF7DMA_CCR1_ENDMA_CCR1_TCIEDMA_CCR1_HTIEDMA_CCR1_TEIEDMA_CCR1_DIRDMA_CCR1_CIRCDMA_CCR1_PINCDMA_CCR1_MINCDMA_CCR1_PSIZEDMA_CCR1_PSIZE_0DMA_CCR1_PSIZE_1DMA_CCR1_MSIZEDMA_CCR1_MSIZE_0DMA_CCR1_MSIZE_1DMA_CCR1_PLDMA_CCR1_PL_0DMA_CCR1_PL_1DMA_CCR1_MEM2MEMDMA_CCR2_ENDMA_CCR2_TCIEDMA_CCR2_HTIEDMA_CCR2_TEIEDMA_CCR2_DIRDMA_CCR2_CIRCDMA_CCR2_PINCDMA_CCR2_MINCDMA_CCR2_PSIZEDMA_CCR2_PSIZE_0DMA_CCR2_PSIZE_1DMA_CCR2_MSIZEDMA_CCR2_MSIZE_0DMA_CCR2_MSIZE_1DMA_CCR2_PLDMA_CCR2_PL_0DMA_CCR2_PL_1DMA_CCR2_MEM2MEMDMA_CCR3_ENDMA_CCR3_TCIEDMA_CCR3_HTIEDMA_CCR3_TEIEDMA_CCR3_DIRDMA_CCR3_CIRCDMA_CCR3_PINCDMA_CCR3_MINCDMA_CCR3_PSIZEDMA_CCR3_PSIZE_0DMA_CCR3_PSIZE_1DMA_CCR3_MSIZEDMA_CCR3_MSIZE_0DMA_CCR3_MSIZE_1DMA_CCR3_PLDMA_CCR3_PL_0DMA_CCR3_PL_1DMA_CCR3_MEM2MEMDMA_CCR4_ENDMA_CCR4_TCIEDMA_CCR4_HTIEDMA_CCR4_TEIEDMA_CCR4_DIRDMA_CCR4_CIRCDMA_CCR4_PINCDMA_CCR4_MINCDMA_CCR4_PSIZEDMA_CCR4_PSIZE_0DMA_CCR4_PSIZE_1DMA_CCR4_MSIZEDMA_CCR4_MSIZE_0DMA_CCR4_MSIZE_1DMA_CCR4_PLDMA_CCR4_PL_0DMA_CCR4_PL_1DMA_CCR4_MEM2MEMDMA_CCR5_ENDMA_CCR5_TCIEDMA_CCR5_HTIEDMA_CCR5_TEIEDMA_CCR5_DIRDMA_CCR5_CIRCDMA_CCR5_PINCDMA_CCR5_MINCDMA_CCR5_PSIZEDMA_CCR5_PSIZE_0DMA_CCR5_PSIZE_1DMA_CCR5_MSIZEDMA_CCR5_MSIZE_0DMA_CCR5_MSIZE_1DMA_CCR5_PLDMA_CCR5_PL_0DMA_CCR5_PL_1DMA_CCR5_MEM2MEMDMA_CCR6_ENDMA_CCR6_TCIEDMA_CCR6_HTIEDMA_CCR6_TEIEDMA_CCR6_DIRDMA_CCR6_CIRCDMA_CCR6_PINCDMA_CCR6_MINCDMA_CCR6_PSIZEDMA_CCR6_PSIZE_0DMA_CCR6_PSIZE_1DMA_CCR6_MSIZEDMA_CCR6_MSIZE_0DMA_CCR6_MSIZE_1DMA_CCR6_PLDMA_CCR6_PL_0DMA_CCR6_PL_1DMA_CCR6_MEM2MEMDMA_CCR7_ENDMA_CCR7_TCIEDMA_CCR7_HTIEDMA_CCR7_TEIEDMA_CCR7_DIRDMA_CCR7_CIRCDMA_CCR7_PINCDMA_CCR7_MINCDMA_CCR7_PSIZEDMA_CCR7_PSIZE_0DMA_CCR7_PSIZE_1DMA_CCR7_MSIZEDMA_CCR7_MSIZE_0DMA_CCR7_MSIZE_1DMA_CCR7_PLDMA_CCR7_PL_0DMA_CCR7_PL_1DMA_CCR7_MEM2MEMDMA_CNDTR1_NDTDMA_CNDTR2_NDTDMA_CNDTR3_NDTDMA_CNDTR4_NDTDMA_CNDTR5_NDTDMA_CNDTR6_NDTDMA_CNDTR7_NDTDMA_CPAR1_PADMA_CPAR2_PADMA_CPAR3_PADMA_CPAR4_PADMA_CPAR5_PADMA_CPAR6_PADMA_CPAR7_PADMA_CMAR1_MADMA_CMAR2_MADMA_CMAR3_MADMA_CMAR4_MADMA_CMAR5_MADMA_CMAR6_MADMA_CMAR7_MAEXTI_IMR_MR0EXTI_IMR_MR1EXTI_IMR_MR2EXTI_IMR_MR3EXTI_IMR_MR4EXTI_IMR_MR5EXTI_IMR_MR6EXTI_IMR_MR7EXTI_IMR_MR8EXTI_IMR_MR9EXTI_IMR_MR10EXTI_IMR_MR11EXTI_IMR_MR12EXTI_IMR_MR13EXTI_IMR_MR14EXTI_IMR_MR15EXTI_IMR_MR16EXTI_IMR_MR17EXTI_IMR_MR18EXTI_IMR_MR19EXTI_IMR_MR20EXTI_IMR_MR21EXTI_IMR_MR22EXTI_IMR_MR23EXTI_EMR_MR0EXTI_EMR_MR1EXTI_EMR_MR2EXTI_EMR_MR3EXTI_EMR_MR4EXTI_EMR_MR5EXTI_EMR_MR6EXTI_EMR_MR7EXTI_EMR_MR8EXTI_EMR_MR9EXTI_EMR_MR10EXTI_EMR_MR11EXTI_EMR_MR12EXTI_EMR_MR13EXTI_EMR_MR14EXTI_EMR_MR15EXTI_EMR_MR16EXTI_EMR_MR17EXTI_EMR_MR18EXTI_EMR_MR19EXTI_EMR_MR20EXTI_EMR_MR21EXTI_EMR_MR22EXTI_EMR_MR23EXTI_RTSR_TR0EXTI_RTSR_TR1EXTI_RTSR_TR2EXTI_RTSR_TR3EXTI_RTSR_TR4EXTI_RTSR_TR5EXTI_RTSR_TR6EXTI_RTSR_TR7EXTI_RTSR_TR8EXTI_RTSR_TR9EXTI_RTSR_TR10EXTI_RTSR_TR11EXTI_RTSR_TR12EXTI_RTSR_TR13EXTI_RTSR_TR14EXTI_RTSR_TR15EXTI_RTSR_TR16EXTI_RTSR_TR17EXTI_RTSR_TR18EXTI_RTSR_TR19EXTI_RTSR_TR20EXTI_RTSR_TR21EXTI_RTSR_TR22EXTI_RTSR_TR23EXTI_FTSR_TR0EXTI_FTSR_TR1EXTI_FTSR_TR2EXTI_FTSR_TR3EXTI_FTSR_TR4EXTI_FTSR_TR5EXTI_FTSR_TR6EXTI_FTSR_TR7EXTI_FTSR_TR8EXTI_FTSR_TR9EXTI_FTSR_TR10EXTI_FTSR_TR11EXTI_FTSR_TR12EXTI_FTSR_TR13EXTI_FTSR_TR14EXTI_FTSR_TR15EXTI_FTSR_TR16EXTI_FTSR_TR17EXTI_FTSR_TR18EXTI_FTSR_TR19EXTI_FTSR_TR20EXTI_FTSR_TR21EXTI_FTSR_TR22EXTI_FTSR_TR23EXTI_SWIER_SWIER0EXTI_SWIER_SWIER1EXTI_SWIER_SWIER2EXTI_SWIER_SWIER3EXTI_SWIER_SWIER4EXTI_SWIER_SWIER5EXTI_SWIER_SWIER6EXTI_SWIER_SWIER7EXTI_SWIER_SWIER8EXTI_SWIER_SWIER9EXTI_SWIER_SWIER10EXTI_SWIER_SWIER11EXTI_SWIER_SWIER12EXTI_SWIER_SWIER13EXTI_SWIER_SWIER14EXTI_SWIER_SWIER15EXTI_SWIER_SWIER16EXTI_SWIER_SWIER17EXTI_SWIER_SWIER18EXTI_SWIER_SWIER19EXTI_SWIER_SWIER20EXTI_SWIER_SWIER21EXTI_SWIER_SWIER22EXTI_SWIER_SWIER23EXTI_PR_PR0EXTI_PR_PR1EXTI_PR_PR2EXTI_PR_PR3EXTI_PR_PR4EXTI_PR_PR5EXTI_PR_PR6EXTI_PR_PR7EXTI_PR_PR8EXTI_PR_PR9EXTI_PR_PR10EXTI_PR_PR11EXTI_PR_PR12EXTI_PR_PR13EXTI_PR_PR14EXTI_PR_PR15EXTI_PR_PR16EXTI_PR_PR17EXTI_PR_PR18EXTI_PR_PR19EXTI_PR_PR20EXTI_PR_PR21EXTI_PR_PR22EXTI_PR_PR23FLASH_ACR_LATENCYFLASH_ACR_PRFTENFLASH_ACR_ACC64FLASH_ACR_SLEEP_PDFLASH_ACR_RUN_PDFLASH_PECR_PELOCKFLASH_PECR_PRGLOCKFLASH_PECR_OPTLOCKFLASH_PECR_PROGFLASH_PECR_DATAFLASH_PECR_FTDWFLASH_PECR_ERASEFLASH_PECR_FPRGFLASH_PECR_PARALLBANKFLASH_PECR_EOPIEFLASH_PECR_ERRIEFLASH_PECR_OBL_LAUNCHFLASH_PDKEYR_PDKEYRFLASH_PEKEYR_PEKEYRFLASH_PRGKEYR_PRGKEYRFLASH_OPTKEYR_OPTKEYRFLASH_SR_BSYFLASH_SR_EOPFLASH_SR_ENHVFLASH_SR_READYFLASH_SR_WRPERRFLASH_SR_PGAERRFLASH_SR_SIZERRFLASH_SR_OPTVERRFLASH_SR_OPTVERRUSRFLASH_OBR_RDPRTFLASH_OBR_BOR_LEVFLASH_OBR_USERFLASH_OBR_IWDG_SWFLASH_OBR_nRST_STOPFLASH_OBR_nRST_STDBYFLASH_OBR_nRST_BFB2FLASH_WRPR_WRPFLASH_WRPR1_WRPFLASH_WRPR2_WRPFSMC_BCR1_MBKENFSMC_BCR1_MUXENFSMC_BCR1_MTYPFSMC_BCR1_MTYP_0FSMC_BCR1_MTYP_1FSMC_BCR1_MWIDFSMC_BCR1_MWID_0FSMC_BCR1_MWID_1FSMC_BCR1_FACCENFSMC_BCR1_BURSTENFSMC_BCR1_WAITPOLFSMC_BCR1_WRAPMODFSMC_BCR1_WAITCFGFSMC_BCR1_WRENFSMC_BCR1_WAITENFSMC_BCR1_EXTMODFSMC_BCR1_ASYNCWAITFSMC_BCR1_CBURSTRWFSMC_BCR2_MBKENFSMC_BCR2_MUXENFSMC_BCR2_MTYPFSMC_BCR2_MTYP_0FSMC_BCR2_MTYP_1FSMC_BCR2_MWIDFSMC_BCR2_MWID_0FSMC_BCR2_MWID_1FSMC_BCR2_FACCENFSMC_BCR2_BURSTENFSMC_BCR2_WAITPOLFSMC_BCR2_WRAPMODFSMC_BCR2_WAITCFGFSMC_BCR2_WRENFSMC_BCR2_WAITENFSMC_BCR2_EXTMODFSMC_BCR2_ASYNCWAITFSMC_BCR2_CBURSTRWFSMC_BCR3_MBKENFSMC_BCR3_MUXENFSMC_BCR3_MTYPFSMC_BCR3_MTYP_0FSMC_BCR3_MTYP_1FSMC_BCR3_MWIDFSMC_BCR3_MWID_0FSMC_BCR3_MWID_1FSMC_BCR3_FACCENFSMC_BCR3_BURSTENFSMC_BCR3_WAITPOLFSMC_BCR3_WRAPMODFSMC_BCR3_WAITCFGFSMC_BCR3_WRENFSMC_BCR3_WAITENFSMC_BCR3_EXTMODFSMC_BCR3_ASYNCWAITFSMC_BCR3_CBURSTRWFSMC_BCR4_MBKENFSMC_BCR4_MUXENFSMC_BCR4_MTYPFSMC_BCR4_MTYP_0FSMC_BCR4_MTYP_1FSMC_BCR4_MWIDFSMC_BCR4_MWID_0FSMC_BCR4_MWID_1FSMC_BCR4_FACCENFSMC_BCR4_BURSTENFSMC_BCR4_WAITPOLFSMC_BCR4_WRAPMODFSMC_BCR4_WAITCFGFSMC_BCR4_WRENFSMC_BCR4_WAITENFSMC_BCR4_EXTMODFSMC_BCR4_ASYNCWAITFSMC_BCR4_CBURSTRWFSMC_BTR1_ADDSETFSMC_BTR1_ADDSET_0FSMC_BTR1_ADDSET_1FSMC_BTR1_ADDSET_2FSMC_BTR1_ADDSET_3FSMC_BTR1_ADDHLDFSMC_BTR1_ADDHLD_0FSMC_BTR1_ADDHLD_1FSMC_BTR1_ADDHLD_2FSMC_BTR1_ADDHLD_3FSMC_BTR1_DATASTFSMC_BTR1_DATAST_0FSMC_BTR1_DATAST_1FSMC_BTR1_DATAST_2FSMC_BTR1_DATAST_3FSMC_BTR1_BUSTURNFSMC_BTR1_BUSTURN_0FSMC_BTR1_BUSTURN_1FSMC_BTR1_BUSTURN_2FSMC_BTR1_BUSTURN_3FSMC_BTR1_CLKDIVFSMC_BTR1_CLKDIV_0FSMC_BTR1_CLKDIV_1FSMC_BTR1_CLKDIV_2FSMC_BTR1_CLKDIV_3FSMC_BTR1_DATLATFSMC_BTR1_DATLAT_0FSMC_BTR1_DATLAT_1FSMC_BTR1_DATLAT_2FSMC_BTR1_DATLAT_3FSMC_BTR1_ACCMODFSMC_BTR1_ACCMOD_0FSMC_BTR1_ACCMOD_1FSMC_BTR2_ADDSETFSMC_BTR2_ADDSET_0FSMC_BTR2_ADDSET_1FSMC_BTR2_ADDSET_2FSMC_BTR2_ADDSET_3FSMC_BTR2_ADDHLDFSMC_BTR2_ADDHLD_0FSMC_BTR2_ADDHLD_1FSMC_BTR2_ADDHLD_2FSMC_BTR2_ADDHLD_3FSMC_BTR2_DATASTFSMC_BTR2_DATAST_0FSMC_BTR2_DATAST_1FSMC_BTR2_DATAST_2FSMC_BTR2_DATAST_3FSMC_BTR2_BUSTURNFSMC_BTR2_BUSTURN_0FSMC_BTR2_BUSTURN_1FSMC_BTR2_BUSTURN_2FSMC_BTR2_BUSTURN_3FSMC_BTR2_CLKDIVFSMC_BTR2_CLKDIV_0FSMC_BTR2_CLKDIV_1FSMC_BTR2_CLKDIV_2FSMC_BTR2_CLKDIV_3FSMC_BTR2_DATLATFSMC_BTR2_DATLAT_0FSMC_BTR2_DATLAT_1FSMC_BTR2_DATLAT_2FSMC_BTR2_DATLAT_3FSMC_BTR2_ACCMODFSMC_BTR2_ACCMOD_0FSMC_BTR2_ACCMOD_1FSMC_BTR3_ADDSETFSMC_BTR3_ADDSET_0FSMC_BTR3_ADDSET_1FSMC_BTR3_ADDSET_2FSMC_BTR3_ADDSET_3FSMC_BTR3_ADDHLDFSMC_BTR3_ADDHLD_0FSMC_BTR3_ADDHLD_1FSMC_BTR3_ADDHLD_2FSMC_BTR3_ADDHLD_3FSMC_BTR3_DATASTFSMC_BTR3_DATAST_0FSMC_BTR3_DATAST_1FSMC_BTR3_DATAST_2FSMC_BTR3_DATAST_3FSMC_BTR3_BUSTURNFSMC_BTR3_BUSTURN_0FSMC_BTR3_BUSTURN_1FSMC_BTR3_BUSTURN_2FSMC_BTR3_BUSTURN_3FSMC_BTR3_CLKDIVFSMC_BTR3_CLKDIV_0FSMC_BTR3_CLKDIV_1FSMC_BTR3_CLKDIV_2FSMC_BTR3_CLKDIV_3FSMC_BTR3_DATLATFSMC_BTR3_DATLAT_0FSMC_BTR3_DATLAT_1FSMC_BTR3_DATLAT_2FSMC_BTR3_DATLAT_3FSMC_BTR3_ACCMODFSMC_BTR3_ACCMOD_0FSMC_BTR3_ACCMOD_1FSMC_BTR4_ADDSETFSMC_BTR4_ADDSET_0FSMC_BTR4_ADDSET_1FSMC_BTR4_ADDSET_2FSMC_BTR4_ADDSET_3FSMC_BTR4_ADDHLDFSMC_BTR4_ADDHLD_0FSMC_BTR4_ADDHLD_1FSMC_BTR4_ADDHLD_2FSMC_BTR4_ADDHLD_3FSMC_BTR4_DATASTFSMC_BTR4_DATAST_0FSMC_BTR4_DATAST_1FSMC_BTR4_DATAST_2FSMC_BTR4_DATAST_3FSMC_BTR4_BUSTURNFSMC_BTR4_BUSTURN_0FSMC_BTR4_BUSTURN_1FSMC_BTR4_BUSTURN_2FSMC_BTR4_BUSTURN_3FSMC_BTR4_CLKDIVFSMC_BTR4_CLKDIV_0FSMC_BTR4_CLKDIV_1FSMC_BTR4_CLKDIV_2FSMC_BTR4_CLKDIV_3FSMC_BTR4_DATLATFSMC_BTR4_DATLAT_0FSMC_BTR4_DATLAT_1FSMC_BTR4_DATLAT_2FSMC_BTR4_DATLAT_3FSMC_BTR4_ACCMODFSMC_BTR4_ACCMOD_0FSMC_BTR4_ACCMOD_1FSMC_BWTR1_ADDSETFSMC_BWTR1_ADDSET_0FSMC_BWTR1_ADDSET_1FSMC_BWTR1_ADDSET_2FSMC_BWTR1_ADDSET_3FSMC_BWTR1_ADDHLDFSMC_BWTR1_ADDHLD_0FSMC_BWTR1_ADDHLD_1FSMC_BWTR1_ADDHLD_2FSMC_BWTR1_ADDHLD_3FSMC_BWTR1_DATASTFSMC_BWTR1_DATAST_0FSMC_BWTR1_DATAST_1FSMC_BWTR1_DATAST_2FSMC_BWTR1_DATAST_3FSMC_BWTR1_CLKDIVFSMC_BWTR1_CLKDIV_0FSMC_BWTR1_CLKDIV_1FSMC_BWTR1_CLKDIV_2FSMC_BWTR1_CLKDIV_3FSMC_BWTR1_DATLATFSMC_BWTR1_DATLAT_0FSMC_BWTR1_DATLAT_1FSMC_BWTR1_DATLAT_2FSMC_BWTR1_DATLAT_3FSMC_BWTR1_ACCMODFSMC_BWTR1_ACCMOD_0FSMC_BWTR1_ACCMOD_1FSMC_BWTR2_ADDSETFSMC_BWTR2_ADDSET_0FSMC_BWTR2_ADDSET_1FSMC_BWTR2_ADDSET_2FSMC_BWTR2_ADDSET_3FSMC_BWTR2_ADDHLDFSMC_BWTR2_ADDHLD_0FSMC_BWTR2_ADDHLD_1FSMC_BWTR2_ADDHLD_2FSMC_BWTR2_ADDHLD_3FSMC_BWTR2_DATASTFSMC_BWTR2_DATAST_0FSMC_BWTR2_DATAST_1FSMC_BWTR2_DATAST_2FSMC_BWTR2_DATAST_3FSMC_BWTR2_CLKDIVFSMC_BWTR2_CLKDIV_0FSMC_BWTR2_CLKDIV_1FSMC_BWTR2_CLKDIV_2FSMC_BWTR2_CLKDIV_3FSMC_BWTR2_DATLATFSMC_BWTR2_DATLAT_0FSMC_BWTR2_DATLAT_1FSMC_BWTR2_DATLAT_2FSMC_BWTR2_DATLAT_3FSMC_BWTR2_ACCMODFSMC_BWTR2_ACCMOD_0FSMC_BWTR2_ACCMOD_1FSMC_BWTR3_ADDSETFSMC_BWTR3_ADDSET_0FSMC_BWTR3_ADDSET_1FSMC_BWTR3_ADDSET_2FSMC_BWTR3_ADDSET_3FSMC_BWTR3_ADDHLDFSMC_BWTR3_ADDHLD_0FSMC_BWTR3_ADDHLD_1FSMC_BWTR3_ADDHLD_2FSMC_BWTR3_ADDHLD_3FSMC_BWTR3_DATASTFSMC_BWTR3_DATAST_0FSMC_BWTR3_DATAST_1FSMC_BWTR3_DATAST_2FSMC_BWTR3_DATAST_3FSMC_BWTR3_CLKDIVFSMC_BWTR3_CLKDIV_0FSMC_BWTR3_CLKDIV_1FSMC_BWTR3_CLKDIV_2FSMC_BWTR3_CLKDIV_3FSMC_BWTR3_DATLATFSMC_BWTR3_DATLAT_0FSMC_BWTR3_DATLAT_1FSMC_BWTR3_DATLAT_2FSMC_BWTR3_DATLAT_3FSMC_BWTR3_ACCMODFSMC_BWTR3_ACCMOD_0FSMC_BWTR3_ACCMOD_1FSMC_BWTR4_ADDSETFSMC_BWTR4_ADDSET_0FSMC_BWTR4_ADDSET_1FSMC_BWTR4_ADDSET_2FSMC_BWTR4_ADDSET_3FSMC_BWTR4_ADDHLDFSMC_BWTR4_ADDHLD_0FSMC_BWTR4_ADDHLD_1FSMC_BWTR4_ADDHLD_2FSMC_BWTR4_ADDHLD_3FSMC_BWTR4_DATASTFSMC_BWTR4_DATAST_0FSMC_BWTR4_DATAST_1FSMC_BWTR4_DATAST_2FSMC_BWTR4_DATAST_3FSMC_BWTR4_CLKDIVFSMC_BWTR4_CLKDIV_0FSMC_BWTR4_CLKDIV_1FSMC_BWTR4_CLKDIV_2FSMC_BWTR4_CLKDIV_3FSMC_BWTR4_DATLATFSMC_BWTR4_DATLAT_0FSMC_BWTR4_DATLAT_1FSMC_BWTR4_DATLAT_2FSMC_BWTR4_DATLAT_3FSMC_BWTR4_ACCMODFSMC_BWTR4_ACCMOD_0FSMC_BWTR4_ACCMOD_1GPIO_MODER_MODER0GPIO_MODER_MODER0_0GPIO_MODER_MODER0_1GPIO_MODER_MODER1GPIO_MODER_MODER1_0GPIO_MODER_MODER1_1GPIO_MODER_MODER2GPIO_MODER_MODER2_0GPIO_MODER_MODER2_1GPIO_MODER_MODER3GPIO_MODER_MODER3_0GPIO_MODER_MODER3_1GPIO_MODER_MODER4GPIO_MODER_MODER4_0GPIO_MODER_MODER4_1GPIO_MODER_MODER5GPIO_MODER_MODER5_0GPIO_MODER_MODER5_1GPIO_MODER_MODER6GPIO_MODER_MODER6_0GPIO_MODER_MODER6_1GPIO_MODER_MODER7GPIO_MODER_MODER7_0GPIO_MODER_MODER7_1GPIO_MODER_MODER8GPIO_MODER_MODER8_0GPIO_MODER_MODER8_1GPIO_MODER_MODER9GPIO_MODER_MODER9_0GPIO_MODER_MODER9_1GPIO_MODER_MODER10GPIO_MODER_MODER10_0GPIO_MODER_MODER10_1GPIO_MODER_MODER11GPIO_MODER_MODER11_0GPIO_MODER_MODER11_1GPIO_MODER_MODER12GPIO_MODER_MODER12_0GPIO_MODER_MODER12_1GPIO_MODER_MODER13GPIO_MODER_MODER13_0GPIO_MODER_MODER13_1GPIO_MODER_MODER14GPIO_MODER_MODER14_0GPIO_MODER_MODER14_1GPIO_MODER_MODER15GPIO_MODER_MODER15_0GPIO_MODER_MODER15_1GPIO_OTYPER_OT_0GPIO_OTYPER_OT_1GPIO_OTYPER_OT_2GPIO_OTYPER_OT_3GPIO_OTYPER_OT_4GPIO_OTYPER_OT_5GPIO_OTYPER_OT_6GPIO_OTYPER_OT_7GPIO_OTYPER_OT_8GPIO_OTYPER_OT_9GPIO_OTYPER_OT_10GPIO_OTYPER_OT_11GPIO_OTYPER_OT_12GPIO_OTYPER_OT_13GPIO_OTYPER_OT_14GPIO_OTYPER_OT_15GPIO_OSPEEDER_OSPEEDR0GPIO_OSPEEDER_OSPEEDR0_0GPIO_OSPEEDER_OSPEEDR0_1GPIO_OSPEEDER_OSPEEDR1GPIO_OSPEEDER_OSPEEDR1_0GPIO_OSPEEDER_OSPEEDR1_1GPIO_OSPEEDER_OSPEEDR2GPIO_OSPEEDER_OSPEEDR2_0GPIO_OSPEEDER_OSPEEDR2_1GPIO_OSPEEDER_OSPEEDR3GPIO_OSPEEDER_OSPEEDR3_0GPIO_OSPEEDER_OSPEEDR3_1GPIO_OSPEEDER_OSPEEDR4GPIO_OSPEEDER_OSPEEDR4_0GPIO_OSPEEDER_OSPEEDR4_1GPIO_OSPEEDER_OSPEEDR5GPIO_OSPEEDER_OSPEEDR5_0GPIO_OSPEEDER_OSPEEDR5_1GPIO_OSPEEDER_OSPEEDR6GPIO_OSPEEDER_OSPEEDR6_0GPIO_OSPEEDER_OSPEEDR6_1GPIO_OSPEEDER_OSPEEDR7GPIO_OSPEEDER_OSPEEDR7_0GPIO_OSPEEDER_OSPEEDR7_1GPIO_OSPEEDER_OSPEEDR8GPIO_OSPEEDER_OSPEEDR8_0GPIO_OSPEEDER_OSPEEDR8_1GPIO_OSPEEDER_OSPEEDR9GPIO_OSPEEDER_OSPEEDR9_0GPIO_OSPEEDER_OSPEEDR9_1GPIO_OSPEEDER_OSPEEDR10GPIO_OSPEEDER_OSPEEDR10_0GPIO_OSPEEDER_OSPEEDR10_1GPIO_OSPEEDER_OSPEEDR11GPIO_OSPEEDER_OSPEEDR11_0GPIO_OSPEEDER_OSPEEDR11_1GPIO_OSPEEDER_OSPEEDR12GPIO_OSPEEDER_OSPEEDR12_0GPIO_OSPEEDER_OSPEEDR12_1GPIO_OSPEEDER_OSPEEDR13GPIO_OSPEEDER_OSPEEDR13_0GPIO_OSPEEDER_OSPEEDR13_1GPIO_OSPEEDER_OSPEEDR14GPIO_OSPEEDER_OSPEEDR14_0GPIO_OSPEEDER_OSPEEDR14_1GPIO_OSPEEDER_OSPEEDR15GPIO_OSPEEDER_OSPEEDR15_0GPIO_OSPEEDER_OSPEEDR15_1GPIO_PUPDR_PUPDR0GPIO_PUPDR_PUPDR0_0GPIO_PUPDR_PUPDR0_1GPIO_PUPDR_PUPDR1GPIO_PUPDR_PUPDR1_0GPIO_PUPDR_PUPDR1_1GPIO_PUPDR_PUPDR2GPIO_PUPDR_PUPDR2_0GPIO_PUPDR_PUPDR2_1GPIO_PUPDR_PUPDR3GPIO_PUPDR_PUPDR3_0GPIO_PUPDR_PUPDR3_1GPIO_PUPDR_PUPDR4GPIO_PUPDR_PUPDR4_0GPIO_PUPDR_PUPDR4_1GPIO_PUPDR_PUPDR5GPIO_PUPDR_PUPDR5_0GPIO_PUPDR_PUPDR5_1GPIO_PUPDR_PUPDR6GPIO_PUPDR_PUPDR6_0GPIO_PUPDR_PUPDR6_1GPIO_PUPDR_PUPDR7GPIO_PUPDR_PUPDR7_0GPIO_PUPDR_PUPDR7_1GPIO_PUPDR_PUPDR8GPIO_PUPDR_PUPDR8_0GPIO_PUPDR_PUPDR8_1GPIO_PUPDR_PUPDR9GPIO_PUPDR_PUPDR9_0GPIO_PUPDR_PUPDR9_1GPIO_PUPDR_PUPDR10GPIO_PUPDR_PUPDR10_0GPIO_PUPDR_PUPDR10_1GPIO_PUPDR_PUPDR11GPIO_PUPDR_PUPDR11_0GPIO_PUPDR_PUPDR11_1GPIO_PUPDR_PUPDR12GPIO_PUPDR_PUPDR12_0GPIO_PUPDR_PUPDR12_1GPIO_PUPDR_PUPDR13GPIO_PUPDR_PUPDR13_0GPIO_PUPDR_PUPDR13_1GPIO_PUPDR_PUPDR14GPIO_PUPDR_PUPDR14_0GPIO_PUPDR_PUPDR14_1GPIO_PUPDR_PUPDR15GPIO_PUPDR_PUPDR15_0GPIO_PUPDR_PUPDR15_1GPIO_IDR_IDR_0GPIO_IDR_IDR_1GPIO_IDR_IDR_2GPIO_IDR_IDR_3GPIO_IDR_IDR_4GPIO_IDR_IDR_5GPIO_IDR_IDR_6GPIO_IDR_IDR_7GPIO_IDR_IDR_8GPIO_IDR_IDR_9GPIO_IDR_IDR_10GPIO_IDR_IDR_11GPIO_IDR_IDR_12GPIO_IDR_IDR_13GPIO_IDR_IDR_14GPIO_IDR_IDR_15GPIO_OTYPER_IDR_0GPIO_OTYPER_IDR_1GPIO_OTYPER_IDR_2GPIO_OTYPER_IDR_3GPIO_OTYPER_IDR_4GPIO_OTYPER_IDR_5GPIO_OTYPER_IDR_6GPIO_OTYPER_IDR_7GPIO_OTYPER_IDR_8GPIO_OTYPER_IDR_9GPIO_OTYPER_IDR_10GPIO_OTYPER_IDR_11GPIO_OTYPER_IDR_12GPIO_OTYPER_IDR_13GPIO_OTYPER_IDR_14GPIO_OTYPER_IDR_15GPIO_ODR_ODR_0GPIO_ODR_ODR_1GPIO_ODR_ODR_2GPIO_ODR_ODR_3GPIO_ODR_ODR_4GPIO_ODR_ODR_5GPIO_ODR_ODR_6GPIO_ODR_ODR_7GPIO_ODR_ODR_8GPIO_ODR_ODR_9GPIO_ODR_ODR_10GPIO_ODR_ODR_11GPIO_ODR_ODR_12GPIO_ODR_ODR_13GPIO_ODR_ODR_14GPIO_ODR_ODR_15GPIO_OTYPER_ODR_0GPIO_OTYPER_ODR_1GPIO_OTYPER_ODR_2GPIO_OTYPER_ODR_3GPIO_OTYPER_ODR_4GPIO_OTYPER_ODR_5GPIO_OTYPER_ODR_6GPIO_OTYPER_ODR_7GPIO_OTYPER_ODR_8GPIO_OTYPER_ODR_9GPIO_OTYPER_ODR_10GPIO_OTYPER_ODR_11GPIO_OTYPER_ODR_12GPIO_OTYPER_ODR_13GPIO_OTYPER_ODR_14GPIO_OTYPER_ODR_15GPIO_BSRR_BS_0GPIO_BSRR_BS_1GPIO_BSRR_BS_2GPIO_BSRR_BS_3GPIO_BSRR_BS_4GPIO_BSRR_BS_5GPIO_BSRR_BS_6GPIO_BSRR_BS_7GPIO_BSRR_BS_8GPIO_BSRR_BS_9GPIO_BSRR_BS_10GPIO_BSRR_BS_11GPIO_BSRR_BS_12GPIO_BSRR_BS_13GPIO_BSRR_BS_14GPIO_BSRR_BS_15GPIO_BSRR_BR_0GPIO_BSRR_BR_1GPIO_BSRR_BR_2GPIO_BSRR_BR_3GPIO_BSRR_BR_4GPIO_BSRR_BR_5GPIO_BSRR_BR_6GPIO_BSRR_BR_7GPIO_BSRR_BR_8GPIO_BSRR_BR_9GPIO_BSRR_BR_10GPIO_BSRR_BR_11GPIO_BSRR_BR_12GPIO_BSRR_BR_13GPIO_BSRR_BR_14GPIO_BSRR_BR_15GPIO_LCKR_LCK0GPIO_LCKR_LCK1GPIO_LCKR_LCK2GPIO_LCKR_LCK3GPIO_LCKR_LCK4GPIO_LCKR_LCK5GPIO_LCKR_LCK6GPIO_LCKR_LCK7GPIO_LCKR_LCK8GPIO_LCKR_LCK9GPIO_LCKR_LCK10GPIO_LCKR_LCK11GPIO_LCKR_LCK12GPIO_LCKR_LCK13GPIO_LCKR_LCK14GPIO_LCKR_LCK15GPIO_LCKR_LCKKGPIO_AFRL_AFRL0GPIO_AFRL_AFRL1GPIO_AFRL_AFRL2GPIO_AFRL_AFRL3GPIO_AFRL_AFRL4GPIO_AFRL_AFRL5GPIO_AFRL_AFRL6GPIO_AFRL_AFRL7GPIO_AFRH_AFRH8GPIO_AFRH_AFRH9GPIO_AFRH_AFRH10GPIO_AFRH_AFRH11GPIO_AFRH_AFRH12GPIO_AFRH_AFRH13GPIO_AFRH_AFRH14GPIO_AFRH_AFRH15I2C_CR1_PEI2C_CR1_SMBUSI2C_CR1_SMBTYPEI2C_CR1_ENARPI2C_CR1_ENPECI2C_CR1_ENGCI2C_CR1_NOSTRETCHI2C_CR1_STARTI2C_CR1_STOPI2C_CR1_ACKI2C_CR1_POSI2C_CR1_PECI2C_CR1_ALERTI2C_CR1_SWRSTI2C_CR2_FREQI2C_CR2_FREQ_0I2C_CR2_FREQ_1I2C_CR2_FREQ_2I2C_CR2_FREQ_3I2C_CR2_FREQ_4I2C_CR2_FREQ_5I2C_CR2_ITERRENI2C_CR2_ITEVTENI2C_CR2_ITBUFENI2C_CR2_DMAENI2C_CR2_LASTI2C_OAR1_ADD1_7I2C_OAR1_ADD8_9I2C_OAR1_ADD0I2C_OAR1_ADD1I2C_OAR1_ADD2I2C_OAR1_ADD3I2C_OAR1_ADD4I2C_OAR1_ADD5I2C_OAR1_ADD6I2C_OAR1_ADD7I2C_OAR1_ADD8I2C_OAR1_ADD9I2C_OAR1_ADDMODEI2C_OAR2_ENDUALI2C_OAR2_ADD2I2C_DR_DRI2C_SR1_SBI2C_SR1_ADDRI2C_SR1_BTFI2C_SR1_ADD10I2C_SR1_STOPFI2C_SR1_RXNEI2C_SR1_TXEI2C_SR1_BERRI2C_SR1_ARLOI2C_SR1_AFI2C_SR1_OVRI2C_SR1_PECERRI2C_SR1_TIMEOUTI2C_SR1_SMBALERTI2C_SR2_MSLI2C_SR2_BUSYI2C_SR2_TRAI2C_SR2_GENCALLI2C_SR2_SMBDEFAULTI2C_SR2_SMBHOSTI2C_SR2_DUALFI2C_SR2_PECI2C_CCR_CCRI2C_CCR_DUTYI2C_CCR_FSI2C_TRISE_TRISEIWDG_KR_KEYIWDG_PR_PRIWDG_PR_PR_0IWDG_PR_PR_1IWDG_PR_PR_2IWDG_RLR_RLIWDG_SR_PVUIWDG_SR_RVULCD_CR_LCDENLCD_CR_VSELLCD_CR_DUTYLCD_CR_DUTY_0LCD_CR_DUTY_1LCD_CR_DUTY_2LCD_CR_BIASLCD_CR_BIAS_0LCD_CR_BIAS_1LCD_CR_MUX_SEGLCD_FCR_HDLCD_FCR_SOFIELCD_FCR_UDDIELCD_FCR_PONLCD_FCR_PON_0LCD_FCR_PON_1LCD_FCR_PON_2LCD_FCR_DEADLCD_FCR_DEAD_0LCD_FCR_DEAD_1LCD_FCR_DEAD_2LCD_FCR_CCLCD_FCR_CC_0LCD_FCR_CC_1LCD_FCR_CC_2LCD_FCR_BLINKFLCD_FCR_BLINKF_0LCD_FCR_BLINKF_1LCD_FCR_BLINKF_2LCD_FCR_BLINKLCD_FCR_BLINK_0LCD_FCR_BLINK_1LCD_FCR_DIVLCD_FCR_PSLCD_SR_ENSLCD_SR_SOFLCD_SR_UDRLCD_SR_UDDLCD_SR_RDYLCD_SR_FCRSRLCD_CLR_SOFCLCD_CLR_UDDCLCD_RAM_SEGMENT_DATAPWR_CR_LPSDSRPWR_CR_PDDSPWR_CR_CWUFPWR_CR_CSBFPWR_CR_PVDEPWR_CR_PLSPWR_CR_PLS_0PWR_CR_PLS_1PWR_CR_PLS_2PWR_CR_PLS_LEV0PWR_CR_PLS_LEV1PWR_CR_PLS_LEV2PWR_CR_PLS_LEV3PWR_CR_PLS_LEV4PWR_CR_PLS_LEV5PWR_CR_PLS_LEV6PWR_CR_PLS_LEV7PWR_CR_DBPPWR_CR_ULPPWR_CR_FWUPWR_CR_VOSPWR_CR_VOS_0PWR_CR_VOS_1PWR_CR_LPRUNPWR_CSR_WUFPWR_CSR_SBFPWR_CSR_PVDOPWR_CSR_VREFINTRDYFPWR_CSR_VOSFPWR_CSR_REGLPFPWR_CSR_EWUP1PWR_CSR_EWUP2PWR_CSR_EWUP3RCC_CR_HSIONRCC_CR_HSIRDYRCC_CR_MSIONRCC_CR_MSIRDYRCC_CR_HSEONRCC_CR_HSERDYRCC_CR_HSEBYPRCC_CR_PLLONRCC_CR_PLLRDYRCC_CR_CSSONRCC_CR_RTCPRERCC_CR_RTCPRE_0RCC_CR_RTCPRE_1RCC_ICSCR_HSICALRCC_ICSCR_HSITRIMRCC_ICSCR_MSIRANGERCC_ICSCR_MSIRANGE_0RCC_ICSCR_MSIRANGE_1RCC_ICSCR_MSIRANGE_2RCC_ICSCR_MSIRANGE_3RCC_ICSCR_MSIRANGE_4RCC_ICSCR_MSIRANGE_5RCC_ICSCR_MSIRANGE_6RCC_ICSCR_MSICALRCC_ICSCR_MSITRIMRCC_CFGR_SWRCC_CFGR_SW_0RCC_CFGR_SW_1RCC_CFGR_SW_MSIRCC_CFGR_SW_HSIRCC_CFGR_SW_HSERCC_CFGR_SW_PLLRCC_CFGR_SWSRCC_CFGR_SWS_0RCC_CFGR_SWS_1RCC_CFGR_SWS_MSIRCC_CFGR_SWS_HSIRCC_CFGR_SWS_HSERCC_CFGR_SWS_PLLRCC_CFGR_HPRERCC_CFGR_HPRE_0RCC_CFGR_HPRE_1RCC_CFGR_HPRE_2RCC_CFGR_HPRE_3RCC_CFGR_HPRE_DIV1RCC_CFGR_HPRE_DIV2RCC_CFGR_HPRE_DIV4RCC_CFGR_HPRE_DIV8RCC_CFGR_HPRE_DIV16RCC_CFGR_HPRE_DIV64RCC_CFGR_HPRE_DIV128RCC_CFGR_HPRE_DIV256RCC_CFGR_HPRE_DIV512RCC_CFGR_PPRE1RCC_CFGR_PPRE1_0RCC_CFGR_PPRE1_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P8STM32_VOS_1P5STM32_VOS_1P2STM32_PLS_MASKSTM32_PLS_LEV0STM32_PLS_LEV1STM32_PLS_LEV2STM32_PLS_LEV3STM32_PLS_LEV4STM32_PLS_LEV5STM32_PLS_LEV6STM32_PLS_LEV7STM32_RTCPRE_MASKSTM32_RTCPRE_DIV2STM32_RTCPRE_DIV4STM32_RTCPRE_DIV8STM32_RTCPRE_DIV16STM32_SW_MSISTM32_SW_HSISTM32_SW_HSESTM32_SW_PLLSTM32_HPRE_DIV1STM32_HPRE_DIV2STM32_HPRE_DIV4STM32_HPRE_DIV8STM32_HPRE_DIV16STM32_HPRE_DIV64STM32_HPRE_DIV128STM32_HPRE_DIV256STM32_HPRE_DIV512STM32_PPRE1_DIV1STM32_PPRE1_DIV2STM32_PPRE1_DIV4STM32_PPRE1_DIV8STM32_PPRE1_DIV16STM32_PPRE2_DIV1STM32_PPRE2_DIV2STM32_PPRE2_DIV4STM32_PPRE2_DIV8STM32_PPRE2_DIV16STM32_PLLSRC_HSISTM32_PLLSRC_HSESTM32_MCOSEL_NOCLOCKSTM32_MCOSEL_SYSCLKSTM32_MCOSEL_HSISTM32_MCOSEL_MSISTM32_MCOSEL_HSESTM32_MCOSEL_PLLSTM32_MCOSEL_LSISTM32_MCOSEL_LSESTM32_MCOPRE_DIV1STM32_MCOPRE_DIV2STM32_MCOPRE_DIV4STM32_MCOPRE_DIV8STM32_MCOPRE_DIV16STM32_MSIRANGE_MASKSTM32_MSIRANGE_64KSTM32_MSIRANGE_128KSTM32_MSIRANGE_256KSTM32_MSIRANGE_512KSTM32_MSIRANGE_1MSTM32_MSIRANGE_2MSTM32_MSIRANGE_4MSTM32_RTCSEL_MASKSTM32_RTCSEL_NOCLOCKSTM32_RTCSEL_LSESTM32_RTCSEL_LSISTM32_RTCSEL_HSEDIVSTM32_HAS_ADC1STM32_HAS_ADC2STM32_HAS_ADC3STM32_HAS_ADC4STM32_HAS_CAN1STM32_HAS_CAN2STM32_CAN_MAX_FILTERSSTM32_HAS_DACSTM32_ADVANCED_DMASTM32_HAS_DMA1STM32_HAS_DMA2STM32_HAS_ETHSTM32_EXTI_NUM_CHANNELSSTM32_HAS_GPIOASTM32_HAS_GPIOBSTM32_HAS_GPIOCSTM32_HAS_GPIODSTM32_HAS_GPIOESTM32_HAS_GPIOFSTM32_HAS_GPIOGSTM32_HAS_GPIOHSTM32_HAS_GPIOISTM32_HAS_I2C1STM32_I2C1_RX_DMA_MSKSTM32_I2C1_RX_DMA_CHNSTM32_I2C1_TX_DMA_MSKSTM32_I2C1_TX_DMA_CHNSTM32_HAS_I2C2STM32_I2C2_RX_DMA_MSKSTM32_I2C2_RX_DMA_CHNSTM32_I2C2_TX_DMA_MSKSTM32_I2C2_TX_DMA_CHNSTM32_HAS_I2C3STM32_I2C3_RX_DMA_MSKSTM32_I2C3_RX_DMA_CHNSTM32_I2C3_TX_DMA_MSKSTM32_I2C3_TX_DMA_CHNSTM32_HAS_RTCSTM32_RTC_HAS_SUBSECONDSSTM32_RTC_IS_CALENDARSTM32_HAS_SDIOSTM32_HAS_SPI1STM32_SPI1_RX_DMA_MSKSTM32_SPI1_RX_DMA_CHNSTM32_SPI1_TX_DMA_MSKSTM32_SPI1_TX_DMA_CHNSTM32_HAS_SPI2STM32_SPI2_RX_DMA_MSKSTM32_SPI2_RX_DMA_CHNSTM32_SPI2_TX_DMA_MSKSTM32_SPI2_TX_DMA_CHNSTM32_HAS_SPI3STM32_SPI3_RX_DMA_MSKSTM32_SPI3_RX_DMA_CHNSTM32_SPI3_TX_DMA_MSKSTM32_SPI3_TX_DMA_CHNSTM32_HAS_TIM1STM32_HAS_TIM2STM32_HAS_TIM3STM32_HAS_TIM4STM32_HAS_TIM5STM32_HAS_TIM6STM32_HAS_TIM7STM32_HAS_TIM8STM32_HAS_TIM9STM32_HAS_TIM10STM32_HAS_TIM11STM32_HAS_TIM12STM32_HAS_TIM13STM32_HAS_TIM14STM32_HAS_TIM15STM32_HAS_TIM16STM32_HAS_TIM17STM32_HAS_TIM18STM32_HAS_TIM19STM32_HAS_USART1STM32_USART1_RX_DMA_MSKSTM32_USART1_RX_DMA_CHNSTM32_USART1_TX_DMA_MSKSTM32_USART1_TX_DMA_CHNSTM32_HAS_USART2STM32_USART2_RX_DMA_MSKSTM32_USART2_RX_DMA_CHNSTM32_USART2_TX_DMA_MSKSTM32_USART2_TX_DMA_CHNSTM32_HAS_USART3STM32_USART3_RX_DMA_MSKSTM32_USART3_RX_DMA_CHNSTM32_USART3_TX_DMA_MSKSTM32_USART3_TX_DMA_CHNSTM32_HAS_UART4STM32_UART4_RX_DMA_MSKSTM32_UART4_RX_DMA_CHNSTM32_UART4_TX_DMA_MSKSTM32_UART4_TX_DMA_CHNSTM32_HAS_UART5STM32_UART5_RX_DMA_MSKSTM32_UART5_RX_DMA_CHNSTM32_UART5_TX_DMA_MSKSTM32_UART5_TX_DMA_CHNSTM32_HAS_USART6STM32_USART6_RX_DMA_MSKSTM32_USART6_RX_DMA_CHNSTM32_USART6_TX_DMA_MSKSTM32_USART6_TX_DMA_CHNSTM32_HAS_USBSTM32_HAS_OTG1STM32_HAS_OTG2WWDG_IRQHandlerPVD_IRQHandlerTAMPER_STAMP_IRQHandlerRTC_WKUP_IRQHandlerFLASH_IRQHandlerRCC_IRQHandlerEXTI0_IRQHandlerEXTI1_IRQHandlerEXTI2_IRQHandlerEXTI3_IRQHandlerEXTI4_IRQHandlerDMA1_Ch1_IRQHandlerDMA1_Ch2_IRQHandlerDMA1_Ch3_IRQHandlerDMA1_Ch4_IRQHandlerDMA1_Ch5_IRQHandlerDMA1_Ch6_IRQHandlerDMA1_Ch7_IRQHandlerADC1_IRQHandlerUSB_HP_IRQHandlerUSB_LP_IRQHandlerDAC_IRQHandlerCOMP_IRQHandlerEXTI9_5_IRQHandlerTIM9_IRQHandlerTIM10_IRQHandlerTIM11_IRQHandlerLCD_IRQHandlerTIM2_IRQHandlerTIM3_IRQHandlerTIM4_IRQHandlerI2C1_EV_IRQHandlerI2C1_ER_IRQHandlerI2C2_EV_IRQHandlerI2C2_ER_IRQHandlerSPI1_IRQHandlerSPI2_IRQHandlerUSART1_IRQHandlerUSART2_IRQHandlerUSART3_IRQHandlerEXTI15_10_IRQHandlerRTC_Alarm_IRQHandlerUSB_FS_WKUP_IRQHandlerTIM6_IRQHandlerTIM7_IRQHandlerSTM32_HSECLK_MAXSTM32_SYSCLK_MAXSTM32_PLLVCO_MAXSTM32_PLLVCO_MINSTM32_PCLK1_MAXSTM32_PCLK2_MAXSTM32_0WS_THRESHOLDSTM32_HSI_AVAILABLESTM32_ACTIVATE_PLLSTM32_PLLMULSTM32_PLLDIVSTM32_PLLCLKINSTM32_PLLVCOSTM32_PLLCLKOUTSTM32_MSICLKSTM32_SYSCLKSTM32_HCLKSTM32_PCLK1STM32_PCLK2STM_MCODIVCLKSTM_MCOCLKSTM32_HSEDIVCLKSTM_RTCCLKSTM32_ADCCLKSTM32_USBCLKSTM32_TIMCLK1STM32_TIMCLK2STM32_FLASHBITS1STM32_FLASHBITS2hal_lld_get_counter_valuehal_lld_get_counter_frequencystm32_isr.h_STM32_ISR_H_STM32_TIM2_HANDLERSTM32_TIM3_HANDLERSTM32_TIM4_HANDLERSTM32_TIM2_NUMBERSTM32_TIM3_NUMBERSTM32_TIM4_NUMBERSTM32_USART1_HANDLERSTM32_USART2_HANDLERSTM32_USART3_HANDLERSTM32_USART1_NUMBERSTM32_USART2_NUMBERSTM32_USART3_NUMBERSTM32_USB1_HP_HANDLERSTM32_USB1_LP_HANDLERSTM32_USB1_HP_NUMBERSTM32_USB1_LP_NUMBERstm32_dma.h_STM32_DMA_H_STM32_DMA_STREAMSSTM32_DMA_ISR_MASKSTM32_DMA_GETCHANNELSTM32_DMA_IS_VALID_PRIORITYSTM32_DMA_STREAM_IDSTM32_DMA_STREAM_ID_MSKSTM32_DMA_IS_VALID_IDSTM32_DMA_STREAMSTM32_DMA1_STREAM1STM32_DMA1_STREAM2STM32_DMA1_STREAM3STM32_DMA1_STREAM4STM32_DMA1_STREAM5STM32_DMA1_STREAM6STM32_DMA1_STREAM7STM32_DMA_CR_ENSTM32_DMA_CR_TEIESTM32_DMA_CR_HTIESTM32_DMA_CR_TCIESTM32_DMA_CR_DIR_MASKSTM32_DMA_CR_DIR_P2MSTM32_DMA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MENTARY_OUTPUT_ACTIVE_LOWSTM32_PWM_USE_ADVANCEDSTM32_PWM_USE_TIM1STM32_PWM_USE_TIM5STM32_PWM_USE_TIM8STM32_PWM_USE_TIM9STM32_PWM_TIM1_IRQ_PRIORITYSTM32_PWM_TIM5_IRQ_PRIORITYSTM32_PWM_TIM8_IRQ_PRIORITYSTM32_PWM_TIM9_IRQ_PRIORITYpwm_lld_change_periodpwm_lld_is_channel_enabledPWM_FRACTION_TO_WIDTHPWM_DEGREES_TO_WIDTHPWM_PERCENTAGE_TO_WIDTHpwmChangePeriodIpwmEnableChannelIpwmDisableChannelIpwmIsChannelEnabledIrtc.h_RTC_H_serial.h_SERIAL_H_SD_PARITY_ERRORSD_FRAMING_ERRORSD_OVERRUN_ERRORSD_NOISE_ERRORSD_BREAK_DETECTEDserial_lld.h_SERIAL_LLD_H_STM32_SERIAL_USE_UART4STM32_SERIAL_USE_UART5STM32_SERIAL_USE_USART6STM32_SERIAL_UART4_PRIORITYSTM32_SERIAL_UART5_PRIORITYSTM32_SERIAL_USART6_PRIORITY_serial_driver_dataUSART_CR2_STOP1_BITSUSART_CR2_STOP0P5_BITSUSART_CR2_STOP2_BITSUSART_CR2_STOP1P5_BITS_serial_driver_methodssdPutWouldBlocksdGetWouldBlocksdPutsdPutTimeoutsdGetsdGetTimeoutsdWritesdWriteTimeoutsdAsynchronousWritesdReadsdReadTimeoutsdAsynchronousReadsdc.h_SDC_H_spi.h_SPI_H_spi_lld.h_SPI_LLD_H_STM32_SPI_USE_SPI3STM32_SPI_SPI3_IRQ_PRIORITYSTM32_SPI_SPI3_DMA_PRIORITYSTM32_SPI_SPI1_RX_DMA_STREAMSTM32_SPI_SPI1_TX_DMA_STREAMSTM32_SPI_SPI2_RX_DMA_STREAMSTM32_SPI_SPI2_TX_DMA_STREAMSTM32_SPI_SPI3_RX_DMA_STREAMSTM32_SPI_SPI3_TX_DMA_STREAMspiSelectIspiUnselectIspiStartIgnoreIspiStartExchangeIspiStartSendIspiStartReceiveIspiPolledExchange_spi_wait_s_spi_wakeup_isr_spi_isr_codeuart.h_UART_H_usb.h_USB_H_mmc_spi.h_MMC_SPI_H_serial_usb.h_SERIAL_USB_H_S2RTTMS2RTTUS2RTTRTT2SRTT2MSRTT2UShalGetCounterValuehalGetCounterFrequency_Ap_VA_LISTstruct _VA_LIST_Longlonglong long_ULonglongunsigned long long_Wchartunsigned short_Wintt_Ptrdifftint_Sizetunsigned int__Va_list__iar_Atexitvoid __iar_Atexit(void (*)(void))void (*)(void)_Wchar_State_Mbstatetstruct _Mbstatet_Off_Wstate_Fpoststruct _Fpost__iar_dlib_perthread_initializevoid __iar_dlib_perthread_initialize(void *)void *__iar_dlib_perthread_allocatevoid * __iar_dlib_perthread_allocate(void)__iar_dlib_perthread_destroyvoid __iar_dlib_perthread_destroy(void)__iar_dlib_perthread_deallocatevoid __iar_dlib_perthread_deallocate(void *)__iar_dlib_perthread_accessvoid * __iar_dlib_perthread_access(void *)__iar_Rmtx__iar_system_Mtxinitvoid __iar_system_Mtxinit(__iar_Rmtx *)m__iar_Rmtx *__iar_system_Mtxdstvoid __iar_system_Mtxdst(__iar_Rmtx *)__iar_system_Mtxlockvoid __iar_system_Mtxlock(__iar_Rmtx *)__iar_system_Mtxunlockvoid __iar_system_Mtxunlock(__iar_Rmtx *)__iar_file_Mtxinitvoid __iar_file_Mtxinit(__iar_Rmtx *)__iar_file_Mtxdstvoid __iar_file_Mtxdst(__iar_Rmtx *)__iar_file_Mtxlockvoid __iar_file_Mtxlock(__iar_Rmtx *)__iar_file_Mtxunlockvoid __iar_file_Mtxunlock(__iar_Rmtx *)__iar_clearlocksvoid __iar_clearlocks(void)_Once_t__iar_Locksyslock_Localevoid __iar_Locksyslock_Locale(void)__iar_Locksyslock_Mallocvoid __iar_Locksyslock_Malloc(void)__iar_Locksyslock_Streamvoid __iar_Locksyslock_Stream(void)__iar_Locksyslock_Debugvoid __iar_Locksyslock_Debug(void)__iar_Locksyslock_StaticGuardvoid __iar_Locksyslock_StaticGuard(void)__iar_Locksyslockvoid __iar_Locksyslock(unsigned int)__iar_Unlocksyslock_Localevoid __iar_Unlocksyslock_Locale(void)__iar_Unlocksyslock_Mallocvoid __iar_Unlocksyslock_Malloc(void)__iar_Unlocksyslock_Streamvoid __iar_Unlocksyslock_Stream(void)__iar_Unlocksyslock_Debugvoid __iar_Unlocksyslock_Debug(void)__iar_Unlocksyslock_StaticGuardvoid __iar_Unlocksyslock_StaticGuard(void)__iar_Unlocksyslockvoid __iar_Unlocksyslock(unsigned int)__iar_Initdynamicfilelockvoid __iar_Initdynamicfilelock(__iar_Rmtx *)__iar_Dstdynamicfilelockvoid __iar_Dstdynamicfilelock(__iar_Rmtx *)__iar_Lockdynamicfilelockvoid __iar_Lockdynamicfilelock(__iar_Rmtx *)__iar_Unlockdynamicfilelockvoid __iar_Unlockdynamicfilelock(__iar_Rmtx *)size_t__data_size_tptrdiff_twchar_tint8_tsigned charuint8_tunsigned charint16_tshortuint16_tint32_tuint32_tint64_tuint64_tint_least8_tuint_least8_tint_least16_tuint_least16_tint_least32_tuint_least32_tint_least64_tuint_least64_tint_fast8_tuint_fast8_tint_fast16_tuint_fast16_tint_fast32_tuint_fast32_tint_fast64_tuint_fast64_tintmax_tuintmax_tintptr_tlonguintptr_tunsigned long__data_intptr_t__data_uintptr_tbool_ttmode_ttstate_ttrefs_ttslices_ttprio_tmsg_teventid_teventmask_tflagsmask_tsystime_tcnt_tThreadstruct Threadp_nextp_prevThreadsQueuestruct ThreadsQueueThreadsListstruct ThreadsListregarm_tstkalign_textctxr0r1r2r3r12lr_thdpcxpsrintctxr4r5r6r7r8r9r10r11lrcontextr13struct intctxport_haltvoid port_halt(void)_port_initvoid _port_init(void)_port_irq_epiloguevoid _port_irq_epilogue(void)_port_switch_from_isrvoid _port_switch_from_isr(void)_port_exit_from_isrvoid _port_exit_from_isr(void)_port_switchvoid _port_switch(Thread *, Thread *)ntpThread *otp_port_thread_startvoid _port_thread_start(void)__no_operationvoid __no_operation(void)__disable_interruptvoid __disable_interrupt(void)__enable_interruptvoid __enable_interrupt(void)__istate_t__get_interrupt_state__istate_t __get_interrupt_state(void)__set_interrupt_statevoid __set_interrupt_state(__istate_t)__get_PSRunsigned long __get_PSR(void)__get_IPSRunsigned long __get_IPSR(void)__get_MSPunsigned long __get_MSP(void)__set_MSPvoid __set_MSP(unsigned long)__get_PSPunsigned long __get_PSP(void)__set_PSPvoid __set_PSP(unsigned long)__get_PRIMASKunsigned long __get_PRIMASK(void)__set_PRIMASKvoid __set_PRIMASK(unsigned long)__get_CONTROLunsigned long __get_CONTROL(void)__set_CONTROLvoid __set_CONTROL(unsigned long)__get_FAULTMASKunsigned long __get_FAULTMASK(void)__set_FAULTMASKvoid __set_FAULTMASK(unsigned long)__get_BASEPRIunsigned long __get_BASEPRI(void)__set_BASEPRIvoid __set_BASEPRI(unsigned long)__disable_fiqvoid __disable_fiq(void)__enable_fiqvoid __enable_fiq(void)__SWPunsigned long __SWP(unsigned long, unsigned long *)unsigned long *__SWPBunsigned char __SWPB(unsigned char, unsigned char *)unsigned char *__ul__MCRvoid __MCR(unsigned int, unsigned int, __ul, unsigned int, unsigned int, unsigned int)coprocopcode_1srcCRnCRmopcode_2__MRCunsigned long __MRC(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)__MCR2void __MCR2(unsigned int, unsigned int, __ul, unsigned int, unsigned int, unsigned int)__MRC2unsigned long __MRC2(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)__LDCvoid __LDC(unsigned int, unsigned int, const __ul *)const __ul *__LDCLvoid __LDCL(unsigned int, unsigned int, const __ul *)__LDC2void __LDC2(unsigned int, unsigned int, const __ul *)__LDC2Lvoid __LDC2L(unsigned int, unsigned int, const __ul *)__STCvoid __STC(unsigned int, unsigned int, __ul *)dst__ul *__STCLvoid __STCL(unsigned int, unsigned int, __ul *)__STC2void __STC2(unsigned int, unsigned int, __ul *)__STC2Lvoid __STC2L(unsigned int, unsigned int, __ul *)__LDC_noidxvoid __LDC_noidx(unsigned int, unsigned int, const __ul *, unsigned int)option__LDCL_noidxvoid __LDCL_noidx(unsigned int, unsigned int, const __ul *, unsigned int)__LDC2_noidxvoid __LDC2_noidx(unsigned int, unsigned int, const __ul *, unsigned int)__LDC2L_noidxvoid __LDC2L_noidx(unsigned int, unsigned int, const __ul *, unsigned int)__STC_noidxvoid __STC_noidx(unsigned int, unsigned int, __ul *, unsigned int)__STCL_noidxvoid __STCL_noidx(unsigned int, unsigned int, __ul *, unsigned int)__STC2_noidxvoid __STC2_noidx(unsigned int, unsigned int, __ul *, unsigned int)__STC2L_noidxvoid __STC2L_noidx(unsigned int, unsigned int, __ul *, unsigned int)__get_APSRunsigned long __get_APSR(void)__set_APSRvoid __set_APSR(unsigned long)__get_FPSCRunsigned long __get_FPSCR(void)__set_FPSCRvoid __set_FPSCR(unsigned long)__CLZunsigned char __CLZ(unsigned long)__QCFlagint __QCFlag(void)__reset_QC_flagvoid __reset_QC_flag(void)__SMULlong __SMUL(short, short)__REVunsigned long __REV(unsigned long)__REVSHlong __REVSH(short)__REV16unsigned long __REV16(unsigned long)__RBITunsigned long __RBIT(unsigned long)__LDREXBunsigned char __LDREXB(unsigned char *)__LDREXHunsigned short __LDREXH(unsigned short *)unsigned short *__LDREXunsigned long __LDREX(unsigned long *)__LDREXDunsigned long long __LDREXD(unsigned long long *)unsigned long long *__STREXBunsigned long __STREXB(unsigned char, unsigned char *)__STREXHunsigned long __STREXH(unsigned short, unsigned short *)__STREXunsigned long __STREX(unsigned long, unsigned long *)__STREXDunsigned long __STREXD(unsigned long long, unsigned long long *)__CLREXvoid __CLREX(void)__SEVvoid __SEV(void)__WFEvoid __WFE(void)__WFIvoid __WFI(void)__YIELDvoid __YIELD(void)__PLIvoid __PLI(const void *)const void *__PLDvoid __PLD(const void *)__PLDWvoid __PLDW(const void *)__SSATunsigned long __SSAT(unsigned long, unsigned int)valsat__USATunsigned long __USAT(unsigned long, unsigned int)__DMBvoid __DMB(void)__DSBvoid __DSB(void)__ISBvoid __ISB(void)IOREG8volatile uint8_tIOREG32volatile uint32_tCSRRVRCVRCBVRCMx_STstruct CMx_STISERunused1ICERunused2ISPRunused3ICPRunused4IABRunused5IPRunused6STIRCMx_NVICstruct CMx_NVICCPUIDICSRVTORAIRCRSCRCCRSHPRSHCSRCFSRHFSRDFSRMMFARBFARAFSRPFRDFRADRMMFRSARCPACRCMx_SCBstruct CMx_SCBFPCCRFPCARFPDSCRMVFR0MVFR1CMx_FPUstruct CMx_FPUDHCSRDCRSRDCRDRDEMCRCMx_SCSstruct CMx_SCSCTRLCYCCNTCPICNTEXCCNTSLEEPCNTLSUCNTFOLDCNTPCSRCMx_DWTstruct CMx_DWTnvicEnableVectorvoid nvicEnableVector(uint32_t, uint32_t)nprionvicDisableVectorvoid nvicDisableVector(uint32_t)nvicSetSystemHandlerPriorityvoid nvicSetSystemHandlerPriority(uint32_t, uint32_t)handlerchSysInitvoid chSysInit(void)chSysTimerHandlerIvoid chSysTimerHandlerI(void)vtfunc_tvoid (*)(void *)VirtualTimerstruct VirtualTimervt_nextvt_prevvt_timevt_funcvt_parvt_systimeVTListstruct VTListvtlist_vt_initvoid _vt_init(void)chVTSetIvoid chVTSetI(VirtualTimer *, systime_t, vtfunc_t, void *)vtpVirtualTimer *timevtfuncparchVTResetIvoid chVTResetI(VirtualTimer *)chTimeIsWithinbool_t chTimeIsWithin(systime_t, systime_t)startendr_queuer_prior_ctxstruct contextr_newerr_olderr_currentReadyListstruct ReadyListrlist_scheduler_initvoid _scheduler_init(void)chSchReadyIThread * chSchReadyI(Thread *)tpchSchGoSleepSvoid chSchGoSleepS(tstate_t)newstatechSchGoSleepTimeoutSmsg_t chSchGoSleepTimeoutS(tstate_t, systime_t)chSchWakeupSvoid chSchWakeupS(Thread *, msg_t)msgchSchRescheduleSvoid chSchRescheduleS(void)chSchDoRescheduleBehindvoid chSchDoRescheduleBehind(void)chSchDoRescheduleAheadvoid chSchDoRescheduleAhead(void)chSchDoReschedulevoid chSchDoReschedule(void)Semaphores_queues_cntstruct SemaphorechSemInitvoid chSemInit(Semaphore *, cnt_t)spSemaphore *chSemResetvoid chSemReset(Semaphore *, cnt_t)chSemResetIvoid chSemResetI(Semaphore *, cnt_t)chSemWaitmsg_t chSemWait(Semaphore *)chSemWaitSmsg_t chSemWaitS(Semaphore *)chSemWaitTimeoutmsg_t chSemWaitTimeout(Semaphore *, systime_t)chSemWaitTimeoutSmsg_t chSemWaitTimeoutS(Semaphore *, systime_t)chSemSignalvoid chSemSignal(Semaphore *)chSemSignalIvoid chSemSignalI(Semaphore *)chSemAddCounterIvoid chSemAddCounterI(Semaphore *, cnt_t)chSemSignalWaitmsg_t chSemSignalWait(Semaphore *, Semaphore *)spsspwbs_semBinarySemaphorestruct BinarySemaphoreMutexm_queuem_ownerm_nextstruct MutexchMtxInitvoid chMtxInit(Mutex *)mpMutex *chMtxLockvoid chMtxLock(Mutex *)chMtxLockSvoid chMtxLockS(Mutex *)chMtxTryLockbool_t chMtxTryLock(Mutex *)chMtxTryLockSbool_t chMtxTryLockS(Mutex *)chMtxUnlockMutex * chMtxUnlock(void)chMtxUnlockSMutex * chMtxUnlockS(void)chMtxUnlockAllvoid chMtxUnlockAll(void)CondVarc_queuestruct CondVarchCondInitvoid chCondInit(CondVar *)cpCondVar *chCondSignalvoid chCondSignal(CondVar *)chCondSignalIvoid chCondSignalI(CondVar *)chCondBroadcastvoid chCondBroadcast(CondVar *)chCondBroadcastIvoid chCondBroadcastI(CondVar *)chCondWaitmsg_t chCondWait(CondVar *)chCondWaitSmsg_t chCondWaitS(CondVar *)chCondWaitTimeoutmsg_t chCondWaitTimeout(CondVar *, systime_t)chCondWaitTimeoutSmsg_t chCondWaitTimeoutS(CondVar *, systime_t)EventListenerstruct EventListenerel_nextel_listenerel_maskel_flagsEventSourcees_nextstruct EventSourceevhandler_tvoid (*)(eventid_t)chEvtRegisterMaskvoid chEvtRegisterMask(EventSource *, EventListener *, eventmask_t)espEventSource *elpEventListener *maskchEvtUnregistervoid chEvtUnregister(EventSource *, EventListener *)chEvtGetAndClearEventseventmask_t chEvtGetAndClearEvents(eventmask_t)chEvtAddEventseventmask_t chEvtAddEvents(eventmask_t)chEvtGetAndClearFlagsflagsmask_t chEvtGetAndClearFlags(EventListener *)chEvtGetAndClearFlagsIflagsmask_t chEvtGetAndClearFlagsI(EventListener *)chEvtSignalvoid chEvtSignal(Thread *, eventmask_t)chEvtSignalIvoid chEvtSignalI(Thread *, eventmask_t)chEvtBroadcastFlagsvoid chEvtBroadcastFlags(EventSource *, flagsmask_t)flagschEvtBroadcastFlagsIvoid chEvtBroadcastFlagsI(EventSource *, flagsmask_t)chEvtDispatchvoid chEvtDispatch(const evhandler_t *, eventmask_t)handlersconst evhandler_t *chEvtWaitOneeventmask_t chEvtWaitOne(eventmask_t)chEvtWaitAnyeventmask_t chEvtWaitAny(eventmask_t)chEvtWaitAlleventmask_t chEvtWaitAll(eventmask_t)chEvtWaitOneTimeouteventmask_t chEvtWaitOneTimeout(eventmask_t, systime_t)chEvtWaitAnyTimeouteventmask_t chEvtWaitAnyTimeout(eventmask_t, systime_t)chEvtWaitAllTimeouteventmask_t chEvtWaitAllTimeout(eventmask_t, systime_t)chMsgSendmsg_t chMsgSend(Thread *, msg_t)chMsgWaitThread * chMsgWait(void)chMsgReleasevoid chMsgRelease(Thread *, msg_t)mb_buffermb_topmb_wrptrmb_rdptrmb_fullsemmb_emptysemMailboxstruct MailboxchMBInitvoid chMBInit(Mailbox *, msg_t *, cnt_t)mbpMailbox *bufmsg_t *chMBResetvoid chMBReset(Mailbox *)chMBPostmsg_t chMBPost(Mailbox *, msg_t, systime_t)timeoutchMBPostSmsg_t chMBPostS(Mailbox *, msg_t, systime_t)chMBPostImsg_t chMBPostI(Mailbox *, msg_t)chMBPostAheadmsg_t chMBPostAhead(Mailbox *, msg_t, systime_t)chMBPostAheadSmsg_t chMBPostAheadS(Mailbox *, msg_t, systime_t)chMBPostAheadImsg_t chMBPostAheadI(Mailbox *, msg_t)chMBFetchmsg_t chMBFetch(Mailbox *, msg_t *, systime_t)msgpchMBFetchSmsg_t chMBFetchS(Mailbox *, msg_t *, systime_t)chMBFetchImsg_t chMBFetchI(Mailbox *, msg_t *)memgetfunc_tvoid *(*)(size_t)size_core_initvoid _core_init(void)chCoreAllocvoid * chCoreAlloc(size_t)chCoreAllocIvoid * chCoreAllocI(size_t)chCoreStatussize_t chCoreStatus(void)memory_heapMemoryHeapstruct memory_heapheap_headeralignnextunion heap_headerheapuhh_providerh_freeh_mtx_heap_initvoid _heap_init(void)chHeapInitvoid chHeapInit(MemoryHeap *, void *, size_t)heappMemoryHeap *chHeapAllocvoid * chHeapAlloc(MemoryHeap *, size_t)chHeapFreevoid chHeapFree(void *)pchHeapStatussize_t chHeapStatus(MemoryHeap *, size_t *)sizepsize_t *pool_headerph_nextstruct pool_headermp_nextmp_object_sizemp_providerMemoryPoolstruct MemoryPoolchPoolInitvoid chPoolInit(MemoryPool *, size_t, memgetfunc_t)MemoryPool *providerchPoolLoadArrayvoid chPoolLoadArray(MemoryPool *, void *, size_t)chPoolAllocIvoid * chPoolAllocI(MemoryPool *)chPoolAllocvoid * chPoolAlloc(MemoryPool *)chPoolFreeIvoid chPoolFreeI(MemoryPool *, void *)objpchPoolFreevoid chPoolFree(MemoryPool *, void *)p_priop_ctxp_newerp_olderp_namep_statep_flagsp_refsp_preemptp_timerdymsgexitcodewtobjpewmaskp_up_waitingp_msgqueuep_msgp_ependingp_mtxlistp_realpriop_mpooltfunc_tmsg_t (*)(void *)_thread_initThread * _thread_init(Thread *, tprio_t)chThdCreateIThread * chThdCreateI(void *, size_t, tprio_t, tfunc_t, void *)wsppfargchThdCreateStaticThread * chThdCreateStatic(void *, size_t, tprio_t, tfunc_t, void *)chThdSetPrioritytprio_t chThdSetPriority(tprio_t)newpriochThdResumeThread * chThdResume(Thread *)chThdTerminatevoid chThdTerminate(Thread *)chThdSleepvoid chThdSleep(systime_t)chThdSleepUntilvoid chThdSleepUntil(systime_t)chThdYieldvoid chThdYield(void)chThdExitvoid chThdExit(msg_t)chThdExitSvoid chThdExitS(msg_t)chThdWaitmsg_t chThdWait(Thread *)chThdAddRefThread * chThdAddRef(Thread *)chThdReleasevoid chThdRelease(Thread *)chThdCreateFromHeapThread * chThdCreateFromHeap(MemoryHeap *, size_t, tprio_t, tfunc_t, void *)chThdCreateFromMemoryPoolThread * chThdCreateFromMemoryPool(MemoryPool *, tprio_t, tfunc_t, void *)ch_identifierch_zeroch_sizech_versionch_ptrsizech_timesizech_threadsizecf_off_priocf_off_ctxcf_off_newercf_off_oldercf_off_namecf_off_stklimitcf_off_statecf_off_flagscf_off_refscf_off_preemptcf_off_timechdebug_tstruct chdebug_tch_debugchRegFirstThreadThread * chRegFirstThread(void)chRegNextThreadThread * chRegNextThread(Thread *)prio_insertvoid prio_insert(Thread *, ThreadsQueue *)tqpThreadsQueue *queue_insertvoid queue_insert(Thread *, ThreadsQueue *)fifo_removeThread * fifo_remove(ThreadsQueue *)lifo_removeThread * lifo_remove(ThreadsQueue *)dequeueThread * dequeue(Thread *)list_insertvoid list_insert(Thread *, ThreadsList *)tlpThreadsList *list_removeThread * list_remove(ThreadsList *)GenericQueuestruct GenericQueueqnotify_tvoid (*)(GenericQueue *)qpGenericQueue *q_waitingq_counterq_bufferq_topq_wrptrq_rdptrq_notifyq_linkInputQueueOutputQueuechIQInitvoid chIQInit(InputQueue *, uint8_t *, size_t, qnotify_t, void *)iqpInputQueue *bpuint8_t *infylinkchIQResetIvoid chIQResetI(InputQueue *)chIQPutImsg_t chIQPutI(InputQueue *, uint8_t)bchIQGetTimeoutmsg_t chIQGetTimeout(InputQueue *, systime_t)chIQReadTimeoutsize_t chIQReadTimeout(InputQueue *, uint8_t *, size_t, systime_t)chOQInitvoid chOQInit(OutputQueue *, uint8_t *, size_t, qnotify_t, void *)oqpOutputQueue *onfychOQResetIvoid chOQResetI(OutputQueue *)chOQPutTimeoutmsg_t chOQPutTimeout(OutputQueue *, uint8_t, systime_t)chOQGetImsg_t chOQGetI(OutputQueue *)chOQWriteTimeoutsize_t chOQWriteTimeout(OutputQueue *, const uint8_t *, size_t, systime_t)const uint8_t *BaseSequentialStreamVMTwriteinstancereadputgetvmtstruct BaseSequentialStreamVMTBaseSequentialStreamstruct BaseSequentialStreamfileoffset_tBaseFileStreamVMTclosegeterrorgetsizegetpositionlseekoffsetstruct BaseFileStreamVMTBaseFileStreamstruct BaseFileStream_idle_thread_wastruct extctx_idle_threadvoid _idle_thread(void *)boardInitvoid boardInit(void)IRQnNonMaskableInt_IRQnMemoryManagement_IRQnBusFault_IRQnUsageFault_IRQnSVC_IRQnDebugMonitor_IRQnPendSV_IRQnSysTick_IRQnWWDG_IRQnPVD_IRQnTAMPER_STAMP_IRQnRTC_WKUP_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQnEXTI4_IRQnDMA1_Channel1_IRQnDMA1_Channel2_IRQnDMA1_Channel3_IRQnDMA1_Channel4_IRQnDMA1_Channel5_IRQnDMA1_Channel6_IRQnDMA1_Channel7_IRQnADC1_IRQnUSB_HP_IRQnUSB_LP_IRQnDAC_IRQnCOMP_IRQnEXTI9_5_IRQnLCD_IRQnTIM9_IRQnTIM10_IRQnTIM11_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQnI2C2_EV_IRQnI2C2_ER_IRQnSPI1_IRQnSPI2_IRQnUSART1_IRQnUSART2_IRQnUSART3_IRQnEXTI15_10_IRQnRTC_Alarm_IRQnUSB_FS_WKUP_IRQnTIM6_IRQnTIM7_IRQnIRQn_Typeenum IRQn__get_xPSRuint32_t __get_xPSR(void)__RORuint32_t __ROR(uint32_t, uint32_t)op1op2_reserved0QVCZNwAPSR_Typeunion APSR_TypeISRIPSR_Typeunion IPSR_TypeTITxPSR_Typeunion xPSR_TypenPRIVSPSELFPCACONTROL_Typeunion CONTROL_TypeRESERVED0RSERVED1RESERVED2RESERVED3RESERVED4IPRESERVED5NVIC_Typestruct NVIC_TypeSHPISARSCB_Typestruct SCB_TypeICTRACTLRSCnSCB_Typestruct SCnSCB_TypeLOADVALCALIBSysTick_Typestruct SysTick_Typeu8u16u32PORTTERRESERVED1TPRTCRIWRIRRIMCRLARLSRPID4PID5PID6PID7PID0PID1PID2PID3CID0CID1CID2CID3ITM_Typestruct ITM_TypeCOMP0MASK0FUNCTION0COMP1MASK1FUNCTION1COMP2MASK2FUNCTION2COMP3MASK3FUNCTION3DWT_Typestruct DWT_TypeSSPSRCSPSRACPRSPPRFFSRFFCRFSCRTRIGGERFIFO0ITATBCTR2ITATBCTR0FIFO1ITCTRLCLAIMSETCLAIMCLRRESERVED7DEVIDDEVTYPETPI_Typestruct TPI_TypeTYPERNRRBARRASRRBAR_A1RASR_A1RBAR_A2RASR_A2RBAR_A3RASR_A3MPU_Typestruct MPU_TypeCoreDebug_Typestruct CoreDebug_TypeNVIC_SetPriorityGroupingvoid NVIC_SetPriorityGrouping(uint32_t)PriorityGroupreg_valuePriorityGroupTmpNVIC_GetPriorityGroupinguint32_t NVIC_GetPriorityGrouping(void)NVIC_EnableIRQvoid NVIC_EnableIRQ(IRQn_Type)NVIC_DisableIRQvoid NVIC_DisableIRQ(IRQn_Type)NVIC_GetPendingIRQuint32_t NVIC_GetPendingIRQ(IRQn_Type)NVIC_SetPendingIRQvoid NVIC_SetPendingIRQ(IRQn_Type)NVIC_ClearPendingIRQvoid NVIC_ClearPendingIRQ(IRQn_Type)NVIC_GetActiveuint32_t NVIC_GetActive(IRQn_Type)NVIC_SetPriorityvoid NVIC_SetPriority(IRQn_Type, uint32_t)priorityNVIC_GetPriorityuint32_t NVIC_GetPriority(IRQn_Type)NVIC_EncodePriorityuint32_t NVIC_EncodePriority(uint32_t, uint32_t, uint32_t)PreemptPrioritySubPriorityPreemptPriorityBitsSubPriorityBitsNVIC_DecodePriorityvoid NVIC_DecodePriority(uint32_t, uint32_t, uint32_t *, uint32_t *)PrioritypPreemptPriorityuint32_t *pSubPriorityNVIC_SystemResetvoid NVIC_SystemReset(void)SysTick_Configuint32_t SysTick_Config(uint32_t)ticksITM_RxBufferITM_SendCharuint32_t ITM_SendChar(uint32_t)chITM_ReceiveCharint32_t ITM_ReceiveChar(void)ITM_CheckCharint32_t ITM_CheckChar(void)RESETSETFlagStatusenum FlagStatusITStatusDISABLEENABLEFunctionalStateenum FunctionalStateERRORSUCCESSErrorStatusenum ErrorStatusSRCR1CR2SMPR1SMPR2SMPR3JOFR1JOFR2JOFR3JOFR4HTRLTRSQR1SQR2SQR3SQR4SQR5JSQRJDR1JDR2JDR3JDR4DRSMPR0ADC_TypeDefstruct ADC_TypeDefADC_Common_TypeDefstruct ADC_Common_TypeDefCRDINRDOUTRKEYR0KEYR1KEYR2KEYR3IVR0IVR1IVR2IVR3AES_TypeDefstruct AES_TypeDefCOMP_TypeDefstruct COMP_TypeDefIDRCRC_TypeDefstruct CRC_TypeDefSWTRIGRDHR12R1DHR12L1DHR8R1DHR12R2DHR12L2DHR8R2DHR12RDDHR12LDDHR8RDDOR1DOR2DAC_TypeDefstruct DAC_TypeDefIDCODEAPB1FZAPB2FZDBGMCU_TypeDefstruct DBGMCU_TypeDefCNDTRCPARCMARDMA_Channel_TypeDefstruct DMA_Channel_TypeDefIFCRDMA_TypeDefstruct DMA_TypeDefIMREMRRTSRFTSRSWIERPREXTI_TypeDefstruct EXTI_TypeDefACRPECRPDKEYRPEKEYRPRGKEYROPTKEYROBRWRPRRESERVEDWRPR1WRPR2FLASH_TypeDefstruct FLASH_TypeDefRDPUSERWRP01WRP23WRP45WRP67WRP89WRP1011OB_TypeDefstruct OB_TypeDefOTRLPOTROPAMP_TypeDefstruct OPAMP_TypeDefBTCRFSMC_Bank1_TypeDefstruct FSMC_Bank1_TypeDefBWTRFSMC_Bank1E_TypeDefstruct FSMC_Bank1E_TypeDefMEMRMPPMCEXTICRSYSCFG_TypeDefstruct SYSCFG_TypeDefOAR1OAR2SR1SR2RESERVED6TRISERESERVED8I2C_TypeDefstruct I2C_TypeDefKRRLRIWDG_TypeDefstruct IWDG_TypeDefFCRCLRRAMLCD_TypeDefstruct LCD_TypeDefPWR_TypeDefstruct PWR_TypeDefICSCRCFGRCIRAHBRSTRAPB2RSTRAPB1RSTRAHBENRAPB2ENRAPB1ENRAHBLPENRAPB2LPENRAPB1LPENRRCC_TypeDefstruct RCC_TypeDefICRASCR1ASCR2HYSCR1HYSCR2HYSCR3HYSCR4RI_TypeDefstruct RI_TypeDefTRPRERWUTRCALIBRALRMARALRMBRWPRSSRSHIFTRTSTRTSDRTSSSRCALRTAFCRALRMASSRALRMBSSRBKP0RBKP1RBKP2RBKP3RBKP4RBKP5RBKP6RBKP7RBKP8RBKP9RBKP10RBKP11RBKP12RBKP13RBKP14RBKP15RBKP16RBKP17RBKP18RBKP19RBKP20RBKP21RBKP22RBKP23RBKP24RBKP25RBKP26RBKP27RBKP28RBKP29RBKP30RBKP31RRTC_TypeDefstruct RTC_TypeDefPOWERCLKCRARGCMDRESPCMDRESP1RESP2RESP3RESP4DTIMERDLENDCTRLDCOUNTSTAMASKFIFOCNTFIFOSDIO_TypeDefstruct SDIO_TypeDefCRCPRRXCRCRTXCRCRI2SCFGRI2SPRSPI_TypeDefstruct SPI_TypeDefSMCRDIEREGRCCMR1CCMR2CCERCNTPSCRESERVED10ARRRESERVED12CCR1CCR2CCR3CCR4RESERVED17DCRRESERVED18DMARRESERVED19ORRESERVED20TIM_TypeDefstruct TIM_TypeDefBRRCR3GTPRUSART_TypeDefstruct USART_TypeDefCFRWWDG_TypeDefstruct WWDG_TypeDef_resvd0_resvd1_resvd2_resvd3_resvd4_resvd5_resvd6_resvd7_resvd8_resvd9RCR_resvd10BDTR_resvd11_resvd12_resvd13_resvd14stm32_tim_tstruct stm32_tim_thalclock_thalrtcnt_tchannelifcrishiftselfindexvectorstm32_dma_stream_tstruct stm32_dma_stream_tstm32_dmaisr_tvoid (*)(void *, uint32_t)_stm32_dma_streamsdmaInitvoid dmaInit(void)dmaStreamAllocatebool_t dmaStreamAllocate(const stm32_dma_stream_t *, uint32_t, stm32_dmaisr_t, void *)dmastpconst stm32_dma_stream_t *funcparamdmaStreamReleasevoid dmaStreamRelease(const stm32_dma_stream_t *)hal_lld_initvoid hal_lld_init(void)stm32_clock_initvoid stm32_clock_init(void)BaseChannelVMTputtgettwritetreadtstruct BaseChannelVMTBaseChannelstruct BaseChannelBaseAsynchronousChannelVMTstruct BaseAsynchronousChannelVMTeventBaseAsynchronousChannelstruct BaseAsynchronousChannelBLK_UNINITBLK_STOPBLK_ACTIVEBLK_CONNECTINGBLK_DISCONNECTINGBLK_READYBLK_READINGBLK_WRITINGBLK_SYNCINGblkstate_tenum blkstate_tblk_sizeblk_numBlockDeviceInfostruct BlockDeviceInfoBaseBlockDeviceVMTis_insertedis_protectedconnectdisconnectstartblkbuffersyncget_infobdipBlockDeviceInfo *struct BaseBlockDeviceVMTstateBaseBlockDevicestruct BaseBlockDeviceTimeMeasurementstruct TimeMeasurementtmpTimeMeasurement *stoplastworstbesttmInitvoid tmInit(void)tmObjectInitvoid tmObjectInit(TimeMeasurement *)MODEROTYPEROSPEEDRPUPDRODRWsetclearHBSRRLCKRAFRLAFRHGPIO_TypeDefstruct GPIO_TypeDefmoderotyperospeedrpupdrodrafrlafrhstm32_gpio_setup_tstruct stm32_gpio_setup_tPADataPBDataPCDataPDDataPEDataPHDataPALConfigstruct PALConfigioportmask_tiomode_tioportid_tGPIO_TypeDef *pal_default_config_pal_lld_initvoid _pal_lld_init(const PALConfig *)configconst PALConfig *_pal_lld_setgroupmodevoid _pal_lld_setgroupmode(ioportid_t, ioportmask_t, iomode_t)portmodeportidIOBusstruct IOBuspalReadBusioportmask_t palReadBus(IOBus *)busIOBus *palWriteBusvoid palWriteBus(IOBus *, ioportmask_t)bitspalSetBusModevoid palSetBusMode(IOBus *, iomode_t)ADC_UNINITADC_STOPADC_READYADC_ACTIVEADC_COMPLETEADC_ERRORadcstate_tenum adcstate_tadcsample_tadc_channels_num_tADC_ERR_DMAFAILUREADC_ERR_OVERFLOWadcerror_tenum adcerror_tADCDriverstruct ADCDriveradccallback_tvoid (*)(ADCDriver *, adcsample_t *, size_t)adcpADCDriver *adcsample_t *adcerrorcallback_tvoid (*)(ADCDriver *, adcerror_t)errcircularnum_channelsend_cberror_cbcr1cr2smpr1smpr2smpr3sqr1sqr2sqr3sqr4sqr5ADCConversionGroupstruct ADCConversionGroupdummyADCConfigstruct ADCConfigsamplesdepthgrppthreadmutexadcdmamodeADCD1adc_lld_initvoid adc_lld_init(void)adc_lld_startvoid adc_lld_start(ADCDriver *)adc_lld_stopvoid adc_lld_stop(ADCDriver *)adc_lld_start_conversionvoid adc_lld_start_conversion(ADCDriver *)adc_lld_stop_conversionvoid adc_lld_stop_conversion(ADCDriver *)adcSTM32EnableTSVREFEvoid adcSTM32EnableTSVREFE(void)adcSTM32DisableTSVREFEvoid adcSTM32DisableTSVREFE(void)adcInitvoid adcInit(void)adcObjectInitvoid adcObjectInit(ADCDriver *)adcStartvoid adcStart(ADCDriver *, const ADCConfig *)const ADCConfig *adcStopvoid adcStop(ADCDriver *)adcStartConversionvoid adcStartConversion(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t)const ADCConversionGroup *adcStartConversionIvoid adcStartConversionI(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t)adcStopConversionvoid adcStopConversion(ADCDriver *)adcStopConversionIvoid adcStopConversionI(ADCDriver *)adcConvertmsg_t adcConvert(ADCDriver *, const ADCConversionGroup *, adcsample_t *, size_t)adcAcquireBusvoid adcAcquireBus(ADCDriver *)adcReleaseBusvoid adcReleaseBus(ADCDriver *)PWM_UNINITPWM_STOPPWM_READYpwmstate_tenum pwmstate_tPWMDriverstruct PWMDriverpwmcallback_tvoid (*)(PWMDriver *)pwmpPWMDriver *pwmmode_tpwmchannel_tpwmcnt_tcallbackPWMChannelConfigstruct PWMChannelConfigfrequencyperiodchannelsPWMConfigstruct PWMConfigclocktimPWMD4pwm_lld_initvoid pwm_lld_init(void)pwm_lld_startvoid pwm_lld_start(PWMDriver *)pwm_lld_stopvoid pwm_lld_stop(PWMDriver *)pwm_lld_enable_channelvoid pwm_lld_enable_channel(PWMDriver *, pwmchannel_t, pwmcnt_t)widthpwm_lld_disable_channelvoid pwm_lld_disable_channel(PWMDriver *, pwmchannel_t)pwmInitvoid pwmInit(void)pwmObjectInitvoid pwmObjectInit(PWMDriver *)pwmStartvoid pwmStart(PWMDriver *, const PWMConfig *)const PWMConfig *pwmStopvoid pwmStop(PWMDriver *)pwmChangePeriodvoid pwmChangePeriod(PWMDriver *, pwmcnt_t)pwmEnableChannelvoid pwmEnableChannel(PWMDriver *, pwmchannel_t, pwmcnt_t)pwmDisableChannelvoid pwmDisableChannel(PWMDriver *, pwmchannel_t)SD_UNINITSD_STOPSD_READYsdstate_tenum sdstate_tSerialDriverstruct SerialDriversc_speedsc_cr1sc_cr2sc_cr3SerialConfigstruct SerialConfigSD1SD2sd_lld_initvoid sd_lld_init(void)sd_lld_startvoid sd_lld_start(SerialDriver *, const SerialConfig *)sdpSerialDriver *const SerialConfig *sd_lld_stopvoid sd_lld_stop(SerialDriver *)SerialDriverVMTstruct SerialDriverVMTiqueueoqueueibobusartsdInitvoid sdInit(void)sdObjectInitvoid sdObjectInit(SerialDriver *, qnotify_t, qnotify_t)inotifyonotifysdStartvoid sdStart(SerialDriver *, const SerialConfig *)sdStopvoid sdStop(SerialDriver *)sdIncomingDataIvoid sdIncomingDataI(SerialDriver *, uint8_t)sdRequestDataImsg_t sdRequestDataI(SerialDriver *)SPI_UNINITSPI_STOPSPI_READYSPI_ACTIVESPI_COMPLETEspistate_tenum spistate_tSPIDriverstruct SPIDriverspicallback_tvoid (*)(SPIDriver *)spipSPIDriver *ssportsspadSPIConfigstruct SPIConfigspidmarxdmatxrxdmamodetxdmamodeSPID2spi_lld_initvoid spi_lld_init(void)spi_lld_startvoid spi_lld_start(SPIDriver *)spi_lld_stopvoid spi_lld_stop(SPIDriver *)spi_lld_selectvoid spi_lld_select(SPIDriver *)spi_lld_unselectvoid spi_lld_unselect(SPIDriver *)spi_lld_ignorevoid spi_lld_ignore(SPIDriver *, size_t)spi_lld_exchangevoid spi_lld_exchange(SPIDriver *, size_t, const void *, void *)txbufrxbufspi_lld_sendvoid spi_lld_send(SPIDriver *, size_t, const void *)spi_lld_receivevoid spi_lld_receive(SPIDriver *, size_t, void *)spi_lld_polled_exchangeuint16_t spi_lld_polled_exchange(SPIDriver *, uint16_t)framespiInitvoid spiInit(void)spiObjectInitvoid spiObjectInit(SPIDriver *)spiStartvoid spiStart(SPIDriver *, const SPIConfig *)const SPIConfig *spiStopvoid spiStop(SPIDriver *)spiSelectvoid spiSelect(SPIDriver *)spiUnselectvoid spiUnselect(SPIDriver *)spiStartIgnorevoid spiStartIgnore(SPIDriver *, size_t)spiStartExchangevoid spiStartExchange(SPIDriver *, size_t, const void *, void *)spiStartSendvoid spiStartSend(SPIDriver *, size_t, const void *)spiStartReceivevoid spiStartReceive(SPIDriver *, size_t, void *)spiIgnorevoid spiIgnore(SPIDriver *, size_t)spiExchangevoid spiExchange(SPIDriver *, size_t, const void *, void *)spiSendvoid spiSend(SPIDriver *, size_t, const void *)spiReceivevoid spiReceive(SPIDriver *, size_t, void *)spiAcquireBusvoid spiAcquireBus(SPIDriver *)spiReleaseBusvoid spiReleaseBus(SPIDriver *)halInitvoid halInit(void)halIsCounterWithinbool_t halIsCounterWithin(halrtcnt_t, halrtcnt_t)halPolledDelayvoid halPolledDelay(halrtcnt_t) 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OE_PIN14c:macro@GPIOE_PIN15c:macro@GPIOH_OSC_INc:macro@GPIOH_OSC_OUTc:macro@GPIOH_PIN2c:macro@GPIOH_PIN3c:macro@GPIOH_PIN4c:macro@GPIOH_PIN5c:macro@GPIOH_PIN6c:macro@GPIOH_PIN7c:macro@GPIOH_PIN8c:macro@GPIOH_PIN9c:macro@GPIOH_PIN10c:macro@GPIOH_PIN11c:macro@GPIOH_PIN12c:macro@GPIOH_PIN13c:macro@GPIOH_PIN14c:macro@GPIOH_PIN15c:macro@PIN_MODE_INPUTc:macro@PIN_MODE_OUTPUTc:macro@PIN_MODE_ALTERNATEc:macro@PIN_MODE_ANALOGc:macro@PIN_ODR_LOWc:macro@PIN_ODR_HIGHc:macro@PIN_OTYPE_PUSHPULLc:macro@PIN_OTYPE_OPENDRAINc:macro@PIN_OSPEED_400Kc:macro@PIN_OSPEED_2Mc:macro@PIN_OSPEED_10Mc:macro@PIN_OSPEED_40Mc:macro@PIN_PUPDR_FLOATINGc:macro@PIN_PUPDR_PULLUPc:macro@PIN_PUPDR_PULLDOWNc:macro@PIN_AFIO_AFc:macro@VAL_GPIOA_MODERc:macro@VAL_GPIOA_OTYPERc:macro@VAL_GPIOA_OSPEEDRc:macro@VAL_GPIOA_PUPDRc:macro@VAL_GPIOA_ODRc:macro@VAL_GPIOA_AFRLc:macro@VAL_GPIOA_AFRHc:macro@VAL_GPIOB_MODERc:macro@VAL_GPIOB_OTYPERc:macro@VAL_GPIOB_OSPEEDRc:macro@VAL_GPIOB_PUPDRc:macro@VAL_GPIOB_ODRc:macro@VAL_GPIOB_AFRLc:macro@VAL_GPIOB_AFRHc:macro@VAL_GPIOC_MODERc:macro@VAL_GPIOC_OTYPERc:macro@VAL_GPIOC_OSPEEDRc:macro@VAL_GPIOC_PUPDRc:macro@VAL_GPIOC_ODRc:macro@VAL_GPIOC_AFRLc:macro@VAL_GPIOC_AFRHc:macro@VAL_GPIOD_MODERc:macro@VAL_GPIOD_OTYPERc:macro@VAL_GPIOD_OSPEEDRc:macro@VAL_GPIOD_PUPDRc:macro@VAL_GPIOD_ODRc:macro@VAL_GPIOD_AFRLc:macro@VAL_GPIOD_AFRHc:macro@VAL_GPIOE_MODERc:macro@VAL_GPIOE_OTYPERc:macro@VAL_GPIOE_OSPEEDRc:macro@VAL_GPIOE_PUPDRc:macro@VAL_GPIOE_ODRc:macro@VAL_GPIOE_AFRLc:macro@VAL_GPIOE_AFRHc:macro@VAL_GPIOH_MODERc:macro@VAL_GPIOH_OTYPERc:macro@VAL_GPIOH_OSPEEDRc:macro@VAL_GPIOH_PUPDRc:macro@VAL_GPIOH_ODRc:macro@VAL_GPIOH_AFRLc:macro@VAL_GPIOH_AFRHc:macro@_HALCONF_H_c:macro@STM32L1xx_MCUCONFc:macro@STM32_NO_INITc:macro@STM32_HSI_ENABLEDc:macro@STM32_LSI_ENABLEDc:macro@STM32_HSE_ENABLEDc:macro@STM32_LSE_ENABLEDc:macro@STM32_ADC_CLOCK_ENABLEDc:macro@STM32_USB_CLOCK_ENABLEDc:macro@STM32_MSIRANGEc:macro@STM32_SWc:macro@STM32_PLLSRCc:macro@STM32_PLLMUL_VALUEc:macro@STM32_PLLDIV_VALUEc:macro@STM32_HPREc:macro@STM32_PPRE1c:macro@STM32_PPRE2c:macro@STM32_MCOSELc:macro@STM32_MCOPREc:macro@STM32_RTCSELc:macro@STM32_RTCPREc:macro@STM32_VOSc:macro@STM32_PVD_ENABLEc:macro@STM32_PLSc:macro@STM32_ADC_USE_ADC1c:macro@STM32_ADC_ADC1_DMA_PRIORITYc:macro@STM32_ADC_IRQ_PRIORITYc:macro@STM32_ADC_ADC1_DMA_IRQ_PRIORITYc:macro@STM32_EXT_EXTI0_IRQ_PRIORITYc:macro@STM32_EXT_EXTI1_IRQ_PRIORITYc:macro@STM32_EXT_EXTI2_IRQ_PRIORITYc:macro@STM32_EXT_EXTI3_IRQ_PRIORITYc:macro@STM32_EXT_EXTI4_IRQ_PRIORITYc:macro@STM32_EXT_EXTI5_9_IRQ_PRIORITYc:macro@STM32_EXT_EXTI10_15_IRQ_PRIORITYc:macro@STM32_EXT_EXTI16_IRQ_PRIORITYc:macro@STM32_EXT_EXTI17_IRQ_PRIORITYc:macro@STM32_EXT_EXTI18_IRQ_PRIORITYc:macro@STM32_EXT_EXTI19_IRQ_PRIORITYc:macro@STM32_EXT_EXTI20_IRQ_PRIORITYc:macro@STM32_EXT_EXTI21_22_IRQ_PRIORITYc:macro@STM32_GPT_USE_TIM2c:macro@STM32_GPT_USE_TIM3c:macro@STM32_GPT_USE_TIM4c:macro@STM32_GPT_TIM2_IRQ_PRIORITYc:macro@STM32_GPT_TIM3_IRQ_PRIORITYc:macro@STM32_GPT_TIM4_IRQ_PRIORITYc:macro@STM32_I2C_USE_I2C1c:macro@STM32_I2C_USE_I2C2c:macro@STM32_I2C_I2C1_IRQ_PRIORITYc:macro@STM32_I2C_I2C2_IRQ_PRIORITYc:macro@STM32_I2C_I2C1_DMA_PRIORITYc:macro@STM32_I2C_I2C2_DMA_PRIORITYc:macro@STM32_I2C_I2C1_DMA_ERROR_HOOKc:macro@STM32_I2C_I2C2_DMA_ERROR_HOOKc:macro@STM32_ICU_USE_TIM2c:macro@STM32_ICU_USE_TIM3c:macro@STM32_ICU_USE_TIM4c:macro@STM32_ICU_TIM2_IRQ_PRIORITYc:macro@STM32_ICU_TIM3_IRQ_PRIORITYc:macro@STM32_ICU_TIM4_IRQ_PRIORITYc:macro@STM32_PWM_USE_TIM2c:macro@STM32_PWM_USE_TIM3c:macro@STM32_PWM_USE_TIM4c:macro@STM32_PWM_TIM2_IRQ_PRIORITYc:macro@STM32_PWM_TIM3_IRQ_PRIORITYc:macro@STM32_PWM_TIM4_IRQ_PRIORITYc:macro@STM32_SERIAL_USE_USART1c:macro@STM32_SERIAL_USE_USART2c:macro@STM32_SERIAL_USE_USART3c:macro@STM32_SERIAL_USART1_PRIORITYc:macro@STM32_SERIAL_USART2_PRIORITYc:macro@STM32_SERIAL_USART3_PRIORITYc:macro@STM32_SPI_USE_SPI1c:macro@STM32_SPI_USE_SPI2c:macro@STM32_SPI_SPI1_DMA_PRIORITYc:macro@STM32_SPI_SPI2_DMA_PRIORITYc:macro@STM32_SPI_SPI1_IRQ_PRIORITYc:macro@STM32_SPI_SPI2_IRQ_PRIORITYc:macro@STM32_SPI_DMA_ERROR_HOOKc:macro@STM32_UART_USE_USART1c:macro@STM32_UART_USE_USART2c:macro@STM32_UART_USE_USART3c:macro@STM32_UART_USART1_IRQ_PRIORITYc:macro@STM32_UART_USART2_IRQ_PRIORITYc:macro@STM32_UART_USART3_IRQ_PRIORITYc:macro@STM32_UART_USART1_DMA_PRIORITYc:macro@STM32_UART_USART2_DMA_PRIORITYc:macro@STM32_UART_USART3_DMA_PRIORITYc:macro@STM32_UART_DMA_ERROR_HOOKc:macro@STM32_USB_USE_USB1c:macro@STM32_USB_LOW_POWER_ON_SUSPENDc:macro@STM32_USB_USB1_HP_IRQ_PRIORITYc:macro@STM32_USB_USB1_LP_IRQ_PRIORITYc:macro@HAL_USE_TMc:macro@HAL_USE_PALc:macro@HAL_USE_ADCc:macro@HAL_USE_CANc:macro@HAL_USE_EXTc:macro@HAL_USE_GPTc:macro@HAL_USE_I2Cc:macro@HAL_USE_ICUc:macro@HAL_USE_MACc:macro@HAL_USE_MMC_SPIc:macro@HAL_USE_PWMc:macro@HAL_USE_RTCc:macro@HAL_USE_SDCc:macro@HAL_USE_SERIALc:macro@HAL_USE_SERIAL_USBc:macro@HAL_USE_SPIc:macro@HAL_USE_UARTc:macro@HAL_USE_USBc:macro@ADC_USE_WAITc:macro@ADC_USE_MUTUAL_EXCLUSIONc:macro@CAN_USE_SLEEP_MODEc:macro@I2C_USE_MUTUAL_EXCLUSIONc:macro@MAC_USE_ZERO_COPYc:macro@MAC_USE_EVENTSc:macro@MMC_NICE_WAITINGc:macro@SDC_INIT_RETRYc:macro@SDC_MMC_SUPPORTc:macro@SDC_NICE_WAITINGc:macro@SERIAL_DEFAULT_BITRATEc:macro@SERIAL_BUFFERS_SIZEc:macro@SPI_USE_WAITc:macro@SPI_USE_MUTUAL_EXCLUSIONc:macro@_HAL_LLD_H_c:macro@_STM32_H_c:macro@__STM32L1XX_Hc:macro@HSE_VALUEc:macro@HSE_STARTUP_TIMEOUTc:macro@HSI_STARTUP_TIMEOUTc:macro@HSI_VALUEc:macro@LSI_VALUEc:macro@LSE_VALUEc:macro@__STM32L1XX_STDPERIPH_VERSION_MAINc:macro@__STM32L1XX_STDPERIPH_VERSION_SUB1c:macro@__STM32L1XX_STDPERIPH_VERSION_SUB2c:macro@__STM32L1XX_STDPERIPH_VERSION_RCc:macro@__STM32L1XX_STDPERIPH_VERSIONc:macro@__CM3_REVc:macro@__MPU_PRESENTc:macro@__NVIC_PRIO_BITSc:macro@__Vendor_SysTickConfigc:macro@__CORE_CM3_H_GENERICc:macro@__CM3_CMSIS_VERSION_MAINc:macro@__CM3_CMSIS_VERSION_SUBc:macro@__CM3_CMSIS_VERSIONc:macro@__CORTEX_Mc:macro@__ASMc:macro@__INLINEc:macro@__STATIC_INLINEc:macro@__FPU_USEDc:macro@__CORE_CMINSTR_Hc:macro@__CMSIS_IAR_H__c:macro@__CORE__c:macro@__ARM6M__c:macro@__enable_irqc:macro@__disable_irqc:macro@__NOPc:macro@__VER__c:macro@__BKPTc:macro@__LDREXWc:macro@__STREXWc:macro@__enable_fault_irqc:macro@__disable_fault_irqc:macro@__CORE_CMFUNC_Hc:macro@__CORE_CM3_H_DEPENDANTc:macro@__Ic:macro@__Oc:macro@__IOc:macro@NVIC_STIR_INTID_Posc:macro@NVIC_STIR_INTID_Mskc:macro@SCB_CPUID_IMPLEMENTER_Posc:macro@SCB_CPUID_IMPLEMENTER_Mskc:macro@SCB_CPUID_VARIANT_Posc:macro@SCB_CPUID_VARIANT_Mskc:macro@SCB_CPUID_ARCHITECTURE_Posc:macro@SCB_CPUID_ARCHITECTURE_Mskc:macro@SCB_CPUID_PARTNO_Posc:macro@SCB_CPUID_PARTNO_Mskc:macro@SCB_CPUID_REVISION_Posc:macro@SCB_CPUID_REVISION_Mskc:macro@SCB_ICSR_NMIPENDSET_Posc:macro@SCB_ICSR_NMIPENDSET_Mskc:macro@SCB_ICSR_PENDSVSET_Posc:macro@SCB_ICSR_PENDSVSET_Mskc:macro@SCB_ICSR_PENDSVCLR_Posc:macro@SCB_ICSR_PENDSVCLR_Mskc:macro@SCB_ICSR_PENDSTSET_Posc:macro@SCB_ICSR_PENDSTSET_Mskc:macro@SCB_ICSR_PENDSTCLR_Posc:macro@SCB_ICSR_PENDSTCLR_Mskc:macro@SCB_ICSR_ISRPREEMPT_Posc:macro@SCB_ICSR_ISRPREEMPT_Mskc:macro@SCB_ICSR_ISRPENDING_Posc:macro@SCB_ICSR_ISRPENDING_Mskc:macro@SCB_ICSR_VECTPENDING_Posc:macro@SCB_ICSR_VECTPENDING_Mskc:macro@SCB_ICSR_RETTOBASE_Posc:macro@SCB_ICSR_RETTOBASE_Mskc:macro@SCB_ICSR_VECTACTIVE_Posc:macro@SCB_ICSR_VECTACTIVE_Mskc:macro@SCB_VTOR_TBLBASE_Posc:macro@SCB_VTOR_TBLBASE_Mskc:macro@SCB_VTOR_TBLOFF_Posc:macro@SCB_VTOR_TBLOFF_Mskc:macro@SCB_AIRCR_VECTKEY_Posc:macro@SCB_AIRCR_VECTKEY_Mskc:macro@SCB_AIRCR_VECTKEYSTAT_Posc:macro@SCB_AIRCR_VECTKEYSTAT_Mskc:macro@SCB_AIRCR_ENDIANESS_Posc:macro@SCB_AIRCR_ENDIANESS_Mskc:macro@SCB_AIRCR_PRIGROUP_Posc:macro@SCB_AIRCR_PRIGROUP_Mskc:macro@SCB_AIRCR_SYSRESETREQ_Posc:macro@SCB_AIRCR_SYSRESETREQ_Mskc:macro@SCB_AIRCR_VECTCLRACTIVE_Posc:macro@SCB_AIRCR_VECTCLRACTIVE_Mskc:macro@SCB_AIRCR_VECTRESET_Posc:macro@SCB_AIRCR_VECTRESET_Mskc:macro@SCB_SCR_SEVONPEND_Posc:macro@SCB_SCR_SEVONPEND_Mskc:macro@SCB_SCR_SLEEPDEEP_Posc:macro@SCB_SCR_SLEEPDEEP_Mskc:macro@SCB_SCR_SLEEPONEXIT_Posc:macro@SCB_SCR_SLEEPONEXIT_Mskc:macro@SCB_CCR_STKALIGN_Posc:macro@SCB_CCR_STKALIGN_Mskc:macro@SCB_CCR_BFHFNMIGN_Posc:macro@SCB_CCR_BFHFNMIGN_Mskc:macro@SCB_CCR_DIV_0_TRP_Posc:macro@SCB_CCR_DIV_0_TRP_Mskc:macro@SCB_CCR_UNALIGN_TRP_Posc:macro@SCB_CCR_UNALIGN_TRP_Mskc:macro@SCB_CCR_USERSETMPEND_Posc:macro@SCB_CCR_USERSETMPEND_Mskc:macro@SCB_CCR_NONBASETHRDENA_Posc:macro@SCB_CCR_NONBASETHRDENA_Mskc:macro@SCB_SHCSR_USGFAULTENA_Posc:macro@SCB_SHCSR_USGFAULTENA_Mskc:macro@SCB_SHCSR_BUSFAULTENA_Posc:macro@SCB_SHCSR_BUSFAULTENA_Mskc:macro@SCB_SHCSR_MEMFAULTENA_Posc:macro@SCB_SHCSR_MEMFAULTENA_Mskc:macro@SCB_SHCSR_SVCALLPENDED_Posc:macro@SCB_SHCSR_SVCALLPENDED_Mskc:macro@SCB_SHCSR_BUSFAULTPENDED_Posc:macro@SCB_SHCSR_BUSFAULTPENDED_Mskc:macro@SCB_SHCSR_MEMFAULTPENDED_Posc:macro@SCB_SHCSR_MEMFAULTPENDED_Mskc:macro@SCB_SHCSR_USGFAULTPENDED_Posc:macro@SCB_SHCSR_USGFAULTPENDED_Mskc:macro@SCB_SHCSR_SYSTICKACT_Posc:macro@SCB_SHCSR_SYSTICKACT_Mskc:macro@SCB_SHCSR_PENDSVACT_Posc:macro@SCB_SHCSR_PENDSVACT_Mskc:macro@SCB_SHCSR_MONITORACT_Posc:macro@SCB_SHCSR_MONITORACT_Mskc:macro@SCB_SHCSR_SVCALLACT_Posc:macro@SCB_SHCSR_SVCALLACT_Mskc:macro@SCB_SHCSR_USGFAULTACT_Posc:macro@SCB_SHCSR_USGFAULTACT_Mskc:macro@SCB_SHCSR_BUSFAULTACT_Posc:macro@SCB_SHCSR_BUSFAULTACT_Mskc:macro@SCB_SHCSR_MEMFAULTACT_Posc:macro@SCB_SHCSR_MEMFAULTACT_Mskc:macro@SCB_CFSR_USGFAULTSR_Posc:macro@SCB_CFSR_USGFAULTSR_Mskc:macro@SCB_CFSR_BUSFAULTSR_Posc:macro@SCB_CFSR_BUSFAULTSR_Mskc:macro@SCB_CFSR_MEMFAULTSR_Posc:macro@SCB_CFSR_MEMFAULTSR_Mskc:macro@SCB_HFSR_DEBUGEVT_Posc:macro@SCB_HFSR_DEBUGEVT_Mskc:macro@SCB_HFSR_FORCED_Posc:macro@SCB_HFSR_FORCED_Mskc:macro@SCB_HFSR_VECTTBL_Posc:macro@SCB_HFSR_VECTTBL_Mskc:macro@SCB_DFSR_EXTERNAL_Posc:macro@SCB_DFSR_EXTERNAL_Mskc:macro@SCB_DFSR_VCATCH_Posc:macro@SCB_DFSR_VCATCH_Mskc:macro@SCB_DFSR_DWTTRAP_Posc:macro@SCB_DFSR_DWTTRAP_Mskc:macro@SCB_DFSR_BKPT_Posc:macro@SCB_DFSR_BKPT_Mskc:macro@SCB_DFSR_HALTED_Posc:macro@SCB_DFSR_HALTED_Mskc:macro@SCnSCB_ICTR_INTLINESNUM_Posc:macro@SCnSCB_ICTR_INTLINESNUM_Mskc:macro@SCnSCB_ACTLR_DISFOLD_Posc:macro@SCnSCB_ACTLR_DISFOLD_Mskc:macro@SCnSCB_ACTLR_DISDEFWBUF_Posc:macro@SCnSCB_ACTLR_DISDEFWBUF_Mskc:macro@SCnSCB_ACTLR_DISMCYCINT_Posc:macro@SCnSCB_ACTLR_DISMCYCINT_Mskc:macro@SysTick_CTRL_COUNTFLAG_Posc:macro@SysTick_CTRL_COUNTFLAG_Mskc:macro@SysTick_CTRL_CLKSOURCE_Posc:macro@SysTick_CTRL_CLKSOURCE_Mskc:macro@SysTick_CTRL_TICKINT_Posc:macro@SysTick_CTRL_TICKINT_Mskc:macro@SysTick_CTRL_ENABLE_Posc:macro@SysTick_CTRL_ENABLE_Mskc:macro@SysTick_LOAD_RELOAD_Posc:macro@SysTick_LOAD_RELOAD_Mskc:macro@SysTick_VAL_CURRENT_Posc:macro@SysTick_VAL_CURRENT_Mskc:macro@SysTick_CALIB_NOREF_Posc:macro@SysTick_CALIB_NOREF_Mskc:macro@SysTick_CALIB_SKEW_Posc:macro@SysTick_CALIB_SKEW_Mskc:macro@SysTick_CALIB_TENMS_Posc:macro@SysTick_CALIB_TENMS_Mskc:macro@ITM_TPR_PRIVMASK_Posc:macro@ITM_TPR_PRIVMASK_Mskc:macro@ITM_TCR_BUSY_Posc:macro@ITM_TCR_BUSY_Mskc:macro@ITM_TCR_TraceBusID_Posc:macro@ITM_TCR_TraceBusID_Mskc:macro@ITM_TCR_GTSFREQ_Posc:macro@ITM_TCR_GTSFREQ_Mskc:macro@ITM_TCR_TSPrescale_Posc:macro@ITM_TCR_TSPrescale_Mskc:macro@ITM_TCR_SWOENA_Posc:macro@ITM_TCR_SWOENA_Mskc:macro@ITM_TCR_DWTENA_Posc:macro@ITM_TCR_DWTENA_Mskc:macro@ITM_TCR_SYNCENA_Posc:macro@ITM_TCR_SYNCENA_Mskc:macro@ITM_TCR_TSENA_Posc:macro@ITM_TCR_TSENA_Mskc:macro@ITM_TCR_ITMENA_Posc:macro@ITM_TCR_ITMENA_Mskc:macro@ITM_IWR_ATVALIDM_Posc:macro@ITM_IWR_ATVALIDM_Mskc:macro@ITM_IRR_ATREADYM_Posc:macro@ITM_IRR_ATREADYM_Mskc:macro@ITM_IMCR_INTEGRATION_Posc:macro@ITM_IMCR_INTEGRATION_Mskc:macro@ITM_LSR_ByteAcc_Posc:macro@ITM_LSR_ByteAcc_Mskc:macro@ITM_LSR_Access_Posc:macro@ITM_LSR_Access_Mskc:macro@ITM_LSR_Present_Posc:macro@ITM_LSR_Present_Mskc:macro@DWT_CTRL_NUMCOMP_Posc:macro@DWT_CTRL_NUMCOMP_Mskc:macro@DWT_CTRL_NOTRCPKT_Posc:macro@DWT_CTRL_NOTRCPKT_Mskc:macro@DWT_CTRL_NOEXTTRIG_Posc:macro@DWT_CTRL_NOEXTTRIG_Mskc:macro@DWT_CTRL_NOCYCCNT_Posc:macro@DWT_CTRL_NOCYCCNT_Mskc:macro@DWT_CTRL_NOPRFCNT_Posc:macro@DWT_CTRL_NOPRFCNT_Mskc:macro@DWT_CTRL_CYCEVTENA_Posc:macro@DWT_CTRL_CYCEVTENA_Mskc:macro@DWT_CTRL_FOLDEVTENA_Posc:macro@DWT_CTRL_FOLDEVTENA_Mskc:macro@DWT_CTRL_LSUEVTENA_Posc:macro@DWT_CTRL_LSUEVTENA_Mskc:macro@DWT_CTRL_SLEEPEVTENA_Posc:macro@DWT_CTRL_SLEEPEVTENA_Mskc:macro@DWT_CTRL_EXCEVTENA_Posc:macro@DWT_CTRL_EXCEVTENA_Mskc:macro@DWT_CTRL_CPIEVTENA_Posc:macro@DWT_CTRL_CPIEVTENA_Mskc:macro@DWT_CTRL_EXCTRCENA_Posc:macro@DWT_CTRL_EXCTRCENA_Mskc:macro@DWT_CTRL_PCSAMPLENA_Posc:macro@DWT_CTRL_PCSAMPLENA_Mskc:macro@DWT_CTRL_SYNCTAP_Posc:macro@DWT_CTRL_SYNCTAP_Mskc:macro@DWT_CTRL_CYCTAP_Posc:macro@DWT_CTRL_CYCTAP_Mskc:macro@DWT_CTRL_POSTINIT_Posc:macro@DWT_CTRL_POSTINIT_Mskc:macro@DWT_CTRL_POSTPRESET_Posc:macro@DWT_CTRL_POSTPRESET_Mskc:macro@DWT_CTRL_CYCCNTENA_Posc:macro@DWT_CTRL_CYCCNTENA_Mskc:macro@DWT_CPICNT_CPICNT_Posc:macro@DWT_CPICNT_CPICNT_Mskc:macro@DWT_EXCCNT_EXCCNT_Posc:macro@DWT_EXCCNT_EXCCNT_Mskc:macro@DWT_SLEEPCNT_SLEEPCNT_Posc:macro@DWT_SLEEPCNT_SLEEPCNT_Mskc:macro@DWT_LSUCNT_LSUCNT_Posc:macro@DWT_LSUCNT_LSUCNT_Mskc:macro@DWT_FOLDCNT_FOLDCNT_Posc:macro@DWT_FOLDCNT_FOLDCNT_Mskc:macro@DWT_MASK_MASK_Posc:macro@DWT_MASK_MASK_Mskc:macro@DWT_FUNCTION_MATCHED_Posc:macro@DWT_FUNCTION_MATCHED_Mskc:macro@DWT_FUNCTION_DATAVADDR1_Posc:macro@DWT_FUNCTION_DATAVADDR1_Mskc:macro@DWT_FUNCTION_DATAVADDR0_Posc:macro@DWT_FUNCTION_DATAVADDR0_Mskc:macro@DWT_FUNCTION_DATAVSIZE_Posc:macro@DWT_FUNCTION_DATAVSIZE_Mskc:macro@DWT_FUNCTION_LNK1ENA_Posc:macro@DWT_FUNCTION_LNK1ENA_Mskc:macro@DWT_FUNCTION_DATAVMATCH_Posc:macro@DWT_FUNCTION_DATAVMATCH_Mskc:macro@DWT_FUNCTION_CYCMATCH_Posc:macro@DWT_FUNCTION_CYCMATCH_Mskc:macro@DWT_FUNCTION_EMITRANGE_Posc:macro@DWT_FUNCTION_EMITRANGE_Mskc:macro@DWT_FUNCTION_FUNCTION_Posc:macro@DWT_FUNCTION_FUNCTION_Mskc:macro@TPI_ACPR_PRESCALER_Posc:macro@TPI_ACPR_PRESCALER_Mskc:macro@TPI_SPPR_TXMODE_Posc:macro@TPI_SPPR_TXMODE_Mskc:macro@TPI_FFSR_FtNonStop_Posc:macro@TPI_FFSR_FtNonStop_Mskc:macro@TPI_FFSR_TCPresent_Posc:macro@TPI_FFSR_TCPresent_Mskc:macro@TPI_FFSR_FtStopped_Posc:macro@TPI_FFSR_FtStopped_Mskc:macro@TPI_FFSR_FlInProg_Posc:macro@TPI_FFSR_FlInProg_Mskc:macro@TPI_FFCR_TrigIn_Posc:macro@TPI_FFCR_TrigIn_Mskc:macro@TPI_FFCR_EnFCont_Posc:macro@TPI_FFCR_EnFCont_Mskc:macro@TPI_TRIGGER_TRIGGER_Posc:macro@TPI_TRIGGER_TRIGGER_Mskc:macro@TPI_FIFO0_ITM_ATVALID_Posc:macro@TPI_FIFO0_ITM_ATVALID_Mskc:macro@TPI_FIFO0_ITM_bytecount_Posc:macro@TPI_FIFO0_ITM_bytecount_Mskc:macro@TPI_FIFO0_ETM_ATVALID_Posc:macro@TPI_FIFO0_ETM_ATVALID_Mskc:macro@TPI_FIFO0_ETM_bytecount_Posc:macro@TPI_FIFO0_ETM_bytecount_Mskc:macro@TPI_FIFO0_ETM2_Posc:macro@TPI_FIFO0_ETM2_Mskc:macro@TPI_FIFO0_ETM1_Posc:macro@TPI_FIFO0_ETM1_Mskc:macro@TPI_FIFO0_ETM0_Posc:macro@TPI_FIFO0_ETM0_Mskc:macro@TPI_ITATBCTR2_ATREADY_Posc:macro@TPI_ITATBCTR2_ATREADY_Mskc:macro@TPI_FIFO1_ITM_ATVALID_Posc:macro@TPI_FIFO1_ITM_ATVALID_Mskc:macro@TPI_FIFO1_ITM_bytecount_Posc:macro@TPI_FIFO1_ITM_bytecount_Mskc:macro@TPI_FIFO1_ETM_ATVALID_Posc:macro@TPI_FIFO1_ETM_ATVALID_Mskc:macro@TPI_FIFO1_ETM_bytecount_Posc:macro@TPI_FIFO1_ETM_bytecount_Mskc:macro@TPI_FIFO1_ITM2_Posc:macro@TPI_FIFO1_ITM2_Mskc:macro@TPI_FIFO1_ITM1_Posc:macro@TPI_FIFO1_ITM1_Mskc:macro@TPI_FIFO1_ITM0_Posc:macro@TPI_FIFO1_ITM0_Mskc:macro@TPI_ITATBCTR0_ATREADY_Posc:macro@TPI_ITATBCTR0_ATREADY_Mskc:macro@TPI_ITCTRL_Mode_Posc:macro@TPI_ITCTRL_Mode_Mskc:macro@TPI_DEVID_NRZVALID_Posc:macro@TPI_DEVID_NRZVALID_Mskc:macro@TPI_DEVID_MANCVALID_Posc:macro@TPI_DEVID_MANCVALID_Mskc:macro@TPI_DEVID_PTINVALID_Posc:macro@TPI_DEVID_PTINVALID_Mskc:macro@TPI_DEVID_MinBufSz_Posc:macro@TPI_DEVID_MinBufSz_Mskc:macro@TPI_DEVID_AsynClkIn_Posc:macro@TPI_DEVID_AsynClkIn_Mskc:macro@TPI_DEVID_NrTraceInput_Posc:macro@TPI_DEVID_NrTraceInput_Mskc:macro@TPI_DEVTYPE_SubType_Posc:macro@TPI_DEVTYPE_SubType_Mskc:macro@TPI_DEVTYPE_MajorType_Posc:macro@TPI_DEVTYPE_MajorType_Mskc:macro@MPU_TYPE_IREGION_Posc:macro@MPU_TYPE_IREGION_Mskc:macro@MPU_TYPE_DREGION_Posc:macro@MPU_TYPE_DREGION_Mskc:macro@MPU_TYPE_SEPARATE_Posc:macro@MPU_TYPE_SEPARATE_Mskc:macro@MPU_CTRL_PRIVDEFENA_Posc:macro@MPU_CTRL_PRIVDEFENA_Mskc:macro@MPU_CTRL_HFNMIENA_Posc:macro@MPU_CTRL_HFNMIENA_Mskc:macro@MPU_CTRL_ENABLE_Posc:macro@MPU_CTRL_ENABLE_Mskc:macro@MPU_RNR_REGION_Posc:macro@MPU_RNR_REGION_Mskc:macro@MPU_RBAR_ADDR_Posc:macro@MPU_RBAR_ADDR_Mskc:macro@MPU_RBAR_VALID_Posc:macro@MPU_RBAR_VALID_Mskc:macro@MPU_RBAR_REGION_Posc:macro@MPU_RBAR_REGION_Mskc:macro@MPU_RASR_ATTRS_Posc:macro@MPU_RASR_ATTRS_Mskc:macro@MPU_RASR_XN_Posc:macro@MPU_RASR_XN_Mskc:macro@MPU_RASR_AP_Posc:macro@MPU_RASR_AP_Mskc:macro@MPU_RASR_TEX_Posc:macro@MPU_RASR_TEX_Mskc:macro@MPU_RASR_S_Posc:macro@MPU_RASR_S_Mskc:macro@MPU_RASR_C_Posc:macro@MPU_RASR_C_Mskc:macro@MPU_RASR_B_Posc:macro@MPU_RASR_B_Mskc:macro@MPU_RASR_SRD_Posc:macro@MPU_RASR_SRD_Mskc:macro@MPU_RASR_SIZE_Posc:macro@MPU_RASR_SIZE_Mskc:macro@MPU_RASR_ENABLE_Posc:macro@MPU_RASR_ENABLE_Mskc:macro@CoreDebug_DHCSR_DBGKEY_Posc:macro@CoreDebug_DHCSR_DBGKEY_Mskc:macro@CoreDebug_DHCSR_S_RESET_ST_Posc:macro@CoreDebug_DHCSR_S_RESET_ST_Mskc:macro@CoreDebug_DHCSR_S_RETIRE_ST_Posc:macro@CoreDebug_DHCSR_S_RETIRE_ST_Mskc:macro@CoreDebug_DHCSR_S_LOCKUP_Posc:macro@CoreDebug_DHCSR_S_LOCKUP_Mskc:macro@CoreDebug_DHCSR_S_SLEEP_Posc:macro@CoreDebug_DHCSR_S_SLEEP_Mskc:macro@CoreDebug_DHCSR_S_HALT_Posc:macro@CoreDebug_DHCSR_S_HALT_Mskc:macro@CoreDebug_DHCSR_S_REGRDY_Posc:macro@CoreDebug_DHCSR_S_REGRDY_Mskc:macro@CoreDebug_DHCSR_C_SNAPSTALL_Posc:macro@CoreDebug_DHCSR_C_SNAPSTALL_Mskc:macro@CoreDebug_DHCSR_C_MASKINTS_Posc:macro@CoreDebug_DHCSR_C_MASKINTS_Mskc:macro@CoreDebug_DHCSR_C_STEP_Posc:macro@CoreDebug_DHCSR_C_STEP_Mskc:macro@CoreDebug_DHCSR_C_HALT_Posc:macro@CoreDebug_DHCSR_C_HALT_Mskc:macro@CoreDebug_DHCSR_C_DEBUGEN_Posc:macro@CoreDebug_DHCSR_C_DEBUGEN_Mskc:macro@CoreDebug_DCRSR_REGWnR_Posc:macro@CoreDebug_DCRSR_REGWnR_Mskc:macro@CoreDebug_DCRSR_REGSEL_Posc:macro@CoreDebug_DCRSR_REGSEL_Mskc:macro@CoreDebug_DEMCR_TRCENA_Posc:macro@CoreDebug_DEMCR_TRCENA_Mskc:macro@CoreDebug_DEMCR_MON_REQ_Posc:macro@CoreDebug_DEMCR_MON_REQ_Mskc:macro@CoreDebug_DEMCR_MON_STEP_Posc:macro@CoreDebug_DEMCR_MON_STEP_Mskc:macro@CoreDebug_DEMCR_MON_PEND_Posc:macro@CoreDebug_DEMCR_MON_PEND_Mskc:macro@CoreDebug_DEMCR_MON_EN_Posc:macro@CoreDebug_DEMCR_MON_EN_Mskc:macro@CoreDebug_DEMCR_VC_HARDERR_Posc:macro@CoreDebug_DEMCR_VC_HARDERR_Mskc:macro@CoreDebug_DEMCR_VC_INTERR_Posc:macro@CoreDebug_DEMCR_VC_INTERR_Mskc:macro@CoreDebug_DEMCR_VC_BUSERR_Posc:macro@CoreDebug_DEMCR_VC_BUSERR_Mskc:macro@CoreDebug_DEMCR_VC_STATERR_Posc:macro@CoreDebug_DEMCR_VC_STATERR_Mskc:macro@CoreDebug_DEMCR_VC_CHKERR_Posc:macro@CoreDebug_DEMCR_VC_CHKERR_Mskc:macro@CoreDebug_DEMCR_VC_NOCPERR_Posc:macro@CoreDebug_DEMCR_VC_NOCPERR_Mskc:macro@CoreDebug_DEMCR_VC_MMERR_Posc:macro@CoreDebug_DEMCR_VC_MMERR_Mskc:macro@CoreDebug_DEMCR_VC_CORERESET_Posc:macro@CoreDebug_DEMCR_VC_CORERESET_Mskc:macro@SCS_BASEc:macro@ITM_BASEc:macro@DWT_BASEc:macro@TPI_BASEc:macro@CoreDebug_BASEc:macro@SysTick_BASEc:macro@NVIC_BASEc:macro@SCB_BASEc:macro@SCnSCBc:macro@SCBc:macro@SysTickc:macro@NVICc:macro@ITMc:macro@DWTc:macro@TPIc:macro@CoreDebugc:macro@MPU_BASEc:macro@MPUc:macro@ITM_RXBUFFER_EMPTYc:macro@IS_FUNCTIONAL_STATEc:macro@__RAM_FUNCc:macro@FLASH_BASEc:macro@SRAM_BASEc:macro@PERIPH_BASEc:macro@SRAM_BB_BASEc:macro@PERIPH_BB_BASEc:macro@FSMC_R_BASEc:macro@APB1PERIPH_BASEc:macro@APB2PERIPH_BASEc:macro@AHBPERIPH_BASEc:macro@TIM2_BASEc:macro@TIM3_BASEc:macro@TIM4_BASEc:macro@TIM5_BASEc:macro@TIM6_BASEc:macro@TIM7_BASEc:macro@LCD_BASEc:macro@RTC_BASEc:macro@WWDG_BASEc:macro@IWDG_BASEc:macro@SPI2_BASEc:macro@SPI3_BASEc:macro@USART2_BASEc:macro@USART3_BASEc:macro@UART4_BASEc:macro@UART5_BASEc:macro@I2C1_BASEc:macro@I2C2_BASEc:macro@PWR_BASEc:macro@DAC_BASEc:macro@COMP_BASEc:macro@RI_BASEc:macro@OPAMP_BASEc:macro@SYSCFG_BASEc:macro@EXTI_BASEc:macro@TIM9_BASEc:macro@TIM10_BASEc:macro@TIM11_BASEc:macro@ADC1_BASEc:macro@ADC_BASEc:macro@SDIO_BASEc:macro@SPI1_BASEc:macro@USART1_BASEc:macro@GPIOA_BASEc:macro@GPIOB_BASEc:macro@GPIOC_BASEc:macro@GPIOD_BASEc:macro@GPIOE_BASEc:macro@GPIOH_BASEc:macro@GPIOF_BASEc:macro@GPIOG_BASEc:macro@CRC_BASEc:macro@RCC_BASEc:macro@FLASH_R_BASEc:macro@OB_BASEc:macro@DMA1_BASEc:macro@DMA1_Channel1_BASEc:macro@DMA1_Channel2_BASEc:macro@DMA1_Channel3_BASEc:macro@DMA1_Channel4_BASEc:macro@DMA1_Channel5_BASEc:macro@DMA1_Channel6_BASEc:macro@DMA1_Channel7_BASEc:macro@DMA2_BASEc:macro@DMA2_Channel1_BASEc:macro@DMA2_Channel2_BASEc:macro@DMA2_Channel3_BASEc:macro@DMA2_Channel4_BASEc:macro@DMA2_Channel5_BASEc:macro@AES_BASEc:macro@FSMC_Bank1_R_BASEc:macro@FSMC_Bank1E_R_BASEc:macro@DBGMCU_BASEc:macro@TIM2c:macro@TIM3c:macro@TIM4c:macro@TIM5c:macro@TIM6c:macro@TIM7c:macro@LCDc:macro@RTCc:macro@WWDGc:macro@IWDGc:macro@SPI2c:macro@SPI3c:macro@USART2c:macro@USART3c:macro@UART4c:macro@UART5c:macro@I2C1c:macro@I2C2c:macro@PWRc:macro@DACc:macro@COMPc:macro@RIc:macro@OPAMPc:macro@SYSCFGc:macro@EXTIc:macro@ADC1c:macro@ADCc:macro@SDIOc:macro@TIM9c:macro@TIM10c:macro@TIM11c:macro@SPI1c:macro@USART1c:macro@DMA1c:macro@DMA1_Channel1c:macro@DMA1_Channel2c:macro@DMA1_Channel3c:macro@DMA1_Channel4c:macro@DMA1_Channel5c:macro@DMA1_Channel6c:macro@DMA1_Channel7c:macro@DMA2c:macro@DMA2_Channel1c:macro@DMA2_Channel2c:macro@DMA2_Channel3c:macro@DMA2_Channel4c:macro@DMA2_Channel5c:macro@RCCc:macro@CRCc:macro@GPIOAc:macro@GPIOBc:macro@GPIOCc:macro@GPIODc:macro@GPIOEc:macro@GPIOHc:macro@GPIOFc:macro@GPIOGc:macro@FLASHc:macro@OBc:macro@AESc:macro@FSMC_Bank1c:macro@FSMC_Bank1Ec:macro@DBGMCUc:macro@ADC_SR_AWDc:macro@ADC_SR_EOCc:macro@ADC_SR_JEOCc:macro@ADC_SR_JSTRTc:macro@ADC_SR_STRTc:macro@ADC_SR_OVRc:macro@ADC_SR_ADONSc:macro@ADC_SR_RCNRc:macro@ADC_SR_JCNRc:macro@ADC_CR1_AWDCHc:macro@ADC_CR1_AWDCH_0c:macro@ADC_CR1_AWDCH_1c:macro@ADC_CR1_AWDCH_2c:macro@ADC_CR1_AWDCH_3c:macro@ADC_CR1_AWDCH_4c:macro@ADC_CR1_EOCIEc:macro@ADC_CR1_AWDIEc:macro@ADC_CR1_JEOCIEc:macro@ADC_CR1_SCANc:macro@ADC_CR1_AWDSGLc:macro@ADC_CR1_JAUTOc:macro@ADC_CR1_DISCENc:macro@ADC_CR1_JDISCENc:macro@ADC_CR1_DISCNUMc:macro@ADC_CR1_DISCNUM_0c:macro@ADC_CR1_DISCNUM_1c:macro@ADC_CR1_DISCNUM_2c:macro@ADC_CR1_PDDc:macro@ADC_CR1_PDIc:macro@ADC_CR1_JAWDENc:macro@ADC_CR1_AWDENc:macro@ADC_CR1_RESc:macro@ADC_CR1_RES_0c:macro@ADC_CR1_RES_1c:macro@ADC_CR1_OVRIEc:macro@ADC_CR2_ADONc:macro@ADC_CR2_CONTc:macro@ADC_CR2_CFGc:macro@ADC_CR2_DELSc:macro@ADC_CR2_DELS_0c:macro@ADC_CR2_DELS_1c:macro@ADC_CR2_DELS_2c:macro@ADC_CR2_DMAc:macro@ADC_CR2_DDSc:macro@ADC_CR2_EOCSc:macro@ADC_CR2_ALIGNc:macro@ADC_CR2_JEXTSELc:macro@ADC_CR2_JEXTSEL_0c:macro@ADC_CR2_JEXTSEL_1c:macro@ADC_CR2_JEXTSEL_2c:macro@ADC_CR2_JEXTSEL_3c:macro@ADC_CR2_JEXTENc:macro@ADC_CR2_JEXTEN_0c:macro@ADC_CR2_JEXTEN_1c:macro@ADC_CR2_JSWSTARTc:macro@ADC_CR2_EXTSELc:macro@ADC_CR2_EXTSEL_0c:macro@ADC_CR2_EXTSEL_1c:macro@ADC_CR2_EXTSEL_2c:macro@ADC_CR2_EXTSEL_3c:macro@ADC_CR2_EXTENc:macro@ADC_CR2_EXTEN_0c:macro@ADC_CR2_EXTEN_1c:macro@ADC_CR2_SWSTARTc:macro@ADC_SMPR1_SMP20c:macro@ADC_SMPR1_SMP20_0c:macro@ADC_SMPR1_SMP20_1c:macro@ADC_SMPR1_SMP20_2c:macro@ADC_SMPR1_SMP21c:macro@ADC_SMPR1_SMP21_0c:macro@ADC_SMPR1_SMP21_1c:macro@ADC_SMPR1_SMP21_2c:macro@ADC_SMPR1_SMP22c:macro@ADC_SMPR1_SMP22_0c:macro@ADC_SMPR1_SMP22_1c:macro@ADC_SMPR1_SMP22_2c:macro@ADC_SMPR1_SMP23c:macro@ADC_SMPR1_SMP23_0c:macro@ADC_SMPR1_SMP23_1c:macro@ADC_SMPR1_SMP23_2c:macro@ADC_SMPR1_SMP24c:macro@ADC_SMPR1_SMP24_0c:macro@ADC_SMPR1_SMP24_1c:macro@ADC_SMPR1_SMP24_2c:macro@ADC_SMPR1_SMP25c:macro@ADC_SMPR1_SMP25_0c:macro@ADC_SMPR1_SMP25_1c:macro@ADC_SMPR1_SMP25_2c:macro@ADC_SMPR1_SMP26c:macro@ADC_SMPR1_SMP26_0c:macro@ADC_SMPR1_SMP26_1c:macro@ADC_SMPR1_SMP26_2c:macro@ADC_SMPR1_SMP27c:macro@ADC_SMPR1_SMP27_0c:macro@ADC_SMPR1_SMP27_1c:macro@ADC_SMPR1_SMP27_2c:macro@ADC_SMPR1_SMP28c:macro@ADC_SMPR1_SMP28_0c:macro@ADC_SMPR1_SMP28_1c:macro@ADC_SMPR1_SMP28_2c:macro@ADC_SMPR1_SMP29c:macro@ADC_SMPR1_SMP29_0c:macro@ADC_SMPR1_SMP29_1c:macro@ADC_SMPR1_SMP29_2c:macro@ADC_SMPR2_SMP10c:macro@ADC_SMPR2_SMP10_0c:macro@ADC_SMPR2_SMP10_1c:macro@ADC_SMPR2_SMP10_2c:macro@ADC_SMPR2_SMP11c:macro@ADC_SMPR2_SMP11_0c:macro@ADC_SMPR2_SMP11_1c:macro@ADC_SMPR2_SMP11_2c:macro@ADC_SMPR2_SMP12c:macro@ADC_SMPR2_SMP12_0c:macro@ADC_SMPR2_SMP12_1c:macro@ADC_SMPR2_SMP12_2c:macro@ADC_SMPR2_SMP13c:macro@ADC_SMPR2_SMP13_0c:macro@ADC_SMPR2_SMP13_1c:macro@ADC_SMPR2_SMP13_2c:macro@ADC_SMPR2_SMP14c:macro@ADC_SMPR2_SMP14_0c:macro@ADC_SMPR2_SMP14_1c:macro@ADC_SMPR2_SMP14_2c:macro@ADC_SMPR2_SMP15c:macro@ADC_SMPR2_SMP15_0c:macro@ADC_SMPR2_SMP15_1c:macro@ADC_SMPR2_SMP15_2c:macro@ADC_SMPR2_SMP16c:macro@ADC_SMPR2_SMP16_0c:macro@ADC_SMPR2_SMP16_1c:macro@ADC_SMPR2_SMP16_2c:macro@ADC_SMPR2_SMP17c:macro@ADC_SMPR2_SMP17_0c:macro@ADC_SMPR2_SMP17_1c:macro@ADC_SMPR2_SMP17_2c:macro@ADC_SMPR2_SMP18c:macro@ADC_SMPR2_SMP18_0c:macro@ADC_SMPR2_SMP18_1c:macro@ADC_SMPR2_SMP18_2c:macro@ADC_SMPR2_SMP19c:macro@ADC_SMPR2_SMP19_0c:macro@ADC_SMPR2_SMP19_1c:macro@ADC_SMPR2_SMP19_2c:macro@ADC_SMPR3_SMP0c:macro@ADC_SMPR3_SMP0_0c:macro@ADC_SMPR3_SMP0_1c:macro@ADC_SMPR3_SMP0_2c:macro@ADC_SMPR3_SMP1c:macro@ADC_SMPR3_SMP1_0c:macro@ADC_SMPR3_SMP1_1c:macro@ADC_SMPR3_SMP1_2c:macro@ADC_SMPR3_SMP2c:macro@ADC_SMPR3_SMP2_0c:macro@ADC_SMPR3_SMP2_1c:macro@ADC_SMPR3_SMP2_2c:macro@ADC_SMPR3_SMP3c:macro@ADC_SMPR3_SMP3_0c:macro@ADC_SMPR3_SMP3_1c:macro@ADC_SMPR3_SMP3_2c:macro@ADC_SMPR3_SMP4c:macro@ADC_SMPR3_SMP4_0c:macro@ADC_SMPR3_SMP4_1c:macro@ADC_SMPR3_SMP4_2c:macro@ADC_SMPR3_SMP5c:macro@ADC_SMPR3_SMP5_0c:macro@ADC_SMPR3_SMP5_1c:macro@ADC_SMPR3_SMP5_2c:macro@ADC_SMPR3_SMP6c:macro@ADC_SMPR3_SMP6_0c:macro@ADC_SMPR3_SMP6_1c:macro@ADC_SMPR3_SMP6_2c:macro@ADC_SMPR3_SMP7c:macro@ADC_SMPR3_SMP7_0c:macro@ADC_SMPR3_SMP7_1c:macro@ADC_SMPR3_SMP7_2c:macro@ADC_SMPR3_SMP8c:macro@ADC_SMPR3_SMP8_0c:macro@ADC_SMPR3_SMP8_1c:macro@ADC_SMPR3_SMP8_2c:macro@ADC_SMPR3_SMP9c:macro@ADC_SMPR3_SMP9_0c:macro@ADC_SMPR3_SMP9_1c:macro@ADC_SMPR3_SMP9_2c:macro@ADC_JOFR1_JOFFSET1c:macro@ADC_JOFR2_JOFFSET2c:macro@ADC_JOFR3_JOFFSET3c:macro@ADC_JOFR4_JOFFSET4c:macro@ADC_HTR_HTc:macro@ADC_LTR_LTc:macro@ADC_SQR1_Lc:macro@ADC_SQR1_L_0c:macro@ADC_SQR1_L_1c:macro@ADC_SQR1_L_2c:macro@ADC_SQR1_L_3c:macro@ADC_SQR1_SQ28c:macro@ADC_SQR1_SQ28_0c:macro@ADC_SQR1_SQ28_1c:macro@ADC_SQR1_SQ28_2c:macro@ADC_SQR1_SQ28_3c:macro@ADC_SQR1_SQ28_4c:macro@ADC_SQR1_SQ27c:macro@ADC_SQR1_SQ27_0c:macro@ADC_SQR1_SQ27_1c:macro@ADC_SQR1_SQ27_2c:macro@ADC_SQR1_SQ27_3c:macro@ADC_SQR1_SQ27_4c:macro@ADC_SQR1_SQ26c:macro@ADC_SQR1_SQ26_0c:macro@ADC_SQR1_SQ26_1c:macro@ADC_SQR1_SQ26_2c:macro@ADC_SQR1_SQ26_3c:macro@ADC_SQR1_SQ26_4c:macro@ADC_SQR1_SQ25c:macro@ADC_SQR1_SQ25_0c:macro@ADC_SQR1_SQ25_1c:macro@ADC_SQR1_SQ25_2c:macro@ADC_SQR1_SQ25_3c:macro@ADC_SQR1_SQ25_4c:macro@ADC_SQR2_SQ19c:macro@ADC_SQR2_SQ19_0c:macro@ADC_SQR2_SQ19_1c:macro@ADC_SQR2_SQ19_2c:macro@ADC_SQR2_SQ19_3c:macro@ADC_SQR2_SQ19_4c:macro@ADC_SQR2_SQ20c:macro@ADC_SQR2_SQ20_0c:macro@ADC_SQR2_SQ20_1c:macro@ADC_SQR2_SQ20_2c:macro@ADC_SQR2_SQ20_3c:macro@ADC_SQR2_SQ20_4c:macro@ADC_SQR2_SQ21c:macro@ADC_SQR2_SQ21_0c:macro@ADC_SQR2_SQ21_1c:macro@ADC_SQR2_SQ21_2c:macro@ADC_SQR2_SQ21_3c:macro@ADC_SQR2_SQ21_4c:macro@ADC_SQR2_SQ22c:macro@ADC_SQR2_SQ22_0c:macro@ADC_SQR2_SQ22_1c:macro@ADC_SQR2_SQ22_2c:macro@ADC_SQR2_SQ22_3c:macro@ADC_SQR2_SQ22_4c:macro@ADC_SQR2_SQ23c:macro@ADC_SQR2_SQ23_0c:macro@ADC_SQR2_SQ23_1c:macro@ADC_SQR2_SQ23_2c:macro@ADC_SQR2_SQ23_3c:macro@ADC_SQR2_SQ23_4c:macro@ADC_SQR2_SQ24c:macro@ADC_SQR2_SQ24_0c:macro@ADC_SQR2_SQ24_1c:macro@ADC_SQR2_SQ24_2c:macro@ADC_SQR2_SQ24_3c:macro@ADC_SQR2_SQ24_4c:macro@ADC_SQR3_SQ13c:macro@ADC_SQR3_SQ13_0c:macro@ADC_SQR3_SQ13_1c:macro@ADC_SQR3_SQ13_2c:macro@ADC_SQR3_SQ13_3c:macro@ADC_SQR3_SQ13_4c:macro@ADC_SQR3_SQ14c:macro@ADC_SQR3_SQ14_0c:macro@ADC_SQR3_SQ14_1c:macro@ADC_SQR3_SQ14_2c:macro@ADC_SQR3_SQ14_3c:macro@ADC_SQR3_SQ14_4c:macro@ADC_SQR3_SQ15c:macro@ADC_SQR3_SQ15_0c:macro@ADC_SQR3_SQ15_1c:macro@ADC_SQR3_SQ15_2c:macro@ADC_SQR3_SQ15_3c:macro@ADC_SQR3_SQ15_4c:macro@ADC_SQR3_SQ16c:macro@ADC_SQR3_SQ16_0c:macro@ADC_SQR3_SQ16_1c:macro@ADC_SQR3_SQ16_2c:macro@ADC_SQR3_SQ16_3c:macro@ADC_SQR3_SQ16_4c:macro@ADC_SQR3_SQ17c:macro@ADC_SQR3_SQ17_0c:macro@ADC_SQR3_SQ17_1c:macro@ADC_SQR3_SQ17_2c:macro@ADC_SQR3_SQ17_3c:macro@ADC_SQR3_SQ17_4c:macro@ADC_SQR3_SQ18c:macro@ADC_SQR3_SQ18_0c:macro@ADC_SQR3_SQ18_1c:macro@ADC_SQR3_SQ18_2c:macro@ADC_SQR3_SQ18_3c:macro@ADC_SQR3_SQ18_4c:macro@ADC_SQR4_SQ7c:macro@ADC_SQR4_SQ7_0c:macro@ADC_SQR4_SQ7_1c:macro@ADC_SQR4_SQ7_2c:macro@ADC_SQR4_SQ7_3c:macro@ADC_SQR4_SQ7_4c:macro@ADC_SQR4_SQ8c:macro@ADC_SQR4_SQ8_0c:macro@ADC_SQR4_SQ8_1c:macro@ADC_SQR4_SQ8_2c:macro@ADC_SQR4_SQ8_3c:macro@ADC_SQR4_SQ8_4c:macro@ADC_SQR4_SQ9c:macro@ADC_SQR4_SQ9_0c:macro@ADC_SQR4_SQ9_1c:macro@ADC_SQR4_SQ9_2c:macro@ADC_SQR4_SQ9_3c:macro@ADC_SQR4_SQ9_4c:macro@ADC_SQR4_SQ10c:macro@ADC_SQR4_SQ10_0c:macro@ADC_SQR4_SQ10_1c:macro@ADC_SQR4_SQ10_2c:macro@ADC_SQR4_SQ10_3c:macro@ADC_SQR4_SQ10_4c:macro@ADC_SQR4_SQ11c:macro@ADC_SQR4_SQ11_0c:macro@ADC_SQR4_SQ11_1c:macro@ADC_SQR4_SQ11_2c:macro@ADC_SQR4_SQ11_3c:macro@ADC_SQR4_SQ11_4c:macro@ADC_SQR4_SQ12c:macro@ADC_SQR4_SQ12_0c:macro@ADC_SQR4_SQ12_1c:macro@ADC_SQR4_SQ12_2c:macro@ADC_SQR4_SQ12_3c:macro@ADC_SQR4_SQ12_4c:macro@ADC_SQR5_SQ1c:macro@ADC_SQR5_SQ1_0c:macro@ADC_SQR5_SQ1_1c:macro@ADC_SQR5_SQ1_2c:macro@ADC_SQR5_SQ1_3c:macro@ADC_SQR5_SQ1_4c:macro@ADC_SQR5_SQ2c:macro@ADC_SQR5_SQ2_0c:macro@ADC_SQR5_SQ2_1c:macro@ADC_SQR5_SQ2_2c:macro@ADC_SQR5_SQ2_3c:macro@ADC_SQR5_SQ2_4c:macro@ADC_SQR5_SQ3c:macro@ADC_SQR5_SQ3_0c:macro@ADC_SQR5_SQ3_1c:macro@ADC_SQR5_SQ3_2c:macro@ADC_SQR5_SQ3_3c:macro@ADC_SQR5_SQ3_4c:macro@ADC_SQR5_SQ4c:macro@ADC_SQR5_SQ4_0c:macro@ADC_SQR5_SQ4_1c:macro@ADC_SQR5_SQ4_2c:macro@ADC_SQR5_SQ4_3c:macro@ADC_SQR5_SQ4_4c:macro@ADC_SQR5_SQ5c:macro@ADC_SQR5_SQ5_0c:macro@ADC_SQR5_SQ5_1c:macro@ADC_SQR5_SQ5_2c:macro@ADC_SQR5_SQ5_3c:macro@ADC_SQR5_SQ5_4c:macro@ADC_SQR5_SQ6c:macro@ADC_SQR5_SQ6_0c:macro@ADC_SQR5_SQ6_1c:macro@ADC_SQR5_SQ6_2c:macro@ADC_SQR5_SQ6_3c:macro@ADC_SQR5_SQ6_4c:macro@ADC_JSQR_JSQ1c:macro@ADC_JSQR_JSQ1_0c:macro@ADC_JSQR_JSQ1_1c:macro@ADC_JSQR_JSQ1_2c:macro@ADC_JSQR_JSQ1_3c:macro@ADC_JSQR_JSQ1_4c:macro@ADC_JSQR_JSQ2c:macro@ADC_JSQR_JSQ2_0c:macro@ADC_JSQR_JSQ2_1c:macro@ADC_JSQR_JSQ2_2c:macro@ADC_JSQR_JSQ2_3c:macro@ADC_JSQR_JSQ2_4c:macro@ADC_JSQR_JSQ3c:macro@ADC_JSQR_JSQ3_0c:macro@ADC_JSQR_JSQ3_1c:macro@ADC_JSQR_JSQ3_2c:macro@ADC_JSQR_JSQ3_3c:macro@ADC_JSQR_JSQ3_4c:macro@ADC_JSQR_JSQ4c:macro@ADC_JSQR_JSQ4_0c:macro@ADC_JSQR_JSQ4_1c:macro@ADC_JSQR_JSQ4_2c:macro@ADC_JSQR_JSQ4_3c:macro@ADC_JSQR_JSQ4_4c:macro@ADC_JSQR_JLc:macro@ADC_JSQR_JL_0c:macro@ADC_JSQR_JL_1c:macro@ADC_JDR1_JDATAc:macro@ADC_JDR2_JDATAc:macro@ADC_JDR3_JDATAc:macro@ADC_JDR4_JDATAc:macro@ADC_DR_DATAc:macro@ADC_SMPR3_SMP30c:macro@ADC_SMPR3_SMP30_0c:macro@ADC_SMPR3_SMP30_1c:macro@ADC_SMPR3_SMP30_2c:macro@ADC_SMPR3_SMP31c:macro@ADC_SMPR3_SMP31_0c:macro@ADC_SMPR3_SMP31_1c:macro@ADC_SMPR3_SMP31_2c:macro@ADC_CSR_AWD1c:macro@ADC_CSR_EOC1c:macro@ADC_CSR_JEOC1c:macro@ADC_CSR_JSTRT1c:macro@ADC_CSR_STRT1c:macro@ADC_CSR_OVR1c:macro@ADC_CSR_ADONS1c:macro@ADC_CCR_ADCPREc:macro@ADC_CCR_ADCPRE_0c:macro@ADC_CCR_ADCPRE_1c:macro@ADC_CCR_TSVREFEc:macro@AES_CR_ENc:macro@AES_CR_DATATYPEc:macro@AES_CR_DATATYPE_0c:macro@AES_CR_DATATYPE_1c:macro@AES_CR_MODEc:macro@AES_CR_MODE_0c:macro@AES_CR_MODE_1c:macro@AES_CR_CHMODc:macro@AES_CR_CHMOD_0c:macro@AES_CR_CHMOD_1c:macro@AES_CR_CCFCc:macro@AES_CR_ERRCc:macro@AES_CR_CCIEc:macro@AES_CR_ERRIEc:macro@AES_CR_DMAINENc:macro@AES_CR_DMAOUTENc:macro@AES_SR_CCFc:macro@AES_SR_RDERRc:macro@AES_SR_WRERRc:macro@AES_DINRc:macro@AES_DOUTRc:macro@AES_KEYR0c:macro@AES_KEYR1c:macro@AES_KEYR2c:macro@AES_KEYR3c:macro@AES_IVR0c:macro@AES_IVR1c:macro@AES_IVR2c:macro@AES_IVR3c:macro@COMP_CSR_10KPUc:macro@COMP_CSR_400KPUc:macro@COMP_CSR_10KPDc:macro@COMP_CSR_400KPDc:macro@COMP_CSR_CMP1ENc:macro@COMP_CSR_SW1c:macro@COMP_CSR_CMP1OUTc:macro@COMP_CSR_SPEEDc:macro@COMP_CSR_CMP2OUTc:macro@COMP_CSR_VREFOUTENc:macro@COMP_CSR_WNDWEc:macro@COMP_CSR_INSELc:macro@COMP_CSR_INSEL_0c:macro@COMP_CSR_INSEL_1c:macro@COMP_CSR_INSEL_2c:macro@COMP_CSR_OUTSELc:macro@COMP_CSR_OUTSEL_0c:macro@COMP_CSR_OUTSEL_1c:macro@COMP_CSR_OUTSEL_2c:macro@COMP_CSR_FCH3c:macro@COMP_CSR_FCH8c:macro@COMP_CSR_RCH13c:macro@COMP_CSR_CAIEc:macro@COMP_CSR_CAIFc:macro@COMP_CSR_TSUSPc:macro@OPAMP_CSR_OPA1PDc:macro@OPAMP_CSR_S3SEL1c:macro@OPAMP_CSR_S4SEL1c:macro@OPAMP_CSR_S5SEL1c:macro@OPAMP_CSR_S6SEL1c:macro@OPAMP_CSR_OPA1CAL_Lc:macro@OPAMP_CSR_OPA1CAL_Hc:macro@OPAMP_CSR_OPA1LPMc:macro@OPAMP_CSR_OPA2PDc:macro@OPAMP_CSR_S3SEL2c:macro@OPAMP_CSR_S4SEL2c:macro@OPAMP_CSR_S5SEL2c:macro@OPAMP_CSR_S6SEL2c:macro@OPAMP_CSR_OPA2CAL_Lc:macro@OPAMP_CSR_OPA2CAL_Hc:macro@OPAMP_CSR_OPA2LPMc:macro@OPAMP_CSR_OPA3PDc:macro@OPAMP_CSR_S3SEL3c:macro@OPAMP_CSR_S4SEL3c:macro@OPAMP_CSR_S5SEL3c:macro@OPAMP_CSR_S6SEL3c:macro@OPAMP_CSR_OPA3CAL_Lc:macro@OPAMP_CSR_OPA3CAL_Hc:macro@OPAMP_CSR_OPA3LPMc:macro@OPAMP_CSR_ANAWSEL1c:macro@OPAMP_CSR_ANAWSEL2c:macro@OPAMP_CSR_ANAWSEL3c:macro@OPAMP_CSR_S7SEL2c:macro@OPAMP_CSR_AOP_RANGEc:macro@OPAMP_CSR_OPA1CALOUTc:macro@OPAMP_CSR_OPA2CALOUTc:macro@OPAMP_CSR_OPA3CALOUTc:macro@OPAMP_OTR_AO1_OPT_OFFSET_TRIMc:macro@OPAMP_OTR_AO2_OPT_OFFSET_TRIMc:macro@OPAMP_OTR_AO3_OPT_OFFSET_TRIMc:macro@OPAMP_OTR_OT_USERc:macro@OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LPc:macro@OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LPc:macro@OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LPc:macro@CRC_DR_DRc:macro@CRC_IDR_IDRc:macro@CRC_CR_RESETc:macro@DAC_CR_EN1c:macro@DAC_CR_BOFF1c:macro@DAC_CR_TEN1c:macro@DAC_CR_TSEL1c:macro@DAC_CR_TSEL1_0c:macro@DAC_CR_TSEL1_1c:macro@DAC_CR_TSEL1_2c:macro@DAC_CR_WAVE1c:macro@DAC_CR_WAVE1_0c:macro@DAC_CR_WAVE1_1c:macro@DAC_CR_MAMP1c:macro@DAC_CR_MAMP1_0c:macro@DAC_CR_MAMP1_1c:macro@DAC_CR_MAMP1_2c:macro@DAC_CR_MAMP1_3c:macro@DAC_CR_DMAEN1c:macro@DAC_CR_DMAUDRIE1c:macro@DAC_CR_EN2c:macro@DAC_CR_BOFF2c:macro@DAC_CR_TEN2c:macro@DAC_CR_TSEL2c:macro@DAC_CR_TSEL2_0c:macro@DAC_CR_TSEL2_1c:macro@DAC_CR_TSEL2_2c:macro@DAC_CR_WAVE2c:macro@DAC_CR_WAVE2_0c:macro@DAC_CR_WAVE2_1c:macro@DAC_CR_MAMP2c:macro@DAC_CR_MAMP2_0c:macro@DAC_CR_MAMP2_1c:macro@DAC_CR_MAMP2_2c:macro@DAC_CR_MAMP2_3c:macro@DAC_CR_DMAEN2c:macro@DAC_CR_DMAUDRIE2c:macro@DAC_SWTRIGR_SWTRIG1c:macro@DAC_SWTRIGR_SWTRIG2c:macro@DAC_DHR12R1_DACC1DHRc:macro@DAC_DHR12L1_DACC1DHRc:macro@DAC_DHR8R1_DACC1DHRc:macro@DAC_DHR12R2_DACC2DHRc:macro@DAC_DHR12L2_DACC2DHRc:macro@DAC_DHR8R2_DACC2DHRc:macro@DAC_DHR12RD_DACC1DHRc:macro@DAC_DHR12RD_DACC2DHRc:macro@DAC_DHR12LD_DACC1DHRc:macro@DAC_DHR12LD_DACC2DHRc:macro@DAC_DHR8RD_DACC1DHRc:macro@DAC_DHR8RD_DACC2DHRc:macro@DAC_DOR1_DACC1DORc:macro@DAC_DOR2_DACC2DORc:macro@DAC_SR_DMAUDR1c:macro@DAC_SR_DMAUDR2c:macro@DBGMCU_IDCODE_DEV_IDc:macro@DBGMCU_IDCODE_REV_IDc:macro@DBGMCU_IDCODE_REV_ID_0c:macro@DBGMCU_IDCODE_REV_ID_1c:macro@DBGMCU_IDCODE_REV_ID_2c:macro@DBGMCU_IDCODE_REV_ID_3c:macro@DBGMCU_IDCODE_REV_ID_4c:macro@DBGMCU_IDCODE_REV_ID_5c:macro@DBGMCU_IDCODE_REV_ID_6c:macro@DBGMCU_IDCODE_REV_ID_7c:macro@DBGMCU_IDCODE_REV_ID_8c:macro@DBGMCU_IDCODE_REV_ID_9c:macro@DBGMCU_IDCODE_REV_ID_10c:macro@DBGMCU_IDCODE_REV_ID_11c:macro@DBGMCU_IDCODE_REV_ID_12c:macro@DBGMCU_IDCODE_REV_ID_13c:macro@DBGMCU_IDCODE_REV_ID_14c:macro@DBGMCU_IDCODE_REV_ID_15c:macro@DBGMCU_CR_DBG_SLEEPc:macro@DBGMCU_CR_DBG_STOPc:macro@DBGMCU_CR_DBG_STANDBYc:macro@DBGMCU_CR_TRACE_IOENc:macro@DBGMCU_CR_TRACE_MODEc:macro@DBGMCU_CR_TRACE_MODE_0c:macro@DBGMCU_CR_TRACE_MODE_1c:macro@DBGMCU_APB1_FZ_DBG_TIM2_STOPc:macro@DBGMCU_APB1_FZ_DBG_TIM3_STOPc:macro@DBGMCU_APB1_FZ_DBG_TIM4_STOPc:macro@DBGMCU_APB1_FZ_DBG_TIM5_STOPc:macro@DBGMCU_APB1_FZ_DBG_TIM6_STOPc:macro@DBGMCU_APB1_FZ_DBG_TIM7_STOPc:macro@DBGMCU_APB1_FZ_DBG_RTC_STOPc:macro@DBGMCU_APB1_FZ_DBG_WWDG_STOPc:macro@DBGMCU_APB1_FZ_DBG_IWDG_STOPc:macro@DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUTc:macro@DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUTc:macro@DBGMCU_APB2_FZ_DBG_TIM9_STOPc:macro@DBGMCU_APB2_FZ_DBG_TIM10_STOPc:macro@DBGMCU_APB2_FZ_DBG_TIM11_STOPc:macro@DMA_ISR_GIF1c:macro@DMA_ISR_TCIF1c:macro@DMA_ISR_HTIF1c:macro@DMA_ISR_TEIF1c:macro@DMA_ISR_GIF2c:macro@DMA_ISR_TCIF2c:macro@DMA_ISR_HTIF2c:macro@DMA_ISR_TEIF2c:macro@DMA_ISR_GIF3c:macro@DMA_ISR_TCIF3c:macro@DMA_ISR_HTIF3c:macro@DMA_ISR_TEIF3c:macro@DMA_ISR_GIF4c:macro@DMA_ISR_TCIF4c:macro@DMA_ISR_HTIF4c:macro@DMA_ISR_TEIF4c:macro@DMA_ISR_GIF5c:macro@DMA_ISR_TCIF5c:macro@DMA_ISR_HTIF5c:macro@DMA_ISR_TEIF5c:macro@DMA_ISR_GIF6c:macro@DMA_ISR_TCIF6c:macro@DMA_ISR_HTIF6c:macro@DMA_ISR_TEIF6c:macro@DMA_ISR_GIF7c:macro@DMA_ISR_TCIF7c:macro@DMA_ISR_HTIF7c:macro@DMA_ISR_TEIF7c:macro@DMA_IFCR_CGIF1c:macro@DMA_IFCR_CTCIF1c:macro@DMA_IFCR_CHTIF1c:macro@DMA_IFCR_CTEIF1c:macro@DMA_IFCR_CGIF2c:macro@DMA_IFCR_CTCIF2c:macro@DMA_IFCR_CHTIF2c:macro@DMA_IFCR_CTEIF2c:macro@DMA_IFCR_CGIF3c:macro@DMA_IFCR_CTCIF3c:macro@DMA_IFCR_CHTIF3c:macro@DMA_IFCR_CTEIF3c:macro@DMA_IFCR_CGIF4c:macro@DMA_IFCR_CTCIF4c:macro@DMA_IFCR_CHTIF4c:macro@DMA_IFCR_CTEIF4c:macro@DMA_IFCR_CGIF5c:macro@DMA_IFCR_CTCIF5c:macro@DMA_IFCR_CHTIF5c:macro@DMA_IFCR_CTEIF5c:macro@DMA_IFCR_CGIF6c:macro@DMA_IFCR_CTCIF6c:macro@DMA_IFCR_CHTIF6c:macro@DMA_IFCR_CTEIF6c:macro@DMA_IFCR_CGIF7c:macro@DMA_IFCR_CTCIF7c:macro@DMA_IFCR_CHTIF7c:macro@DMA_IFCR_CTEIF7c:macro@DMA_CCR1_ENc:macro@DMA_CCR1_TCIEc:macro@DMA_CCR1_HTIEc:macro@DMA_CCR1_TEIEc:macro@DMA_CCR1_DIRc:macro@DMA_CCR1_CIRCc:macro@DMA_CCR1_PINCc:macro@DMA_CCR1_MINCc:macro@DMA_CCR1_PSIZEc:macro@DMA_CCR1_PSIZE_0c:macro@DMA_CCR1_PSIZE_1c:macro@DMA_CCR1_MSIZEc:macro@DMA_CCR1_MSIZE_0c:macro@DMA_CCR1_MSIZE_1c:macro@DMA_CCR1_PLc:macro@DMA_CCR1_PL_0c:macro@DMA_CCR1_PL_1c:macro@DMA_CCR1_MEM2MEMc:macro@DMA_CCR2_ENc:macro@DMA_CCR2_TCIEc:macro@DMA_CCR2_HTIEc:macro@DMA_CCR2_TEIEc:macro@DMA_CCR2_DIRc:macro@DMA_CCR2_CIRCc:macro@DMA_CCR2_PINCc:macro@DMA_CCR2_MINCc:macro@DMA_CCR2_PSIZEc:macro@DMA_CCR2_PSIZE_0c:macro@DMA_CCR2_PSIZE_1c:macro@DMA_CCR2_MSIZEc:macro@DMA_CCR2_MSIZE_0c:macro@DMA_CCR2_MSIZE_1c:macro@DMA_CCR2_PLc:macro@DMA_CCR2_PL_0c:macro@DMA_CCR2_PL_1c:macro@DMA_CCR2_MEM2MEMc:macro@DMA_CCR3_ENc:macro@DMA_CCR3_TCIEc:macro@DMA_CCR3_HTIEc:macro@DMA_CCR3_TEIEc:macro@DMA_CCR3_DIRc:macro@DMA_CCR3_CIRCc:macro@DMA_CCR3_PINCc:macro@DMA_CCR3_MINCc:macro@DMA_CCR3_PSIZEc:macro@DMA_CCR3_PSIZE_0c:macro@DMA_CCR3_PSIZE_1c:macro@DMA_CCR3_MSIZEc:macro@DMA_CCR3_MSIZE_0c:macro@DMA_CCR3_MSIZE_1c:macro@DMA_CCR3_PLc:macro@DMA_CCR3_PL_0c:macro@DMA_CCR3_PL_1c:macro@DMA_CCR3_MEM2MEMc:macro@DMA_CCR4_ENc:macro@DMA_CCR4_TCIEc:macro@DMA_CCR4_HTIEc:macro@DMA_CCR4_TEIEc:macro@DMA_CCR4_DIRc:macro@DMA_CCR4_CIRCc:macro@DMA_CCR4_PINCc:macro@DMA_CCR4_MINCc:macro@DMA_CCR4_PSIZEc:macro@DMA_CCR4_PSIZE_0c:macro@DMA_CCR4_PSIZE_1c:macro@DMA_CCR4_MSIZEc:macro@DMA_CCR4_MSIZE_0c:macro@DMA_CCR4_MSIZE_1c:macro@DMA_CCR4_PLc:macro@DMA_CCR4_PL_0c:macro@DMA_CCR4_PL_1c:macro@DMA_CCR4_MEM2MEMc:macro@DMA_CCR5_ENc:macro@DMA_CCR5_TCIEc:macro@DMA_CCR5_HTIEc:macro@DMA_CCR5_TEIEc:macro@DMA_CCR5_DIRc:macro@DMA_CCR5_CIRCc:macro@DMA_CCR5_PINCc:macro@DMA_CCR5_MINCc:macro@DMA_CCR5_PSIZEc:macro@DMA_CCR5_PSIZE_0c:macro@DMA_CCR5_PSIZE_1c:macro@DMA_CCR5_MSIZEc:macro@DMA_CCR5_MSIZE_0c:macro@DMA_CCR5_MSIZE_1c:macro@DMA_CCR5_PLc:macro@DMA_CCR5_PL_0c:macro@DMA_CCR5_PL_1c:macro@DMA_CCR5_MEM2MEMc:macro@DMA_CCR6_ENc:macro@DMA_CCR6_TCIEc:macro@DMA_CCR6_HTIEc:macro@DMA_CCR6_TEIEc:macro@DMA_CCR6_DIRc:macro@DMA_CCR6_CIRCc:macro@DMA_CCR6_PINCc:macro@DMA_CCR6_MINCc:macro@DMA_CCR6_PSIZEc:macro@DMA_CCR6_PSIZE_0c:macro@DMA_CCR6_PSIZE_1c:macro@DMA_CCR6_MSIZEc:macro@DMA_CCR6_MSIZE_0c:macro@DMA_CCR6_MSIZE_1c:macro@DMA_CCR6_PLc:macro@DMA_CCR6_PL_0c:macro@DMA_CCR6_PL_1c:macro@DMA_CCR6_MEM2MEMc:macro@DMA_CCR7_ENc:macro@DMA_CCR7_TCIEc:macro@DMA_CCR7_HTIEc:macro@DMA_CCR7_TEIEc:macro@DMA_CCR7_DIRc:macro@DMA_CCR7_CIRCc:macro@DMA_CCR7_PINCc:macro@DMA_CCR7_MINCc:macro@DMA_CCR7_PSIZEc:macro@DMA_CCR7_PSIZE_0c:macro@DMA_CCR7_PSIZE_1c:macro@DMA_CCR7_MSIZEc:macro@DMA_CCR7_MSIZE_0c:macro@DMA_CCR7_MSIZE_1c:macro@DMA_CCR7_PLc:macro@DMA_CCR7_PL_0c:macro@DMA_CCR7_PL_1c:macro@DMA_CCR7_MEM2MEMc:macro@DMA_CNDTR1_NDTc:macro@DMA_CNDTR2_NDTc:macro@DMA_CNDTR3_NDTc:macro@DMA_CNDTR4_NDTc:macro@DMA_CNDTR5_NDTc:macro@DMA_CNDTR6_NDTc:macro@DMA_CNDTR7_NDTc:macro@DMA_CPAR1_PAc:macro@DMA_CPAR2_PAc:macro@DMA_CPAR3_PAc:macro@DMA_CPAR4_PAc:macro@DMA_CPAR5_PAc:macro@DMA_CPAR6_PAc:macro@DMA_CPAR7_PAc:macro@DMA_CMAR1_MAc:macro@DMA_CMAR2_MAc:macro@DMA_CMAR3_MAc:macro@DMA_CMAR4_MAc:macro@DMA_CMAR5_MAc:macro@DMA_CMAR6_MAc:macro@DMA_CMAR7_MAc:macro@EXTI_IMR_MR0c:macro@EXTI_IMR_MR1c:macro@EXTI_IMR_MR2c:macro@EXTI_IMR_MR3c:macro@EXTI_IMR_MR4c:macro@EXTI_IMR_MR5c:macro@EXTI_IMR_MR6c:macro@EXTI_IMR_MR7c:macro@EXTI_IMR_MR8c:macro@EXTI_IMR_MR9c:macro@EXTI_IMR_MR10c:macro@EXTI_IMR_MR11c:macro@EXTI_IMR_MR12c:macro@EXTI_IMR_MR13c:macro@EXTI_IMR_MR14c:macro@EXTI_IMR_MR15c:macro@EXTI_IMR_MR16c:macro@EXTI_IMR_MR17c:macro@EXTI_IMR_MR18c:macro@EXTI_IMR_MR19c:macro@EXTI_IMR_MR20c:macro@EXTI_IMR_MR21c:macro@EXTI_IMR_MR22c:macro@EXTI_IMR_MR23c:macro@EXTI_EMR_MR0c:macro@EXTI_EMR_MR1c:macro@EXTI_EMR_MR2c:macro@EXTI_EMR_MR3c:macro@EXTI_EMR_MR4c:macro@EXTI_EMR_MR5c:macro@EXTI_EMR_MR6c:macro@EXTI_EMR_MR7c:macro@EXTI_EMR_MR8c:macro@EXTI_EMR_MR9c:macro@EXTI_EMR_MR10c:macro@EXTI_EMR_MR11c:macro@EXTI_EMR_MR12c:macro@EXTI_EMR_MR13c:macro@EXTI_EMR_MR14c:macro@EXTI_EMR_MR15c:macro@EXTI_EMR_MR16c:macro@EXTI_EMR_MR17c:macro@EXTI_EMR_MR18c:macro@EXTI_EMR_MR19c:macro@EXTI_EMR_MR20c:macro@EXTI_EMR_MR21c:macro@EXTI_EMR_MR22c:macro@EXTI_EMR_MR23c:macro@EXTI_RTSR_TR0c:macro@EXTI_RTSR_TR1c:macro@EXTI_RTSR_TR2c:macro@EXTI_RTSR_TR3c:macro@EXTI_RTSR_TR4c:macro@EXTI_RTSR_TR5c:macro@EXTI_RTSR_TR6c:macro@EXTI_RTSR_TR7c:macro@EXTI_RTSR_TR8c:macro@EXTI_RTSR_TR9c:macro@EXTI_RTSR_TR10c:macro@EXTI_RTSR_TR11c:macro@EXTI_RTSR_TR12c:macro@EXTI_RTSR_TR13c:macro@EXTI_RTSR_TR14c:macro@EXTI_RTSR_TR15c:macro@EXTI_RTSR_TR16c:macro@EXTI_RTSR_TR17c:macro@EXTI_RTSR_TR18c:macro@EXTI_RTSR_TR19c:macro@EXTI_RTSR_TR20c:macro@EXTI_RTSR_TR21c:macro@EXTI_RTSR_TR22c:macro@EXTI_RTSR_TR23c:macro@EXTI_FTSR_TR0c:macro@EXTI_FTSR_TR1c:macro@EXTI_FTSR_TR2c:macro@EXTI_FTSR_TR3c:macro@EXTI_FTSR_TR4c:macro@EXTI_FTSR_TR5c:macro@EXTI_FTSR_TR6c:macro@EXTI_FTSR_TR7c:macro@EXTI_FTSR_TR8c:macro@EXTI_FTSR_TR9c:macro@EXTI_FTSR_TR10c:macro@EXTI_FTSR_TR11c:macro@EXTI_FTSR_TR12c:macro@EXTI_FTSR_TR13c:macro@EXTI_FTSR_TR14c:macro@EXTI_FTSR_TR15c:macro@EXTI_FTSR_TR16c:macro@EXTI_FTSR_TR17c:macro@EXTI_FTSR_TR18c:macro@EXTI_FTSR_TR19c:macro@EXTI_FTSR_TR20c:macro@EXTI_FTSR_TR21c:macro@EXTI_FTSR_TR22c:macro@EXTI_FTSR_TR23c:macro@EXTI_SWIER_SWIER0c:macro@EXTI_SWIER_SWIER1c:macro@EXTI_SWIER_SWIER2c:macro@EXTI_SWIER_SWIER3c:macro@EXTI_SWIER_SWIER4c:macro@EXTI_SWIER_SWIER5c:macro@EXTI_SWIER_SWIER6c:macro@EXTI_SWIER_SWIER7c:macro@EXTI_SWIER_SWIER8c:macro@EXTI_SWIER_SWIER9c:macro@EXTI_SWIER_SWIER10c:macro@EXTI_SWIER_SWIER11c:macro@EXTI_SWIER_SWIER12c:macro@EXTI_SWIER_SWIER13c:macro@EXTI_SWIER_SWIER14c:macro@EXTI_SWIER_SWIER15c:macro@EXTI_SWIER_SWIER16c:macro@EXTI_SWIER_SWIER17c:macro@EXTI_SWIER_SWIER18c:macro@EXTI_SWIER_SWIER19c:macro@EXTI_SWIER_SWIER20c:macro@EXTI_SWIER_SWIER21c:macro@EXTI_SWIER_SWIER22c:macro@EXTI_SWIER_SWIER23c:macro@EXTI_PR_PR0c:macro@EXTI_PR_PR1c:macro@EXTI_PR_PR2c:macro@EXTI_PR_PR3c:macro@EXTI_PR_PR4c:macro@EXTI_PR_PR5c:macro@EXTI_PR_PR6c:macro@EXTI_PR_PR7c:macro@EXTI_PR_PR8c:macro@EXTI_PR_PR9c:macro@EXTI_PR_PR10c:macro@EXTI_PR_PR11c:macro@EXTI_PR_PR12c:macro@EXTI_PR_PR13c:macro@EXTI_PR_PR14c:macro@EXTI_PR_PR15c:macro@EXTI_PR_PR16c:macro@EXTI_PR_PR17c:macro@EXTI_PR_PR18c:macro@EXTI_PR_PR19c:macro@EXTI_PR_PR20c:macro@EXTI_PR_PR21c:macro@EXTI_PR_PR22c:macro@EXTI_PR_PR23c:macro@FLASH_ACR_LATENCYc:macro@FLASH_ACR_PRFTENc:macro@FLASH_ACR_ACC64c:macro@FLASH_ACR_SLEEP_PDc:macro@FLASH_ACR_RUN_PDc:macro@FLASH_PECR_PELOCKc:macro@FLASH_PECR_PRGLOCKc:macro@FLASH_PECR_OPTLOCKc:macro@FLASH_PECR_PROGc:macro@FLASH_PECR_DATAc:macro@FLASH_PECR_FTDWc:macro@FLASH_PECR_ERASEc:macro@FLASH_PECR_FPRGc:macro@FLASH_PECR_PARALLBANKc:macro@FLASH_PECR_EOPIEc:macro@FLASH_PECR_ERRIEc:macro@FLASH_PECR_OBL_LAUNCHc:macro@FLASH_PDKEYR_PDKEYRc:macro@FLASH_PEKEYR_PEKEYRc:macro@FLASH_PRGKEYR_PRGKEYRc:macro@FLASH_OPTKEYR_OPTKEYRc:macro@FLASH_SR_BSYc:macro@FLASH_SR_EOPc:macro@FLASH_SR_ENHVc:macro@FLASH_SR_READYc:macro@FLASH_SR_WRPERRc:macro@FLASH_SR_PGAERRc:macro@FLASH_SR_SIZERRc:macro@FLASH_SR_OPTVERRc:macro@FLASH_SR_OPTVERRUSRc:macro@FLASH_OBR_RDPRTc:macro@FLASH_OBR_BOR_LEVc:macro@FLASH_OBR_USERc:macro@FLASH_OBR_IWDG_SWc:macro@FLASH_OBR_nRST_STOPc:macro@FLASH_OBR_nRST_STDBYc:macro@FLASH_OBR_nRST_BFB2c:macro@FLASH_WRPR_WRPc:macro@FLASH_WRPR1_WRPc:macro@FLASH_WRPR2_WRPc:macro@FSMC_BCR1_MBKENc:macro@FSMC_BCR1_MUXENc:macro@FSMC_BCR1_MTYPc:macro@FSMC_BCR1_MTYP_0c:macro@FSMC_BCR1_MTYP_1c:macro@FSMC_BCR1_MWIDc:macro@FSMC_BCR1_MWID_0c:macro@FSMC_BCR1_MWID_1c:macro@FSMC_BCR1_FACCENc:macro@FSMC_BCR1_BURSTENc:macro@FSMC_BCR1_WAITPOLc:macro@FSMC_BCR1_WRAPMODc:macro@FSMC_BCR1_WAITCFGc:macro@FSMC_BCR1_WRENc:macro@FSMC_BCR1_WAITENc:macro@FSMC_BCR1_EXTMODc:macro@FSMC_BCR1_ASYNCWAITc:macro@FSMC_BCR1_CBURSTRWc:macro@FSMC_BCR2_MBKENc:macro@FSMC_BCR2_MUXENc:macro@FSMC_BCR2_MTYPc:macro@FSMC_BCR2_MTYP_0c:macro@FSMC_BCR2_MTYP_1c:macro@FSMC_BCR2_MWIDc:macro@FSMC_BCR2_MWID_0c:macro@FSMC_BCR2_MWID_1c:macro@FSMC_BCR2_FACCENc:macro@FSMC_BCR2_BURSTENc:macro@FSMC_BCR2_WAITPOLc:macro@FSMC_BCR2_WRAPMODc:macro@FSMC_BCR2_WAITCFGc:macro@FSMC_BCR2_WRENc:macro@FSMC_BCR2_WAITENc:macro@FSMC_BCR2_EXTMODc:macro@FSMC_BCR2_ASYNCWAITc:macro@FSMC_BCR2_CBURSTRWc:macro@FSMC_BCR3_MBKENc:macro@FSMC_BCR3_MUXENc:macro@FSMC_BCR3_MTYPc:macro@FSMC_BCR3_MTYP_0c:macro@FSMC_BCR3_MTYP_1c:macro@FSMC_BCR3_MWIDc:macro@FSMC_BCR3_MWID_0c:macro@FSMC_BCR3_MWID_1c:macro@FSMC_BCR3_FACCENc:macro@FSMC_BCR3_BURSTENc:macro@FSMC_BCR3_WAITPOLc:macro@FSMC_BCR3_WRAPMODc:macro@FSMC_BCR3_WAITCFGc:macro@FSMC_BCR3_WRENc:macro@FSMC_BCR3_WAITENc:macro@FSMC_BCR3_EXTMODc:macro@FSMC_BCR3_ASYNCWAITc:macro@FSMC_BCR3_CBURSTRWc:macro@FSMC_BCR4_MBKENc:macro@FSMC_BCR4_MUXENc:macro@FSMC_BCR4_MTYPc:macro@FSMC_BCR4_MTYP_0c:macro@FSMC_BCR4_MTYP_1c:macro@FSMC_BCR4_MWIDc:macro@FSMC_BCR4_MWID_0c:macro@FSMC_BCR4_MWID_1c:macro@FSMC_BCR4_FACCENc:macro@FSMC_BCR4_BURSTENc:macro@FSMC_BCR4_WAITPOLc:macro@FSMC_BCR4_WRAPMODc:macro@FSMC_BCR4_WAITCFGc:macro@FSMC_BCR4_WRENc:macro@FSMC_BCR4_WAITENc:macro@FSMC_BCR4_EXTMODc:macro@FSMC_BCR4_ASYNCWAITc:macro@FSMC_BCR4_CBURSTRWc:macro@FSMC_BTR1_ADDSETc:macro@FSMC_BTR1_ADDSET_0c:macro@FSMC_BTR1_ADDSET_1c:macro@FSMC_BTR1_ADDSET_2c:macro@FSMC_BTR1_ADDSET_3c:macro@FSMC_BTR1_ADDHLDc:macro@FSMC_BTR1_ADDHLD_0c:macro@FSMC_BTR1_ADDHLD_1c:macro@FSMC_BTR1_ADDHLD_2c:macro@FSMC_BTR1_ADDHLD_3c:macro@FSMC_BTR1_DATASTc:macro@FSMC_BTR1_DATAST_0c:macro@FSMC_BTR1_DATAST_1c:macro@FSMC_BTR1_DATAST_2c:macro@FSMC_BTR1_DATAST_3c:macro@FSMC_BTR1_BUSTURNc:macro@FSMC_BTR1_BUSTURN_0c:macro@FSMC_BTR1_BUSTURN_1c:macro@FSMC_BTR1_BUSTURN_2c:macro@FSMC_BTR1_BUSTURN_3c:macro@FSMC_BTR1_CLKDIVc:macro@FSMC_BTR1_CLKDIV_0c:macro@FSMC_BTR1_CLKDIV_1c:macro@FSMC_BTR1_CLKDIV_2c:macro@FSMC_BTR1_CLKDIV_3c:macro@FSMC_BTR1_DATLATc:macro@FSMC_BTR1_DATLAT_0c:macro@FSMC_BTR1_DATLAT_1c:macro@FSMC_BTR1_DATLAT_2c:macro@FSMC_BTR1_DATLAT_3c:macro@FSMC_BTR1_ACCMODc:macro@FSMC_BTR1_ACCMOD_0c:macro@FSMC_BTR1_ACCMOD_1c:macro@FSMC_BTR2_ADDSETc:macro@FSMC_BTR2_ADDSET_0c:macro@FSMC_BTR2_ADDSET_1c:macro@FSMC_BTR2_ADDSET_2c:macro@FSMC_BTR2_ADDSET_3c:macro@FSMC_BTR2_ADDHLDc:macro@FSMC_BTR2_ADDHLD_0c:macro@FSMC_BTR2_ADDHLD_1c:macro@FSMC_BTR2_ADDHLD_2c:macro@FSMC_BTR2_ADDHLD_3c:macro@FSMC_BTR2_DATASTc:macro@FSMC_BTR2_DATAST_0c:macro@FSMC_BTR2_DATAST_1c:macro@FSMC_BTR2_DATAST_2c:macro@FSMC_BTR2_DATAST_3c:macro@FSMC_BTR2_BUSTURNc:macro@FSMC_BTR2_BUSTURN_0c:macro@FSMC_BTR2_BUSTURN_1c:macro@FSMC_BTR2_BUSTURN_2c:macro@FSMC_BTR2_BUSTURN_3c:macro@FSMC_BTR2_CLKDIVc:macro@FSMC_BTR2_CLKDIV_0c:macro@FSMC_BTR2_CLKDIV_1c:macro@FSMC_BTR2_CLKDIV_2c:macro@FSMC_BTR2_CLKDIV_3c:macro@FSMC_BTR2_DATLATc:macro@FSMC_BTR2_DATLAT_0c:macro@FSMC_BTR2_DATLAT_1c:macro@FSMC_BTR2_DATLAT_2c:macro@FSMC_BTR2_DATLAT_3c:macro@FSMC_BTR2_ACCMODc:macro@FSMC_BTR2_ACCMOD_0c:macro@FSMC_BTR2_ACCMOD_1c:macro@FSMC_BTR3_ADDSETc:macro@FSMC_BTR3_ADDSET_0c:macro@FSMC_BTR3_ADDSET_1c:macro@FSMC_BTR3_ADDSET_2c:macro@FSMC_BTR3_ADDSET_3c:macro@FSMC_BTR3_ADDHLDc:macro@FSMC_BTR3_ADDHLD_0c:macro@FSMC_BTR3_ADDHLD_1c:macro@FSMC_BTR3_ADDHLD_2c:macro@FSMC_BTR3_ADDHLD_3c:macro@FSMC_BTR3_DATASTc:macro@FSMC_BTR3_DATAST_0c:macro@FSMC_BTR3_DATAST_1c:macro@FSMC_BTR3_DATAST_2c:macro@FSMC_BTR3_DATAST_3c:macro@FSMC_BTR3_BUSTURNc:macro@FSMC_BTR3_BUSTURN_0c:macro@FSMC_BTR3_BUSTURN_1c:macro@FSMC_BTR3_BUSTURN_2c:macro@FSMC_BTR3_BUSTURN_3c:macro@FSMC_BTR3_CLKDIVc:macro@FSMC_BTR3_CLKDIV_0c:macro@FSMC_BTR3_CLKDIV_1c:macro@FSMC_BTR3_CLKDIV_2c:macro@FSMC_BTR3_CLKDIV_3c:macro@FSMC_BTR3_DATLATc:macro@FSMC_BTR3_DATLAT_0c:macro@FSMC_BTR3_DATLAT_1c:macro@FSMC_BTR3_DATLAT_2c:macro@FSMC_BTR3_DATLAT_3c:macro@FSMC_BTR3_ACCMODc:macro@FSMC_BTR3_ACCMOD_0c:macro@FSMC_BTR3_ACCMOD_1c:macro@FSMC_BTR4_ADDSETc:macro@FSMC_BTR4_ADDSET_0c:macro@FSMC_BTR4_ADDSET_1c:macro@FSMC_BTR4_ADDSET_2c:macro@FSMC_BTR4_ADDSET_3c:macro@FSMC_BTR4_ADDHLDc:macro@FSMC_BTR4_ADDHLD_0c:macro@FSMC_BTR4_ADDHLD_1c:macro@FSMC_BTR4_ADDHLD_2c:macro@FSMC_BTR4_ADDHLD_3c:macro@FSMC_BTR4_DATASTc:macro@FSMC_BTR4_DATAST_0c:macro@FSMC_BTR4_DATAST_1c:macro@FSMC_BTR4_DATAST_2c:macro@FSMC_BTR4_DATAST_3c:macro@FSMC_BTR4_BUSTURNc:macro@FSMC_BTR4_BUSTURN_0c:macro@FSMC_BTR4_BUSTURN_1c:macro@FSMC_BTR4_BUSTURN_2c:macro@FSMC_BTR4_BUSTURN_3c:macro@FSMC_BTR4_CLKDIVc:macro@FSMC_BTR4_CLKDIV_0c:macro@FSMC_BTR4_CLKDIV_1c:macro@FSMC_BTR4_CLKDIV_2c:macro@FSMC_BTR4_CLKDIV_3c:macro@FSMC_BTR4_DATLATc:macro@FSMC_BTR4_DATLAT_0c:macro@FSMC_BTR4_DATLAT_1c:macro@FSMC_BTR4_DATLAT_2c:macro@FSMC_BTR4_DATLAT_3c:macro@FSMC_BTR4_ACCMODc:macro@FSMC_BTR4_ACCMOD_0c:macro@FSMC_BTR4_ACCMOD_1c:macro@FSMC_BWTR1_ADDSETc:macro@FSMC_BWTR1_ADDSET_0c:macro@FSMC_BWTR1_ADDSET_1c:macro@FSMC_BWTR1_ADDSET_2c:macro@FSMC_BWTR1_ADDSET_3c:macro@FSMC_BWTR1_ADDHLDc:macro@FSMC_BWTR1_ADDHLD_0c:macro@FSMC_BWTR1_ADDHLD_1c:macro@FSMC_BWTR1_ADDHLD_2c:macro@FSMC_BWTR1_ADDHLD_3c:macro@FSMC_BWTR1_DATASTc:macro@FSMC_BWTR1_DATAST_0c:macro@FSMC_BWTR1_DATAST_1c:macro@FSMC_BWTR1_DATAST_2c:macro@FSMC_BWTR1_DATAST_3c:macro@FSMC_BWTR1_CLKDIVc:macro@FSMC_BWTR1_CLKDIV_0c:macro@FSMC_BWTR1_CLKDIV_1c:macro@FSMC_BWTR1_CLKDIV_2c:macro@FSMC_BWTR1_CLKDIV_3c:macro@FSMC_BWTR1_DATLATc:macro@FSMC_BWTR1_DATLAT_0c:macro@FSMC_BWTR1_DATLAT_1c:macro@FSMC_BWTR1_DATLAT_2c:macro@FSMC_BWTR1_DATLAT_3c:macro@FSMC_BWTR1_ACCMODc:macro@FSMC_BWTR1_ACCMOD_0c:macro@FSMC_BWTR1_ACCMOD_1c:macro@FSMC_BWTR2_ADDSETc:macro@FSMC_BWTR2_ADDSET_0c:macro@FSMC_BWTR2_ADDSET_1c:macro@FSMC_BWTR2_ADDSET_2c:macro@FSMC_BWTR2_ADDSET_3c:macro@FSMC_BWTR2_ADDHLDc:macro@FSMC_BWTR2_ADDHLD_0c:macro@FSMC_BWTR2_ADDHLD_1c:macro@FSMC_BWTR2_ADDHLD_2c:macro@FSMC_BWTR2_ADDHLD_3c:macro@FSMC_BWTR2_DATASTc:macro@FSMC_BWTR2_DATAST_0c:macro@FSMC_BWTR2_DATAST_1c:macro@FSMC_BWTR2_DATAST_2c:macro@FSMC_BWTR2_DATAST_3c:macro@FSMC_BWTR2_CLKDIVc:macro@FSMC_BWTR2_CLKDIV_0c:macro@FSMC_BWTR2_CLKDIV_1c:macro@FSMC_BWTR2_CLKDIV_2c:macro@FSMC_BWTR2_CLKDIV_3c:macro@FSMC_BWTR2_DATLATc:macro@FSMC_BWTR2_DATLAT_0c:macro@FSMC_BWTR2_DATLAT_1c:macro@FSMC_BWTR2_DATLAT_2c:macro@FSMC_BWTR2_DATLAT_3c:macro@FSMC_BWTR2_ACCMODc:macro@FSMC_BWTR2_ACCMOD_0c:macro@FSMC_BWTR2_ACCMOD_1c:macro@FSMC_BWTR3_ADDSETc:macro@FSMC_BWTR3_ADDSET_0c:macro@FSMC_BWTR3_ADDSET_1c:macro@FSMC_BWTR3_ADDSET_2c:macro@FSMC_BWTR3_ADDSET_3c:macro@FSMC_BWTR3_ADDHLDc:macro@FSMC_BWTR3_ADDHLD_0c:macro@FSMC_BWTR3_ADDHLD_1c:macro@FSMC_BWTR3_ADDHLD_2c:macro@FSMC_BWTR3_ADDHLD_3c:macro@FSMC_BWTR3_DATASTc:macro@FSMC_BWTR3_DATAST_0c:macro@FSMC_BWTR3_DATAST_1c:macro@FSMC_BWTR3_DATAST_2c:macro@FSMC_BWTR3_DATAST_3c:macro@FSMC_BWTR3_CLKDIVc:macro@FSMC_BWTR3_CLKDIV_0c:macro@FSMC_BWTR3_CLKDIV_1c:macro@FSMC_BWTR3_CLKDIV_2c:macro@FSMC_BWTR3_CLKDIV_3c:macro@FSMC_BWTR3_DATLATc:macro@FSMC_BWTR3_DATLAT_0c:macro@FSMC_BWTR3_DATLAT_1c:macro@FSMC_BWTR3_DATLAT_2c:macro@FSMC_BWTR3_DATLAT_3c:macro@FSMC_BWTR3_ACCMODc:macro@FSMC_BWTR3_ACCMOD_0c:macro@FSMC_BWTR3_ACCMOD_1c:macro@FSMC_BWTR4_ADDSETc:macro@FSMC_BWTR4_ADDSET_0c:macro@FSMC_BWTR4_ADDSET_1c:macro@FSMC_BWTR4_ADDSET_2c:macro@FSMC_BWTR4_ADDSET_3c:macro@FSMC_BWTR4_ADDHLDc:macro@FSMC_BWTR4_ADDHLD_0c:macro@FSMC_BWTR4_ADDHLD_1c:macro@FSMC_BWTR4_ADDHLD_2c:macro@FSMC_BWTR4_ADDHLD_3c:macro@FSMC_BWTR4_DATASTc:macro@FSMC_BWTR4_DATAST_0c:macro@FSMC_BWTR4_DATAST_1c:macro@FSMC_BWTR4_DATAST_2c:macro@FSMC_BWTR4_DATAST_3c:macro@FSMC_BWTR4_CLKDIVc:macro@FSMC_BWTR4_CLKDIV_0c:macro@FSMC_BWTR4_CLKDIV_1c:macro@FSMC_BWTR4_CLKDIV_2c:macro@FSMC_BWTR4_CLKDIV_3c:macro@FSMC_BWTR4_DATLATc:macro@FSMC_BWTR4_DATLAT_0c:macro@FSMC_BWTR4_DATLAT_1c:macro@FSMC_BWTR4_DATLAT_2c:macro@FSMC_BWTR4_DATLAT_3c:macro@FSMC_BWTR4_ACCMODc:macro@FSMC_BWTR4_ACCMOD_0c:macro@FSMC_BWTR4_ACCMOD_1c:macro@GPIO_MODER_MODER0c:macro@GPIO_MODER_MODER0_0c:macro@GPIO_MODER_MODER0_1c:macro@GPIO_MODER_MODER1c:macro@GPIO_MODER_MODER1_0c:macro@GPIO_MODER_MODER1_1c:macro@GPIO_MODER_MODER2c:macro@GPIO_MODER_MODER2_0c:macro@GPIO_MODER_MODER2_1c:macro@GPIO_MODER_MODER3c:macro@GPIO_MODER_MODER3_0c:macro@GPIO_MODER_MODER3_1c:macro@GPIO_MODER_MODER4c:macro@GPIO_MODER_MODER4_0c:macro@GPIO_MODER_MODER4_1c:macro@GPIO_MODER_MODER5c:macro@GPIO_MODER_MODER5_0c:macro@GPIO_MODER_MODER5_1c:macro@GPIO_MODER_MODER6c:macro@GPIO_MODER_MODER6_0c:macro@GPIO_MODER_MODER6_1c:macro@GPIO_MODER_MODER7c:macro@GPIO_MODER_MODER7_0c:macro@GPIO_MODER_MODER7_1c:macro@GPIO_MODER_MODER8c:macro@GPIO_MODER_MODER8_0c:macro@GPIO_MODER_MODER8_1c:macro@GPIO_MODER_MODER9c:macro@GPIO_MODER_MODER9_0c:macro@GPIO_MODER_MODER9_1c:macro@GPIO_MODER_MODER10c:macro@GPIO_MODER_MODER10_0c:macro@GPIO_MODER_MODER10_1c:macro@GPIO_MODER_MODER11c:macro@GPIO_MODER_MODER11_0c:macro@GPIO_MODER_MODER11_1c:macro@GPIO_MODER_MODER12c:macro@GPIO_MODER_MODER12_0c:macro@GPIO_MODER_MODER12_1c:macro@GPIO_MODER_MODER13c:macro@GPIO_MODER_MODER13_0c:macro@GPIO_MODER_MODER13_1c:macro@GPIO_MODER_MODER14c:macro@GPIO_MODER_MODER14_0c:macro@GPIO_MODER_MODER14_1c:macro@GPIO_MODER_MODER15c:macro@GPIO_MODER_MODER15_0c:macro@GPIO_MODER_MODER15_1c:macro@GPIO_OTYPER_OT_0c:macro@GPIO_OTYPER_OT_1c:macro@GPIO_OTYPER_OT_2c:macro@GPIO_OTYPER_OT_3c:macro@GPIO_OTYPER_OT_4c:macro@GPIO_OTYPER_OT_5c:macro@GPIO_OTYPER_OT_6c:macro@GPIO_OTYPER_OT_7c:macro@GPIO_OTYPER_OT_8c:macro@GPIO_OTYPER_OT_9c:macro@GPIO_OTYPER_OT_10c:macro@GPIO_OTYPER_OT_11c:macro@GPIO_OTYPER_OT_12c:macro@GPIO_OTYPER_OT_13c:macro@GPIO_OTYPER_OT_14c:macro@GPIO_OTYPER_OT_15c:macro@GPIO_OSPEEDER_OSPEEDR0c:macro@GPIO_OSPEEDER_OSPEEDR0_0c:macro@GPIO_OSPEEDER_OSPEEDR0_1c:macro@GPIO_OSPEEDER_OSPEEDR1c:macro@GPIO_OSPEEDER_OSPEEDR1_0c:macro@GPIO_OSPEEDER_OSPEEDR1_1c:macro@GPIO_OSPEEDER_OSPEEDR2c:macro@GPIO_OSPEEDER_OSPEEDR2_0c:macro@GPIO_OSPEEDER_OSPEEDR2_1c:macro@GPIO_OSPEEDER_OSPEEDR3c:macro@GPIO_OSPEEDER_OSPEEDR3_0c:macro@GPIO_OSPEEDER_OSPEEDR3_1c:macro@GPIO_OSPEEDER_OSPEEDR4c:macro@GPIO_OSPEEDER_OSPEEDR4_0c:macro@GPIO_OSPEEDER_OSPEEDR4_1c:macro@GPIO_OSPEEDER_OSPEEDR5c:macro@GPIO_OSPEEDER_OSPEEDR5_0c:macro@GPIO_OSPEEDER_OSPEEDR5_1c:macro@GPIO_OSPEEDER_OSPEEDR6c:macro@GPIO_OSPEEDER_OSPEEDR6_0c:macro@GPIO_OSPEEDER_OSPEEDR6_1c:macro@GPIO_OSPEEDER_OSPEEDR7c:macro@GPIO_OSPEEDER_OSPEEDR7_0c:macro@GPIO_OSPEEDER_OSPEEDR7_1c:macro@GPIO_OSPEEDER_OSPEEDR8c:macro@GPIO_OSPEEDER_OSPEEDR8_0c:macro@GPIO_OSPEEDER_OSPEEDR8_1c:macro@GPIO_OSPEEDER_OSPEEDR9c:macro@GPIO_OSPEEDER_OSPEEDR9_0c:macro@GPIO_OSPEEDER_OSPEEDR9_1c:macro@GPIO_OSPEEDER_OSPEEDR10c:macro@GPIO_OSPEEDER_OSPEEDR10_0c:macro@GPIO_OSPEEDER_OSPEEDR10_1c:macro@GPIO_OSPEEDER_OSPEEDR11c:macro@GPIO_OSPEEDER_OSPEEDR11_0c:macro@GPIO_OSPEEDER_OSPEEDR11_1c:macro@GPIO_OSPEEDER_OSPEEDR12c:macro@GPIO_OSPEEDER_OSPEEDR12_0c:macro@GPIO_OSPEEDER_OSPEEDR12_1c:macro@GPIO_OSPEEDER_OSPEEDR13c:macro@GPIO_OSPEEDER_OSPEEDR13_0c:macro@GPIO_OSPEEDER_OSPEEDR13_1c:macro@GPIO_OSPEEDER_OSPEEDR14c:macro@GPIO_OSPEEDER_OSPEEDR14_0c:macro@GPIO_OSPEEDER_OSPEEDR14_1c:macro@GPIO_OSPEEDER_OSPEEDR15c:macro@GPIO_OSPEEDER_OSPEEDR15_0c:macro@GPIO_OSPEEDER_OSPEEDR15_1c:macro@GPIO_PUPDR_PUPDR0c:macro@GPIO_PUPDR_PUPDR0_0c:macro@GPIO_PUPDR_PUPDR0_1c:macro@GPIO_PUPDR_PUPDR1c:macro@GPIO_PUPDR_PUPDR1_0c:macro@GPIO_PUPDR_PUPDR1_1c:macro@GPIO_PUPDR_PUPDR2c:macro@GPIO_PUPDR_PUPDR2_0c:macro@GPIO_PUPDR_PUPDR2_1c:macro@GPIO_PUPDR_PUPDR3c:macro@GPIO_PUPDR_PUPDR3_0c:macro@GPIO_PUPDR_PUPDR3_1c:macro@GPIO_PUPDR_PUPDR4c:macro@GPIO_PUPDR_PUPDR4_0c:macro@GPIO_PUPDR_PUPDR4_1c:macro@GPIO_PUPDR_PUPDR5c:macro@GPIO_PUPDR_PUPDR5_0c:macro@GPIO_PUPDR_PUPDR5_1c:macro@GPIO_PUPDR_PUPDR6c:macro@GPIO_PUPDR_PUPDR6_0c:macro@GPIO_PUPDR_PUPDR6_1c:macro@GPIO_PUPDR_PUPDR7c:macro@GPIO_PUPDR_PUPDR7_0c:macro@GPIO_PUPDR_PUPDR7_1c:macro@GPIO_PUPDR_PUPDR8c:macro@GPIO_PUPDR_PUPDR8_0c:macro@GPIO_PUPDR_PUPDR8_1c:macro@GPIO_PUPDR_PUPDR9c:macro@GPIO_PUPDR_PUPDR9_0c:macro@GPIO_PUPDR_PUPDR9_1c:macro@GPIO_PUPDR_PUPDR10c:macro@GPIO_PUPDR_PUPDR10_0c:macro@GPIO_PUPDR_PUPDR10_1c:macro@GPIO_PUPDR_PUPDR11c:macro@GPIO_PUPDR_PUPDR11_0c:macro@GPIO_PUPDR_PUPDR11_1c:macro@GPIO_PUPDR_PUPDR12c:macro@GPIO_PUPDR_PUPDR12_0c:macro@GPIO_PUPDR_PUPDR12_1c:macro@GPIO_PUPDR_PUPDR13c:macro@GPIO_PUPDR_PUPDR13_0c:macro@GPIO_PUPDR_PUPDR13_1c:macro@GPIO_PUPDR_PUPDR14c:macro@GPIO_PUPDR_PUPDR14_0c:macro@GPIO_PUPDR_PUPDR14_1c:macro@GPIO_PUPDR_PUPDR15c:macro@GPIO_PUPDR_PUPDR15_0c:macro@GPIO_PUPDR_PUPDR15_1c:macro@GPIO_IDR_IDR_0c:macro@GPIO_IDR_IDR_1c:macro@GPIO_IDR_IDR_2c:macro@GPIO_IDR_IDR_3c:macro@GPIO_IDR_IDR_4c:macro@GPIO_IDR_IDR_5c:macro@GPIO_IDR_IDR_6c:macro@GPIO_IDR_IDR_7c:macro@GPIO_IDR_IDR_8c:macro@GPIO_IDR_IDR_9c:macro@GPIO_IDR_IDR_10c:macro@GPIO_IDR_IDR_11c:macro@GPIO_IDR_IDR_12c:macro@GPIO_IDR_IDR_13c:macro@GPIO_IDR_IDR_14c:macro@GPIO_IDR_IDR_15c:macro@GPIO_OTYPER_IDR_0c:macro@GPIO_OTYPER_IDR_1c:macro@GPIO_OTYPER_IDR_2c:macro@GPIO_OTYPER_IDR_3c:macro@GPIO_OTYPER_IDR_4c:macro@GPIO_OTYPER_IDR_5c:macro@GPIO_OTYPER_IDR_6c:macro@GPIO_OTYPER_IDR_7c:macro@GPIO_OTYPER_IDR_8c:macro@GPIO_OTYPER_IDR_9c:macro@GPIO_OTYPER_IDR_10c:macro@GPIO_OTYPER_IDR_11c:macro@GPIO_OTYPER_IDR_12c:macro@GPIO_OTYPER_IDR_13c:macro@GPIO_OTYPER_IDR_14c:macro@GPIO_OTYPER_IDR_15c:macro@GPIO_ODR_ODR_0c:macro@GPIO_ODR_ODR_1c:macro@GPIO_ODR_ODR_2c:macro@GPIO_ODR_ODR_3c:macro@GPIO_ODR_ODR_4c:macro@GPIO_ODR_ODR_5c:macro@GPIO_ODR_ODR_6c:macro@GPIO_ODR_ODR_7c:macro@GPIO_ODR_ODR_8c:macro@GPIO_ODR_ODR_9c:macro@GPIO_ODR_ODR_10c:macro@GPIO_ODR_ODR_11c:macro@GPIO_ODR_ODR_12c:macro@GPIO_ODR_ODR_13c:macro@GPIO_ODR_ODR_14c:macro@GPIO_ODR_ODR_15c:macro@GPIO_OTYPER_ODR_0c:macro@GPIO_OTYPER_ODR_1c:macro@GPIO_OTYPER_ODR_2c:macro@GPIO_OTYPER_ODR_3c:macro@GPIO_OTYPER_ODR_4c:macro@GPIO_OTYPER_ODR_5c:macro@GPIO_OTYPER_ODR_6c:macro@GPIO_OTYPER_ODR_7c:macro@GPIO_OTYPER_ODR_8c:macro@GPIO_OTYPER_ODR_9c:macro@GPIO_OTYPER_ODR_10c:macro@GPIO_OTYPER_ODR_11c:macro@GPIO_OTYPER_ODR_12c:macro@GPIO_OTYPER_ODR_13c:macro@GPIO_OTYPER_ODR_14c:macro@GPIO_OTYPER_ODR_15c:macro@GPIO_BSRR_BS_0c:macro@GPIO_BSRR_BS_1c:macro@GPIO_BSRR_BS_2c:macro@GPIO_BSRR_BS_3c:macro@GPIO_BSRR_BS_4c:macro@GPIO_BSRR_BS_5c:macro@GPIO_BSRR_BS_6c:macro@GPIO_BSRR_BS_7c:macro@GPIO_BSRR_BS_8c:macro@GPIO_BSRR_BS_9c:macro@GPIO_BSRR_BS_10c:macro@GPIO_BSRR_BS_11c:macro@GPIO_BSRR_BS_12c:macro@GPIO_BSRR_BS_13c:macro@GPIO_BSRR_BS_14c:macro@GPIO_BSRR_BS_15c:macro@GPIO_BSRR_BR_0c:macro@GPIO_BSRR_BR_1c:macro@GPIO_BSRR_BR_2c:macro@GPIO_BSRR_BR_3c:macro@GPIO_BSRR_BR_4c:macro@GPIO_BSRR_BR_5c:macro@GPIO_BSRR_BR_6c:macro@GPIO_BSRR_BR_7c:macro@GPIO_BSRR_BR_8c:macro@GPIO_BSRR_BR_9c:macro@GPIO_BSRR_BR_10c:macro@GPIO_BSRR_BR_11c:macro@GPIO_BSRR_BR_12c:macro@GPIO_BSRR_BR_13c:macro@GPIO_BSRR_BR_14c:macro@GPIO_BSRR_BR_15c:macro@GPIO_LCKR_LCK0c:macro@GPIO_LCKR_LCK1c:macro@GPIO_LCKR_LCK2c:macro@GPIO_LCKR_LCK3c:macro@GPIO_LCKR_LCK4c:macro@GPIO_LCKR_LCK5c:macro@GPIO_LCKR_LCK6c:macro@GPIO_LCKR_LCK7c:macro@GPIO_LCKR_LCK8c:macro@GPIO_LCKR_LCK9c:macro@GPIO_LCKR_LCK10c:macro@GPIO_LCKR_LCK11c:macro@GPIO_LCKR_LCK12c:macro@GPIO_LCKR_LCK13c:macro@GPIO_LCKR_LCK14c:macro@GPIO_LCKR_LCK15c:macro@GPIO_LCKR_LCKKc:macro@GPIO_AFRL_AFRL0c:macro@GPIO_AFRL_AFRL1c:macro@GPIO_AFRL_AFRL2c:macro@GPIO_AFRL_AFRL3c:macro@GPIO_AFRL_AFRL4c:macro@GPIO_AFRL_AFRL5c:macro@GPIO_AFRL_AFRL6c:macro@GPIO_AFRL_AFRL7c:macro@GPIO_AFRH_AFRH8c:macro@GPIO_AFRH_AFRH9c:macro@GPIO_AFRH_AFRH10c:macro@GPIO_AFRH_AFRH11c:macro@GPIO_AFRH_AFRH12c:macro@GPIO_AFRH_AFRH13c:macro@GPIO_AFRH_AFRH14c:macro@GPIO_AFRH_AFRH15c:macro@I2C_CR1_PEc:macro@I2C_CR1_SMBUSc:macro@I2C_CR1_SMBTYPEc:macro@I2C_CR1_ENARPc:macro@I2C_CR1_ENPECc:macro@I2C_CR1_ENGCc:macro@I2C_CR1_NOSTRETCHc:macro@I2C_CR1_STARTc:macro@I2C_CR1_STOPc:macro@I2C_CR1_ACKc:macro@I2C_CR1_POSc:macro@I2C_CR1_PECc:macro@I2C_CR1_ALERTc:macro@I2C_CR1_SWRSTc:macro@I2C_CR2_FREQc:macro@I2C_CR2_FREQ_0c:macro@I2C_CR2_FREQ_1c:macro@I2C_CR2_FREQ_2c:macro@I2C_CR2_FREQ_3c:macro@I2C_CR2_FREQ_4c:macro@I2C_CR2_FREQ_5c:macro@I2C_CR2_ITERRENc:macro@I2C_CR2_ITEVTENc:macro@I2C_CR2_ITBUFENc:macro@I2C_CR2_DMAENc:macro@I2C_CR2_LASTc:macro@I2C_OAR1_ADD1_7c:macro@I2C_OAR1_ADD8_9c:macro@I2C_OAR1_ADD0c:macro@I2C_OAR1_ADD1c:macro@I2C_OAR1_ADD2c:macro@I2C_OAR1_ADD3c:macro@I2C_OAR1_ADD4c:macro@I2C_OAR1_ADD5c:macro@I2C_OAR1_ADD6c:macro@I2C_OAR1_ADD7c:macro@I2C_OAR1_ADD8c:macro@I2C_OAR1_ADD9c:macro@I2C_OAR1_ADDMODEc:macro@I2C_OAR2_ENDUALc:macro@I2C_OAR2_ADD2c:macro@I2C_DR_DRc:macro@I2C_SR1_SBc:macro@I2C_SR1_ADDRc:macro@I2C_SR1_BTFc:macro@I2C_SR1_ADD10c:macro@I2C_SR1_STOPFc:macro@I2C_SR1_RXNEc:macro@I2C_SR1_TXEc:macro@I2C_SR1_BERRc:macro@I2C_SR1_ARLOc:macro@I2C_SR1_AFc:macro@I2C_SR1_OVRc:macro@I2C_SR1_PECERRc:macro@I2C_SR1_TIMEOUTc:macro@I2C_SR1_SMBALERTc:macro@I2C_SR2_MSLc:macro@I2C_SR2_BUSYc:macro@I2C_SR2_TRAc:macro@I2C_SR2_GENCALLc:macro@I2C_SR2_SMBDEFAULTc:macro@I2C_SR2_SMBHOSTc:macro@I2C_SR2_DUALFc:macro@I2C_SR2_PECc:macro@I2C_CCR_CCRc:macro@I2C_CCR_DUTYc:macro@I2C_CCR_FSc:macro@I2C_TRISE_TRISEc:macro@IWDG_KR_KEYc:macro@IWDG_PR_PRc:macro@IWDG_PR_PR_0c:macro@IWDG_PR_PR_1c:macro@IWDG_PR_PR_2c:macro@IWDG_RLR_RLc:macro@IWDG_SR_PVUc:macro@IWDG_SR_RVUc:macro@LCD_CR_LCDENc:macro@LCD_CR_VSELc:macro@LCD_CR_DUTYc:macro@LCD_CR_DUTY_0c:macro@LCD_CR_DUTY_1c:macro@LCD_CR_DUTY_2c:macro@LCD_CR_BIASc:macro@LCD_CR_BIAS_0c:macro@LCD_CR_BIAS_1c:macro@LCD_CR_MUX_SEGc:macro@LCD_FCR_HDc:macro@LCD_FCR_SOFIEc:macro@LCD_FCR_UDDIEc:macro@LCD_FCR_PONc:macro@LCD_FCR_PON_0c:macro@LCD_FCR_PON_1c:macro@LCD_FCR_PON_2c:macro@LCD_FCR_DEADc:macro@LCD_FCR_DEAD_0c:macro@LCD_FCR_DEAD_1c:macro@LCD_FCR_DEAD_2c:macro@LCD_FCR_CCc:macro@LCD_FCR_CC_0c:macro@LCD_FCR_CC_1c:macro@LCD_FCR_CC_2c:macro@LCD_FCR_BLINKFc:macro@LCD_FCR_BLINKF_0c:macro@LCD_FCR_BLINKF_1c:macro@LCD_FCR_BLINKF_2c:macro@LCD_FCR_BLINKc:macro@LCD_FCR_BLINK_0c:macro@LCD_FCR_BLINK_1c:macro@LCD_FCR_DIVc:macro@LCD_FCR_PSc:macro@LCD_SR_ENSc:macro@LCD_SR_SOFc:macro@LCD_SR_UDRc:macro@LCD_SR_UDDc:macro@LCD_SR_RDYc:macro@LCD_SR_FCRSRc:macro@LCD_CLR_SOFCc:macro@LCD_CLR_UDDCc:macro@LCD_RAM_SEGMENT_DATAc:macro@PWR_CR_LPSDSRc:macro@PWR_CR_PDDSc:macro@PWR_CR_CWUFc:macro@PWR_CR_CSBFc:macro@PWR_CR_PVDEc:macro@PWR_CR_PLSc:macro@PWR_CR_PLS_0c:macro@PWR_CR_PLS_1c:macro@PWR_CR_PLS_2c:macro@PWR_CR_PLS_LEV0c:macro@PWR_CR_PLS_LEV1c:macro@PWR_CR_PLS_LEV2c:macro@PWR_CR_PLS_LEV3c:macro@PWR_CR_PLS_LEV4c:macro@PWR_CR_PLS_LEV5c:macro@PWR_CR_PLS_LEV6c:macro@PWR_CR_PLS_LEV7c:macro@PWR_CR_DBPc:macro@PWR_CR_ULPc:macro@PWR_CR_FWUc:macro@PWR_CR_VOSc:macro@PWR_CR_VOS_0c:macro@PWR_CR_VOS_1c:macro@PWR_CR_LPRUNc:macro@PWR_CSR_WUFc:macro@PWR_CSR_SBFc:macro@PWR_CSR_PVDOc:macro@PWR_CSR_VREFINTRDYFc:macro@PWR_CSR_VOSFc:macro@PWR_CSR_REGLPFc:macro@PWR_CSR_EWUP1c:macro@PWR_CSR_EWUP2c:macro@PWR_CSR_EWUP3c:macro@RCC_CR_HSIONc:macro@RCC_CR_HSIRDYc:macro@RCC_CR_MSIONc:macro@RCC_CR_MSIRDYc:macro@RCC_CR_HSEONc:macro@RCC_CR_HSERDYc:macro@RCC_CR_HSEBYPc:macro@RCC_CR_PLLONc:macro@RCC_CR_PLLRDYc:macro@RCC_CR_CSSONc:macro@RCC_CR_RTCPREc:macro@RCC_CR_RTCPRE_0c:macro@RCC_CR_RTCPRE_1c:macro@RCC_ICSCR_HSICALc:macro@RCC_ICSCR_HSITRIMc:macro@RCC_ICSCR_MSIRANGEc:macro@RCC_ICSCR_MSIRANGE_0c:macro@RCC_ICSCR_MSIRANGE_1c:macro@RCC_ICSCR_MSIRANGE_2c:macro@RCC_ICSCR_MSIRANGE_3c:macro@RCC_ICSCR_MSIRANGE_4c:macro@RCC_ICSCR_MSIRANGE_5c:macro@RCC_ICSCR_MSIRANGE_6c:macro@RCC_ICSCR_MSICALc:macro@RCC_ICSCR_MSITRIMc:macro@RCC_CFGR_SWc:macro@RCC_CFGR_SW_0c:macro@RCC_CFGR_SW_1c:macro@RCC_CFGR_SW_MSIc:macro@RCC_CFGR_SW_HSIc:macro@RCC_CFGR_SW_HSEc:macro@RCC_CFGR_SW_PLLc:macro@RCC_CFGR_SWSc:macro@RCC_CFGR_SWS_0c:macro@RCC_CFGR_SWS_1c:macro@RCC_CFGR_SWS_MSIc:macro@RCC_CFGR_SWS_HSIc:macro@RCC_CFGR_SWS_HSEc:macro@RCC_CFGR_SWS_PLLc:macro@RCC_CFGR_HPREc:macro@RCC_CFGR_HPRE_0c:macro@RCC_CFGR_HPRE_1c:macro@RCC_CFGR_HPRE_2c:macro@RCC_CFGR_HPRE_3c:macro@RCC_CFGR_HPRE_DIV1c:macro@RCC_CFGR_HPRE_DIV2c:macro@RCC_CFGR_HPRE_DIV4c:macro@RCC_CFGR_HPRE_DIV8c:macro@RCC_CFGR_HPRE_DIV16c:macro@RCC_CFGR_HPRE_DIV64c:macro@RCC_CFGR_HPRE_DIV128c:macro@RCC_CFGR_HPRE_DIV256c:macro@RCC_CFGR_HPRE_DIV512c:macro@RCC_CFGR_PPRE1c:macro@RCC_CFGR_PPRE1_0c:macro@RCC_CFGR_PPRE1_1c:macro@RCC_CFGR_PPRE1_2c:macro@RCC_CFGR_PPRE1_DIV1c:macro@RCC_CFGR_PPRE1_DIV2c:macro@RCC_CFGR_PPRE1_DIV4c:macro@RCC_CFGR_PPRE1_DIV8c:macro@RCC_CFGR_PPRE1_DIV16c:macro@RCC_CFGR_PPRE2c:macro@RCC_CFGR_PPRE2_0c:macro@RCC_CFGR_PPRE2_1c:macro@RCC_CFGR_PPRE2_2c:macro@RCC_CFGR_PPRE2_DIV1c:macro@RCC_CFGR_PPRE2_DIV2c:macro@RCC_CFGR_PPRE2_DIV4c:macro@RCC_CFGR_PPRE2_DIV8c:macro@RCC_CFGR_PPRE2_DIV16c:macro@RCC_CFGR_PLLSRCc:macro@RCC_CFGR_PLLSRC_HSIc:macro@RCC_CFGR_PLLSRC_HSEc:macro@RCC_CFGR_PLLMULc:macro@RCC_CFGR_PLLMUL_0c:macro@RCC_CFGR_PLLMUL_1c:macro@RCC_CFGR_PLLMUL_2c:macro@RCC_CFGR_PLLMUL_3c:macro@RCC_CFGR_PLLMUL3c:macro@RCC_CFGR_PLLMUL4c:macro@RCC_CFGR_PLLMUL6c:macro@RCC_CFGR_PLLMUL8c:macro@RCC_CFGR_PLLMUL12c:macro@RCC_CFGR_PLLMUL16c:macro@RCC_CFGR_PLLMUL24c:macro@RCC_CFGR_PLLMUL32c:macro@RCC_CFGR_PLLMUL48c:macro@RCC_CFGR_PLLDIVc:macro@RCC_CFGR_PLLDIV_0c:macro@RCC_CFGR_PLLDIV_1c:macro@RCC_CFGR_PLLDIV1c:macro@RCC_CFGR_PLLDIV2c:macro@RCC_CFGR_PLLDIV3c:macro@RCC_CFGR_PLLDIV4c:macro@RCC_CFGR_MCOSELc:macro@RCC_CFGR_MCOSEL_0c:macro@RCC_CFGR_MCOSEL_1c:macro@RCC_CFGR_MCOSEL_2c:macro@RCC_CFGR_MCO_NOCLOCKc:macro@RCC_CFGR_MCO_SYSCLKc:macro@RCC_CFGR_MCO_HSIc:macro@RCC_CFGR_MCO_MSIc:macro@RCC_CFGR_MCO_HSEc:macro@RCC_CFGR_MCO_PLLc:macro@RCC_CFGR_MCO_LSIc:macro@RCC_CFGR_MCO_LSEc:macro@RCC_CFGR_MCOPREc:macro@RCC_CFGR_MCOPRE_0c:macro@RCC_CFGR_MCOPRE_1c:macro@RCC_CFGR_MCOPRE_2c:macro@RCC_CFGR_MCO_DIV1c:macro@RCC_CFGR_MCO_DIV2c:macro@RCC_CFGR_MCO_DIV4c:macro@RCC_CFGR_MCO_DIV8c:macro@RCC_CFGR_MCO_DIV16c:macro@RCC_CIR_LSIRDYFc:macro@RCC_CIR_LSERDYFc:macro@RCC_CIR_HSIRDYFc:macro@RCC_CIR_HSERDYFc:macro@RCC_CIR_PLLRDYFc:macro@RCC_CIR_MSIRDYFc:macro@RCC_CIR_LSECSSc:macro@RCC_CIR_CSSFc:macro@RCC_CIR_LSIRDYIEc:macro@RCC_CIR_LSERDYIEc:macro@RCC_CIR_HSIRDYIEc:macro@RCC_CIR_HSERDYIEc:macro@RCC_CIR_PLLRDYIEc:macro@RCC_CIR_MSIRDYIEc:macro@RCC_CIR_LSECSSIEc:macro@RCC_CIR_LSIRDYCc:macro@RCC_CIR_LSERDYCc:macro@RCC_CIR_HSIRDYCc:macro@RCC_CIR_HSERDYCc:macro@RCC_CIR_PLLRDYCc:macro@RCC_CIR_MSIRDYCc:macro@RCC_CIR_LSECSSCc:macro@RCC_CIR_CSSCc:macro@RCC_AHBRSTR_GPIOARSTc:macro@RCC_AHBRSTR_GPIOBRSTc:macro@RCC_AHBRSTR_GPIOCRSTc:macro@RCC_AHBRSTR_GPIODRSTc:macro@RCC_AHBRSTR_GPIOERSTc:macro@RCC_AHBRSTR_GPIOHRSTc:macro@RCC_AHBRSTR_GPIOFRSTc:macro@RCC_AHBRSTR_GPIOGRSTc:macro@RCC_AHBRSTR_CRCRSTc:macro@RCC_AHBRSTR_FLITFRSTc:macro@RCC_AHBRSTR_DMA1RSTc:macro@RCC_AHBRSTR_DMA2RSTc:macro@RCC_AHBRSTR_AESRSTc:macro@RCC_AHBRSTR_FSMCRSTc:macro@RCC_APB2RSTR_SYSCFGRSTc:macro@RCC_APB2RSTR_TIM9RSTc:macro@RCC_APB2RSTR_TIM10RSTc:macro@RCC_APB2RSTR_TIM11RSTc:macro@RCC_APB2RSTR_ADC1RSTc:macro@RCC_APB2RSTR_SDIORSTc:macro@RCC_APB2RSTR_SPI1RSTc:macro@RCC_APB2RSTR_USART1RSTc:macro@RCC_APB1RSTR_TIM2RSTc:macro@RCC_APB1RSTR_TIM3RSTc:macro@RCC_APB1RSTR_TIM4RSTc:macro@RCC_APB1RSTR_TIM5RSTc:macro@RCC_APB1RSTR_TIM6RSTc:macro@RCC_APB1RSTR_TIM7RSTc:macro@RCC_APB1RSTR_LCDRSTc:macro@RCC_APB1RSTR_WWDGRSTc:macro@RCC_APB1RSTR_SPI2RSTc:macro@RCC_APB1RSTR_SPI3RSTc:macro@RCC_APB1RSTR_USART2RSTc:macro@RCC_APB1RSTR_USART3RSTc:macro@RCC_APB1RSTR_UART4RSTc:macro@RCC_APB1RSTR_UART5RSTc:macro@RCC_APB1RSTR_I2C1RSTc:macro@RCC_APB1RSTR_I2C2RSTc:macro@RCC_APB1RSTR_USBRSTc:macro@RCC_APB1RSTR_PWRRSTc:macro@RCC_APB1RSTR_DACRSTc:macro@RCC_APB1RSTR_COMPRSTc:macro@RCC_AHBENR_GPIOAENc:macro@RCC_AHBENR_GPIOBENc:macro@RCC_AHBENR_GPIOCENc:macro@RCC_AHBENR_GPIODENc:macro@RCC_AHBENR_GPIOEENc:macro@RCC_AHBENR_GPIOHENc:macro@RCC_AHBENR_GPIOFENc:macro@RCC_AHBENR_GPIOGENc:macro@RCC_AHBENR_CRCENc:macro@RCC_AHBENR_FLITFENc:macro@RCC_AHBENR_DMA1ENc:macro@RCC_AHBENR_DMA2ENc:macro@RCC_AHBENR_AESENc:macro@RCC_AHBENR_FSMCENc:macro@RCC_APB2ENR_SYSCFGENc:macro@RCC_APB2ENR_TIM9ENc:macro@RCC_APB2ENR_TIM10ENc:macro@RCC_APB2ENR_TIM11ENc:macro@RCC_APB2ENR_ADC1ENc:macro@RCC_APB2ENR_SDIOENc:macro@RCC_APB2ENR_SPI1ENc:macro@RCC_APB2ENR_USART1ENc:macro@RCC_APB1ENR_TIM2ENc:macro@RCC_APB1ENR_TIM3ENc:macro@RCC_APB1ENR_TIM4ENc:macro@RCC_APB1ENR_TIM5ENc:macro@RCC_APB1ENR_TIM6ENc:macro@RCC_APB1ENR_TIM7ENc:macro@RCC_APB1ENR_LCDENc:macro@RCC_APB1ENR_WWDGENc:macro@RCC_APB1ENR_SPI2ENc:macro@RCC_APB1ENR_SPI3ENc:macro@RCC_APB1ENR_USART2ENc:macro@RCC_APB1ENR_USART3ENc:macro@RCC_APB1ENR_UART4ENc:macro@RCC_APB1ENR_UART5ENc:macro@RCC_APB1ENR_I2C1ENc:macro@RCC_APB1ENR_I2C2ENc:macro@RCC_APB1ENR_USBENc:macro@RCC_APB1ENR_PWRENc:macro@RCC_APB1ENR_DACENc:macro@RCC_APB1ENR_COMPENc:macro@RCC_AHBLPENR_GPIOALPENc:macro@RCC_AHBLPENR_GPIOBLPENc:macro@RCC_AHBLPENR_GPIOCLPENc:macro@RCC_AHBLPENR_GPIODLPENc:macro@RCC_AHBLPENR_GPIOELPENc:macro@RCC_AHBLPENR_GPIOHLPENc:macro@RCC_AHBLPENR_GPIOFLPENc:macro@RCC_AHBLPENR_GPIOGLPENc:macro@RCC_AHBLPENR_CRCLPENc:macro@RCC_AHBLPENR_FLITFLPENc:macro@RCC_AHBLPENR_SRAMLPENc:macro@RCC_AHBLPENR_DMA1LPENc:macro@RCC_AHBLPENR_DMA2LPENc:macro@RCC_AHBLPENR_AESLPENc:macro@RCC_AHBLPENR_FSMCLPENc:macro@RCC_APB2LPENR_SYSCFGLPENc:macro@RCC_APB2LPENR_TIM9LPENc:macro@RCC_APB2LPENR_TIM10LPENc:macro@RCC_APB2LPENR_TIM11LPENc:macro@RCC_APB2LPENR_ADC1LPENc:macro@RCC_APB2LPENR_SDIOLPENc:macro@RCC_APB2LPENR_SPI1LPENc:macro@RCC_APB2LPENR_USART1LPENc:macro@RCC_APB1LPENR_TIM2LPENc:macro@RCC_APB1LPENR_TIM3LPENc:macro@RCC_APB1LPENR_TIM4LPENc:macro@RCC_APB1LPENR_TIM5LPENc:macro@RCC_APB1LPENR_TIM6LPENc:macro@RCC_APB1LPENR_TIM7LPENc:macro@RCC_APB1LPENR_LCDLPENc:macro@RCC_APB1LPENR_WWDGLPENc:macro@RCC_APB1LPENR_SPI2LPENc:macro@RCC_APB1LPENR_SPI3LPENc:macro@RCC_APB1LPENR_USART2LPENc:macro@RCC_APB1LPENR_USART3LPENc:macro@RCC_APB1LPENR_UART4LPENc:macro@RCC_APB1LPENR_UART5LPENc:macro@RCC_APB1LPENR_I2C1LPENc:macro@RCC_APB1LPENR_I2C2LPENc:macro@RCC_APB1LPENR_USBLPENc:macro@RCC_APB1LPENR_PWRLPENc:macro@RCC_APB1LPENR_DACLPENc:macro@RCC_APB1LPENR_COMPLPENc:macro@RCC_CSR_LSIONc:macro@RCC_CSR_LSIRDYc:macro@RCC_CSR_LSEONc:macro@RCC_CSR_LSERDYc:macro@RCC_CSR_LSEBYPc:macro@RCC_CSR_LSECSSONc:macro@RCC_CSR_LSECSSDc:macro@RCC_CSR_RTCSELc:macro@RCC_CSR_RTCSEL_0c:macro@RCC_CSR_RTCSEL_1c:macro@RCC_CSR_RTCSEL_NOCLOCKc:macro@RCC_CSR_RTCSEL_LSEc:macro@RCC_CSR_RTCSEL_LSIc:macro@RCC_CSR_RTCSEL_HSEc:macro@RCC_CSR_RTCENc:macro@RCC_CSR_RTCRSTc:macro@RCC_CSR_RMVFc:macro@RCC_CSR_OBLRSTFc:macro@RCC_CSR_PINRSTFc:macro@RCC_CSR_PORRSTFc:macro@RCC_CSR_SFTRSTFc:macro@RCC_CSR_IWDGRSTFc:macro@RCC_CSR_WWDGRSTFc:macro@RCC_CSR_LPWRRSTFc:macro@RTC_TR_PMc:macro@RTC_TR_HTc:macro@RTC_TR_HT_0c:macro@RTC_TR_HT_1c:macro@RTC_TR_HUc:macro@RTC_TR_HU_0c:macro@RTC_TR_HU_1c:macro@RTC_TR_HU_2c:macro@RTC_TR_HU_3c:macro@RTC_TR_MNTc:macro@RTC_TR_MNT_0c:macro@RTC_TR_MNT_1c:macro@RTC_TR_MNT_2c:macro@RTC_TR_MNUc:macro@RTC_TR_MNU_0c:macro@RTC_TR_MNU_1c:macro@RTC_TR_MNU_2c:macro@RTC_TR_MNU_3c:macro@RTC_TR_STc:macro@RTC_TR_ST_0c:macro@RTC_TR_ST_1c:macro@RTC_TR_ST_2c:macro@RTC_TR_SUc:macro@RTC_TR_SU_0c:macro@RTC_TR_SU_1c:macro@RTC_TR_SU_2c:macro@RTC_TR_SU_3c:macro@RTC_DR_YTc:macro@RTC_DR_YT_0c:macro@RTC_DR_YT_1c:macro@RTC_DR_YT_2c:macro@RTC_DR_YT_3c:macro@RTC_DR_YUc:macro@RTC_DR_YU_0c:macro@RTC_DR_YU_1c:macro@RTC_DR_YU_2c:macro@RTC_DR_YU_3c:macro@RTC_DR_WDUc:macro@RTC_DR_WDU_0c:macro@RTC_DR_WDU_1c:macro@RTC_DR_WDU_2c:macro@RTC_DR_MTc:macro@RTC_DR_MUc:macro@RTC_DR_MU_0c:macro@RTC_DR_MU_1c:macro@RTC_DR_MU_2c:macro@RTC_DR_MU_3c:macro@RTC_DR_DTc:macro@RTC_DR_DT_0c:macro@RTC_DR_DT_1c:macro@RTC_DR_DUc:macro@RTC_DR_DU_0c:macro@RTC_DR_DU_1c:macro@RTC_DR_DU_2c:macro@RTC_DR_DU_3c:macro@RTC_CR_COEc:macro@RTC_CR_OSELc:macro@RTC_CR_OSEL_0c:macro@RTC_CR_OSEL_1c:macro@RTC_CR_POLc:macro@RTC_CR_COSELc:macro@RTC_CR_BCKc:macro@RTC_CR_SUB1Hc:macro@RTC_CR_ADD1Hc:macro@RTC_CR_TSIEc:macro@RTC_CR_WUTIEc:macro@RTC_CR_ALRBIEc:macro@RTC_CR_ALRAIEc:macro@RTC_CR_TSEc:macro@RTC_CR_WUTEc:macro@RTC_CR_ALRBEc:macro@RTC_CR_ALRAEc:macro@RTC_CR_DCEc:macro@RTC_CR_FMTc:macro@RTC_CR_BYPSHADc:macro@RTC_CR_REFCKONc:macro@RTC_CR_TSEDGEc:macro@RTC_CR_WUCKSELc:macro@RTC_CR_WUCKSEL_0c:macro@RTC_CR_WUCKSEL_1c:macro@RTC_CR_WUCKSEL_2c:macro@RTC_ISR_RECALPFc:macro@RTC_ISR_TAMP3Fc:macro@RTC_ISR_TAMP2Fc:macro@RTC_ISR_TAMP1Fc:macro@RTC_ISR_TSOVFc:macro@RTC_ISR_TSFc:macro@RTC_ISR_WUTFc:macro@RTC_ISR_ALRBFc:macro@RTC_ISR_ALRAFc:macro@RTC_ISR_INITc:macro@RTC_ISR_INITFc:macro@RTC_ISR_RSFc:macro@RTC_ISR_INITSc:macro@RTC_ISR_SHPFc:macro@RTC_ISR_WUTWFc:macro@RTC_ISR_ALRBWFc:macro@RTC_ISR_ALRAWFc:macro@RTC_PRER_PREDIV_Ac:macro@RTC_PRER_PREDIV_Sc:macro@RTC_WUTR_WUTc:macro@RTC_CALIBR_DCSc:macro@RTC_CALIBR_DCc:macro@RTC_ALRMAR_MSK4c:macro@RTC_ALRMAR_WDSELc:macro@RTC_ALRMAR_DTc:macro@RTC_ALRMAR_DT_0c:macro@RTC_ALRMAR_DT_1c:macro@RTC_ALRMAR_DUc:macro@RTC_ALRMAR_DU_0c:macro@RTC_ALRMAR_DU_1c:macro@RTC_ALRMAR_DU_2c:macro@RTC_ALRMAR_DU_3c:macro@RTC_ALRMAR_MSK3c:macro@RTC_ALRMAR_PMc:macro@RTC_ALRMAR_HTc:macro@RTC_ALRMAR_HT_0c:macro@RTC_ALRMAR_HT_1c:macro@RTC_ALRMAR_HUc:macro@RTC_ALRMAR_HU_0c:macro@RTC_ALRMAR_HU_1c:macro@RTC_ALRMAR_HU_2c:macro@RTC_ALRMAR_HU_3c:macro@RTC_ALRMAR_MSK2c:macro@RTC_ALRMAR_MNTc:macro@RTC_ALRMAR_MNT_0c:macro@RTC_ALRMAR_MNT_1c:macro@RTC_ALRMAR_MNT_2c:macro@RTC_ALRMAR_MNUc:macro@RTC_ALRMAR_MNU_0c:macro@RTC_ALRMAR_MNU_1c:macro@RTC_ALRMAR_MNU_2c:macro@RTC_ALRMAR_MNU_3c:macro@RTC_ALRMAR_MSK1c:macro@RTC_ALRMAR_STc:macro@RTC_ALRMAR_ST_0c:macro@RTC_ALRMAR_ST_1c:macro@RTC_ALRMAR_ST_2c:macro@RTC_ALRMAR_SUc:macro@RTC_ALRMAR_SU_0c:macro@RTC_ALRMAR_SU_1c:macro@RTC_ALRMAR_SU_2c:macro@RTC_ALRMAR_SU_3c:macro@RTC_ALRMBR_MSK4c:macro@RTC_ALRMBR_WDSELc:macro@RTC_ALRMBR_DTc:macro@RTC_ALRMBR_DT_0c:macro@RTC_ALRMBR_DT_1c:macro@RTC_ALRMBR_DUc:macro@RTC_ALRMBR_DU_0c:macro@RTC_ALRMBR_DU_1c:macro@RTC_ALRMBR_DU_2c:macro@RTC_ALRMBR_DU_3c:macro@RTC_ALRMBR_MSK3c:macro@RTC_ALRMBR_PMc:macro@RTC_ALRMBR_HTc:macro@RTC_ALRMBR_HT_0c:macro@RTC_ALRMBR_HT_1c:macro@RTC_ALRMBR_HUc:macro@RTC_ALRMBR_HU_0c:macro@RTC_ALRMBR_HU_1c:macro@RTC_ALRMBR_HU_2c:macro@RTC_ALRMBR_HU_3c:macro@RTC_ALRMBR_MSK2c:macro@RTC_ALRMBR_MNTc:macro@RTC_ALRMBR_MNT_0c:macro@RTC_ALRMBR_MNT_1c:macro@RTC_ALRMBR_MNT_2c:macro@RTC_ALRMBR_MNUc:macro@RTC_ALRMBR_MNU_0c:macro@RTC_ALRMBR_MNU_1c:macro@RTC_ALRMBR_MNU_2c:macro@RTC_ALRMBR_MNU_3c:macro@RTC_ALRMBR_MSK1c:macro@RTC_ALRMBR_STc:macro@RTC_ALRMBR_ST_0c:macro@RTC_ALRMBR_ST_1c:macro@RTC_ALRMBR_ST_2c:macro@RTC_ALRMBR_SUc:macro@RTC_ALRMBR_SU_0c:macro@RTC_ALRMBR_SU_1c:macro@RTC_ALRMBR_SU_2c:macro@RTC_ALRMBR_SU_3c:macro@RTC_WPR_KEYc:macro@RTC_SSR_SSc:macro@RTC_SHIFTR_SUBFSc:macro@RTC_SHIFTR_ADD1Sc:macro@RTC_TSTR_PMc:macro@RTC_TSTR_HTc:macro@RTC_TSTR_HT_0c:macro@RTC_TSTR_HT_1c:macro@RTC_TSTR_HUc:macro@RTC_TSTR_HU_0c:macro@RTC_TSTR_HU_1c:macro@RTC_TSTR_HU_2c:macro@RTC_TSTR_HU_3c:macro@RTC_TSTR_MNTc:macro@RTC_TSTR_MNT_0c:macro@RTC_TSTR_MNT_1c:macro@RTC_TSTR_MNT_2c:macro@RTC_TSTR_MNUc:macro@RTC_TSTR_MNU_0c:macro@RTC_TSTR_MNU_1c:macro@RTC_TSTR_MNU_2c:macro@RTC_TSTR_MNU_3c:macro@RTC_TSTR_STc:macro@RTC_TSTR_ST_0c:macro@RTC_TSTR_ST_1c:macro@RTC_TSTR_ST_2c:macro@RTC_TSTR_SUc:macro@RTC_TSTR_SU_0c:macro@RTC_TSTR_SU_1c:macro@RTC_TSTR_SU_2c:macro@RTC_TSTR_SU_3c:macro@RTC_TSDR_WDUc:macro@RTC_TSDR_WDU_0c:macro@RTC_TSDR_WDU_1c:macro@RTC_TSDR_WDU_2c:macro@RTC_TSDR_MTc:macro@RTC_TSDR_MUc:macro@RTC_TSDR_MU_0c:macro@RTC_TSDR_MU_1c:macro@RTC_TSDR_MU_2c:macro@RTC_TSDR_MU_3c:macro@RTC_TSDR_DTc:macro@RTC_TSDR_DT_0c:macro@RTC_TSDR_DT_1c:macro@RTC_TSDR_DUc:macro@RTC_TSDR_DU_0c:macro@RTC_TSDR_DU_1c:macro@RTC_TSDR_DU_2c:macro@RTC_TSDR_DU_3c:macro@RTC_TSSSR_SSc:macro@RTC_CALR_CALPc:macro@RTC_CALR_CALW8c:macro@RTC_CALR_CALW16c:macro@RTC_CALR_CALMc:macro@RTC_CALR_CALM_0c:macro@RTC_CALR_CALM_1c:macro@RTC_CALR_CALM_2c:macro@RTC_CALR_CALM_3c:macro@RTC_CALR_CALM_4c:macro@RTC_CALR_CALM_5c:macro@RTC_CALR_CALM_6c:macro@RTC_CALR_CALM_7c:macro@RTC_CALR_CALM_8c:macro@RTC_TAFCR_ALARMOUTTYPEc:macro@RTC_TAFCR_TAMPPUDISc:macro@RTC_TAFCR_TAMPPRCHc:macro@RTC_TAFCR_TAMPPRCH_0c:macro@RTC_TAFCR_TAMPPRCH_1c:macro@RTC_TAFCR_TAMPFLTc:macro@RTC_TAFCR_TAMPFLT_0c:macro@RTC_TAFCR_TAMPFLT_1c:macro@RTC_TAFCR_TAMPFREQc:macro@RTC_TAFCR_TAMPFREQ_0c:macro@RTC_TAFCR_TAMPFREQ_1c:macro@RTC_TAFCR_TAMPFREQ_2c:macro@RTC_TAFCR_TAMPTSc:macro@RTC_TAFCR_TAMP3TRGc:macro@RTC_TAFCR_TAMP3Ec:macro@RTC_TAFCR_TAMP2TRGc:macro@RTC_TAFCR_TAMP2Ec:macro@RTC_TAFCR_TAMPIEc:macro@RTC_TAFCR_TAMP1TRGc:macro@RTC_TAFCR_TAMP1Ec:macro@RTC_ALRMASSR_MASKSSc:macro@RTC_ALRMASSR_MASKSS_0c:macro@RTC_ALRMASSR_MASKSS_1c:macro@RTC_ALRMASSR_MASKSS_2c:macro@RTC_ALRMASSR_MASKSS_3c:macro@RTC_ALRMASSR_SSc:macro@RTC_ALRMBSSR_MASKSSc:macro@RTC_ALRMBSSR_MASKSS_0c:macro@RTC_ALRMBSSR_MASKSS_1c:macro@RTC_ALRMBSSR_MASKSS_2c:macro@RTC_ALRMBSSR_MASKSS_3c:macro@RTC_ALRMBSSR_SSc:macro@RTC_BKP0Rc:macro@RTC_BKP1Rc:macro@RTC_BKP2Rc:macro@RTC_BKP3Rc:macro@RTC_BKP4Rc:macro@RTC_BKP5Rc:macro@RTC_BKP6Rc:macro@RTC_BKP7Rc:macro@RTC_BKP8Rc:macro@RTC_BKP9Rc:macro@RTC_BKP10Rc:macro@RTC_BKP11Rc:macro@RTC_BKP12Rc:macro@RTC_BKP13Rc:macro@RTC_BKP14Rc:macro@RTC_BKP15Rc:macro@RTC_BKP16Rc:macro@RTC_BKP17Rc:macro@RTC_BKP18Rc:macro@RTC_BKP19Rc:macro@RTC_BKP20Rc:macro@RTC_BKP21Rc:macro@RTC_BKP22Rc:macro@RTC_BKP23Rc:macro@RTC_BKP24Rc:macro@RTC_BKP25Rc:macro@RTC_BKP26Rc:macro@RTC_BKP27Rc:macro@RTC_BKP28Rc:macro@RTC_BKP29Rc:macro@RTC_BKP30Rc:macro@RTC_BKP31Rc:macro@SDIO_POWER_PWRCTRLc:macro@SDIO_POWER_PWRCTRL_0c:macro@SDIO_POWER_PWRCTRL_1c:macro@SDIO_CLKCR_CLKDIVc:macro@SDIO_CLKCR_CLKENc:macro@SDIO_CLKCR_PWRSAVc:macro@SDIO_CLKCR_BYPASSc:macro@SDIO_CLKCR_WIDBUSc:macro@SDIO_CLKCR_WIDBUS_0c:macro@SDIO_CLKCR_WIDBUS_1c:macro@SDIO_CLKCR_NEGEDGEc:macro@SDIO_CLKCR_HWFC_ENc:macro@SDIO_ARG_CMDARGc:macro@SDIO_CMD_CMDINDEXc:macro@SDIO_CMD_WAITRESPc:macro@SDIO_CMD_WAITRESP_0c:macro@SDIO_CMD_WAITRESP_1c:macro@SDIO_CMD_WAITINTc:macro@SDIO_CMD_WAITPENDc:macro@SDIO_CMD_CPSMENc:macro@SDIO_CMD_SDIOSUSPENDc:macro@SDIO_CMD_ENCMDCOMPLc:macro@SDIO_CMD_NIENc:macro@SDIO_CMD_CEATACMDc:macro@SDIO_RESPCMD_RESPCMDc:macro@SDIO_RESP0_CARDSTATUS0c:macro@SDIO_RESP1_CARDSTATUS1c:macro@SDIO_RESP2_CARDSTATUS2c:macro@SDIO_RESP3_CARDSTATUS3c:macro@SDIO_RESP4_CARDSTATUS4c:macro@SDIO_DTIMER_DATATIMEc:macro@SDIO_DLEN_DATALENGTHc:macro@SDIO_DCTRL_DTENc:macro@SDIO_DCTRL_DTDIRc:macro@SDIO_DCTRL_DTMODEc:macro@SDIO_DCTRL_DMAENc:macro@SDIO_DCTRL_DBLOCKSIZEc:macro@SDIO_DCTRL_DBLOCKSIZE_0c:macro@SDIO_DCTRL_DBLOCKSIZE_1c:macro@SDIO_DCTRL_DBLOCKSIZE_2c:macro@SDIO_DCTRL_DBLOCKSIZE_3c:macro@SDIO_DCTRL_RWSTARTc:macro@SDIO_DCTRL_RWSTOPc:macro@SDIO_DCTRL_RWMODc:macro@SDIO_DCTRL_SDIOENc:macro@SDIO_DCOUNT_DATACOUNTc:macro@SDIO_STA_CCRCFAILc:macro@SDIO_STA_DCRCFAILc:macro@SDIO_STA_CTIMEOUTc:macro@SDIO_STA_DTIMEOUTc:macro@SDIO_STA_TXUNDERRc:macro@SDIO_STA_RXOVERRc:macro@SDIO_STA_CMDRENDc:macro@SDIO_STA_CMDSENTc:macro@SDIO_STA_DATAENDc:macro@SDIO_STA_STBITERRc:macro@SDIO_STA_DBCKENDc:macro@SDIO_STA_CMDACTc:macro@SDIO_STA_TXACTc:macro@SDIO_STA_RXACTc:macro@SDIO_STA_TXFIFOHEc:macro@SDIO_STA_RXFIFOHFc:macro@SDIO_STA_TXFIFOFc:macro@SDIO_STA_RXFIFOFc:macro@SDIO_STA_TXFIFOEc:macro@SDIO_STA_RXFIFOEc:macro@SDIO_STA_TXDAVLc:macro@SDIO_STA_RXDAVLc:macro@SDIO_STA_SDIOITc:macro@SDIO_STA_CEATAENDc:macro@SDIO_ICR_CCRCFAILCc:macro@SDIO_ICR_DCRCFAILCc:macro@SDIO_ICR_CTIMEOUTCc:macro@SDIO_ICR_DTIMEOUTCc:macro@SDIO_ICR_TXUNDERRCc:macro@SDIO_ICR_RXOVERRCc:macro@SDIO_ICR_CMDRENDCc:macro@SDIO_ICR_CMDSENTCc:macro@SDIO_ICR_DATAENDCc:macro@SDIO_ICR_STBITERRCc:macro@SDIO_ICR_DBCKENDCc:macro@SDIO_ICR_SDIOITCc:macro@SDIO_ICR_CEATAENDCc:macro@SDIO_MASK_CCRCFAILIEc:macro@SDIO_MASK_DCRCFAILIEc:macro@SDIO_MASK_CTIMEOUTIEc:macro@SDIO_MASK_DTIMEOUTIEc:macro@SDIO_MASK_TXUNDERRIEc:macro@SDIO_MASK_RXOVERRIEc:macro@SDIO_MASK_CMDRENDIEc:macro@SDIO_MASK_CMDSENTIEc:macro@SDIO_MASK_DATAENDIEc:macro@SDIO_MASK_STBITERRIEc:macro@SDIO_MASK_DBCKENDIEc:macro@SDIO_MASK_CMDACTIEc:macro@SDIO_MASK_TXACTIEc:macro@SDIO_MASK_RXACTIEc:macro@SDIO_MASK_TXFIFOHEIEc:macro@SDIO_MASK_RXFIFOHFIEc:macro@SDIO_MASK_TXFIFOFIEc:macro@SDIO_MASK_RXFIFOFIEc:macro@SDIO_MASK_TXFIFOEIEc:macro@SDIO_MASK_RXFIFOEIEc:macro@SDIO_MASK_TXDAVLIEc:macro@SDIO_MASK_RXDAVLIEc:macro@SDIO_MASK_SDIOITIEc:macro@SDIO_MASK_CEATAENDIEc:macro@SDIO_FIFOCNT_FIFOCOUNTc:macro@SDIO_FIFO_FIFODATAc:macro@SPI_CR1_CPHAc:macro@SPI_CR1_CPOLc:macro@SPI_CR1_MSTRc:macro@SPI_CR1_BRc:macro@SPI_CR1_BR_0c:macro@SPI_CR1_BR_1c:macro@SPI_CR1_BR_2c:macro@SPI_CR1_SPEc:macro@SPI_CR1_LSBFIRSTc:macro@SPI_CR1_SSIc:macro@SPI_CR1_SSMc:macro@SPI_CR1_RXONLYc:macro@SPI_CR1_DFFc:macro@SPI_CR1_CRCNEXTc:macro@SPI_CR1_CRCENc:macro@SPI_CR1_BIDIOEc:macro@SPI_CR1_BIDIMODEc:macro@SPI_CR2_RXDMAENc:macro@SPI_CR2_TXDMAENc:macro@SPI_CR2_SSOEc:macro@SPI_CR2_FRFc:macro@SPI_CR2_ERRIEc:macro@SPI_CR2_RXNEIEc:macro@SPI_CR2_TXEIEc:macro@SPI_SR_RXNEc:macro@SPI_SR_TXEc:macro@SPI_SR_CHSIDEc:macro@SPI_SR_UDRc:macro@SPI_SR_CRCERRc:macro@SPI_SR_MODFc:macro@SPI_SR_OVRc:macro@SPI_SR_BSYc:macro@SPI_DR_DRc:macro@SPI_CRCPR_CRCPOLYc:macro@SPI_RXCRCR_RXCRCc:macro@SPI_TXCRCR_TXCRCc:macro@SPI_I2SCFGR_CHLENc:macro@SPI_I2SCFGR_DATLENc:macro@SPI_I2SCFGR_DATLEN_0c:macro@SPI_I2SCFGR_DATLEN_1c:macro@SPI_I2SCFGR_CKPOLc:macro@SPI_I2SCFGR_I2SSTDc:macro@SPI_I2SCFGR_I2SSTD_0c:macro@SPI_I2SCFGR_I2SSTD_1c:macro@SPI_I2SCFGR_PCMSYNCc:macro@SPI_I2SCFGR_I2SCFGc:macro@SPI_I2SCFGR_I2SCFG_0c:macro@SPI_I2SCFGR_I2SCFG_1c:macro@SPI_I2SCFGR_I2SEc:macro@SPI_I2SCFGR_I2SMODc:macro@SPI_I2SPR_I2SDIVc:macro@SPI_I2SPR_ODDc:macro@SPI_I2SPR_MCKOEc:macro@SYSCFG_MEMRMP_MEM_MODEc:macro@SYSCFG_MEMRMP_MEM_MODE_0c:macro@SYSCFG_MEMRMP_MEM_MODE_1c:macro@SYSCFG_MEMRMP_BOOT_MODEc:macro@SYSCFG_MEMRMP_BOOT_MODE_0c:macro@SYSCFG_MEMRMP_BOOT_MODE_1c:macro@SYSCFG_PMC_USB_PUc:macro@SYSCFG_EXTICR1_EXTI0c:macro@SYSCFG_EXTICR1_EXTI1c:macro@SYSCFG_EXTICR1_EXTI2c:macro@SYSCFG_EXTICR1_EXTI3c:macro@SYSCFG_EXTICR1_EXTI0_PAc:macro@SYSCFG_EXTICR1_EXTI0_PBc:macro@SYSCFG_EXTICR1_EXTI0_PCc:macro@SYSCFG_EXTICR1_EXTI0_PDc:macro@SYSCFG_EXTICR1_EXTI0_PEc:macro@SYSCFG_EXTICR1_EXTI0_PHc:macro@SYSCFG_EXTICR1_EXTI0_PFc:macro@SYSCFG_EXTICR1_EXTI0_PGc:macro@SYSCFG_EXTICR1_EXTI1_PAc:macro@SYSCFG_EXTICR1_EXTI1_PBc:macro@SYSCFG_EXTICR1_EXTI1_PCc:macro@SYSCFG_EXTICR1_EXTI1_PDc:macro@SYSCFG_EXTICR1_EXTI1_PEc:macro@SYSCFG_EXTICR1_EXTI1_PHc:macro@SYSCFG_EXTICR1_EXTI1_PFc:macro@SYSCFG_EXTICR1_EXTI1_PGc:macro@SYSCFG_EXTICR1_EXTI2_PAc:macro@SYSCFG_EXTICR1_EXTI2_PBc:macro@SYSCFG_EXTICR1_EXTI2_PCc:macro@SYSCFG_EXTICR1_EXTI2_PDc:macro@SYSCFG_EXTICR1_EXTI2_PEc:macro@SYSCFG_EXTICR1_EXTI2_PHc:macro@SYSCFG_EXTICR1_EXTI2_PFc:macro@SYSCFG_EXTICR1_EXTI2_PGc:macro@SYSCFG_EXTICR1_EXTI3_PAc:macro@SYSCFG_EXTICR1_EXTI3_PBc:macro@SYSCFG_EXTICR1_EXTI3_PCc:macro@SYSCFG_EXTICR1_EXTI3_PDc:macro@SYSCFG_EXTICR1_EXTI3_PEc:macro@SYSCFG_EXTICR1_EXTI3_PFc:macro@SYSCFG_EXTICR1_EXTI3_PGc:macro@SYSCFG_EXTICR2_EXTI4c:macro@SYSCFG_EXTICR2_EXTI5c:macro@SYSCFG_EXTICR2_EXTI6c:macro@SYSCFG_EXTICR2_EXTI7c:macro@SYSCFG_EXTICR2_EXTI4_PAc:macro@SYSCFG_EXTICR2_EXTI4_PBc:macro@SYSCFG_EXTICR2_EXTI4_PCc:macro@SYSCFG_EXTICR2_EXTI4_PDc:macro@SYSCFG_EXTICR2_EXTI4_PEc:macro@SYSCFG_EXTICR2_EXTI4_PFc:macro@SYSCFG_EXTICR2_EXTI4_PGc:macro@SYSCFG_EXTICR2_EXTI5_PAc:macro@SYSCFG_EXTICR2_EXTI5_PBc:macro@SYSCFG_EXTICR2_EXTI5_PCc:macro@SYSCFG_EXTICR2_EXTI5_PDc:macro@SYSCFG_EXTICR2_EXTI5_PEc:macro@SYSCFG_EXTICR2_EXTI5_PFc:macro@SYSCFG_EXTICR2_EXTI5_PGc:macro@SYSCFG_EXTICR2_EXTI6_PAc:macro@SYSCFG_EXTICR2_EXTI6_PBc:macro@SYSCFG_EXTICR2_EXTI6_PCc:macro@SYSCFG_EXTICR2_EXTI6_PDc:macro@SYSCFG_EXTICR2_EXTI6_PEc:macro@SYSCFG_EXTICR2_EXTI6_PFc:macro@SYSCFG_EXTICR2_EXTI6_PGc:macro@SYSCFG_EXTICR2_EXTI7_PAc:macro@SYSCFG_EXTICR2_EXTI7_PBc:macro@SYSCFG_EXTICR2_EXTI7_PCc:macro@SYSCFG_EXTICR2_EXTI7_PDc:macro@SYSCFG_EXTICR2_EXTI7_PEc:macro@SYSCFG_EXTICR2_EXTI7_PFc:macro@SYSCFG_EXTICR2_EXTI7_PGc:macro@SYSCFG_EXTICR3_EXTI8c:macro@SYSCFG_EXTICR3_EXTI9c:macro@SYSCFG_EXTICR3_EXTI10c:macro@SYSCFG_EXTICR3_EXTI11c:macro@SYSCFG_EXTICR3_EXTI8_PAc:macro@SYSCFG_EXTICR3_EXTI8_PBc:macro@SYSCFG_EXTICR3_EXTI8_PCc:macro@SYSCFG_EXTICR3_EXTI8_PDc:macro@SYSCFG_EXTICR3_EXTI8_PEc:macro@SYSCFG_EXTICR3_EXTI8_PFc:macro@SYSCFG_EXTICR3_EXTI8_PGc:macro@SYSCFG_EXTICR3_EXTI9_PAc:macro@SYSCFG_EXTICR3_EXTI9_PBc:macro@SYSCFG_EXTICR3_EXTI9_PCc:macro@SYSCFG_EXTICR3_EXTI9_PDc:macro@SYSCFG_EXTICR3_EXTI9_PEc:macro@SYSCFG_EXTICR3_EXTI9_PFc:macro@SYSCFG_EXTICR3_EXTI9_PGc:macro@SYSCFG_EXTICR3_EXTI10_PAc:macro@SYSCFG_EXTICR3_EXTI10_PBc:macro@SYSCFG_EXTICR3_EXTI10_PCc:macro@SYSCFG_EXTICR3_EXTI10_PDc:macro@SYSCFG_EXTICR3_EXTI10_PEc:macro@SYSCFG_EXTICR3_EXTI10_PFc:macro@SYSCFG_EXTICR3_EXTI10_PGc:macro@SYSCFG_EXTICR3_EXTI11_PAc:macro@SYSCFG_EXTICR3_EXTI11_PBc:macro@SYSCFG_EXTICR3_EXTI11_PCc:macro@SYSCFG_EXTICR3_EXTI11_PDc:macro@SYSCFG_EXTICR3_EXTI11_PEc:macro@SYSCFG_EXTICR3_EXTI11_PFc:macro@SYSCFG_EXTICR3_EXTI11_PGc:macro@SYSCFG_EXTICR4_EXTI12c:macro@SYSCFG_EXTICR4_EXTI13c:macro@SYSCFG_EXTICR4_EXTI14c:macro@SYSCFG_EXTICR4_EXTI15c:macro@SYSCFG_EXTICR4_EXTI12_PAc:macro@SYSCFG_EXTICR4_EXTI12_PBc:macro@SYSCFG_EXTICR4_EXTI12_PCc:macro@SYSCFG_EXTICR4_EXTI12_PDc:macro@SYSCFG_EXTICR4_EXTI12_PEc:macro@SYSCFG_EXTICR4_EXTI12_PFc:macro@SYSCFG_EXTICR4_EXTI12_PGc:macro@SYSCFG_EXTICR4_EXTI13_PAc:macro@SYSCFG_EXTICR4_EXTI13_PBc:macro@SYSCFG_EXTICR4_EXTI13_PCc:macro@SYSCFG_EXTICR4_EXTI13_PDc:macro@SYSCFG_EXTICR4_EXTI13_PEc:macro@SYSCFG_EXTICR4_EXTI13_PFc:macro@SYSCFG_EXTICR4_EXTI13_PGc:macro@SYSCFG_EXTICR4_EXTI14_PAc:macro@SYSCFG_EXTICR4_EXTI14_PBc:macro@SYSCFG_EXTICR4_EXTI14_PCc:macro@SYSCFG_EXTICR4_EXTI14_PDc:macro@SYSCFG_EXTICR4_EXTI14_PEc:macro@SYSCFG_EXTICR4_EXTI14_PFc:macro@SYSCFG_EXTICR4_EXTI14_PGc:macro@SYSCFG_EXTICR4_EXTI15_PAc:macro@SYSCFG_EXTICR4_EXTI15_PBc:macro@SYSCFG_EXTICR4_EXTI15_PCc:macro@SYSCFG_EXTICR4_EXTI15_PDc:macro@SYSCFG_EXTICR4_EXTI15_PEc:macro@SYSCFG_EXTICR4_EXTI15_PFc:macro@SYSCFG_EXTICR4_EXTI15_PGc:macro@RI_ICR_IC1Zc:macro@RI_ICR_IC1Z_0c:macro@RI_ICR_IC1Z_1c:macro@RI_ICR_IC1Z_2c:macro@RI_ICR_IC1Z_3c:macro@RI_ICR_IC2Zc:macro@RI_ICR_IC2Z_0c:macro@RI_ICR_IC2Z_1c:macro@RI_ICR_IC2Z_2c:macro@RI_ICR_IC2Z_3c:macro@RI_ICR_IC3Zc:macro@RI_ICR_IC3Z_0c:macro@RI_ICR_IC3Z_1c:macro@RI_ICR_IC3Z_2c:macro@RI_ICR_IC3Z_3c:macro@RI_ICR_IC4Zc:macro@RI_ICR_IC4Z_0c:macro@RI_ICR_IC4Z_1c:macro@RI_ICR_IC4Z_2c:macro@RI_ICR_IC4Z_3c:macro@RI_ICR_TIMc:macro@RI_ICR_TIM_0c:macro@RI_ICR_TIM_1c:macro@RI_ICR_IC1c:macro@RI_ICR_IC2c:macro@RI_ICR_IC3c:macro@RI_ICR_IC4c:macro@RI_ASCR1_CHc:macro@RI_ASCR1_CH_0c:macro@RI_ASCR1_CH_1c:macro@RI_ASCR1_CH_2c:macro@RI_ASCR1_CH_3c:macro@RI_ASCR1_CH_4c:macro@RI_ASCR1_CH_5c:macro@RI_ASCR1_CH_6c:macro@RI_ASCR1_CH_7c:macro@RI_ASCR1_CH_8c:macro@RI_ASCR1_CH_9c:macro@RI_ASCR1_CH_10c:macro@RI_ASCR1_CH_11c:macro@RI_ASCR1_CH_12c:macro@RI_ASCR1_CH_13c:macro@RI_ASCR1_CH_14c:macro@RI_ASCR1_CH_15c:macro@RI_ASCR1_CH_31c:macro@RI_ASCR1_CH_18c:macro@RI_ASCR1_CH_19c:macro@RI_ASCR1_CH_20c:macro@RI_ASCR1_CH_21c:macro@RI_ASCR1_CH_22c:macro@RI_ASCR1_CH_23c:macro@RI_ASCR1_CH_24c:macro@RI_ASCR1_CH_25c:macro@RI_ASCR1_VCOMPc:macro@RI_ASCR1_CH_27c:macro@RI_ASCR1_CH_28c:macro@RI_ASCR1_CH_29c:macro@RI_ASCR1_CH_30c:macro@RI_ASCR1_SCMc:macro@RI_ASCR2_GR10_1c:macro@RI_ASCR2_GR10_2c:macro@RI_ASCR2_GR10_3c:macro@RI_ASCR2_GR10_4c:macro@RI_ASCR2_GR6_1c:macro@RI_ASCR2_GR6_2c:macro@RI_ASCR2_GR5_1c:macro@RI_ASCR2_GR5_2c:macro@RI_ASCR2_GR5_3c:macro@RI_ASCR2_GR4_1c:macro@RI_ASCR2_GR4_2c:macro@RI_ASCR2_GR4_3c:macro@RI_ASCR2_GR4_4c:macro@RI_ASCR2_CH0bc:macro@RI_ASCR2_CH1bc:macro@RI_ASCR2_CH2bc:macro@RI_ASCR2_CH3bc:macro@RI_ASCR2_CH6bc:macro@RI_ASCR2_CH7bc:macro@RI_ASCR2_CH8bc:macro@RI_ASCR2_CH9bc:macro@RI_ASCR2_CH10bc:macro@RI_ASCR2_CH11bc:macro@RI_ASCR2_CH12bc:macro@RI_ASCR2_GR6_3c:macro@RI_ASCR2_GR6_4c:macro@RI_ASCR2_GR5_4c:macro@RI_HYSCR1_PAc:macro@RI_HYSCR1_PA_0c:macro@RI_HYSCR1_PA_1c:macro@RI_HYSCR1_PA_2c:macro@RI_HYSCR1_PA_3c:macro@RI_HYSCR1_PA_4c:macro@RI_HYSCR1_PA_5c:macro@RI_HYSCR1_PA_6c:macro@RI_HYSCR1_PA_7c:macro@RI_HYSCR1_PA_8c:macro@RI_HYSCR1_PA_9c:macro@RI_HYSCR1_PA_10c:macro@RI_HYSCR1_PA_11c:macro@RI_HYSCR1_PA_12c:macro@RI_HYSCR1_PA_13c:macro@RI_HYSCR1_PA_14c:macro@RI_HYSCR1_PA_15c:macro@RI_HYSCR1_PBc:macro@RI_HYSCR1_PB_0c:macro@RI_HYSCR1_PB_1c:macro@RI_HYSCR1_PB_2c:macro@RI_HYSCR1_PB_3c:macro@RI_HYSCR1_PB_4c:macro@RI_HYSCR1_PB_5c:macro@RI_HYSCR1_PB_6c:macro@RI_HYSCR1_PB_7c:macro@RI_HYSCR1_PB_8c:macro@RI_HYSCR1_PB_9c:macro@RI_HYSCR1_PB_10c:macro@RI_HYSCR1_PB_11c:macro@RI_HYSCR1_PB_12c:macro@RI_HYSCR1_PB_13c:macro@RI_HYSCR1_PB_14c:macro@RI_HYSCR1_PB_15c:macro@RI_HYSCR2_PCc:macro@RI_HYSCR2_PC_0c:macro@RI_HYSCR2_PC_1c:macro@RI_HYSCR2_PC_2c:macro@RI_HYSCR2_PC_3c:macro@RI_HYSCR2_PC_4c:macro@RI_HYSCR2_PC_5c:macro@RI_HYSCR2_PC_6c:macro@RI_HYSCR2_PC_7c:macro@RI_HYSCR2_PC_8c:macro@RI_HYSCR2_PC_9c:macro@RI_HYSCR2_PC_10c:macro@RI_HYSCR2_PC_11c:macro@RI_HYSCR2_PC_12c:macro@RI_HYSCR2_PC_13c:macro@RI_HYSCR2_PC_14c:macro@RI_HYSCR2_PC_15c:macro@RI_HYSCR2_PDc:macro@RI_HYSCR2_PD_0c:macro@RI_HYSCR2_PD_1c:macro@RI_HYSCR2_PD_2c:macro@RI_HYSCR2_PD_3c:macro@RI_HYSCR2_PD_4c:macro@RI_HYSCR2_PD_5c:macro@RI_HYSCR2_PD_6c:macro@RI_HYSCR2_PD_7c:macro@RI_HYSCR2_PD_8c:macro@RI_HYSCR2_PD_9c:macro@RI_HYSCR2_PD_10c:macro@RI_HYSCR2_PD_11c:macro@RI_HYSCR2_PD_12c:macro@RI_HYSCR2_PD_13c:macro@RI_HYSCR2_PD_14c:macro@RI_HYSCR2_PD_15c:macro@RI_HYSCR2_PEc:macro@RI_HYSCR2_PE_0c:macro@RI_HYSCR2_PE_1c:macro@RI_HYSCR2_PE_2c:macro@RI_HYSCR2_PE_3c:macro@RI_HYSCR2_PE_4c:macro@RI_HYSCR2_PE_5c:macro@RI_HYSCR2_PE_6c:macro@RI_HYSCR2_PE_7c:macro@RI_HYSCR2_PE_8c:macro@RI_HYSCR2_PE_9c:macro@RI_HYSCR2_PE_10c:macro@RI_HYSCR2_PE_11c:macro@RI_HYSCR2_PE_12c:macro@RI_HYSCR2_PE_13c:macro@RI_HYSCR2_PE_14c:macro@RI_HYSCR2_PE_15c:macro@RI_HYSCR3_PFc:macro@RI_HYSCR3_PF_0c:macro@RI_HYSCR3_PF_1c:macro@RI_HYSCR3_PF_2c:macro@RI_HYSCR3_PF_3c:macro@RI_HYSCR3_PF_4c:macro@RI_HYSCR3_PF_5c:macro@RI_HYSCR3_PF_6c:macro@RI_HYSCR3_PF_7c:macro@RI_HYSCR3_PF_8c:macro@RI_HYSCR3_PF_9c:macro@RI_HYSCR3_PF_10c:macro@RI_HYSCR3_PF_11c:macro@RI_HYSCR3_PF_12c:macro@RI_HYSCR3_PF_13c:macro@RI_HYSCR3_PF_14c:macro@RI_HYSCR3_PF_15c:macro@RI_HYSCR4_PGc:macro@RI_HYSCR4_PG_0c:macro@RI_HYSCR4_PG_1c:macro@RI_HYSCR4_PG_2c:macro@RI_HYSCR4_PG_3c:macro@RI_HYSCR4_PG_4c:macro@RI_HYSCR4_PG_5c:macro@RI_HYSCR4_PG_6c:macro@RI_HYSCR4_PG_7c:macro@RI_HYSCR4_PG_8c:macro@RI_HYSCR4_PG_9c:macro@RI_HYSCR4_PG_10c:macro@RI_HYSCR4_PG_11c:macro@RI_HYSCR4_PG_12c:macro@RI_HYSCR4_PG_13c:macro@RI_HYSCR4_PG_14c:macro@RI_HYSCR4_PG_15c:macro@TIM_CR1_CENc:macro@TIM_CR1_UDISc:macro@TIM_CR1_URSc:macro@TIM_CR1_OPMc:macro@TIM_CR1_DIRc:macro@TIM_CR1_CMSc:macro@TIM_CR1_CMS_0c:macro@TIM_CR1_CMS_1c:macro@TIM_CR1_ARPEc:macro@TIM_CR1_CKDc:macro@TIM_CR1_CKD_0c:macro@TIM_CR1_CKD_1c:macro@TIM_CR2_CCDSc:macro@TIM_CR2_MMSc:macro@TIM_CR2_MMS_0c:macro@TIM_CR2_MMS_1c:macro@TIM_CR2_MMS_2c:macro@TIM_CR2_TI1Sc:macro@TIM_SMCR_SMSc:macro@TIM_SMCR_SMS_0c:macro@TIM_SMCR_SMS_1c:macro@TIM_SMCR_SMS_2c:macro@TIM_SMCR_OCCSc:macro@TIM_SMCR_TSc:macro@TIM_SMCR_TS_0c:macro@TIM_SMCR_TS_1c:macro@TIM_SMCR_TS_2c:macro@TIM_SMCR_MSMc:macro@TIM_SMCR_ETFc:macro@TIM_SMCR_ETF_0c:macro@TIM_SMCR_ETF_1c:macro@TIM_SMCR_ETF_2c:macro@TIM_SMCR_ETF_3c:macro@TIM_SMCR_ETPSc:macro@TIM_SMCR_ETPS_0c:macro@TIM_SMCR_ETPS_1c:macro@TIM_SMCR_ECEc:macro@TIM_SMCR_ETPc:macro@TIM_DIER_UIEc:macro@TIM_DIER_CC1IEc:macro@TIM_DIER_CC2IEc:macro@TIM_DIER_CC3IEc:macro@TIM_DIER_CC4IEc:macro@TIM_DIER_TIEc:macro@TIM_DIER_UDEc:macro@TIM_DIER_CC1DEc:macro@TIM_DIER_CC2DEc:macro@TIM_DIER_CC3DEc:macro@TIM_DIER_CC4DEc:macro@TIM_DIER_TDEc:macro@TIM_SR_UIFc:macro@TIM_SR_CC1IFc:macro@TIM_SR_CC2IFc:macro@TIM_SR_CC3IFc:macro@TIM_SR_CC4IFc:macro@TIM_SR_TIFc:macro@TIM_SR_CC1OFc:macro@TIM_SR_CC2OFc:macro@TIM_SR_CC3OFc:macro@TIM_SR_CC4OFc:macro@TIM_EGR_UGc:macro@TIM_EGR_CC1Gc:macro@TIM_EGR_CC2Gc:macro@TIM_EGR_CC3Gc:macro@TIM_EGR_CC4Gc:macro@TIM_EGR_TGc:macro@TIM_CCMR1_CC1Sc:macro@TIM_CCMR1_CC1S_0c:macro@TIM_CCMR1_CC1S_1c:macro@TIM_CCMR1_OC1FEc:macro@TIM_CCMR1_OC1PEc:macro@TIM_CCMR1_OC1Mc:macro@TIM_CCMR1_OC1M_0c:macro@TIM_CCMR1_OC1M_1c:macro@TIM_CCMR1_OC1M_2c:macro@TIM_CCMR1_OC1CEc:macro@TIM_CCMR1_CC2Sc:macro@TIM_CCMR1_CC2S_0c:macro@TIM_CCMR1_CC2S_1c:macro@TIM_CCMR1_OC2FEc:macro@TIM_CCMR1_OC2PEc:macro@TIM_CCMR1_OC2Mc:macro@TIM_CCMR1_OC2M_0c:macro@TIM_CCMR1_OC2M_1c:macro@TIM_CCMR1_OC2M_2c:macro@TIM_CCMR1_OC2CEc:macro@TIM_CCMR1_IC1PSCc:macro@TIM_CCMR1_IC1PSC_0c:macro@TIM_CCMR1_IC1PSC_1c:macro@TIM_CCMR1_IC1Fc:macro@TIM_CCMR1_IC1F_0c:macro@TIM_CCMR1_IC1F_1c:macro@TIM_CCMR1_IC1F_2c:macro@TIM_CCMR1_IC1F_3c:macro@TIM_CCMR1_IC2PSCc:macro@TIM_CCMR1_IC2PSC_0c:macro@TIM_CCMR1_IC2PSC_1c:macro@TIM_CCMR1_IC2Fc:macro@TIM_CCMR1_IC2F_0c:macro@TIM_CCMR1_IC2F_1c:macro@TIM_CCMR1_IC2F_2c:macro@TIM_CCMR1_IC2F_3c:macro@TIM_CCMR2_CC3Sc:macro@TIM_CCMR2_CC3S_0c:macro@TIM_CCMR2_CC3S_1c:macro@TIM_CCMR2_OC3FEc:macro@TIM_CCMR2_OC3PEc:macro@TIM_CCMR2_OC3Mc:macro@TIM_CCMR2_OC3M_0c:macro@TIM_CCMR2_OC3M_1c:macro@TIM_CCMR2_OC3M_2c:macro@TIM_CCMR2_OC3CEc:macro@TIM_CCMR2_CC4Sc:macro@TIM_CCMR2_CC4S_0c:macro@TIM_CCMR2_CC4S_1c:macro@TIM_CCMR2_OC4FEc:macro@TIM_CCMR2_OC4PEc:macro@TIM_CCMR2_OC4Mc:macro@TIM_CCMR2_OC4M_0c:macro@TIM_CCMR2_OC4M_1c:macro@TIM_CCMR2_OC4M_2c:macro@TIM_CCMR2_OC4CEc:macro@TIM_CCMR2_IC3PSCc:macro@TIM_CCMR2_IC3PSC_0c:macro@TIM_CCMR2_IC3PSC_1c:macro@TIM_CCMR2_IC3Fc:macro@TIM_CCMR2_IC3F_0c:macro@TIM_CCMR2_IC3F_1c:macro@TIM_CCMR2_IC3F_2c:macro@TIM_CCMR2_IC3F_3c:macro@TIM_CCMR2_IC4PSCc:macro@TIM_CCMR2_IC4PSC_0c:macro@TIM_CCMR2_IC4PSC_1c:macro@TIM_CCMR2_IC4Fc:macro@TIM_CCMR2_IC4F_0c:macro@TIM_CCMR2_IC4F_1c:macro@TIM_CCMR2_IC4F_2c:macro@TIM_CCMR2_IC4F_3c:macro@TIM_CCER_CC1Ec:macro@TIM_CCER_CC1Pc:macro@TIM_CCER_CC1NPc:macro@TIM_CCER_CC2Ec:macro@TIM_CCER_CC2Pc:macro@TIM_CCER_CC2NPc:macro@TIM_CCER_CC3Ec:macro@TIM_CCER_CC3Pc:macro@TIM_CCER_CC3NPc:macro@TIM_CCER_CC4Ec:macro@TIM_CCER_CC4Pc:macro@TIM_CCER_CC4NPc:macro@TIM_CNT_CNTc:macro@TIM_PSC_PSCc:macro@TIM_ARR_ARRc:macro@TIM_CCR1_CCR1c:macro@TIM_CCR2_CCR2c:macro@TIM_CCR3_CCR3c:macro@TIM_CCR4_CCR4c:macro@TIM_DCR_DBAc:macro@TIM_DCR_DBA_0c:macro@TIM_DCR_DBA_1c:macro@TIM_DCR_DBA_2c:macro@TIM_DCR_DBA_3c:macro@TIM_DCR_DBA_4c:macro@TIM_DCR_DBLc:macro@TIM_DCR_DBL_0c:macro@TIM_DCR_DBL_1c:macro@TIM_DCR_DBL_2c:macro@TIM_DCR_DBL_3c:macro@TIM_DCR_DBL_4c:macro@TIM_DMAR_DMABc:macro@TIM_OR_TI1RMPc:macro@TIM_OR_TI1RMP_0c:macro@TIM_OR_TI1RMP_1c:macro@USART_SR_PEc:macro@USART_SR_FEc:macro@USART_SR_NEc:macro@USART_SR_OREc:macro@USART_SR_IDLEc:macro@USART_SR_RXNEc:macro@USART_SR_TCc:macro@USART_SR_TXEc:macro@USART_SR_LBDc:macro@USART_SR_CTSc:macro@USART_DR_DRc:macro@USART_BRR_DIV_FRACTIONc:macro@USART_BRR_DIV_MANTISSAc:macro@USART_CR1_SBKc:macro@USART_CR1_RWUc:macro@USART_CR1_REc:macro@USART_CR1_TEc:macro@USART_CR1_IDLEIEc:macro@USART_CR1_RXNEIEc:macro@USART_CR1_TCIEc:macro@USART_CR1_TXEIEc:macro@USART_CR1_PEIEc:macro@USART_CR1_PSc:macro@USART_CR1_PCEc:macro@USART_CR1_WAKEc:macro@USART_CR1_Mc:macro@USART_CR1_UEc:macro@USART_CR1_OVER8c:macro@USART_CR2_ADDc:macro@USART_CR2_LBDLc:macro@USART_CR2_LBDIEc:macro@USART_CR2_LBCLc:macro@USART_CR2_CPHAc:macro@USART_CR2_CPOLc:macro@USART_CR2_CLKENc:macro@USART_CR2_STOPc:macro@USART_CR2_STOP_0c:macro@USART_CR2_STOP_1c:macro@USART_CR2_LINENc:macro@USART_CR3_EIEc:macro@USART_CR3_IRENc:macro@USART_CR3_IRLPc:macro@USART_CR3_HDSELc:macro@USART_CR3_NACKc:macro@USART_CR3_SCENc:macro@USART_CR3_DMARc:macro@USART_CR3_DMATc:macro@USART_CR3_RTSEc:macro@USART_CR3_CTSEc:macro@USART_CR3_CTSIEc:macro@USART_CR3_ONEBITc:macro@USART_GTPR_PSCc:macro@USART_GTPR_PSC_0c:macro@USART_GTPR_PSC_1c:macro@USART_GTPR_PSC_2c:macro@USART_GTPR_PSC_3c:macro@USART_GTPR_PSC_4c:macro@USART_GTPR_PSC_5c:macro@USART_GTPR_PSC_6c:macro@USART_GTPR_PSC_7c:macro@USART_GTPR_GTc:macro@USB_EP0R_EAc:macro@USB_EP0R_STAT_TXc:macro@USB_EP0R_STAT_TX_0c:macro@USB_EP0R_STAT_TX_1c:macro@USB_EP0R_DTOG_TXc:macro@USB_EP0R_CTR_TXc:macro@USB_EP0R_EP_KINDc:macro@USB_EP0R_EP_TYPEc:macro@USB_EP0R_EP_TYPE_0c:macro@USB_EP0R_EP_TYPE_1c:macro@USB_EP0R_SETUPc:macro@USB_EP0R_STAT_RXc:macro@USB_EP0R_STAT_RX_0c:macro@USB_EP0R_STAT_RX_1c:macro@USB_EP0R_DTOG_RXc:macro@USB_EP0R_CTR_RXc:macro@USB_EP1R_EAc:macro@USB_EP1R_STAT_TXc:macro@USB_EP1R_STAT_TX_0c:macro@USB_EP1R_STAT_TX_1c:macro@USB_EP1R_DTOG_TXc:macro@USB_EP1R_CTR_TXc:macro@USB_EP1R_EP_KINDc:macro@USB_EP1R_EP_TYPEc:macro@USB_EP1R_EP_TYPE_0c:macro@USB_EP1R_EP_TYPE_1c:macro@USB_EP1R_SETUPc:macro@USB_EP1R_STAT_RXc:macro@USB_EP1R_STAT_RX_0c:macro@USB_EP1R_STAT_RX_1c:macro@USB_EP1R_DTOG_RXc:macro@USB_EP1R_CTR_RXc:macro@USB_EP2R_EAc:macro@USB_EP2R_STAT_TXc:macro@USB_EP2R_STAT_TX_0c:macro@USB_EP2R_STAT_TX_1c:macro@USB_EP2R_DTOG_TXc:macro@USB_EP2R_CTR_TXc:macro@USB_EP2R_EP_KINDc:macro@USB_EP2R_EP_TYPEc:macro@USB_EP2R_EP_TYPE_0c:macro@USB_EP2R_EP_TYPE_1c:macro@USB_EP2R_SETUPc:macro@USB_EP2R_STAT_RXc:macro@USB_EP2R_STAT_RX_0c:macro@USB_EP2R_STAT_RX_1c:macro@USB_EP2R_DTOG_RXc:macro@USB_EP2R_CTR_RXc:macro@USB_EP3R_EAc:macro@USB_EP3R_STAT_TXc:macro@USB_EP3R_STAT_TX_0c:macro@USB_EP3R_STAT_TX_1c:macro@USB_EP3R_DTOG_TXc:macro@USB_EP3R_CTR_TXc:macro@USB_EP3R_EP_KINDc:macro@USB_EP3R_EP_TYPEc:macro@USB_EP3R_EP_TYPE_0c:macro@USB_EP3R_EP_TYPE_1c:macro@USB_EP3R_SETUPc:macro@USB_EP3R_STAT_RXc:macro@USB_EP3R_STAT_RX_0c:macro@USB_EP3R_STAT_RX_1c:macro@USB_EP3R_DTOG_RXc:macro@USB_EP3R_CTR_RXc:macro@USB_EP4R_EAc:macro@USB_EP4R_STAT_TXc:macro@USB_EP4R_STAT_TX_0c:macro@USB_EP4R_STAT_TX_1c:macro@USB_EP4R_DTOG_TXc:macro@USB_EP4R_CTR_TXc:macro@USB_EP4R_EP_KINDc:macro@USB_EP4R_EP_TYPEc:macro@USB_EP4R_EP_TYPE_0c:macro@USB_EP4R_EP_TYPE_1c:macro@USB_EP4R_SETUPc:macro@USB_EP4R_STAT_RXc:macro@USB_EP4R_STAT_RX_0c:macro@USB_EP4R_STAT_RX_1c:macro@USB_EP4R_DTOG_RXc:macro@USB_EP4R_CTR_RXc:macro@USB_EP5R_EAc:macro@USB_EP5R_STAT_TXc:macro@USB_EP5R_STAT_TX_0c:macro@USB_EP5R_STAT_TX_1c:macro@USB_EP5R_DTOG_TXc:macro@USB_EP5R_CTR_TXc:macro@USB_EP5R_EP_KINDc:macro@USB_EP5R_EP_TYPEc:macro@USB_EP5R_EP_TYPE_0c:macro@USB_EP5R_EP_TYPE_1c:macro@USB_EP5R_SETUPc:macro@USB_EP5R_STAT_RXc:macro@USB_EP5R_STAT_RX_0c:macro@USB_EP5R_STAT_RX_1c:macro@USB_EP5R_DTOG_RXc:macro@USB_EP5R_CTR_RXc:macro@USB_EP6R_EAc:macro@USB_EP6R_STAT_TXc:macro@USB_EP6R_STAT_TX_0c:macro@USB_EP6R_STAT_TX_1c:macro@USB_EP6R_DTOG_TXc:macro@USB_EP6R_CTR_TXc:macro@USB_EP6R_EP_KINDc:macro@USB_EP6R_EP_TYPEc:macro@USB_EP6R_EP_TYPE_0c:macro@USB_EP6R_EP_TYPE_1c:macro@USB_EP6R_SETUPc:macro@USB_EP6R_STAT_RXc:macro@USB_EP6R_STAT_RX_0c:macro@USB_EP6R_STAT_RX_1c:macro@USB_EP6R_DTOG_RXc:macro@USB_EP6R_CTR_RXc:macro@USB_EP7R_EAc:macro@USB_EP7R_STAT_TXc:macro@USB_EP7R_STAT_TX_0c:macro@USB_EP7R_STAT_TX_1c:macro@USB_EP7R_DTOG_TXc:macro@USB_EP7R_CTR_TXc:macro@USB_EP7R_EP_KINDc:macro@USB_EP7R_EP_TYPEc:macro@USB_EP7R_EP_TYPE_0c:macro@USB_EP7R_EP_TYPE_1c:macro@USB_EP7R_SETUPc:macro@USB_EP7R_STAT_RXc:macro@USB_EP7R_STAT_RX_0c:macro@USB_EP7R_STAT_RX_1c:macro@USB_EP7R_DTOG_RXc:macro@USB_EP7R_CTR_RXc:macro@USB_CNTR_FRESc:macro@USB_CNTR_PDWNc:macro@USB_CNTR_LP_MODEc:macro@USB_CNTR_FSUSPc:macro@USB_CNTR_RESUMEc:macro@USB_CNTR_ESOFMc:macro@USB_CNTR_SOFMc:macro@USB_CNTR_RESETMc:macro@USB_CNTR_SUSPMc:macro@USB_CNTR_WKUPMc:macro@USB_CNTR_ERRMc:macro@USB_CNTR_PMAOVRMc:macro@USB_CNTR_CTRMc:macro@USB_ISTR_EP_IDc:macro@USB_ISTR_DIRc:macro@USB_ISTR_ESOFc:macro@USB_ISTR_SOFc:macro@USB_ISTR_RESETc:macro@USB_ISTR_SUSPc:macro@USB_ISTR_WKUPc:macro@USB_ISTR_ERRc:macro@USB_ISTR_PMAOVRc:macro@USB_ISTR_CTRc:macro@USB_FNR_FNc:macro@USB_FNR_LSOFc:macro@USB_FNR_LCKc:macro@USB_FNR_RXDMc:macro@USB_FNR_RXDPc:macro@USB_DADDR_ADDc:macro@USB_DADDR_ADD0c:macro@USB_DADDR_ADD1c:macro@USB_DADDR_ADD2c:macro@USB_DADDR_ADD3c:macro@USB_DADDR_ADD4c:macro@USB_DADDR_ADD5c:macro@USB_DADDR_ADD6c:macro@USB_DADDR_EFc:macro@USB_BTABLE_BTABLEc:macro@USB_ADDR0_TX_ADDR0_TXc:macro@USB_ADDR1_TX_ADDR1_TXc:macro@USB_ADDR2_TX_ADDR2_TXc:macro@USB_ADDR3_TX_ADDR3_TXc:macro@USB_ADDR4_TX_ADDR4_TXc:macro@USB_ADDR5_TX_ADDR5_TXc:macro@USB_ADDR6_TX_ADDR6_TXc:macro@USB_ADDR7_TX_ADDR7_TXc:macro@USB_COUNT0_TX_COUNT0_TXc:macro@USB_COUNT1_TX_COUNT1_TXc:macro@USB_COUNT2_TX_COUNT2_TXc:macro@USB_COUNT3_TX_COUNT3_TXc:macro@USB_COUNT4_TX_COUNT4_TXc:macro@USB_COUNT5_TX_COUNT5_TXc:macro@USB_COUNT6_TX_COUNT6_TXc:macro@USB_COUNT7_TX_COUNT7_TXc:macro@USB_COUNT0_TX_0_COUNT0_TX_0c:macro@USB_COUNT0_TX_1_COUNT0_TX_1c:macro@USB_COUNT1_TX_0_COUNT1_TX_0c:macro@USB_COUNT1_TX_1_COUNT1_TX_1c:macro@USB_COUNT2_TX_0_COUNT2_TX_0c:macro@USB_COUNT2_TX_1_COUNT2_TX_1c:macro@USB_COUNT3_TX_0_COUNT3_TX_0c:macro@USB_COUNT3_TX_1_COUNT3_TX_1c:macro@USB_COUNT4_TX_0_COUNT4_TX_0c:macro@USB_COUNT4_TX_1_COUNT4_TX_1c:macro@USB_COUNT5_TX_0_COUNT5_TX_0c:macro@USB_COUNT5_TX_1_COUNT5_TX_1c:macro@USB_COUNT6_TX_0_COUNT6_TX_0c:macro@USB_COUNT6_TX_1_COUNT6_TX_1c:macro@USB_COUNT7_TX_0_COUNT7_TX_0c:macro@USB_COUNT7_TX_1_COUNT7_TX_1c:macro@USB_ADDR0_RX_ADDR0_RXc:macro@USB_ADDR1_RX_ADDR1_RXc:macro@USB_ADDR2_RX_ADDR2_RXc:macro@USB_ADDR3_RX_ADDR3_RXc:macro@USB_ADDR4_RX_ADDR4_RXc:macro@USB_ADDR5_RX_ADDR5_RXc:macro@USB_ADDR6_RX_ADDR6_RXc:macro@USB_ADDR7_RX_ADDR7_RXc:macro@USB_COUNT0_RX_COUNT0_RXc:macro@USB_COUNT0_RX_NUM_BLOCKc:macro@USB_COUNT0_RX_NUM_BLOCK_0c:macro@USB_COUNT0_RX_NUM_BLOCK_1c:macro@USB_COUNT0_RX_NUM_BLOCK_2c:macro@USB_COUNT0_RX_NUM_BLOCK_3c:macro@USB_COUNT0_RX_NUM_BLOCK_4c:macro@USB_COUNT0_RX_BLSIZEc:macro@USB_COUNT1_RX_COUNT1_RXc:macro@USB_COUNT1_RX_NUM_BLOCKc:macro@USB_COUNT1_RX_NUM_BLOCK_0c:macro@USB_COUNT1_RX_NUM_BLOCK_1c:macro@USB_COUNT1_RX_NUM_BLOCK_2c:macro@USB_COUNT1_RX_NUM_BLOCK_3c:macro@USB_COUNT1_RX_NUM_BLOCK_4c:macro@USB_COUNT1_RX_BLSIZEc:macro@USB_COUNT2_RX_COUNT2_RXc:macro@USB_COUNT2_RX_NUM_BLOCKc:macro@USB_COUNT2_RX_NUM_BLOCK_0c:macro@USB_COUNT2_RX_NUM_BLOCK_1c:macro@USB_COUNT2_RX_NUM_BLOCK_2c:macro@USB_COUNT2_RX_NUM_BLOCK_3c:macro@USB_COUNT2_RX_NUM_BLOCK_4c:macro@USB_COUNT2_RX_BLSIZEc:macro@USB_COUNT3_RX_COUNT3_RXc:macro@USB_COUNT3_RX_NUM_BLOCKc:macro@USB_COUNT3_RX_NUM_BLOCK_0c:macro@USB_COUNT3_RX_NUM_BLOCK_1c:macro@USB_COUNT3_RX_NUM_BLOCK_2c:macro@USB_COUNT3_RX_NUM_BLOCK_3c:macro@USB_COUNT3_RX_NUM_BLOCK_4c:macro@USB_COUNT3_RX_BLSIZEc:macro@USB_COUNT4_RX_COUNT4_RXc:macro@USB_COUNT4_RX_NUM_BLOCKc:macro@USB_COUNT4_RX_NUM_BLOCK_0c:macro@USB_COUNT4_RX_NUM_BLOCK_1c:macro@USB_COUNT4_RX_NUM_BLOCK_2c:macro@USB_COUNT4_RX_NUM_BLOCK_3c:macro@USB_COUNT4_RX_NUM_BLOCK_4c:macro@USB_COUNT4_RX_BLSIZEc:macro@USB_COUNT5_RX_COUNT5_RXc:macro@USB_COUNT5_RX_NUM_BLOCKc:macro@USB_COUNT5_RX_NUM_BLOCK_0c:macro@USB_COUNT5_RX_NUM_BLOCK_1c:macro@USB_COUNT5_RX_NUM_BLOCK_2c:macro@USB_COUNT5_RX_NUM_BLOCK_3c:macro@USB_COUNT5_RX_NUM_BLOCK_4c:macro@USB_COUNT5_RX_BLSIZEc:macro@USB_COUNT6_RX_COUNT6_RXc:macro@USB_COUNT6_RX_NUM_BLOCKc:macro@USB_COUNT6_RX_NUM_BLOCK_0c:macro@USB_COUNT6_RX_NUM_BLOCK_1c:macro@USB_COUNT6_RX_NUM_BLOCK_2c:macro@USB_COUNT6_RX_NUM_BLOCK_3c:macro@USB_COUNT6_RX_NUM_BLOCK_4c:macro@USB_COUNT6_RX_BLSIZEc:macro@USB_COUNT7_RX_COUNT7_RXc:macro@USB_COUNT7_RX_NUM_BLOCKc:macro@USB_COUNT7_RX_NUM_BLOCK_0c:macro@USB_COUNT7_RX_NUM_BLOCK_1c:macro@USB_COUNT7_RX_NUM_BLOCK_2c:macro@USB_COUNT7_RX_NUM_BLOCK_3c:macro@USB_COUNT7_RX_NUM_BLOCK_4c:macro@USB_COUNT7_RX_BLSIZEc:macro@USB_COUNT0_RX_0_COUNT0_RX_0c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT0_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT0_RX_0_BLSIZE_0c:macro@USB_COUNT0_RX_1_COUNT0_RX_1c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT0_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT0_RX_1_BLSIZE_1c:macro@USB_COUNT1_RX_0_COUNT1_RX_0c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT1_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT1_RX_0_BLSIZE_0c:macro@USB_COUNT1_RX_1_COUNT1_RX_1c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT1_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT1_RX_1_BLSIZE_1c:macro@USB_COUNT2_RX_0_COUNT2_RX_0c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT2_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT2_RX_0_BLSIZE_0c:macro@USB_COUNT2_RX_1_COUNT2_RX_1c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT2_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT2_RX_1_BLSIZE_1c:macro@USB_COUNT3_RX_0_COUNT3_RX_0c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT3_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT3_RX_0_BLSIZE_0c:macro@USB_COUNT3_RX_1_COUNT3_RX_1c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT3_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT3_RX_1_BLSIZE_1c:macro@USB_COUNT4_RX_0_COUNT4_RX_0c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT4_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT4_RX_0_BLSIZE_0c:macro@USB_COUNT4_RX_1_COUNT4_RX_1c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT4_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT4_RX_1_BLSIZE_1c:macro@USB_COUNT5_RX_0_COUNT5_RX_0c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT5_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT5_RX_0_BLSIZE_0c:macro@USB_COUNT5_RX_1_COUNT5_RX_1c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT5_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT5_RX_1_BLSIZE_1c:macro@USB_COUNT6_RX_0_COUNT6_RX_0c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT6_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT6_RX_0_BLSIZE_0c:macro@USB_COUNT6_RX_1_COUNT6_RX_1c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT6_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT6_RX_1_BLSIZE_1c:macro@USB_COUNT7_RX_0_COUNT7_RX_0c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_0c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_1c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_2c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_3c:macro@USB_COUNT7_RX_0_NUM_BLOCK_0_4c:macro@USB_COUNT7_RX_0_BLSIZE_0c:macro@USB_COUNT7_RX_1_COUNT7_RX_1c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_0c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_1c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_2c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_3c:macro@USB_COUNT7_RX_1_NUM_BLOCK_1_4c:macro@USB_COUNT7_RX_1_BLSIZE_1c:macro@WWDG_CR_Tc:macro@WWDG_CR_T0c:macro@WWDG_CR_T1c:macro@WWDG_CR_T2c:macro@WWDG_CR_T3c:macro@WWDG_CR_T4c:macro@WWDG_CR_T5c:macro@WWDG_CR_T6c:macro@WWDG_CR_WDGAc:macro@WWDG_CFR_Wc:macro@WWDG_CFR_W0c:macro@WWDG_CFR_W1c:macro@WWDG_CFR_W2c:macro@WWDG_CFR_W3c:macro@WWDG_CFR_W4c:macro@WWDG_CFR_W5c:macro@WWDG_CFR_W6c:macro@WWDG_CFR_WDGTBc:macro@WWDG_CFR_WDGTB0c:macro@WWDG_CFR_WDGTB1c:macro@WWDG_CFR_EWIc:macro@WWDG_SR_EWIFc:macro@SysTick_CTRL_ENABLEc:macro@SysTick_CTRL_TICKINTc:macro@SysTick_CTRL_CLKSOURCEc:macro@SysTick_CTRL_COUNTFLAGc:macro@SysTick_LOAD_RELOADc:macro@SysTick_VAL_CURRENTc:macro@SysTick_CALIB_TENMSc:macro@SysTick_CALIB_SKEWc:macro@SysTick_CALIB_NOREFc:macro@NVIC_ISER_SETENAc:macro@NVIC_ISER_SETENA_0c:macro@NVIC_ISER_SETENA_1c:macro@NVIC_ISER_SETENA_2c:macro@NVIC_ISER_SETENA_3c:macro@NVIC_ISER_SETENA_4c:macro@NVIC_ISER_SETENA_5c:macro@NVIC_ISER_SETENA_6c:macro@NVIC_ISER_SETENA_7c:macro@NVIC_ISER_SETENA_8c:macro@NVIC_ISER_SETENA_9c:macro@NVIC_ISER_SETENA_10c:macro@NVIC_ISER_SETENA_11c:macro@NVIC_ISER_SETENA_12c:macro@NVIC_ISER_SETENA_13c:macro@NVIC_ISER_SETENA_14c:macro@NVIC_ISER_SETENA_15c:macro@NVIC_ISER_SETENA_16c:macro@NVIC_ISER_SETENA_17c:macro@NVIC_ISER_SETENA_18c:macro@NVIC_ISER_SETENA_19c:macro@NVIC_ISER_SETENA_20c:macro@NVIC_ISER_SETENA_21c:macro@NVIC_ISER_SETENA_22c:macro@NVIC_ISER_SETENA_23c:macro@NVIC_ISER_SETENA_24c:macro@NVIC_ISER_SETENA_25c:macro@NVIC_ISER_SETENA_26c:macro@NVIC_ISER_SETENA_27c:macro@NVIC_ISER_SETENA_28c:macro@NVIC_ISER_SETENA_29c:macro@NVIC_ISER_SETENA_30c:macro@NVIC_ISER_SETENA_31c:macro@NVIC_ICER_CLRENAc:macro@NVIC_ICER_CLRENA_0c:macro@NVIC_ICER_CLRENA_1c:macro@NVIC_ICER_CLRENA_2c:macro@NVIC_ICER_CLRENA_3c:macro@NVIC_ICER_CLRENA_4c:macro@NVIC_ICER_CLRENA_5c:macro@NVIC_ICER_CLRENA_6c:macro@NVIC_ICER_CLRENA_7c:macro@NVIC_ICER_CLRENA_8c:macro@NVIC_ICER_CLRENA_9c:macro@NVIC_ICER_CLRENA_10c:macro@NVIC_ICER_CLRENA_11c:macro@NVIC_ICER_CLRENA_12c:macro@NVIC_ICER_CLRENA_13c:macro@NVIC_ICER_CLRENA_14c:macro@NVIC_ICER_CLRENA_15c:macro@NVIC_ICER_CLRENA_16c:macro@NVIC_ICER_CLRENA_17c:macro@NVIC_ICER_CLRENA_18c:macro@NVIC_ICER_CLRENA_19c:macro@NVIC_ICER_CLRENA_20c:macro@NVIC_ICER_CLRENA_21c:macro@NVIC_ICER_CLRENA_22c:macro@NVIC_ICER_CLRENA_23c:macro@NVIC_ICER_CLRENA_24c:macro@NVIC_ICER_CLRENA_25c:macro@NVIC_ICER_CLRENA_26c:macro@NVIC_ICER_CLRENA_27c:macro@NVIC_ICER_CLRENA_28c:macro@NVIC_ICER_CLRENA_29c:macro@NVIC_ICER_CLRENA_30c:macro@NVIC_ICER_CLRENA_31c:macro@NVIC_ISPR_SETPENDc:macro@NVIC_ISPR_SETPEND_0c:macro@NVIC_ISPR_SETPEND_1c:macro@NVIC_ISPR_SETPEND_2c:macro@NVIC_ISPR_SETPEND_3c:macro@NVIC_ISPR_SETPEND_4c:macro@NVIC_ISPR_SETPEND_5c:macro@NVIC_ISPR_SETPEND_6c:macro@NVIC_ISPR_SETPEND_7c:macro@NVIC_ISPR_SETPEND_8c:macro@NVIC_ISPR_SETPEND_9c:macro@NVIC_ISPR_SETPEND_10c:macro@NVIC_ISPR_SETPEND_11c:macro@NVIC_ISPR_SETPEND_12c:macro@NVIC_ISPR_SETPEND_13c:macro@NVIC_ISPR_SETPEND_14c:macro@NVIC_ISPR_SETPEND_15c:macro@NVIC_ISPR_SETPEND_16c:macro@NVIC_ISPR_SETPEND_17c:macro@NVIC_ISPR_SETPEND_18c:macro@NVIC_ISPR_SETPEND_19c:macro@NVIC_ISPR_SETPEND_20c:macro@NVIC_ISPR_SETPEND_21c:macro@NVIC_ISPR_SETPEND_22c:macro@NVIC_ISPR_SETPEND_23c:macro@NVIC_ISPR_SETPEND_24c:macro@NVIC_ISPR_SETPEND_25c:macro@NVIC_ISPR_SETPEND_26c:macro@NVIC_ISPR_SETPEND_27c:macro@NVIC_ISPR_SETPEND_28c:macro@NVIC_ISPR_SETPEND_29c:macro@NVIC_ISPR_SETPEND_30c:macro@NVIC_ISPR_SETPEND_31c:macro@NVIC_ICPR_CLRPENDc:macro@NVIC_ICPR_CLRPEND_0c:macro@NVIC_ICPR_CLRPEND_1c:macro@NVIC_ICPR_CLRPEND_2c:macro@NVIC_ICPR_CLRPEND_3c:macro@NVIC_ICPR_CLRPEND_4c:macro@NVIC_ICPR_CLRPEND_5c:macro@NVIC_ICPR_CLRPEND_6c:macro@NVIC_ICPR_CLRPEND_7c:macro@NVIC_ICPR_CLRPEND_8c:macro@NVIC_ICPR_CLRPEND_9c:macro@NVIC_ICPR_CLRPEND_10c:macro@NVIC_ICPR_CLRPEND_11c:macro@NVIC_ICPR_CLRPEND_12c:macro@NVIC_ICPR_CLRPEND_13c:macro@NVIC_ICPR_CLRPEND_14c:macro@NVIC_ICPR_CLRPEND_15c:macro@NVIC_ICPR_CLRPEND_16c:macro@NVIC_ICPR_CLRPEND_17c:macro@NVIC_ICPR_CLRPEND_18c:macro@NVIC_ICPR_CLRPEND_19c:macro@NVIC_ICPR_CLRPEND_20c:macro@NVIC_ICPR_CLRPEND_21c:macro@NVIC_ICPR_CLRPEND_22c:macro@NVIC_ICPR_CLRPEND_23c:macro@NVIC_ICPR_CLRPEND_24c:macro@NVIC_ICPR_CLRPEND_25c:macro@NVIC_ICPR_CLRPEND_26c:macro@NVIC_ICPR_CLRPEND_27c:macro@NVIC_ICPR_CLRPEND_28c:macro@NVIC_ICPR_CLRPEND_29c:macro@NVIC_ICPR_CLRPEND_30c:macro@NVIC_ICPR_CLRPEND_31c:macro@NVIC_IABR_ACTIVEc:macro@NVIC_IABR_ACTIVE_0c:macro@NVIC_IABR_ACTIVE_1c:macro@NVIC_IABR_ACTIVE_2c:macro@NVIC_IABR_ACTIVE_3c:macro@NVIC_IABR_ACTIVE_4c:macro@NVIC_IABR_ACTIVE_5c:macro@NVIC_IABR_ACTIVE_6c:macro@NVIC_IABR_ACTIVE_7c:macro@NVIC_IABR_ACTIVE_8c:macro@NVIC_IABR_ACTIVE_9c:macro@NVIC_IABR_ACTIVE_10c:macro@NVIC_IABR_ACTIVE_11c:macro@NVIC_IABR_ACTIVE_12c:macro@NVIC_IABR_ACTIVE_13c:macro@NVIC_IABR_ACTIVE_14c:macro@NVIC_IABR_ACTIVE_15c:macro@NVIC_IABR_ACTIVE_16c:macro@NVIC_IABR_ACTIVE_17c:macro@NVIC_IABR_ACTIVE_18c:macro@NVIC_IABR_ACTIVE_19c:macro@NVIC_IABR_ACTIVE_20c:macro@NVIC_IABR_ACTIVE_21c:macro@NVIC_IABR_ACTIVE_22c:macro@NVIC_IABR_ACTIVE_23c:macro@NVIC_IABR_ACTIVE_24c:macro@NVIC_IABR_ACTIVE_25c:macro@NVIC_IABR_ACTIVE_26c:macro@NVIC_IABR_ACTIVE_27c:macro@NVIC_IABR_ACTIVE_28c:macro@NVIC_IABR_ACTIVE_29c:macro@NVIC_IABR_ACTIVE_30c:macro@NVIC_IABR_ACTIVE_31c:macro@NVIC_IPR0_PRI_0c:macro@NVIC_IPR0_PRI_1c:macro@NVIC_IPR0_PRI_2c:macro@NVIC_IPR0_PRI_3c:macro@NVIC_IPR1_PRI_4c:macro@NVIC_IPR1_PRI_5c:macro@NVIC_IPR1_PRI_6c:macro@NVIC_IPR1_PRI_7c:macro@NVIC_IPR2_PRI_8c:macro@NVIC_IPR2_PRI_9c:macro@NVIC_IPR2_PRI_10c:macro@NVIC_IPR2_PRI_11c:macro@NVIC_IPR3_PRI_12c:macro@NVIC_IPR3_PRI_13c:macro@NVIC_IPR3_PRI_14c:macro@NVIC_IPR3_PRI_15c:macro@NVIC_IPR4_PRI_16c:macro@NVIC_IPR4_PRI_17c:macro@NVIC_IPR4_PRI_18c:macro@NVIC_IPR4_PRI_19c:macro@NVIC_IPR5_PRI_20c:macro@NVIC_IPR5_PRI_21c:macro@NVIC_IPR5_PRI_22c:macro@NVIC_IPR5_PRI_23c:macro@NVIC_IPR6_PRI_24c:macro@NVIC_IPR6_PRI_25c:macro@NVIC_IPR6_PRI_26c:macro@NVIC_IPR6_PRI_27c:macro@NVIC_IPR7_PRI_28c:macro@NVIC_IPR7_PRI_29c:macro@NVIC_IPR7_PRI_30c:macro@NVIC_IPR7_PRI_31c:macro@SCB_CPUID_REVISIONc:macro@SCB_CPUID_PARTNOc:macro@SCB_CPUID_Constantc:macro@SCB_CPUID_VARIANTc:macro@SCB_CPUID_IMPLEMENTERc:macro@SCB_ICSR_VECTACTIVEc:macro@SCB_ICSR_RETTOBASEc:macro@SCB_ICSR_VECTPENDINGc:macro@SCB_ICSR_ISRPENDINGc:macro@SCB_ICSR_ISRPREEMPTc:macro@SCB_ICSR_PENDSTCLRc:macro@SCB_ICSR_PENDSTSETc:macro@SCB_ICSR_PENDSVCLRc:macro@SCB_ICSR_PENDSVSETc:macro@SCB_ICSR_NMIPENDSETc:macro@SCB_VTOR_TBLOFFc:macro@SCB_VTOR_TBLBASEc:macro@SCB_AIRCR_VECTRESETc:macro@SCB_AIRCR_VECTCLRACTIVEc:macro@SCB_AIRCR_SYSRESETREQc:macro@SCB_AIRCR_PRIGROUPc:macro@SCB_AIRCR_PRIGROUP_0c:macro@SCB_AIRCR_PRIGROUP_1c:macro@SCB_AIRCR_PRIGROUP_2c:macro@SCB_AIRCR_PRIGROUP0c:macro@SCB_AIRCR_PRIGROUP1c:macro@SCB_AIRCR_PRIGROUP2c:macro@SCB_AIRCR_PRIGROUP3c:macro@SCB_AIRCR_PRIGROUP4c:macro@SCB_AIRCR_PRIGROUP5c:macro@SCB_AIRCR_PRIGROUP6c:macro@SCB_AIRCR_PRIGROUP7c:macro@SCB_AIRCR_ENDIANESSc:macro@SCB_AIRCR_VECTKEYc:macro@SCB_SCR_SLEEPONEXITc:macro@SCB_SCR_SLEEPDEEPc:macro@SCB_SCR_SEVONPENDc:macro@SCB_CCR_NONBASETHRDENAc:macro@SCB_CCR_USERSETMPENDc:macro@SCB_CCR_UNALIGN_TRPc:macro@SCB_CCR_DIV_0_TRPc:macro@SCB_CCR_BFHFNMIGNc:macro@SCB_CCR_STKALIGNc:macro@SCB_SHPR_PRI_Nc:macro@SCB_SHPR_PRI_N1c:macro@SCB_SHPR_PRI_N2c:macro@SCB_SHPR_PRI_N3c:macro@SCB_SHCSR_MEMFAULTACTc:macro@SCB_SHCSR_BUSFAULTACTc:macro@SCB_SHCSR_USGFAULTACTc:macro@SCB_SHCSR_SVCALLACTc:macro@SCB_SHCSR_MONITORACTc:macro@SCB_SHCSR_PENDSVACTc:macro@SCB_SHCSR_SYSTICKACTc:macro@SCB_SHCSR_USGFAULTPENDEDc:macro@SCB_SHCSR_MEMFAULTPENDEDc:macro@SCB_SHCSR_BUSFAULTPENDEDc:macro@SCB_SHCSR_SVCALLPENDEDc:macro@SCB_SHCSR_MEMFAULTENAc:macro@SCB_SHCSR_BUSFAULTENAc:macro@SCB_SHCSR_USGFAULTENAc:macro@SCB_CFSR_IACCVIOLc:macro@SCB_CFSR_DACCVIOLc:macro@SCB_CFSR_MUNSTKERRc:macro@SCB_CFSR_MSTKERRc:macro@SCB_CFSR_MMARVALIDc:macro@SCB_CFSR_IBUSERRc:macro@SCB_CFSR_PRECISERRc:macro@SCB_CFSR_IMPRECISERRc:macro@SCB_CFSR_UNSTKERRc:macro@SCB_CFSR_STKERRc:macro@SCB_CFSR_BFARVALIDc:macro@SCB_CFSR_UNDEFINSTRc:macro@SCB_CFSR_INVSTATEc:macro@SCB_CFSR_INVPCc:macro@SCB_CFSR_NOCPc:macro@SCB_CFSR_UNALIGNEDc:macro@SCB_CFSR_DIVBYZEROc:macro@SCB_HFSR_VECTTBLc:macro@SCB_HFSR_FORCEDc:macro@SCB_HFSR_DEBUGEVTc:macro@SCB_DFSR_HALTEDc:macro@SCB_DFSR_BKPTc:macro@SCB_DFSR_DWTTRAPc:macro@SCB_DFSR_VCATCHc:macro@SCB_DFSR_EXTERNALc:macro@SCB_MMFAR_ADDRESSc:macro@SCB_BFAR_ADDRESSc:macro@SCB_AFSR_IMPDEFc:macro@SET_BITc:macro@CLEAR_BITc:macro@READ_BITc:macro@CLEAR_REGc:macro@WRITE_REGc:macro@READ_REGc:macro@MODIFY_REGc:macro@STM32_TIM1c:macro@STM32_TIM2c:macro@STM32_TIM3c:macro@STM32_TIM4c:macro@STM32_TIM5c:macro@STM32_TIM6c:macro@STM32_TIM7c:macro@STM32_TIM8c:macro@STM32_TIM9c:macro@STM32_TIM10c:macro@STM32_TIM11c:macro@STM32_TIM12c:macro@STM32_TIM13c:macro@STM32_TIM14c:macro@HAL_IMPLEMENTS_COUNTERSc:macro@PLATFORM_NAMEc:macro@STM32_HSICLKc:macro@STM32_LSICLKc:macro@STM32_VOS_MASKc:macro@STM32_VOS_1P8c:macro@STM32_VOS_1P5c:macro@STM32_VOS_1P2c:macro@STM32_PLS_MASKc:macro@STM32_PLS_LEV0c:macro@STM32_PLS_LEV1c:macro@STM32_PLS_LEV2c:macro@STM32_PLS_LEV3c:macro@STM32_PLS_LEV4c:macro@STM32_PLS_LEV5c:macro@STM32_PLS_LEV6c:macro@STM32_PLS_LEV7c:macro@STM32_RTCPRE_MASKc:macro@STM32_RTCPRE_DIV2c:macro@STM32_RTCPRE_DIV4c:macro@STM32_RTCPRE_DIV8c:macro@STM32_RTCPRE_DIV16c:macro@STM32_SW_MSIc:macro@STM32_SW_HSIc:macro@STM32_SW_HSEc:macro@STM32_SW_PLLc:macro@STM32_HPRE_DIV1c:macro@STM32_HPRE_DIV2c:macro@STM32_HPRE_DIV4c:macro@STM32_HPRE_DIV8c:macro@STM32_HPRE_DIV16c:macro@STM32_HPRE_DIV64c:macro@STM32_HPRE_DIV128c:macro@STM32_HPRE_DIV256c:macro@STM32_HPRE_DIV512c:macro@STM32_PPRE1_DIV1c:macro@STM32_PPRE1_DIV2c:macro@STM32_PPRE1_DIV4c:macro@STM32_PPRE1_DIV8c:macro@STM32_PPRE1_DIV16c:macro@STM32_PPRE2_DIV1c:macro@STM32_PPRE2_DIV2c:macro@STM32_PPRE2_DIV4c:macro@STM32_PPRE2_DIV8c:macro@STM32_PPRE2_DIV16c:macro@STM32_PLLSRC_HSIc:macro@STM32_PLLSRC_HSEc:macro@STM32_MCOSEL_NOCLOCKc:macro@STM32_MCOSEL_SYSCLKc:macro@STM32_MCOSEL_HSIc:macro@STM32_MCOSEL_MSIc:macro@STM32_MCOSEL_HSEc:macro@STM32_MCOSEL_PLLc:macro@STM32_MCOSEL_LSIc:macro@STM32_MCOSEL_LSEc:macro@STM32_MCOPRE_DIV1c:macro@STM32_MCOPRE_DIV2c:macro@STM32_MCOPRE_DIV4c:macro@STM32_MCOPRE_DIV8c:macro@STM32_MCOPRE_DIV16c:macro@STM32_MSIRANGE_MASKc:macro@STM32_MSIRANGE_64Kc:macro@STM32_MSIRANGE_128Kc:macro@STM32_MSIRANGE_256Kc:macro@STM32_MSIRANGE_512Kc:macro@STM32_MSIRANGE_1Mc:macro@STM32_MSIRANGE_2Mc:macro@STM32_MSIRANGE_4Mc:macro@STM32_RTCSEL_MASKc:macro@STM32_RTCSEL_NOCLOCKc:macro@STM32_RTCSEL_LSEc:macro@STM32_RTCSEL_LSIc:macro@STM32_RTCSEL_HSEDIVc:macro@STM32_HAS_ADC1c:macro@STM32_HAS_ADC2c:macro@STM32_HAS_ADC3c:macro@STM32_HAS_ADC4c:macro@STM32_HAS_CAN1c:macro@STM32_HAS_CAN2c:macro@STM32_CAN_MAX_FILTERSc:macro@STM32_HAS_DACc:macro@STM32_ADVANCED_DMAc:macro@STM32_HAS_DMA1c:macro@STM32_HAS_DMA2c:macro@STM32_HAS_ETHc:macro@STM32_EXTI_NUM_CHANNELSc:macro@STM32_HAS_GPIOAc:macro@STM32_HAS_GPIOBc:macro@STM32_HAS_GPIOCc:macro@STM32_HAS_GPIODc:macro@STM32_HAS_GPIOEc:macro@STM32_HAS_GPIOFc:macro@STM32_HAS_GPIOGc:macro@STM32_HAS_GPIOHc:macro@STM32_HAS_GPIOIc:macro@STM32_HAS_I2C1c:macro@STM32_I2C1_RX_DMA_MSKc:macro@STM32_I2C1_RX_DMA_CHNc:macro@STM32_I2C1_TX_DMA_MSKc:macro@STM32_I2C1_TX_DMA_CHNc:macro@STM32_HAS_I2C2c:macro@STM32_I2C2_RX_DMA_MSKc:macro@STM32_I2C2_RX_DMA_CHNc:macro@STM32_I2C2_TX_DMA_MSKc:macro@STM32_I2C2_TX_DMA_CHNc:macro@STM32_HAS_I2C3c:macro@STM32_I2C3_RX_DMA_MSKc:macro@STM32_I2C3_RX_DMA_CHNc:macro@STM32_I2C3_TX_DMA_MSKc:macro@STM32_I2C3_TX_DMA_CHNc:macro@STM32_HAS_RTCc:macro@STM32_RTC_HAS_SUBSECONDSc:macro@STM32_RTC_IS_CALENDARc:macro@STM32_HAS_SDIOc:macro@STM32_HAS_SPI1c:macro@STM32_SPI1_RX_DMA_MSKc:macro@STM32_SPI1_RX_DMA_CHNc:macro@STM32_SPI1_TX_DMA_MSKc:macro@STM32_SPI1_TX_DMA_CHNc:macro@STM32_HAS_SPI2c:macro@STM32_SPI2_RX_DMA_MSKc:macro@STM32_SPI2_RX_DMA_CHNc:macro@STM32_SPI2_TX_DMA_MSKc:macro@STM32_SPI2_TX_DMA_CHNc:macro@STM32_HAS_SPI3c:macro@STM32_SPI3_RX_DMA_MSKc:macro@STM32_SPI3_RX_DMA_CHNc:macro@STM32_SPI3_TX_DMA_MSKc:macro@STM32_SPI3_TX_DMA_CHNc:macro@STM32_HAS_TIM1c:macro@STM32_HAS_TIM2c:macro@STM32_HAS_TIM3c:macro@STM32_HAS_TIM4c:macro@STM32_HAS_TIM5c:macro@STM32_HAS_TIM6c:macro@STM32_HAS_TIM7c:macro@STM32_HAS_TIM8c:macro@STM32_HAS_TIM9c:macro@STM32_HAS_TIM10c:macro@STM32_HAS_TIM11c:macro@STM32_HAS_TIM12c:macro@STM32_HAS_TIM13c:macro@STM32_HAS_TIM14c:macro@STM32_HAS_TIM15c:macro@STM32_HAS_TIM16c:macro@STM32_HAS_TIM17c:macro@STM32_HAS_TIM18c:macro@STM32_HAS_TIM19c:macro@STM32_HAS_USART1c:macro@STM32_USART1_RX_DMA_MSKc:macro@STM32_USART1_RX_DMA_CHNc:macro@STM32_USART1_TX_DMA_MSKc:macro@STM32_USART1_TX_DMA_CHNc:macro@STM32_HAS_USART2c:macro@STM32_USART2_RX_DMA_MSKc:macro@STM32_USART2_RX_DMA_CHNc:macro@STM32_USART2_TX_DMA_MSKc:macro@STM32_USART2_TX_DMA_CHNc:macro@STM32_HAS_USART3c:macro@STM32_USART3_RX_DMA_MSKc:macro@STM32_USART3_RX_DMA_CHNc:macro@STM32_USART3_TX_DMA_MSKc:macro@STM32_USART3_TX_DMA_CHNc:macro@STM32_HAS_UART4c:macro@STM32_UART4_RX_DMA_MSKc:macro@STM32_UART4_RX_DMA_CHNc:macro@STM32_UART4_TX_DMA_MSKc:macro@STM32_UART4_TX_DMA_CHNc:macro@STM32_HAS_UART5c:macro@STM32_UART5_RX_DMA_MSKc:macro@STM32_UART5_RX_DMA_CHNc:macro@STM32_UART5_TX_DMA_MSKc:macro@STM32_UART5_TX_DMA_CHNc:macro@STM32_HAS_USART6c:macro@STM32_USART6_RX_DMA_MSKc:macro@STM32_USART6_RX_DMA_CHNc:macro@STM32_USART6_TX_DMA_MSKc:macro@STM32_USART6_TX_DMA_CHNc:macro@STM32_HAS_USBc:macro@STM32_HAS_OTG1c:macro@STM32_HAS_OTG2c:macro@WWDG_IRQHandlerc:macro@PVD_IRQHandlerc:macro@TAMPER_STAMP_IRQHandlerc:macro@RTC_WKUP_IRQHandlerc:macro@FLASH_IRQHandlerc:macro@RCC_IRQHandlerc:macro@EXTI0_IRQHandlerc:macro@EXTI1_IRQHandlerc:macro@EXTI2_IRQHandlerc:macro@EXTI3_IRQHandlerc:macro@EXTI4_IRQHandlerc:macro@DMA1_Ch1_IRQHandlerc:macro@DMA1_Ch2_IRQHandlerc:macro@DMA1_Ch3_IRQHandlerc:macro@DMA1_Ch4_IRQHandlerc:macro@DMA1_Ch5_IRQHandlerc:macro@DMA1_Ch6_IRQHandlerc:macro@DMA1_Ch7_IRQHandlerc:macro@ADC1_IRQHandlerc:macro@USB_HP_IRQHandlerc:macro@USB_LP_IRQHandlerc:macro@DAC_IRQHandlerc:macro@COMP_IRQHandlerc:macro@EXTI9_5_IRQHandlerc:macro@TIM9_IRQHandlerc:macro@TIM10_IRQHandlerc:macro@TIM11_IRQHandlerc:macro@LCD_IRQHandlerc:macro@TIM2_IRQHandlerc:macro@TIM3_IRQHandlerc:macro@TIM4_IRQHandlerc:macro@I2C1_EV_IRQHandlerc:macro@I2C1_ER_IRQHandlerc:macro@I2C2_EV_IRQHandlerc:macro@I2C2_ER_IRQHandlerc:macro@SPI1_IRQHandlerc:macro@SPI2_IRQHandlerc:macro@USART1_IRQHandlerc:macro@USART2_IRQHandlerc:macro@USART3_IRQHandlerc:macro@EXTI15_10_IRQHandlerc:macro@RTC_Alarm_IRQHandlerc:macro@USB_FS_WKUP_IRQHandlerc:macro@TIM6_IRQHandlerc:macro@TIM7_IRQHandlerc:macro@STM32_HSECLK_MAXc:macro@STM32_SYSCLK_MAXc:macro@STM32_PLLVCO_MAXc:macro@STM32_PLLVCO_MINc:macro@STM32_PCLK1_MAXc:macro@STM32_PCLK2_MAXc:macro@STM32_0WS_THRESHOLDc:macro@STM32_HSI_AVAILABLEc:macro@STM32_ACTIVATE_PLLc:macro@STM32_PLLMULc:macro@STM32_PLLDIVc:macro@STM32_PLLCLKINc:macro@STM32_PLLVCOc:macro@STM32_PLLCLKOUTc:macro@STM32_MSICLKc:macro@STM32_SYSCLKc:macro@STM32_HCLKc:macro@STM32_PCLK1c:macro@STM32_PCLK2c:macro@STM_MCODIVCLKc:macro@STM_MCOCLKc:macro@STM32_HSEDIVCLKc:macro@STM_RTCCLKc:macro@STM32_ADCCLKc:macro@STM32_USBCLKc:macro@STM32_TIMCLK1c:macro@STM32_TIMCLK2c:macro@STM32_FLASHBITS1c:macro@STM32_FLASHBITS2c:macro@hal_lld_get_counter_valuec:macro@hal_lld_get_counter_frequencyc:macro@_STM32_ISR_H_c:macro@STM32_TIM2_HANDLERc:macro@STM32_TIM3_HANDLERc:macro@STM32_TIM4_HANDLERc:macro@STM32_TIM2_NUMBERc:macro@STM32_TIM3_NUMBERc:macro@STM32_TIM4_NUMBERc:macro@STM32_USART1_HANDLERc:macro@STM32_USART2_HANDLERc:macro@STM32_USART3_HANDLERc:macro@STM32_USART1_NUMBERc:macro@STM32_USART2_NUMBERc:macro@STM32_USART3_NUMBERc:macro@STM32_USB1_HP_HANDLERc:macro@STM32_USB1_LP_HANDLERc:macro@STM32_USB1_HP_NUMBERc:macro@STM32_USB1_LP_NUMBERc:macro@_STM32_DMA_H_c:macro@STM32_DMA_STREAMSc:macro@STM32_DMA_ISR_MASKc:macro@STM32_DMA_GETCHANNELc:macro@STM32_DMA_IS_VALID_PRIORITYc:macro@STM32_DMA_STREAM_IDc:macro@STM32_DMA_STREAM_ID_MSKc:macro@STM32_DMA_IS_VALID_IDc:macro@STM32_DMA_STREAMc:macro@STM32_DMA1_STREAM1c:macro@STM32_DMA1_STREAM2c:macro@STM32_DMA1_STREAM3c:macro@STM32_DMA1_STREAM4c:macro@STM32_DMA1_STREAM5c:macro@STM32_DMA1_STREAM6c:macro@STM32_DMA1_STREAM7c:macro@STM32_DMA_CR_ENc:macro@STM32_DMA_CR_TEIEc:macro@STM32_DMA_CR_HTIEc:macro@STM32_DMA_CR_TCIEc:macro@STM32_DMA_CR_DIR_MASKc:macro@STM32_DMA_CR_DIR_P2Mc:macro@STM32_DMA_CR_DIR_M2Pc:macro@STM32_DMA_CR_DIR_M2Mc:macro@STM32_DMA_CR_CIRCc:macro@STM32_DMA_CR_PINCc:macro@STM32_DMA_CR_MINCc:macro@STM32_DMA_CR_PSIZE_MASKc:macro@STM32_DMA_CR_PSIZE_BYTEc:macro@STM32_DMA_CR_PSIZE_HWORDc:macro@STM32_DMA_CR_PSIZE_WORDc:macro@STM32_DMA_CR_MSIZE_MASKc:macro@STM32_DMA_CR_MSIZE_BYTEc:macro@STM32_DMA_CR_MSIZE_HWORDc:macro@STM32_DMA_CR_MSIZE_WORDc:macro@STM32_DMA_CR_SIZE_MASKc:macro@STM32_DMA_CR_PL_MASKc:macro@STM32_DMA_CR_PLc:macro@STM32_DMA_CR_DMEIEc:macro@STM32_DMA_CR_CHSEL_MASKc:macro@STM32_DMA_CR_CHSELc:macro@STM32_DMA_ISR_FEIFc:macro@STM32_DMA_ISR_DMEIFc:macro@STM32_DMA_ISR_TEIFc:macro@STM32_DMA_ISR_HTIFc:macro@STM32_DMA_ISR_TCIFc:macro@dmaStreamSetPeripheralc:macro@dmaStreamSetMemory0c:macro@dmaStreamSetTransactionSizec:macro@dmaStreamGetTransactionSizec:macro@dmaStreamSetModec:macro@dmaStreamEnablec:macro@dmaStreamDisablec:macro@dmaStreamClearInterruptc:macro@dmaStartMemCopyc:macro@dmaWaitCompletionc:macro@_STM32_RCC_c:macro@rccEnableAPB1c:macro@rccDisableAPB1c:macro@rccResetAPB1c:macro@rccEnableAPB2c:macro@rccDisableAPB2c:macro@rccResetAPB2c:macro@rccEnableAHBc:macro@rccDisableAHBc:macro@rccResetAHBc:macro@rccEnableADC1c:macro@rccDisableADC1c:macro@rccResetADC1c:macro@rccEnableDMA1c:macro@rccDisableDMA1c:macro@rccResetDMA1c:macro@rccEnablePWRInterfacec:macro@rccDisablePWRInterfacec:macro@rccResetPWRInterfacec:macro@rccEnableI2C1c:macro@rccDisableI2C1c:macro@rccResetI2C1c:macro@rccEnableI2C2c:macro@rccDisableI2C2c:macro@rccResetI2C2c:macro@rccEnableSPI1c:macro@rccDisableSPI1c:macro@rccResetSPI1c:macro@rccEnableSPI2c:macro@rccDisableSPI2c:macro@rccResetSPI2c:macro@rccEnableTIM2c:macro@rccDisableTIM2c:macro@rccResetTIM2c:macro@rccEnableTIM3c:macro@rccDisableTIM3c:macro@rccResetTIM3c:macro@rccEnableTIM4c:macro@rccDisableTIM4c:macro@rccResetTIM4c:macro@rccEnableUSART1c:macro@rccDisableUSART1c:macro@rccResetUSART1c:macro@rccEnableUSART2c:macro@rccDisableUSART2c:macro@rccResetUSART2c:macro@rccEnableUSART3c:macro@rccDisableUSART3c:macro@rccResetUSART3c:macro@rccEnableUSBc:macro@rccDisableUSBc:macro@rccResetUSBc:macro@_IO_CHANNEL_H_c:macro@_base_channel_methodsc:macro@_base_channel_datac:macro@chnPutTimeoutc:macro@chnGetTimeoutc:macro@chnWritec:macro@chnWriteTimeoutc:macro@chnReadc:macro@chnReadTimeoutc:macro@CHN_NO_ERRORc:macro@CHN_CONNECTEDc:macro@CHN_DISCONNECTEDc:macro@CHN_INPUT_AVAILABLEc:macro@CHN_OUTPUT_EMPTYc:macro@CHN_TRANSMISSION_ENDc:macro@_base_asynchronous_channel_methodsc:macro@_base_asynchronous_channel_datac:macro@chnGetEventSourcec:macro@chnAddFlagsIc:macro@_IO_BLOCK_H_c:macro@_base_block_device_methodsc:macro@_base_block_device_datac:macro@blkGetDriverStatec:macro@blkIsTransferringc:macro@blkIsInsertedc:macro@blkIsWriteProtectedc:macro@blkConnectc:macro@blkDisconnectc:macro@blkReadc:macro@blkWritec:macro@blkSyncc:macro@blkGetInfoc:macro@_MMCSD_H_c:macro@_TM_H_c:macro@tmStartMeasurementc:macro@tmStopMeasurementc:macro@_PAL_H_c:macro@PAL_MODE_RESETc:macro@PAL_MODE_UNCONNECTEDc:macro@PAL_MODE_INPUTc:macro@PAL_MODE_INPUT_PULLUPc:macro@PAL_MODE_INPUT_PULLDOWNc:macro@PAL_MODE_INPUT_ANALOGc:macro@PAL_MODE_OUTPUT_PUSHPULLc:macro@PAL_MODE_OUTPUT_OPENDRAINc:macro@PAL_LOWc:macro@PAL_HIGHc:macro@_PAL_LLD_H_c:macro@PAL_STM32_MODE_MASKc:macro@PAL_STM32_MODE_INPUTc:macro@PAL_STM32_MODE_OUTPUTc:macro@PAL_STM32_MODE_ALTERNATEc:macro@PAL_STM32_MODE_ANALOGc:macro@PAL_STM32_OTYPE_MASKc:macro@PAL_STM32_OTYPE_PUSHPULLc:macro@PAL_STM32_OTYPE_OPENDRAINc:macro@PAL_STM32_OSPEED_MASKc:macro@PAL_STM32_OSPEED_LOWESTc:macro@PAL_STM32_OSPEED_MID1c:macro@PAL_STM32_OSPEED_MID2c:macro@PAL_STM32_OSPEED_HIGHESTc:macro@PAL_STM32_PUDR_MASKc:macro@PAL_STM32_PUDR_FLOATINGc:macro@PAL_STM32_PUDR_PULLUPc:macro@PAL_STM32_PUDR_PULLDOWNc:macro@PAL_STM32_ALTERNATE_MASKc:macro@PAL_STM32_ALTERNATEc:macro@PAL_MODE_ALTERNATEc:macro@PAL_IOPORTS_WIDTHc:macro@PAL_WHOLE_PORTc:macro@IOPORT1c:macro@IOPORT2c:macro@IOPORT3c:macro@IOPORT4c:macro@IOPORT5c:macro@IOPORT8c:macro@pal_lld_initc:macro@pal_lld_readportc:macro@pal_lld_readlatchc:macro@pal_lld_writeportc:macro@pal_lld_setportc:macro@pal_lld_clearportc:macro@pal_lld_writegroupc:macro@pal_lld_setgroupmodec:macro@pal_lld_writepadc:macro@PAL_PORT_BITc:macro@PAL_GROUP_MASKc:macro@_IOBUS_DATAc:macro@IOBUS_DECLc:macro@palInitc:macro@palReadPortc:macro@palReadLatchc:macro@palWritePortc:macro@palSetPortc:macro@palClearPortc:macro@palTogglePortc:macro@palReadGroupc:macro@palWriteGroupc:macro@palSetGroupModec:macro@palReadPadc:macro@palWritePadc:macro@palSetPadc:macro@palClearPadc:macro@palTogglePadc:macro@palSetPadModec:macro@_ADC_H_c:macro@_ADC_LLD_H_c:macro@ADC_CR2_EXTSEL_SRCc:macro@ADC_CCR_ADCPRE_DIV1c:macro@ADC_CCR_ADCPRE_DIV2c:macro@ADC_CCR_ADCPRE_DIV4c:macro@ADC_CHANNEL_IN0c:macro@ADC_CHANNEL_IN1c:macro@ADC_CHANNEL_IN2c:macro@ADC_CHANNEL_IN3c:macro@ADC_CHANNEL_IN4c:macro@ADC_CHANNEL_IN5c:macro@ADC_CHANNEL_IN6c:macro@ADC_CHANNEL_IN7c:macro@ADC_CHANNEL_IN8c:macro@ADC_CHANNEL_IN9c:macro@ADC_CHANNEL_IN10c:macro@ADC_CHANNEL_IN11c:macro@ADC_CHANNEL_IN12c:macro@ADC_CHANNEL_IN13c:macro@ADC_CHANNEL_IN14c:macro@ADC_CHANNEL_IN15c:macro@ADC_CHANNEL_SENSORc:macro@ADC_CHANNEL_VREFINTc:macro@ADC_CHANNEL_IN18c:macro@ADC_CHANNEL_IN19c:macro@ADC_CHANNEL_IN20c:macro@ADC_CHANNEL_IN21c:macro@ADC_CHANNEL_IN22c:macro@ADC_CHANNEL_IN23c:macro@ADC_CHANNEL_IN24c:macro@ADC_CHANNEL_IN25c:macro@ADC_SAMPLE_4c:macro@ADC_SAMPLE_9c:macro@ADC_SAMPLE_16c:macro@ADC_SAMPLE_24c:macro@ADC_SAMPLE_48c:macro@ADC_SAMPLE_96c:macro@ADC_SAMPLE_192c:macro@ADC_SAMPLE_384c:macro@STM32_ADC_ADCPREc:macro@STM32_DMA_REQUIREDc:macro@ADC_SQR1_NUM_CHc:macro@ADC_SQR5_SQ1_Nc:macro@ADC_SQR5_SQ2_Nc:macro@ADC_SQR5_SQ3_Nc:macro@ADC_SQR5_SQ4_Nc:macro@ADC_SQR5_SQ5_Nc:macro@ADC_SQR5_SQ6_Nc:macro@ADC_SQR4_SQ7_Nc:macro@ADC_SQR4_SQ8_Nc:macro@ADC_SQR4_SQ9_Nc:macro@ADC_SQR4_SQ10_Nc:macro@ADC_SQR4_SQ11_Nc:macro@ADC_SQR4_SQ12_Nc:macro@ADC_SQR3_SQ13_Nc:macro@ADC_SQR3_SQ14_Nc:macro@ADC_SQR3_SQ15_Nc:macro@ADC_SQR3_SQ16_Nc:macro@ADC_SQR3_SQ17_Nc:macro@ADC_SQR3_SQ18_Nc:macro@ADC_SQR2_SQ19_Nc:macro@ADC_SQR2_SQ20_Nc:macro@ADC_SQR2_SQ21_Nc:macro@ADC_SQR2_SQ22_Nc:macro@ADC_SQR2_SQ23_Nc:macro@ADC_SQR2_SQ24_Nc:macro@ADC_SQR1_SQ25_Nc:macro@ADC_SQR1_SQ26_Nc:macro@ADC_SQR1_SQ27_Nc:macro@ADC_SMPR3_SMP_AN0c:macro@ADC_SMPR3_SMP_AN1c:macro@ADC_SMPR3_SMP_AN2c:macro@ADC_SMPR3_SMP_AN3c:macro@ADC_SMPR3_SMP_AN4c:macro@ADC_SMPR3_SMP_AN5c:macro@ADC_SMPR3_SMP_AN6c:macro@ADC_SMPR3_SMP_AN7c:macro@ADC_SMPR3_SMP_AN8c:macro@ADC_SMPR3_SMP_AN9c:macro@ADC_SMPR2_SMP_AN10c:macro@ADC_SMPR2_SMP_AN11c:macro@ADC_SMPR2_SMP_AN12c:macro@ADC_SMPR2_SMP_AN13c:macro@ADC_SMPR2_SMP_AN14c:macro@ADC_SMPR2_SMP_AN15c:macro@ADC_SMPR2_SMP_SENSORc:macro@ADC_SMPR2_SMP_VREFc:macro@ADC_SMPR2_SMP_AN18c:macro@ADC_SMPR2_SMP_AN19c:macro@ADC_SMPR1_SMP_AN20c:macro@ADC_SMPR1_SMP_AN21c:macro@ADC_SMPR1_SMP_AN22c:macro@ADC_SMPR1_SMP_AN23c:macro@ADC_SMPR1_SMP_AN24c:macro@ADC_SMPR1_SMP_AN25c:macro@_adc_reset_ic:macro@_adc_reset_sc:macro@_adc_wakeup_isrc:macro@_adc_timeout_isrc:macro@_adc_isr_half_codec:macro@_adc_isr_full_codec:macro@_adc_isr_error_codec:macro@_CAN_H_c:macro@_EXT_H_c:macro@_GPT_H_c:macro@_I2C_H_c:macro@_ICU_H_c:macro@_MAC_H_c:macro@_PWM_H_c:macro@PWM_OUTPUT_MASKc:macro@PWM_OUTPUT_DISABLEDc:macro@PWM_OUTPUT_ACTIVE_HIGHc:macro@PWM_OUTPUT_ACTIVE_LOWc:macro@_PWM_LLD_H_c:macro@PWM_CHANNELSc:macro@PWM_COMPLEMENTARY_OUTPUT_MASKc:macro@PWM_COMPLEMENTARY_OUTPUT_DISABLEDc:macro@PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGHc:macro@PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOWc:macro@STM32_PWM_USE_ADVANCEDc:macro@STM32_PWM_USE_TIM1c:macro@STM32_PWM_USE_TIM5c:macro@STM32_PWM_USE_TIM8c:macro@STM32_PW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