Rev 3092 – kakl – 4449 d 18 h (2012-09-02 13:40:37)
Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL.
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CPLD_FPGA
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S3AN01B/
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PCB/
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SCH/
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VHDL/
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PrjInfo.txt
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S3AN01B_Bot_Small.jpg
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