Rev Age Author Path Log message Diff Changes
1985 4795 d 22 h kaklik /Designs/Tools/LOGSCOPE/SW/ firmware k logickemu analyzatoru Diff
/Designs/Tools/LOGSCOPE/SW/README.en.txt
1984 4796 d 2 h kaklik /Designs/Tools/LOGSCOPE/SW/ pridan firmware pro logicky analyzator Diff
/Designs/Tools/LOGSCOPE/SW
/Designs/Tools/LOGSCOPE/SW/fw.hex
1983 4796 d 3 h kaklik /Designs/Tools/LOGSCOPE/ Diff
/Designs/Tools/LOGSCOPE/PrjInfo.txt
/Designs/Tools/LOGSCOPE/SCH
1982 4796 d 3 h kaklik /Designs/Tools/LOGSCOPE/ pridan navod na vyrobu logickeho analyzatoru Diff
/Designs/Tools/LOGSCOPE
/Designs/Tools/LOGSCOPE/DOC
/Designs/Tools/LOGSCOPE/DOC/HTML
/Designs/Tools/LOGSCOPE/DOC/SRC
1981 4796 d 22 h miho /Articles/Texts/Sluneční články/DOC/HTML/ Oprava odkazu Diff
/Articles/Texts/Sluneční články/DOC/HTML/Sluneční články 1.cs.html
1980 4800 d 0 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ pokus o zprovozneni mericiho modu 1.
V tomto stavu ale asi nefunguje ani mereni teploty.
Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1979 4800 d 3 h kaklik /Library/DirStructure/Design/ vytvorena vzrorova slozka pro design. Diff
/Library/DirStructure/Design
/Library/DirStructure/Design/CAM_AMA
/Library/DirStructure/Design/CAM_DOC
/Library/DirStructure/Design/CAM_PROFI
/Library/DirStructure/Design/PCB
1978 4800 d 6 h kaklik /Modules/CommRF/ZIGBEE01A/ pridan popisek Diff
/Modules/CommRF/ZIGBEE01A/PrjInfo.txt
1977 4800 d 6 h kaklik /Modules/ založen nový modul pro RF směšovač.. Diff
/Modules/CommRF/RFMIX01A
/Modules/CommRF/RFMIX01A/PrjInfo.txt
/Modules/CommRF/RFMIX01A/pdf
/Modules/CommRF/RFMIX01A/pdf/AD8343.pdf
/Modules/Clock/CLKHUB02A/PrjInfo.txt
1976 4801 d 1 h kaklik /Modules/CommSerial/USBIO01A/ doplneni anglickeho popisku. Diff
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.en.pdf
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.pdf
/Modules/CommSerial/USBIO01A/PrjInfo.txt
1975 4801 d 19 h kakl /Designs/LABduino/DOC/ Do navodu pridan Wiring. Diff
/Designs/LABduino/DOC/LABduino.cs.pdf
/Designs/LABduino/DOC/LABduino.doc
1974 4804 d 23 h kakl /Designs/LABduino/DOC/ Pridana tabulka prirazeni vstupu. Diff
/Designs/LABduino/DOC/LABduino.cs.pdf
/Designs/LABduino/DOC/LABduino.doc
1973 4805 d 0 h kakl /Designs/LABduino/DOC/ Zmena formatovani, aby nebyla pretrzena tabulka. Diff
/Designs/LABduino/DOC/LABduino.cs.pdf
/Designs/LABduino/DOC/LABduino.doc
1972 4805 d 0 h kakl /Designs/LABduino/ Diff
/Designs/LABduino/DOC
/Designs/LABduino/doc
1971 4805 d 0 h kakl /Designs/LABduino/doc/ Prejmenovan navod. Diff
/Designs/LABduino/doc/LABduino.cs.pdf
/Designs/LABduino/doc/LABduino.doc
1970 4805 d 0 h kakl /Designs/LABduino/doc/ Prejmenovano. Diff
/Designs/LABduino/doc/LABduino_HowTo.doc
/Designs/LABduino/doc/LABduino_HowTo.pdf
1969 4805 d 0 h kakl /Designs/LABduino/ Jak postavir z MLABu Arduino. Diff
/Designs/LABduino
/Designs/LABduino/LABduino_Big.jpg
/Designs/LABduino/LABduino_Small.jpg
/Designs/LABduino/PrjInfo.txt
/Designs/LABduino/doc
/Designs/LABduino/doc/LABduino_HowTo.doc
/Designs/LABduino/doc/LABduino_HowTo.pdf
1968 4805 d 8 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/ Doplněna PDF verze dokumentace S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf
1967 4805 d 16 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ oprava chyby ve vypoctu casu a implementace mereni teploty. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1966 4805 d 17 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prvni implementace prepoctu na realne jednotky. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/GP2.h
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1965 4805 d 20 h kaklik /Modules/TDC/GP201A/ implementace i posledni primitivy pro nastavovani registru Diff
/Modules/TDC/GP201A/DOC/datasheet.txt
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1964 4805 d 21 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prepsani cteni dat do puvodnich primitiv. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1963 4806 d 2 h kaklik /Designs/Tools/reflow2/SW/ programovani reflow procesu. Diff
/Designs/Tools/reflow2/SW/reflow.PJT
/Designs/Tools/reflow2/SW/reflow.c
/Designs/Tools/reflow2/SW/reflow.hex
1962 4806 d 17 h kaklik /Modules/Sensors/IUC01A/ vytvoreni modulu pro proudove cidlo. Diff
/Modules/Sensors/IUC01A
/Modules/Sensors/IUC01A/CAM_DOC/IUC01.pdf
/Modules/Sensors/IUC01A/DOC/IUC01A.pdf
/Modules/Sensors/IUC01A/PCB/IUC01.pcb
/Modules/Sensors/IUC01A/SCH/IUC01.DSN
/Modules/Sensors/IUC01A/SCH/IUC01.pdf
/Modules/Sensors/IUC01A/PrjInfo.txt
1961 4806 d 19 h kaklik /Designs/Thermometer/ dokumentace Diff
/Designs/Thermometer/DOC
/Designs/Thermometer/DOC/SRC
/Designs/Thermometer/DOC/SRC/Thermometer_Big.JPG
/Designs/Thermometer/Thermometer_Small.JPG
1960 4806 d 20 h kaklik /Designs/Tools/reflow2/SW/ naprogramovani prvni casti reflow procesu Diff
/Designs/Tools/reflow2/SW/process.h
/Designs/Tools/reflow2/SW/reflow.PJT
/Designs/Tools/reflow2/SW/reflow.c
/Designs/Tools/reflow2/SW/reflow.hex
1959 4807 d 0 h kakl /Designs/MRAKOMER4/SW/HEX/ Pro Sibir. Diff
/Designs/MRAKOMER4/SW/HEX/irmrak4.hex
1958 4807 d 0 h kakl /Designs/MRAKOMER4/SW/ Pro Sibir. Diff
/Designs/MRAKOMER4/SW/HEX/irmrak4.hex
/Designs/MRAKOMER4/SW/irmrak4.c
1957 4807 d 0 h kaklik /Designs/Tools/reflow2/SW/ zkalibrovani teplomeru v troube Diff
/Designs/Tools/reflow2/SW/reflow.c
/Designs/Tools/reflow2/SW/reflow.hex
1956 4807 d 3 h kaklik /Modules/PIC/PICPROGUSB02A/ vylepseni fotografii Diff
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_Big.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Small.jpg
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Big.jpg
1955 4807 d 4 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
1954 4807 d 4 h miho /Modules/CPLD_FPGA/S3AN01A/ Dokumentace pro S3AN01A (podomácku vyrobená verze) Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1953 4807 d 19 h kaklik /Modules/Clock/CLKGEN01B/DOC/SRC/ prejmenovani podle konvence Diff
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1952 4807 d 19 h kaklik /Modules/Clock/CLKGEN01B/DOC/ oprava preklepu Diff
/Modules/Clock/CLKGEN01B/DOC/DG8SAQ_emulator.cs.pdf
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1951 4812 d 3 h kakl /Designs/dum/SW/2patra/ Pridan datasheet k PIC na hvezdarnu. Diff
/Designs/dum/SW/2patra/18f8310.pdf
1950 4812 d 9 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B doplněny obrázky (pro dokumentaci) Diff
/Modules/CPLD_FPGA/S3AN01B/DOC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg
1949 4812 d 17 h kaklik /Designs/Thermometer/ prejmenovani souboru podle konvence Diff
/Designs/Thermometer/PrjInfo.txt
1948 4812 d 17 h kaklik /Designs/GPSnavigator/DOC/ prejmenovani souboru podle konvence Diff
/Designs/GPSnavigator/DOC/GPSnavigator.cs.pdf
/Designs/GPSnavigator/DOC/GPSnavigator.pdf
1947 4812 d 17 h kaklik / prejmenovani souboru podle konvence Diff
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.cs.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.cs.pdf
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.pdf
1946 4812 d 22 h kaklik /Modules/PIC/PIC18F8xTQ8001A/DOC/ aktualizace dokumentace Diff
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.cs.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.en.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8x2001A.cs.pdf