2947 |
4125 d 2 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
|
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/EEPROM /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/EEPROM/Readme.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/EEPROM/XVC_FT220X.xml /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/EEPROM/XVC_FT230X.xml /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/EEPROM/prog_EEPROM.bat /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_SOFTWARE_Small.png |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/prog_EEPROM.bat |
|
2942 |
4126 d 6 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ |
Uvolněna Linux verze programu mlab_xvcd (ověřeno na Ubuntu 12.04LTS) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/10-MLAB-XVC-FTDI.rules /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/linuxBuild.sh |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd_i386 /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp |
|
2941 |
4126 d 6 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ |
Program mlab_xvcd po restrukturalizaci zdrojáků a opravě cest a komentářů (formální změny) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h |
|
2940 |
4130 d 1 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ |
Rozšíření programu mlab_xvcd o podporu pro Linux (Linux verze ještě nutno doladit, funguje jen někde). |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd_i386 /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_linux_i386 /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_win32 /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_win32/ftd2xx.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/lib_win32/ftd2xx.lib |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.lib |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/!____!.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.h |
|
2939 |
4130 d 14 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Dokončena dokumentace modulu XVC_FT220X02A |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs.html /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image001.jpg /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image002.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image003.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image004.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image005.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image006.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image007.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image008.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image009.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/!____!.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A.cs.doc /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A_Bot.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A_Top.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_BOM.xls |
|
2937 |
4132 d 0 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
Přidány obrázky do sekce XVC |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/SchemaCyklu_Small.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/XVC_FT220X02A_Bot_Small.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/XVC_FT220X02A_Top_Small.JPG |
|
2936 |
4132 d 0 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/ |
Dokončena dokumentace modulu XVC_FT220X01A (včetně HTML verze) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs.html /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image001.jpg /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image002.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image003.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image004.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image005.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image006.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image007.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image008.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML/XVC_FT220X01A.cs_soubory/image009.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/FT_Prog.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/FT_Prog_Description.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/IMPACT_Plugin.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/IMPACT_Prog.png /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/IdeovéSchéma.odg /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/XVC_FT220X01A.cs.doc /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/XVC_FT220X01A.cs.pdf |
|
2935 |
4133 d 12 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ |
Oprava ošetření chybových stavů programu mlab_xvcd.exe (test odpojení kabelu během čekání na accept) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.h |
|
2933 |
4136 d 1 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ |
Zlepšení chybových výpisů (vícenásobné spuštění programu a zařízení používané jiným programem) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp |
|
2932 |
4136 d 2 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Aktualizace SCH a PCB souborů (opravy součástek) pro XVC_FT220X02A (jen formální změny a změny hodnot) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_BOM.xls |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.ASC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.DSN /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_SCH.PDF |
|
2931 |
4136 d 2 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/ |
Aktualizace SCH a PCB souborů (opravy součástek) pro XVC_FT220X01A (jen formální změny a změny hodnot) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A_BOM.xls |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB/XVC_FT220X01A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.ASC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.DSN /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A_SCH.pdf |
|
2930 |
4136 d 10 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/ |
Doplněna konfigurace pro obvod FT230XS pro modul XVC_FT220X |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT230X.xml /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT230X_Original.xml |
|
2929 |
4136 d 15 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/ |
Přidána dávka pro programování EEPROM obvodu FTDI modulu XVC_FT220X |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/XVC_FT220X.xml /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/EEPROM/prog_EEPROM.bat |
|
2879 |
4159 d 14 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Oprava M1 (maskování FIDU značek). |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt |
|
2878 |
4163 d 13 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Posunul jsem některé SMD součástky aby se nedotýkaly otvory v masce. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/T2_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_REAL.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/V1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/P1.pho /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb |
|
2874 |
4167 d 13 h |
kaklik |
/ |
zapis pripominek ke konstrukci modulu |
Diff |
/Designs/HAM Constructions/SDRX01A/DOC/SRC/mereniSDRX.txt /Designs/Measuring_instruments/ABL01A/SW/models /Designs/Measuring_instruments/ABL01A/SW/models/list.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/XVC_FT220X02A.gvp /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt /Modules/CommSerial/I2CHUB02A/TODO.txt |
/Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.brd /Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.sch |
|
2856 |
4170 d 9 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Nový modul XVC_FT220X02A (odvozený z XVC_FT220X01A), zatím bez dokumentace. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/T2_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_REAL.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/V1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/drill.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/P1.pho /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/T2.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PrjInfo.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.ASC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.DSN /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_SCH.PDF |
|
2697 |
4252 d 7 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/ |
Program mlab_xvcd.exe včetně zdrojáků. Obslužný program Xilinx Virtual Cable pro Windows a FTDI. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/PrjInfo.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/!____!.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.lib /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp /Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.h |
|
2682 |
4262 d 12 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/ |
Doplněny technologické a dokumentační výstupy XVC_FT220X01A, chybí návod, BOM a dávka pro naprogramování EEPROM. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/DRILL.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/V1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/XVC_FT220X01A_Bot_Big.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/XVC_FT220X01A_Top_Big.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A_SCH.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/XVC_FT220X01A_Bot_Small.JPG /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/XVC_FT220X01A_Top_Small.JPG |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB/XVC_FT220X01A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.ASC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.DSN |
|
2681 |
4266 d 2 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
Oprava popisného souboru (formální změna) |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/DirInfo.txt |
/Modules/CPLD_FPGA/XILINX_XVC/PrjInfo.txt |
|
2680 |
4266 d 3 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
Nový modul XVC s FT220X (zatím jen design soubory). Čeká na otestování. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC /Modules/CPLD_FPGA/XILINX_XVC/PrjInfo.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA/T2_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA/V1_AMA.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/P1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/T2.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB/XVC_FT220X01A.pcb /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PrjInfo.txt /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.ASC /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.DSN |
|
2534 |
4371 d 9 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ |
Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
2533 |
4371 d 9 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pridano automaticke verzovani. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
2528 |
4375 d 23 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf |
|
2338 |
4628 d 7 h |
miho |
/Modules/CPLD_FPGA/ |
Opravena cesta k ikoně |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html |
|
2337 |
4628 d 7 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/ |
Doplněna HTML verze dokumentace pro S3AN01B |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image001.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image002.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image003.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image004.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image005.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image006.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image007.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image008.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image009.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image010.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image011.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image012.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image013.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image014.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image015.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image016.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image017.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image018.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image019.jpg |
|
2336 |
4628 d 9 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
Aktualizovaná HW dokumentace desky S3AN01B s obvodem FPGA XILINX Sparatn3AN |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/S3AN01B_HW_Reference.cs.pdf /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_HW_Reference.cs.doc |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
2335 |
4629 d 0 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/ |
Rozepsaná dokumentace pro FPGA desku S3AN01B |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
|
1968 |
4866 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/ |
Doplněna PDF verze dokumentace S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf |
|
1955 |
4868 d 12 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ |
|
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg |
|
1954 |
4868 d 12 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
Dokumentace pro S3AN01A (podomácku vyrobená verze) |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc |
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
1950 |
4873 d 16 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B doplněny obrázky (pro dokumentaci) |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC /Modules/CPLD_FPGA/S3AN01B/DOC/SRC /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg |
|
1937 |
4880 d 9 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/PCB/ |
Aktualizovány hodnoty součástek (synchronizace se schématem). |
Diff |
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb |
|
1936 |
4880 d 10 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). |
Diff |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
1935 |
4880 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN |
|
1906 |
4901 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A doplnění obrázků |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg |
|
1899 |
4902 d 7 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A je již zastaralá konstrukce |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
1898 |
4902 d 7 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B revize desky S3AN01A (s opravami) |
Diff |
/Modules/CPLD_FPGA/S3AN01B /Modules/CPLD_FPGA/S3AN01B/CAM_AMA /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO /Modules/CPLD_FPGA/S3AN01B/PCB /Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb /Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt /Modules/CPLD_FPGA/S3AN01B/SCH /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB /Modules/CPLD_FPGA/S3AN01B/VHDL |
|
1897 |
4902 d 7 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
S3AN01A doplněny texty |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1896 |
4906 d 5 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|