Rev Age Author Path Log message Diff
1572 5142 d 10 h kaklik / poznamky problemu Diff
1555 5170 d 18 h kaklik /Modules/Clock/ pokus s ladenim delky spoju Diff
1548 5181 d 6 h kaklik /Modules/Clock/ aktualizace popisu modulů. Diff
1547 5181 d 6 h kaklik /Modules/Clock/CLKGEN01A/ Fotky LO. Diff
1546 5184 d 3 h kaklik /Modules/Clock/CLKGEN01A/ seznam chyb. Diff
1545 5184 d 4 h kaklik /Modules/Clock/CLKGEN01A/ potisk Diff
1544 5185 d 5 h kaklik / Diff
1543 5185 d 6 h kaklik /Modules/Clock/CLKGEN01A/ vymena CAM vystupu Diff
1542 5185 d 7 h kaklik /Modules/Clock/CLKGEN01A/ generovani technologickych dat. Diff
1541 5185 d 19 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1540 5185 d 20 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1539 5185 d 20 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1531 5202 d 19 h kaklik /Modules/Clock/CLKGEN01A/ pridani chybejicich terminacnich odporu.. Diff
1530 5203 d 3 h kaklik /Modules/Clock/CLKGEN01A/ Temer konecna verze PCB pro Si570. Respektive Si5XX Diff
1529 5203 d 4 h kaklik /Modules/Clock/CLKGEN01A/ Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru. Diff
1528 5203 d 5 h kaklik /Modules/ Diff
1527 5203 d 7 h kaklik /Modules/Clock/CLKGEN01A/SCH/ pridani zapomenutych der a fidu znacek Diff
1526 5203 d 21 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1525 5203 d 21 h kaklik /Modules/Clock/CLKGEN01A/PCB/ zacatek prace na plosnem spoji. Diff
1524 5204 d 2 h kaklik /Modules/Clock/CLKGEN01A/SCH/ export dat pro PADs. Diff
1523 5204 d 2 h kaklik /Modules/Clock/CLKGEN01A/SCH/ Diff
1522 5205 d 0 h kaklik /Modules/Clock/CLKGEN01A/ pridani zdroje Diff
1521 5206 d 21 h kaklik /Modules/ schema modulu pro generovani hodin. Diff
1519 5207 d 22 h kaklik /Modules/ popisek modulu. Diff
1518 5207 d 22 h kaklik /Modules/Clock/ datasheety pouzitych obvodu jsou misto dokumentace. Diff
1517 5208 d 0 h kaklik /Modules/ presunuti a vytvoreni noveho modulu pro hodiny Diff