| 2879 |
4248 d 17 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Oprava M1 (maskování FIDU značek). |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt |
|
| 2878 |
4252 d 16 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Posunul jsem některé SMD součástky aby se nedotýkaly otvory v masce. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/T2_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_REAL.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/P1.pho
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb |
|
| 2874 |
4256 d 15 h |
kaklik |
/ |
zapis pripominek ke konstrukci modulu |
Diff |
/Designs/HAM Constructions/SDRX01A/DOC/SRC/mereniSDRX.txt
/Designs/Measuring_instruments/ABL01A/SW/models
/Designs/Measuring_instruments/ABL01A/SW/models/list.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/XVC_FT220X02A.gvp
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/TODO.txt
/Modules/CommSerial/I2CHUB02A/TODO.txt |
/Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.brd
/Modules/CommSerial/I2CHUB02A/SCH_PCB/untitled.sch |
|
| 2856 |
4259 d 12 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ |
Nový modul XVC_FT220X02A (odvozený z XVC_FT220X01A), zatím bez dokumentace. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/T2_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_AMA/V1_REAL.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/drill.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/P1.pho
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/T2.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PrjInfo.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.ASC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A.DSN
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_SCH.PDF |
|
| 2697 |
4341 d 10 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/ |
Program mlab_xvcd.exe včetně zdrojáků. Obslužný program Xilinx Virtual Cable pro Windows a FTDI. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/PrjInfo.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/!____!.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/BIN/mlab_xvcd.exe
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.h
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/ftd2xx.lib
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.cpp
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd.h
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.cpp
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/mlab_xvcd_port_FTDI.h |
|
| 2682 |
4351 d 15 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/ |
Doplněny technologické a dokumentační výstupy XVC_FT220X01A, chybí návod, BOM a dávka pro naprogramování EEPROM. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/HTML
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/XVC_FT220X01A_Bot_Big.JPG
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/XVC_FT220X01A_Top_Big.JPG
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A_SCH.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/XVC_FT220X01A_Bot_Small.JPG
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/XVC_FT220X01A_Top_Small.JPG |
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB/XVC_FT220X01A.pcb
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.ASC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.DSN |
|
| 2681 |
4355 d 5 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
Oprava popisného souboru (formální změna) |
Diff |
| /Modules/CPLD_FPGA/XILINX_XVC/DirInfo.txt |
| /Modules/CPLD_FPGA/XILINX_XVC/PrjInfo.txt |
|
| 2680 |
4355 d 5 h |
miho |
/Modules/CPLD_FPGA/XILINX_XVC/ |
Nový modul XVC s FT220X (zatím jen design soubory). Čeká na otestování. |
Diff |
/Modules/CPLD_FPGA/XILINX_XVC
/Modules/CPLD_FPGA/XILINX_XVC/PrjInfo.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA/T2_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_AMA/V1_AMA.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/P1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/T2.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PCB/XVC_FT220X01A.pcb
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/PrjInfo.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.ASC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/SCH/XVC_FT220X01A.DSN |
|
| 2534 |
4460 d 11 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ |
Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. |
Diff |
| /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
| 2533 |
4460 d 11 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pridano automaticke verzovani. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
| 2528 |
4465 d 2 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf |
|
| 2338 |
4717 d 10 h |
miho |
/Modules/CPLD_FPGA/ |
Opravena cesta k ikoně |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html |
|
| 2337 |
4717 d 10 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/ |
Doplněna HTML verze dokumentace pro S3AN01B |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image001.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image002.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image003.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image004.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image005.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image006.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image007.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image008.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image009.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image010.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image011.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image012.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image013.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image014.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image015.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image016.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image017.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image018.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image019.jpg |
|
| 2336 |
4717 d 12 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
Aktualizovaná HW dokumentace desky S3AN01B s obvodem FPGA XILINX Sparatn3AN |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/S3AN01B_HW_Reference.cs.pdf
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_HW_Reference.cs.doc |
| /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
| /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
| 2335 |
4718 d 3 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/ |
Rozepsaná dokumentace pro FPGA desku S3AN01B |
Diff |
| /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
|
| 1968 |
4955 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/ |
Doplněna PDF verze dokumentace S3AN01A |
Diff |
| /Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf |
|
| 1955 |
4957 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ |
|
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg |
|
| 1954 |
4957 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
Dokumentace pro S3AN01A (podomácku vyrobená verze) |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc |
| /Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
| 1950 |
4962 d 19 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B doplněny obrázky (pro dokumentaci) |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg |
|
| 1937 |
4969 d 12 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/PCB/ |
Aktualizovány hodnoty součástek (synchronizace se schématem). |
Diff |
| /Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb |
|
| 1936 |
4969 d 12 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). |
Diff |
| /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
| 1935 |
4969 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN |
|
| 1906 |
4990 d 17 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A doplnění obrázků |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg |
|
| 1899 |
4991 d 9 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A je již zastaralá konstrukce |
Diff |
| /Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
| 1898 |
4991 d 10 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B revize desky S3AN01A (s opravami) |
Diff |
/Modules/CPLD_FPGA/S3AN01B
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01B/PCB
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01B/SCH
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB
/Modules/CPLD_FPGA/S3AN01B/VHDL |
|
| 1897 |
4991 d 10 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
S3AN01A doplněny texty |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
| 1896 |
4995 d 7 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
| 1792 |
5052 d 8 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
Ještě pracovní knihovna projektu S3AN01A |
Diff |
| /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.OLB |
|
| 1791 |
5052 d 8 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/Drill.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01A/PCB
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01A/SCH
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
| 1790 |
5052 d 9 h |
miho |
/Modules/ |
Přejmenování podstromu CPLD na CPLD_FPGA |
Diff |
| /Modules/CPLD_FPGA |
/Modules/CPLD
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/LATTICE.OBK
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/isplsi1016a.opj |
| /Modules/CPLD_FPGA/DirInfo.txt |
|
| 1062 |
6124 d 13 h |
kakl |
/Modules/CPLD/ |
|
Diff |
| /Modules/CPLD/DirInfo.txt |
|
| 1049 |
6125 d 10 h |
kakl |
/Modules/ |
|
Diff |
/Modules/CPLD/cpld_Small.jpg
/Modules/CommRF/RC_Small.jpg
/Modules/H_Bridge/stepper_Small.jpg
/Modules/Measuring/probe_Small.jpg
/Modules/OpAmps/opamp_Small.jpg
/Modules/PowerSW/fet_Small.jpg
/Modules/PowerSupply/Supply_Small.jpg
/Modules/Sensors/sensors_Small.jpg
/Modules/Universal/BASE162101A_Small.jpg |
|
| 1001 |
6147 d 7 h |
miho |
/Modules/ |
Doplněny metainformace pro sekci Modules (nejvyšší úroveň) |
Diff |
/Modules/CPLD/DirInfo.txt
/Modules/CommSerial/DirInfo.txt
/Modules/PowerSW/DirInfo.txt |
/Modules/AVR/info.cs.txt
/Modules/AVR/info.en.txt
/Modules/Audio/info.cs.txt
/Modules/Audio/info.en.txt
/Modules/CPLD/info.cs.txt
/Modules/CommIR/info.cs.txt
/Modules/CommIR/info.en.txt
/Modules/CommSerial/info.cs.txt
/Modules/H_Bridge/info.cs.txt
/Modules/H_Bridge/info.en.txt
/Modules/HumanInterfaces/info.cs.txt
/Modules/HumanInterfaces/info.en.txt |
/Modules/CommIR/DirInfo.txt
/Modules/CommRF/DirInfo.txt
/Modules/H_Bridge/DirInfo.txt
/Modules/HumanInterfaces/DirInfo.txt
/Modules/Measuring/DirInfo.txt
/Modules/OpAmps/DirInfo.txt
/Modules/PIC/DirInfo.txt
/Modules/PowerSupply/DirInfo.txt
/Modules/Sensors/DirInfo.txt
/Modules/Universal/DirInfo.txt |
|
| 927 |
6178 d 8 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD/ISPLSI1016A/SCH/LIBRARY1.OLB
/Modules/CPLD/ISPLSI1016A/SCH/isplsi1016a.opj |
|
| 926 |
6178 d 8 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OBK
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB |
|
| 923 |
6182 d 11 h |
kaklik |
/Modules/CPLD/ |
upravy schematu chybi dodelat programovaci konektor. |
Diff |
| /Modules/CPLD/info.cs.txt |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj |
| /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN |
|
| 921 |
6183 d 13 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj |
|
| 920 |
6183 d 14 h |
spirek |
/Modules/CPLD/ |
|
Diff |
/Modules/CPLD
/Modules/CPLD/ISPLSI1016A
/Modules/CPLD/ISPLSI1016A/SCH
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OBK
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB |
|