Rev Age Author Path Log message Diff
1898 4985 d 2 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4985 d 2 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4989 d 0 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4989 d 18 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 4998 d 19 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 4998 d 20 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff
1890 5001 d 0 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1888 5001 d 1 h kaklik / vygenerevani osazovaku Diff
1887 5006 d 0 h kaklik /Modules/CommSerial/ založen nový modul s ethernet konektorem. Diff
1886 5006 d 20 h kakl /Modules/TDC/GP201A/SW/PICinterface/ Prvni verze, co neco meri. Diff
1883 5009 d 20 h jacho /Modules/ pridani odkazu na UST Diff
1882 5009 d 20 h jacho /Modules/ADconverters/ADCmonoSPI01B/ pridani odkazu na ust Diff
1879 5012 d 1 h jacho / Diff
1878 5012 d 1 h jacho /Modules/AVR/ Diff
1877 5012 d 1 h jacho /Modules/AVR/ATmega801B/ Diff
1876 5012 d 1 h jacho /Modules/AVR/ATmegaTQ4401A/ Diff
1875 5012 d 1 h jacho /Modules/AVR/ATmega801B/ Diff
1874 5012 d 2 h kaklik /Modules/CommSerial/ETH01A/SCH/ vylepseni odruseni Diff
1871 5012 d 18 h kaklik /Modules/CommSerial/ETH01A/ vygenerovani zakladni obrazkove dokumentace. Diff
1870 5012 d 20 h kaklik /Modules/PIC/PIC16F87xTQ4401B/ pridani spravne cesty Diff
1866 5012 d 22 h kaklik / vytvořena buňka s okkazem do obchodu. Diff
1863 5013 d 6 h kaklik /Modules/Clock/CLKGEN01B/DOC/ napsan clanek o pripojeni CLKGEN k pocitaci. Diff
1856 5015 d 3 h kaklik /Modules/ARM/STM32F10xRxT/ pridani fotky ARMu Diff
1855 5016 d 18 h kaklik /Modules/CommSerial/ETH01A/PCB/ Dokončena hlavní část návrhu PCB. Diff
1854 5017 d 7 h kaklik / drobná SEO oprimalizace podle návrhu google. Diff
1852 5017 d 19 h kaklik /Modules/CommSerial/ETH01A/SCH/ Diff
1851 5017 d 19 h kaklik /Modules/CommSerial/ETH01A/ pokracovani v navrhu PCB pro ethernet. Diff
1850 5017 d 20 h kaklik /Modules/CommSerial/ETH01A/PCB/ Diff
1849 5017 d 21 h kaklik /Modules/CommSerial/ETH01A/PCB/ pokracovani v navrhu PCB pro ethernet. Diff
1848 5017 d 22 h kaklik /Modules/CommSerial/ETH01A/ vyreseno krizeni spoju Diff
1847 5017 d 22 h kaklik /Modules/CommSerial/ETH01A/ navrh PCB pro ethernet. Diff
1846 5017 d 23 h kaklik /Modules/CommSerial/ETH01A/ navrh PCB pro ethernet. Diff
1845 5018 d 0 h kaklik /Modules/CommSerial/ETH01A/ navrh PCB pro ethernet. Diff
1844 5018 d 0 h kaklik /Modules/ Diff
1843 5018 d 1 h kaklik /Modules/CommSerial/ETH01A/PCB/ navrh PCB pro ethernet. Diff
1842 5018 d 1 h kaklik /Modules/CommSerial/ETH01A/PCB/ navrh PCB pro ethernet. Diff
1841 5018 d 19 h kaklik /Modules/Clock/CLKGEN01B/DOC/ aktualizace dokumentce. Diff
1840 5018 d 19 h kaklik / aktualizace dokumentce. Diff
1839 5018 d 23 h kaklik /Modules/Clock/CLKGEN01B/ zacatek dokumentace Diff
1838 5019 d 5 h kaklik / zacatek dokumentace Diff