Rev Age Author Path Log message Diff Changes
1987 4938 d 11 h kaklik /Modules/ aktualizovany seznamy ssoucastek Diff
/Modules/CommSerial/USB232R01B/opravit.txt
/Modules/Memory/SDcard01B/SCH/SDCARD.BOM
/Modules/PIC/PICPROGUSB02A/SCH/BOM.pdf
/Modules/PIC/PICPROGUSB02A/SCH/BOM.xls
1986 4939 d 10 h kaklik /Modules/Memory/SDcard01B/SCH/ jumpery slouceny do skupin Diff
/Modules/Memory/SDcard01B/SCH/SDCARD.BOM
1980 4944 d 13 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ pokus o zprovozneni mericiho modu 1.
V tomto stavu ale asi nefunguje ani mereni teploty.
Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1978 4944 d 18 h kaklik /Modules/CommRF/ZIGBEE01A/ pridan popisek Diff
/Modules/CommRF/ZIGBEE01A/PrjInfo.txt
1977 4944 d 19 h kaklik /Modules/ založen nový modul pro RF směšovač.. Diff
/Modules/CommRF/RFMIX01A
/Modules/CommRF/RFMIX01A/PrjInfo.txt
/Modules/CommRF/RFMIX01A/pdf
/Modules/CommRF/RFMIX01A/pdf/AD8343.pdf
/Modules/Clock/CLKHUB02A/PrjInfo.txt
1976 4945 d 14 h kaklik /Modules/CommSerial/USBIO01A/ doplneni anglickeho popisku. Diff
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.en.pdf
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.pdf
/Modules/CommSerial/USBIO01A/PrjInfo.txt
1968 4949 d 21 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/ Doplněna PDF verze dokumentace S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf
1967 4950 d 5 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ oprava chyby ve vypoctu casu a implementace mereni teploty. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1966 4950 d 6 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prvni implementace prepoctu na realne jednotky. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/GP2.h
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1965 4950 d 9 h kaklik /Modules/TDC/GP201A/ implementace i posledni primitivy pro nastavovani registru Diff
/Modules/TDC/GP201A/DOC/datasheet.txt
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1964 4950 d 10 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prepsani cteni dat do puvodnich primitiv. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1962 4951 d 6 h kaklik /Modules/Sensors/IUC01A/ vytvoreni modulu pro proudove cidlo. Diff
/Modules/Sensors/IUC01A
/Modules/Sensors/IUC01A/CAM_DOC/IUC01.pdf
/Modules/Sensors/IUC01A/DOC/IUC01A.pdf
/Modules/Sensors/IUC01A/PCB/IUC01.pcb
/Modules/Sensors/IUC01A/SCH/IUC01.DSN
/Modules/Sensors/IUC01A/SCH/IUC01.pdf
/Modules/Sensors/IUC01A/PrjInfo.txt
1956 4951 d 16 h kaklik /Modules/PIC/PICPROGUSB02A/ vylepseni fotografii Diff
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_Big.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Small.jpg
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Big.jpg
1955 4951 d 17 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
1954 4951 d 17 h miho /Modules/CPLD_FPGA/S3AN01A/ Dokumentace pro S3AN01A (podomácku vyrobená verze) Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1953 4952 d 8 h kaklik /Modules/Clock/CLKGEN01B/DOC/SRC/ prejmenovani podle konvence Diff
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1952 4952 d 8 h kaklik /Modules/Clock/CLKGEN01B/DOC/ oprava preklepu Diff
/Modules/Clock/CLKGEN01B/DOC/DG8SAQ_emulator.cs.pdf
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1950 4956 d 21 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B doplněny obrázky (pro dokumentaci) Diff
/Modules/CPLD_FPGA/S3AN01B/DOC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg
1947 4957 d 6 h kaklik / prejmenovani souboru podle konvence Diff
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.cs.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.cs.pdf
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.pdf
1946 4957 d 11 h kaklik /Modules/PIC/PIC18F8xTQ8001A/DOC/ aktualizace dokumentace Diff
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.cs.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.en.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8x2001A.cs.pdf
1941 4959 d 19 h kaklik /Modules/H_Bridge/MPC17511HB01A/DOC/ oprava dokumentace Diff
/Modules/H_Bridge/MPC17511HB01A/DOC/MPC17511HB01A.cs.pdf
/Modules/H_Bridge/MPC17511HB01A/DOC/SRC/MPC17511HB01A.doc
1939 4961 d 17 h kaklik /Modules/Clock/CLKGEN01B/ preklad Diff
/Modules/Clock/CLKGEN01B/DOC/CLKGEN01B.en.pdf
/Modules/Clock/CLKGEN01B/opravit.txt
1937 4963 d 14 h miho /Modules/CPLD_FPGA/S3AN01B/PCB/ Aktualizovány hodnoty součástek (synchronizace se schématem). Diff
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
1936 4963 d 15 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
1935 4963 d 20 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
1934 4964 d 11 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
/Modules/Clock/CLKGEN01B/DOC/CLKGEN01B.en.pdf
/Modules/Clock/CLKGEN01B/DOC/CLKGEN.en.pdf
1933 4964 d 11 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
/Modules/Clock/CLKGEN01B/DOC/CLKGEN.en.pdf
1932 4966 d 14 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
/Modules/Clock/CLKGEN01B/DOC/DG8SAQ_emulator.cs.pdf
/Modules/Clock/CLKGEN01B/DOC/DG8SAQ_emulator.pdf
1931 4969 d 6 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1930 4969 d 10 h kaklik / preklad kodu Diff
/Designs/Tools/reflow2/SW/reflow.PJT
/Designs/Tools/reflow2/SW/reflow.hex
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1914 4979 d 14 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
/Modules/CommSerial/ETH02A/CAM_AMA/T1.pdf
/Modules/CommSerial/ETH02A/PCB/ETH02.pcb
1913 4979 d 14 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
/Modules/CommSerial/ETH02A/CAM_AMA/V2.pdf
/Modules/CommSerial/ETH02A/CAM_PROFI/V2.PHO
/Modules/CommSerial/ETH02A/PCB/ETH02.pcb
1912 4979 d 14 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
/Modules/CommSerial/ETH02A/CAM_AMA/V2.pdf
/Modules/CommSerial/ETH02A/CAM_PROFI/BOARD.PHO
/Modules/CommSerial/ETH02A/CAM_PROFI/DRILL.DRL
/Modules/CommSerial/ETH02A/CAM_PROFI/V2.PHO
/Modules/CommSerial/ETH02A/PCB/ETH02.pcb
/Modules/CommSerial/ETH02A/SCH/ETH02.DSN
/Modules/CommSerial/ETH02A/SCH/ETH02.opj
1911 4980 d 8 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
/Modules/CommSerial/ETH02A/PCB/ETH02.pcb
/Modules/CommSerial/ETH02A/SCH/ETH02.opj
/Modules/PowerSupply/klimma/Design5.opj
1910 4981 d 9 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
/Modules/ARM/STM32F10xRxT/opravit.txt
1908 4983 d 4 h klimma /Modules/PowerSupply/klimma/ Diff
/Modules/PowerSupply/klimma
/Modules/PowerSupply/klimma/DESIGN5.DSN
/Modules/PowerSupply/klimma/Design5.opj
1907 4983 d 8 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
/Modules/PowerSupply/MC3406301A/pdf
/Modules/PowerSupply/MC3406301A/pdf/MC34063A-D.PDF
1906 4984 d 20 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
/Modules/CPLD_FPGA/S3AN01A/DOC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg
1899 4985 d 12 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1898 4985 d 12 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
/Modules/CPLD_FPGA/S3AN01B
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01B/PCB
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01B/SCH
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB
/Modules/CPLD_FPGA/S3AN01B/VHDL