Rev Age Author Path Log message Diff
1805 4906 d 16 h kaklik /Designs/HAM Constructions/SDRX01B/PCB/ Diff
1804 4906 d 18 h kaklik /Designs/HAM Constructions/SDRX01B/PCB/ Diff
1803 4906 d 19 h kaklik /Designs/HAM Constructions/SDRX01B/ ve schematu aktualizovano zapojeni trimru Diff
1802 4908 d 0 h kaklik /Modules/ARM/STM32F10xRxT/ upravy ve vyliti medi. Diff
1801 4908 d 1 h kaklik /Modules/Sensors/ prejmenovani dokumentacni slozky GSENSE01A Diff
1800 4908 d 1 h kaklik /Modules/Sensors/MMA7260/DOC/ Diff
1799 4908 d 1 h kaklik /Modules/PIC/PICPROGUSB02A/DOC/ oprava nadpisu Diff
1798 4911 d 23 h kaklik / aktualizace schemat v PDF. Diff
1797 4915 d 2 h kaklik /Modules/ARM/STM32F10xRxT/ uprava potisku Diff
1796 4915 d 3 h kaklik /Modules/ARM/STM32F10xRxT/ aktualizace vyrobnich dat. Diff
1795 4915 d 13 h kaklik /Modules/CommSerial/ETH01A/ zacatek navrhu PCB. Diff
1794 4915 d 16 h kaklik /Modules/CommSerial/ETH01A/SCH/ doklesleno schema. Diff
1793 4916 d 20 h kaklik /Modules/CommSerial/ETH01A/SCH/ dokresleni schema casti na PoE.

Jeste je treba prekleslit pripojeni RJ45 konektoru.		 Diff
1792 4916 d 20 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ Ještě pracovní knihovna projektu S3AN01A Diff
1791 4916 d 20 h miho /Modules/CPLD_FPGA/S3AN01A/ Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A Diff
1790 4916 d 20 h miho /Modules/ Přejmenování podstromu CPLD na CPLD_FPGA Diff
1789 4917 d 3 h miho / Vygenerované podklady pro amatérskou výrobu plošných spojů. Diff
1788 4918 d 17 h kaklik /Designs/HAM Constructions/SDRX01B/ zapis aktualniho stavu Diff
1787 4919 d 20 h kakl /Designs/MRAKOMER4/DOC/ Zapomnel jsem na informaci, ze MM vraci -273,15 , kdyz je chyba. Diff
1786 4923 d 14 h kaklik /Modules/Translators/TTLPECL01A/ vygenerovani technologickych vystupu Diff