Rev 1542 – kaklik – 187 d 9 h (2024-02-19 21:55:10)
Repair the MLAB template.
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Rev 1542
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Diff
1542
5168 d 21 h
kaklik
/Modules/Clock/CLKGEN01A/
generovani technologickych dat.
Diff
1541
5169 d 10 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1540
5169 d 10 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1539
5169 d 10 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1538
5172 d 11 h
kaklik
/Modules/Clock/
Rozhodnuti pouzit pro CLKHUB jinou soucastku, protoze AD95010 nejde zapojit.
Diff
1537
5172 d 17 h
kaklik
/Modules/Clock/CLKHUB01A/
zacatek navrhu PCB
Diff
1536
5173 d 7 h
kaklik
/Modules/Clock/CLKHUB01A/SCH/
Temer hotove schema
Diff
1535
5182 d 14 h
kaklik
/Modules/CommSerial/USBIO01A/DOC/SRC/
fotky k modulu USBIO01A
Diff
1534
5182 d 14 h
kaklik
/Modules/CommSerial/USBIO01A/
fotky k modulu USBIO01A
Diff
1533
5182 d 14 h
kaklik
/Modules/ADconverters/ADCmonoSPI01B/
fotky k modulu ADCmonoSPI01B
Diff
1532
5184 d 18 h
kaklik
/Designs/MRAKOMER4/DOC/
oprava vecne chyby v dokumentaci
Diff
1531
5186 d 10 h
kaklik
/Modules/Clock/CLKGEN01A/
pridani chybejicich terminacnich odporu..
Diff
1530
5186 d 17 h
kaklik
/Modules/Clock/CLKGEN01A/
Temer konecna verze PCB pro Si570. Respektive Si5XX
Diff
1529
5186 d 18 h
kaklik
/Modules/Clock/CLKGEN01A/
Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru.
Diff
1528
5186 d 19 h
kaklik
/Modules/
Diff
1527
5186 d 21 h
kaklik
/Modules/Clock/CLKGEN01A/SCH/
pridani zapomenutych der a fidu znacek
Diff
1526
5187 d 11 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
Diff
1525
5187 d 12 h
kaklik
/Modules/Clock/CLKGEN01A/PCB/
zacatek prace na plosnem spoji.
Diff
1524
5187 d 16 h
kaklik
/Modules/Clock/CLKGEN01A/SCH/
export dat pro PADs.
Diff
1523
5187 d 16 h
kaklik
/Modules/Clock/CLKGEN01A/SCH/
Diff