←Prev12Next→ Show All
Rev Age Author Path Log message Diff
2550 4329 d 22 h jacho /Modules/HumanInterfaces/LED01A/ Diff
2549 4329 d 23 h jacho /Modules/H_Bridge/HBSTEP01A/DOC/ Diff
2548 4330 d 0 h jacho /Modules/H_Bridge/HBSTEP01A/ Diff
2547 4330 d 3 h jacho /Modules/Universal/ Diff
2546 4330 d 3 h jacho /Modules/Universal/ Diff
2545 4330 d 4 h jacho /Modules/Universal/ALBASE1115/ Diff
2544 4333 d 18 h kakl /Designs/HAM Constructions/SDRX01B/SW/meteor_detect/ Nazvy soboru s obrazky jsou nove pojmenovavany podle casu. Diff
2543 4335 d 18 h kaklik /Modules/CommSerial/USB232R01B/SW/FT_prog/ vytvoreni vzoru pro obsah EEPROM usb prevodniku. Diff
2542 4336 d 18 h jacho /Modules/Universal/ALBASE1115/ Diff
2541 4336 d 18 h kaklik /Modules/PowerSW/LDD01A/ informace k novym modulum. Diff
2540 4336 d 18 h jacho /Modules/Universal/ALBASE1521/ Diff
2539 4336 d 18 h jacho /Modules/Universal/ Diff
2538 4336 d 19 h jacho /Modules/Universal/ALBASE1521/ Diff
2537 4336 d 19 h jacho /Modules/Universal/ALBASE1521/ Diff
2536 4336 d 20 h jacho /Modules/Universal/ALBASE1521/ Diff
2535 4338 d 1 h kaklik /Library/grafika/ vygenerovno logo v PDF formatu. Diff
2534 4339 d 2 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. Diff
2533 4339 d 2 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pridano automaticke verzovani. Diff
2532 4340 d 0 h kaklik /Modules/PowerSW/LDD01A/SCH/ pregenerovani schema. Diff
2531 4340 d 0 h kaklik /Modules/PowerSW/LDD01A/ vygenerovany technologicke vystupy Diff