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Rev Age Author Path Log message Diff
1980 4941 d 3 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ pokus o zprovozneni mericiho modu 1.
V tomto stavu ale asi nefunguje ani mereni teploty.		 Diff
1978 4941 d 8 h kaklik /Modules/CommRF/ZIGBEE01A/ pridan popisek Diff
1977 4941 d 8 h kaklik /Modules/ založen nový modul pro RF směšovač.. Diff
1976 4942 d 4 h kaklik /Modules/CommSerial/USBIO01A/ doplneni anglickeho popisku. Diff
1968 4946 d 10 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/ Doplněna PDF verze dokumentace S3AN01A Diff
1967 4946 d 19 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ oprava chyby ve vypoctu casu a implementace mereni teploty. Diff
1966 4946 d 20 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prvni implementace prepoctu na realne jednotky. Diff
1965 4946 d 22 h kaklik /Modules/TDC/GP201A/ implementace i posledni primitivy pro nastavovani registru Diff
1964 4946 d 23 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prepsani cteni dat do puvodnich primitiv. Diff
1962 4947 d 20 h kaklik /Modules/Sensors/IUC01A/ vytvoreni modulu pro proudove cidlo. Diff
1956 4948 d 6 h kaklik /Modules/PIC/PICPROGUSB02A/ vylepseni fotografii Diff
1955 4948 d 7 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ Diff
1954 4948 d 7 h miho /Modules/CPLD_FPGA/S3AN01A/ Dokumentace pro S3AN01A (podomácku vyrobená verze) Diff
1953 4948 d 22 h kaklik /Modules/Clock/CLKGEN01B/DOC/SRC/ prejmenovani podle konvence Diff
1952 4948 d 22 h kaklik /Modules/Clock/CLKGEN01B/DOC/ oprava preklepu Diff
1950 4953 d 11 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B doplněny obrázky (pro dokumentaci) Diff
1947 4953 d 20 h kaklik / prejmenovani souboru podle konvence Diff
1946 4954 d 1 h kaklik /Modules/PIC/PIC18F8xTQ8001A/DOC/ aktualizace dokumentace Diff
1941 4956 d 8 h kaklik /Modules/H_Bridge/MPC17511HB01A/DOC/ oprava dokumentace Diff
1939 4958 d 6 h kaklik /Modules/Clock/CLKGEN01B/ preklad Diff