2534 |
4375 d 19 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ |
Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
2533 |
4375 d 19 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pridano automaticke verzovani. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd |
|
2528 |
4380 d 10 h |
kakl |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ |
Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf |
|
2338 |
4632 d 18 h |
miho |
/Modules/CPLD_FPGA/ |
Opravena cesta k ikoně |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html |
|
2337 |
4632 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/ |
Doplněna HTML verze dokumentace pro S3AN01B |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image001.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image002.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image003.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image004.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image005.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image006.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image007.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image008.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image009.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image010.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image011.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image012.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image013.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image014.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image015.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image016.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image017.png /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image018.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image019.jpg |
|
2336 |
4632 d 20 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
Aktualizovaná HW dokumentace desky S3AN01B s obvodem FPGA XILINX Sparatn3AN |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/S3AN01B_HW_Reference.cs.pdf /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_HW_Reference.cs.doc |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
2335 |
4633 d 11 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/ |
Rozepsaná dokumentace pro FPGA desku S3AN01B |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc |
|
1968 |
4871 d 2 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/ |
Doplněna PDF verze dokumentace S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf |
|
1955 |
4872 d 23 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ |
|
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg |
|
1954 |
4872 d 23 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
Dokumentace pro S3AN01A (podomácku vyrobená verze) |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc |
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
1950 |
4878 d 3 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B doplněny obrázky (pro dokumentaci) |
Diff |
/Modules/CPLD_FPGA/S3AN01B/DOC /Modules/CPLD_FPGA/S3AN01B/DOC/SRC /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg |
|
1937 |
4884 d 20 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/PCB/ |
Aktualizovány hodnoty součástek (synchronizace se schématem). |
Diff |
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb |
|
1936 |
4884 d 20 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). |
Diff |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls |
|
1935 |
4885 d 2 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/SCH/ |
Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. |
Diff |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF |
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN |
|
1906 |
4906 d 2 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A doplnění obrázků |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg |
|
1899 |
4906 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A je již zastaralá konstrukce |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
1898 |
4906 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B revize desky S3AN01A (s opravami) |
Diff |
/Modules/CPLD_FPGA/S3AN01B /Modules/CPLD_FPGA/S3AN01B/CAM_AMA /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO /Modules/CPLD_FPGA/S3AN01B/PCB /Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb /Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt /Modules/CPLD_FPGA/S3AN01B/SCH /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB /Modules/CPLD_FPGA/S3AN01B/VHDL |
|
1897 |
4906 d 18 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
S3AN01A doplněny texty |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1896 |
4910 d 15 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1792 |
4967 d 16 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
Ještě pracovní knihovna projektu S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.OLB |
|