Rev Age Author Path Log message Diff Changes
1906 4830 d 19 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
/Modules/CPLD_FPGA/S3AN01A/DOC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg
1899 4831 d 11 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1897 4831 d 11 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf
1896 4835 d 9 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf
1792 4892 d 9 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ Ještě pracovní knihovna projektu S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.OLB
1791 4892 d 10 h miho /Modules/CPLD_FPGA/S3AN01A/ Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/Drill.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01A/PCB
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01A/SCH
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf