Rev Age Author Path Log message Diff Changes
2534 4291 d 6 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2533 4291 d 6 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pridano automaticke verzovani. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2528 4295 d 20 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz.
Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf
2338 4548 d 4 h miho /Modules/CPLD_FPGA/ Opravena cesta k ikoně Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html
2337 4548 d 4 h miho /Modules/CPLD_FPGA/S3AN01B/DOC/HTML/ Doplněna HTML verze dokumentace pro S3AN01B Diff
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs.html
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image001.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image002.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image003.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image004.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image005.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image006.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image007.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image008.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image009.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image010.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image011.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image012.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image013.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image014.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image015.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image016.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image017.png
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image018.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/HTML/S3AN01B_HW_Reference.cs_soubory/image019.jpg
2336 4548 d 6 h miho /Modules/CPLD_FPGA/S3AN01B/ Aktualizovaná HW dokumentace desky S3AN01B s obvodem FPGA XILINX Sparatn3AN Diff
/Modules/CPLD_FPGA/S3AN01B/DOC/S3AN01B_HW_Reference.cs.pdf
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_HW_Reference.cs.doc
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
2335 4548 d 21 h miho /Modules/CPLD_FPGA/S3AN01B/DOC/SRC/ Rozepsaná dokumentace pro FPGA desku S3AN01B Diff
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B.cs.doc
1950 4793 d 13 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B doplněny obrázky (pro dokumentaci) Diff
/Modules/CPLD_FPGA/S3AN01B/DOC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg
1937 4800 d 6 h miho /Modules/CPLD_FPGA/S3AN01B/PCB/ Aktualizovány hodnoty součástek (synchronizace se schématem). Diff
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
1936 4800 d 6 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
1935 4800 d 12 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
1898 4822 d 4 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
/Modules/CPLD_FPGA/S3AN01B
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01B/PCB
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01B/SCH
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB
/Modules/CPLD_FPGA/S3AN01B/VHDL