Rev Age Author Path Log message Diff Changes
2534 4451 d 23 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2533 4452 d 0 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pridano automaticke verzovani. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2528 4456 d 14 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz.		 Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf
1898 4982 d 22 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
/Modules/CPLD_FPGA/S3AN01B
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01B/PCB
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01B/SCH
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB
/Modules/CPLD_FPGA/S3AN01B/VHDL