Rev Age Author Path Log message Diff
3243 3978 d 4 h kaklik /Modules/CPLD_FPGA/ uprava jmenne konvence projektovych slozek. Diff
3091 4009 d 8 h miho /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ Demo aplikace Xilinx ChipScope pro S3AN01 s použitím Xilinx Virtual Cable technologie Diff