Rev Age Author Path Log message Diff
3243 3995 d 20 h kaklik /Modules/CPLD_FPGA/ uprava jmenne konvence projektovych slozek. Diff
3091 4027 d 0 h miho /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ Demo aplikace Xilinx ChipScope pro S3AN01 s použitím Xilinx Virtual Cable technologie Diff