Rev Age Author Path Log message Diff Changes
3178 4012 d 1 h kaklik / uprava skriptu pro vyrobu qr kodu a vyroba QR kodu pro nove moduly.. Diff
/Library/DirStructure/Module/CAM_PROFI/Preview.gvp
/Modules/ARM/STM32F10xRxT01A/DOC/SRC/img/STM32F10xRxT01A_QRcode.png
/Library/Templates/PADS/DEFAULT.cam.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/img/XVC_FT220X01A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/img/XVC_FT220X02A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC/img/XVC_SOFTWARE_QRcode.png
/Modules/CommSerial/ETH01A/CAM_PROFI/ETH01A.gvp
/Modules/CommSerial/ETH01A/pdf/LM5073.pdf
/Modules/Mechanical/Boxes/UNIBOX01A/DOC/SRC/img/UNIBOX01A_QRcode.png
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC/SRC/img/RGBHD01A_QRcode.png
/ServerPrivate/Tools/generate_QR_all.sh
/Web/About.cs.html
3108 4029 d 21 h kaklik /Modules/ pridani QR kodu i v dalsich adresarich. Diff
/Modules/CPLD_FPGA/XILINX_XVC/DOC
/Modules/CPLD_FPGA/XILINX_XVC/DOC/SRC
/Modules/CPLD_FPGA/XILINX_XVC/DOC/SRC/img
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/img
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/img/XVC_FT220X01A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/img
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/img/XVC_FT220X02A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC/img
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC/img/XVC_SOFTWARE_QRcode.png
/Modules/Mechanical/Boxes/DOC
/Modules/Mechanical/Boxes/DOC/SRC
/Modules/Mechanical/Boxes/DOC/SRC/img
/Modules/Mechanical/Boxes/UNIBOX01A/DOC/SRC/img/UNIBOX01A_QRcode.png
/Modules/Sensors/RGBFEE01A/DOC
/Modules/Sensors/RGBFEE01A/DOC/SRC
/Modules/Sensors/RGBFEE01A/DOC/SRC/img
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC/SRC
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC/SRC/img
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC/SRC/img/RGBHD01A_QRcode.png
2939 4090 d 12 h miho /Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/ Dokončena dokumentace modulu XVC_FT220X02A Diff
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs.html
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image001.jpg
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image002.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image003.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image004.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image005.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image006.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image007.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image008.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/HTML/XVC_FT220X02A.cs_soubory/image009.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/!____!.txt
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A.cs.doc
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A_Bot.JPG
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/XVC_FT220X02A_Top.JPG
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/PCB/XVC_FT220X02A.pcb
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/SCH/XVC_FT220X02A_BOM.xls