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Rev Age Author Path Log message Diff Changes
3731 3682 d 11 h jacho /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PrjInfo.txt
3730 3682 d 11 h jacho /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PrjInfo.txt
3677 3812 d 5 h roman /Modules/Clock/CLKDIV01A/FZP/ add fritzing CLKDIV01A Diff
/Modules/Clock/CLKDIV01A/FZP
/Modules/Clock/CLKDIV01A/FZP/CLKDIV01A.fzpz
3620 3868 d 9 h kaklik /Modules/Clock/CLKDIV01A/ aktualizace dokumentacniho PDF od modulu. Diff
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A/DOC/CLKDIV01A.cs.pdf
/Modules/Clock/CLKDIV01A/DOC/SRC/CLKDIV01A.cs.tex
3592 3884 d 7 h kaklik /Modules/Clock/CLKDIV01A/ Opraveno oznaceni 1 u integrovaneh oobvodu. Diff
/Modules/Clock/CLKDIV01A/CAM_DOC/O2.pdf
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3509 3911 d 2 h kaklik /Modules/ pregenerovani dokumentace. Diff
/Modules/Clock/CLKDIV01A/CAM_DOC/O1.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/O2.pdf
/Modules/Sensors/IUC01A/CAM_DOC/O1.pdf
/Modules/Sensors/IUC01A/CAM_DOC/O2.pdf
/Modules/Sensors/IUC01A/CAM_DOC/V2.pdf
/Modules/ADconverters/ADCmonoSPI01B/CAM_DOC/O1.pdf
/Modules/ADconverters/ADCmonoSPI01B/CAM_DOC/O2.pdf
/Modules/ADconverters/ADCmonoSPI01B/PCB/ADCMONOSPI.pcb
/Modules/ADconverters/ADCmonoSPI01B/SCH/ADCmonoSPI01B.pdf
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/Clock/CLKDIV01A/CAM_DOC/DRILL.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V1.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V2.pdf
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/TODO.txt
/Modules/Sensors/IUC01A/CAM_DOC/V1.pdf
/Modules/Sensors/IUC01A/PCB/IUC01.pcb
3507 3911 d 20 h kaklik /Modules/ založen nový modul pro digitalizaci signálu z SDRX01B. Diff
/Modules/Audio/ADCaudio01A
/Modules/Audio/ADCaudio01A/CAM_AMA
/Modules/Audio/ADCaudio01A/CAM_DOC
/Modules/Audio/ADCaudio01A/CAM_PROFI
/Modules/Audio/ADCaudio01A/CAM_PROFI/Preview.gvp
/Modules/Audio/ADCaudio01A/DOC
/Modules/Audio/ADCaudio01A/DOC/HTML
/Modules/Audio/ADCaudio01A/DOC/SRC
/Modules/Audio/ADCaudio01A/PCB
/Modules/Audio/ADCaudio01A/PrjInfo.txt
/Modules/Audio/ADCaudio01A/SCH
/Modules/Audio/ADCaudio01A/SW
/Modules/Audio/ADCaudio01A/pdf
/Modules/Clock/CLKDIV01A/PrjInfo.txt
3475 3930 d 1 h kaklik / Pridani dalsi dokumentace. Diff
/Designs/Measuring_instruments/AWS01B/SW/PIC16F887/i2c_wind_sensor/main.hex
/Modules/Clock/CLKDIV01A/DOC/SRC/CLKDIV01A.cs.tex
3447 3957 d 4 h kaklik /Modules/Clock/CLKDIV01A/ pradani maleho obrazku modulu. Diff
/Modules/Clock/CLKDIV01A/CLKDIV01A_Top_Small.jpg
3445 3957 d 4 h kaklik / zlepseni dokumentace modulu. Diff
/Modules/ADconverters/ACOMP01A/DOC/SRC/img
/Modules/ADconverters/ACOMP01A/DOC/SRC/img/ACOMP01A_QRcode.png
/Modules/ADconverters/ADCdual01A/DOC/SRC/img
/Modules/ADconverters/ADCdual01A/DOC/SRC/img/ADCdual01A_QRcode.png
/Modules/CPLD_FPGA/S6AN01A/DOC/SRC/img
/Modules/CPLD_FPGA/S6AN01A/DOC/SRC/img/S6AN01A_QRcode.png
/Modules/Clock/CLK1PLL01A/DOC/SRC
/Modules/Clock/CLK1PLL01A/DOC/SRC/img
/Modules/Clock/CLK1PLL01A/DOC/SRC/img/CLK1PLL01A_QRcode.png
/Modules/Clock/CLKDIV01A/DOC/CLKDIV01A.cs.pdf
/Modules/Clock/CLKDIV01A/DOC/SRC/img
/Modules/Clock/CLKDIV01A/DOC/SRC/img/CLKDIV01A_QRcode.png
/Modules/Clock/CLKDIV01A/DOC/SRC/img/CLKDIV01A_Top_Big.jpg
/Modules/CommRF/FORX01A/DOC/SRC/img
/Modules/CommRF/FORX01A/DOC/SRC/img/FORX01A_QRcode.png
/Modules/CommRF/FOTX01A/DOC/SRC/img
/Modules/CommRF/FOTX01A/DOC/SRC/img/FOTX01A_QRcode.png
/Modules/CommSerial/USBI2C01A/DOC/SRC/img
/Modules/CommSerial/USBI2C01A/DOC/SRC/img/USBI2C01A_QRcode.png
/Modules/CommSerial/USBIO01A/DOC/SRC/img/USBIO01A_Bottom_Big.jpg
/Modules/CommSerial/USBIO01A/DOC/SRC/img/USBIO01A_Top_Big.jpg
/Modules/PowerSupply/BATPOWER04A/DOC/SRC/img
/Modules/PowerSupply/BATPOWER04A/DOC/SRC/img/BATPOWER04A_QRcode.png
/Modules/PowerSupply/BATPOWER04B/DOC/SRC/img
/Modules/PowerSupply/BATPOWER04B/DOC/SRC/img/BATPOWER04B_QRcode.png
/Modules/PowerSupply/CHPUMP01A/DOC/SRC/img
/Modules/PowerSupply/CHPUMP01A/DOC/SRC/img/CHPUMP01A_QRcode.png
/Modules/PowerSupply/TPS63060V01A/DOC/SRC/img
/Modules/PowerSupply/TPS63060V01A/DOC/SRC/img/TPS63060V01A_QRcode.png
/Modules/Sensors/RPS01A/DOC/SRC/img
/Modules/Sensors/RPS01A/DOC/SRC/img/RPS01A_QRcode.png
/Modules/Universal/UNISERIAL01A/DOC/SRC/img
/Modules/Universal/UNISERIAL01A/DOC/SRC/img/UNISERIAL01A_QRcode.png
/Modules/Clock/CLKDIV01A/SW
/Modules/CommSerial/USBIO01A/DOC/SRC/USBIO01A_Bottom_Big.jpg
/Modules/CommSerial/USBIO01A/DOC/SRC/USBIO01A_Top_Big.jpg
/Designs/HAM Constructions/SDRX01B/DOC/SDRX01B.cs.pdf
/Designs/Measuring_instruments/GNSS01A/DOC/SRC/GNSS_SDR.dia
/Designs/Measuring_instruments/GNSS01A/DOC/SRC/GNSS_SDR.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X01A/DOC/SRC/img/XVC_FT220X01A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/SRC/img/XVC_FT220X02A_QRcode.png
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/DOC/SRC/img/XVC_SOFTWARE_QRcode.png
/Modules/Clock/CLKDIV01A/PrjInfo.txt
/Modules/Measuring/GPS01A/TODO.txt
/Modules/Mechanical/Boxes/UNIBOX01A/DOC/SRC/img/UNIBOX01A_QRcode.png
/Modules/Sensors/RGBFEE01A/RGBHD01A/DOC/SRC/img/RGBHD01A_QRcode.png
3444 3957 d 5 h kaklik /Modules/Clock/CLKDIV01A/ zaznam chyb na modulu. Diff
/Modules/Clock/CLKDIV01A/TODO.txt
3425 3965 d 22 h kaklik / pridani dalsi dokumentace. Diff
/Designs/Laboratory_instruments/High_voltage_power_supply/pdf
/Designs/Laboratory_instruments/High_voltage_power_supply/pdf/ADuM3190.pdf
/Modules/CPLD_FPGA/S6AN01A/pdf/HDMI_connector.pdf
/Modules/Sensors/ALTIMET01A/SW/Python/dpi145_test.py
/Modules/Clock/CLKDIV01A/TODO.txt
/Modules/Clock/CLKGEN01B/pdf/Si570.pdf
/Modules/CommSerial/I2CHUB02A/TODO.txt
/Modules/H_Bridge/DRV8835HB01A/TODO.txt
/Modules/Measuring/GPS01A/TODO.txt
3404 3987 d 18 h kaklik /Modules/Clock/CLKDIV01A/ vygenerovani nahledu. Diff
/Modules/Clock/CLKDIV01A/CAM_DOC/DRILL.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V1.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V2.pdf
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3403 3987 d 18 h kaklik /Modules/Clock/CLKDIV01A/ oprava chyb z TODO. Diff
/Modules/Clock/CLKDIV01A/CAM_PROFI/DRILL.DRL
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3402 3987 d 20 h kaklik /Modules/Clock/CLKDIV01A/ zaznam nalezenych chyb.. Diff
/Modules/Clock/CLKDIV01A/TODO.txt
3401 3987 d 20 h kaklik /Modules/Clock/CLKDIV01A/ pridani popisu nalezenych chyb. Diff
/Modules/Clock/CLKDIV01A/TODO.txt
3398 3988 d 0 h kaklik /Modules/Clock/CLKDIV01A/SCH/ Diff
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
/Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf
3397 3988 d 0 h kaklik /Modules/Clock/CLKDIV01A/SCH/ Diff
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3396 3988 d 0 h kaklik /Modules/Clock/CLKDIV01A/ vygenerovanitechnologickych vystupu Diff
/Modules/Clock/CLKDIV01A/CAM_PROFI/BOARD.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/DRILL.DRL
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3395 3988 d 1 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc