| 3620 |
3856 d 19 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
aktualizace dokumentacniho PDF od modulu. |
Diff |
| /Modules/Clock/CLKDIV01A/SCH/navrh.PDF |
/Modules/Clock/CLKDIV01A/DOC/CLKDIV01A.cs.pdf
/Modules/Clock/CLKDIV01A/DOC/SRC/CLKDIV01A.cs.tex |
|
| 3398 |
3976 d 10 h |
kaklik |
/Modules/Clock/CLKDIV01A/SCH/ |
|
Diff |
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
/Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf |
|
| 3397 |
3976 d 10 h |
kaklik |
/Modules/Clock/CLKDIV01A/SCH/ |
|
Diff |
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj |
|
| 3395 |
3976 d 11 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
|
Diff |
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc |
|
| 3394 |
3976 d 12 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
ulozeni verze pred otocenim konektoru. |
Diff |
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN |
|
| 3388 |
3976 d 14 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
|
Diff |
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj |
|
| 3387 |
3976 d 15 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
|
Diff |
| /Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf |
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj |
|
| 3386 |
3976 d 18 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
aktualizace podle noveho navrhu. |
Diff |
| /Modules/Clock/CLKDIV01A/pdf/NB6L239.PDF |
| /Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf |
| /Modules/Clock/CLKDIV01A/SCH/navrh.PDF |
|
| 3384 |
3977 d 10 h |
kaklik |
/Modules/Clock/CLKDIV01A/ |
prvni schema a plosny spoj modulu delicky. |
Diff |
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj |
|
| 3383 |
3977 d 13 h |
kaklik |
/Modules/ |
zalozeni noveho modulu pro delicku hodin. |
Diff |
/Modules/CPLD_FPGA/S6AN01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A
/Modules/Clock/CLKDIV01A/CAM_AMA
/Modules/Clock/CLKDIV01A/CAM_DOC
/Modules/Clock/CLKDIV01A/CAM_PROFI
/Modules/Clock/CLKDIV01A/CAM_PROFI/Preview.gvp
/Modules/Clock/CLKDIV01A/DOC
/Modules/Clock/CLKDIV01A/DOC/HTML
/Modules/Clock/CLKDIV01A/DOC/SRC
/Modules/Clock/CLKDIV01A/PCB
/Modules/Clock/CLKDIV01A/PrjInfo.txt
/Modules/Clock/CLKDIV01A/SCH
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A/SW
/Modules/Clock/CLKDIV01A/pdf
/Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf |
|