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Rev Age Author Path Log message Diff
1572 5055 d 7 h kaklik / poznamky problemu Diff
1555 5083 d 16 h kaklik /Modules/Clock/ pokus s ladenim delky spoju Diff
1548 5094 d 3 h kaklik /Modules/Clock/ aktualizace popisu modulů. Diff
1547 5094 d 4 h kaklik /Modules/Clock/CLKGEN01A/ Fotky LO. Diff
1546 5097 d 1 h kaklik /Modules/Clock/CLKGEN01A/ seznam chyb. Diff
1545 5097 d 2 h kaklik /Modules/Clock/CLKGEN01A/ potisk Diff
1544 5098 d 3 h kaklik / Diff
1543 5098 d 3 h kaklik /Modules/Clock/CLKGEN01A/ vymena CAM vystupu Diff
1542 5098 d 5 h kaklik /Modules/Clock/CLKGEN01A/ generovani technologickych dat. Diff
1541 5098 d 17 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1540 5098 d 18 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1539 5098 d 18 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1531 5115 d 17 h kaklik /Modules/Clock/CLKGEN01A/ pridani chybejicich terminacnich odporu.. Diff
1530 5116 d 0 h kaklik /Modules/Clock/CLKGEN01A/ Temer konecna verze PCB pro Si570. Respektive Si5XX Diff
1529 5116 d 2 h kaklik /Modules/Clock/CLKGEN01A/ Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru. Diff
1528 5116 d 3 h kaklik /Modules/ Diff
1527 5116 d 4 h kaklik /Modules/Clock/CLKGEN01A/SCH/ pridani zapomenutych der a fidu znacek Diff
1526 5116 d 19 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1525 5116 d 19 h kaklik /Modules/Clock/CLKGEN01A/PCB/ zacatek prace na plosnem spoji. Diff
1524 5117 d 0 h kaklik /Modules/Clock/CLKGEN01A/SCH/ export dat pro PADs. Diff