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Rev Age Author Path Log message Diff Changes
1977 4948 d 9 h kaklik /Modules/ založen nový modul pro RF směšovač.. Diff
/Modules/CommRF/RFMIX01A
/Modules/CommRF/RFMIX01A/PrjInfo.txt
/Modules/CommRF/RFMIX01A/pdf
/Modules/CommRF/RFMIX01A/pdf/AD8343.pdf
/Modules/Clock/CLKHUB02A/PrjInfo.txt
1976 4949 d 4 h kaklik /Modules/CommSerial/USBIO01A/ doplneni anglickeho popisku. Diff
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.en.pdf
/Modules/CommSerial/USBIO01A/DOC/USBIO01A.pdf
/Modules/CommSerial/USBIO01A/PrjInfo.txt
1968 4953 d 11 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/ Doplněna PDF verze dokumentace S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/S3AN01A.cs.pdf
1967 4953 d 19 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ oprava chyby ve vypoctu casu a implementace mereni teploty. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1966 4953 d 20 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prvni implementace prepoctu na realne jednotky. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/GP2.h
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
1965 4953 d 23 h kaklik /Modules/TDC/GP201A/ implementace i posledni primitivy pro nastavovani registru Diff
/Modules/TDC/GP201A/DOC/datasheet.txt
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1964 4954 d 0 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ prepsani cteni dat do puvodnich primitiv. Diff
/Modules/TDC/GP201A/SW/PICinterface/GP2.c
/Modules/TDC/GP201A/SW/PICinterface/main.c
/Modules/TDC/GP201A/SW/PICinterface/main.hex
/Modules/TDC/GP201A/SW/PICinterface/main.pjt
1962 4954 d 20 h kaklik /Modules/Sensors/IUC01A/ vytvoreni modulu pro proudove cidlo. Diff
/Modules/Sensors/IUC01A
/Modules/Sensors/IUC01A/CAM_DOC/IUC01.pdf
/Modules/Sensors/IUC01A/DOC/IUC01A.pdf
/Modules/Sensors/IUC01A/PCB/IUC01.pcb
/Modules/Sensors/IUC01A/SCH/IUC01.DSN
/Modules/Sensors/IUC01A/SCH/IUC01.pdf
/Modules/Sensors/IUC01A/PrjInfo.txt
1956 4955 d 6 h kaklik /Modules/PIC/PICPROGUSB02A/ vylepseni fotografii Diff
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_Big.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Small.jpg
/Modules/PIC/PICPROGUSB02A/DOC/SRC/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_.Small.jpg
/Modules/PIC/PICPROGUSB02A/PICPROGUSB02A_Top_Big.jpg
1955 4955 d 7 h miho /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/ Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg
1954 4955 d 7 h miho /Modules/CPLD_FPGA/S3AN01A/ Dokumentace pro S3AN01A (podomácku vyrobená verze) Diff
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A.cs.html
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image001.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image002.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image003.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image004.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image005.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image006.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image007.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image008.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image009.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/HTML/S3AN01A_files/image010.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2a.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Drát2b.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/NákresSpoje.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Potisk.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/S3AN01A_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje1.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Spoje2.png
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka1.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Picures/Vrtačka2.jpg
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A.cs.doc
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1953 4955 d 22 h kaklik /Modules/Clock/CLKGEN01B/DOC/SRC/ prejmenovani podle konvence Diff
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.cs.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/CLKGEN.tex
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1952 4955 d 22 h kaklik /Modules/Clock/CLKGEN01B/DOC/ oprava preklepu Diff
/Modules/Clock/CLKGEN01B/DOC/DG8SAQ_emulator.cs.pdf
/Modules/Clock/CLKGEN01B/DOC/SRC/DG8SAQ_emulator.tex
1950 4960 d 12 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B doplněny obrázky (pro dokumentaci) Diff
/Modules/CPLD_FPGA/S3AN01B/DOC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Big.jpg
/Modules/CPLD_FPGA/S3AN01B/DOC/SRC/S3AN01B_Top_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Bot_Small.jpg
/Modules/CPLD_FPGA/S3AN01B/S3AN01B_Top_Small.jpg
1947 4960 d 20 h kaklik / prejmenovani souboru podle konvence Diff
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.cs.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.cs.pdf
/Designs/STOPWATCH02A/DOC/STOPWATCH02A.pdf
/Modules/PIC/PICPROGUSB02A/DOC/PICPROGUSB02A.pdf
1946 4961 d 1 h kaklik /Modules/PIC/PIC18F8xTQ8001A/DOC/ aktualizace dokumentace Diff
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.cs.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8xTQ8001A.en.pdf
/Modules/PIC/PIC18F8xTQ8001A/DOC/PIC18F8x2001A.cs.pdf
1941 4963 d 9 h kaklik /Modules/H_Bridge/MPC17511HB01A/DOC/ oprava dokumentace Diff
/Modules/H_Bridge/MPC17511HB01A/DOC/MPC17511HB01A.cs.pdf
/Modules/H_Bridge/MPC17511HB01A/DOC/SRC/MPC17511HB01A.doc
1939 4965 d 7 h kaklik /Modules/Clock/CLKGEN01B/ preklad Diff
/Modules/Clock/CLKGEN01B/DOC/CLKGEN01B.en.pdf
/Modules/Clock/CLKGEN01B/opravit.txt
1937 4967 d 4 h miho /Modules/CPLD_FPGA/S3AN01B/PCB/ Aktualizovány hodnoty součástek (synchronizace se schématem). Diff
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
1936 4967 d 5 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizovaný seznam součástek a cenový přehled (nutno doplnit reálnou cenu PCB z faktury). Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls