Rev 1828 – ?author? – ?age? (?date?)
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Modules/
@ 1884
Rev 1828
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Log message
Diff
1798
4958 d 3 h
kaklik
/
aktualizace schemat v PDF.
Diff
1797
4961 d 7 h
kaklik
/Modules/ARM/STM32F10xRxT/
uprava potisku
Diff
1796
4961 d 7 h
kaklik
/Modules/ARM/STM32F10xRxT/
aktualizace vyrobnich dat.
Diff
1795
4961 d 17 h
kaklik
/Modules/CommSerial/ETH01A/
zacatek navrhu PCB.
Diff
1794
4961 d 21 h
kaklik
/Modules/CommSerial/ETH01A/SCH/
doklesleno schema.
Diff
1793
4963 d 0 h
kaklik
/Modules/CommSerial/ETH01A/SCH/
dokresleni schema casti na PoE.
Jeste je treba prekleslit pripojeni RJ45 konektoru.
Diff
1792
4963 d 0 h
miho
/Modules/CPLD_FPGA/S3AN01A/SCH/
Ještě pracovní knihovna projektu S3AN01A
Diff
1791
4963 d 0 h
miho
/Modules/CPLD_FPGA/S3AN01A/
Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A
Diff
1790
4963 d 1 h
miho
/Modules/
Přejmenování podstromu CPLD na CPLD_FPGA
Diff
1789
4963 d 7 h
miho
/
Vygenerované podklady pro amatérskou výrobu plošných spojů.
Diff
1786
4969 d 18 h
kaklik
/Modules/Translators/TTLPECL01A/
vygenerovani technologickych vystupu
Diff
1785
4969 d 19 h
kaklik
/Modules/Translators/TTLPECL01A/PCB/
Diff
1784
4969 d 19 h
kaklik
/
zacatek navrhu spoje.
Diff
1783
4970 d 0 h
kaklik
/Modules/Translators/TTLPECL01A/DOC/
Zalozena nоvá třída modulů pro převod signálových úrovní.
Diff
1782
4970 d 0 h
kaklik
/
presunuti mezi nove zavedeny typ modulu.
Diff
1781
4970 d 1 h
kaklik
/
Zalozena nоvá třída modulů pro převod signálových úrovní.
Diff
1780
4970 d 20 h
kaklik
/
vytvoren modul pro vlhkostni cidlo.
Diff
1779
4970 d 21 h
kaklik
/Modules/Sensors/HUM01A/PCB/
zakladni verze PCB
Diff
1778
4970 d 23 h
kaklik
/Modules/
zalozen novy modul - na mereni vlhkosti.
Diff
1775
4974 d 0 h
kaklik
/Modules/TDC/GP201A/SW/PICinterface/
TDC nwmwri ani v modu 1
Diff