Rev 1839 – ?author? – ?age? (?date?)
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Modules/
Rev 1839
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Age
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Log message
Diff
1810
4947 d 8 h
kaklik
/
aktualizace odmaskování. Odstaraněno odmaskování VIA
Diff
1809
4947 d 16 h
kaklik
/
drobné úpravy a vygenerování technologických výstupů
Diff
1808
4948 d 6 h
kaklik
/Modules/Clock/CLKGEN01B/PCB/
přidání prokovů
Diff
1802
4949 d 17 h
kaklik
/Modules/ARM/STM32F10xRxT/
upravy ve vyliti medi.
Diff
1801
4949 d 18 h
kaklik
/Modules/Sensors/
prejmenovani dokumentacni slozky GSENSE01A
Diff
1800
4949 d 18 h
kaklik
/Modules/Sensors/MMA7260/DOC/
Diff
1799
4949 d 18 h
kaklik
/Modules/PIC/PICPROGUSB02A/DOC/
oprava nadpisu
Diff
1798
4953 d 15 h
kaklik
/
aktualizace schemat v PDF.
Diff
1797
4956 d 19 h
kaklik
/Modules/ARM/STM32F10xRxT/
uprava potisku
Diff
1796
4956 d 19 h
kaklik
/Modules/ARM/STM32F10xRxT/
aktualizace vyrobnich dat.
Diff
1795
4957 d 6 h
kaklik
/Modules/CommSerial/ETH01A/
zacatek navrhu PCB.
Diff
1794
4957 d 9 h
kaklik
/Modules/CommSerial/ETH01A/SCH/
doklesleno schema.
Diff
1793
4958 d 12 h
kaklik
/Modules/CommSerial/ETH01A/SCH/
dokresleni schema casti na PoE.
Jeste je treba prekleslit pripojeni RJ45 konektoru.
Diff
1792
4958 d 13 h
miho
/Modules/CPLD_FPGA/S3AN01A/SCH/
Ještě pracovní knihovna projektu S3AN01A
Diff
1791
4958 d 13 h
miho
/Modules/CPLD_FPGA/S3AN01A/
Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A
Diff
1790
4958 d 13 h
miho
/Modules/
Přejmenování podstromu CPLD na CPLD_FPGA
Diff
1789
4958 d 19 h
miho
/
Vygenerované podklady pro amatérskou výrobu plošných spojů.
Diff
1786
4965 d 7 h
kaklik
/Modules/Translators/TTLPECL01A/
vygenerovani technologickych vystupu
Diff
1785
4965 d 7 h
kaklik
/Modules/Translators/TTLPECL01A/PCB/
Diff
1784
4965 d 8 h
kaklik
/
zacatek navrhu spoje.
Diff