Rev Age Author Path Log message Diff Changes
3421 4008 d 1 h kaklik / vylepseni dokumentace. Diff
/Modules/CommSerial/TBPCIE01A/pdf/konektory/MB-0248-1E_DP3.pdf
/Modules/CommSerial/TBPCIE01A/pdf/thunderbolt-technology-brief.pdf
/Modules/PowerSupply/BATPOWER04B/pdf/15mq040n.pdf
/Modules/Universal/UNISERIAL01A/CAM_DOC
/Modules/Universal/UNISERIAL01A/CAM_DOC/O1.pdf
/Modules/Universal/UNISERIAL01A/CAM_DOC/O2.pdf
/Modules/Universal/UNISERIAL01A/CAM_DOC/SCH.pdf
/Modules/Universal/UNISERIAL01A/CAM_DOC/V2.pdf
/Modules/Universal/UNISERIAL01A/DOC
/Modules/Universal/UNISERIAL01A/DOC/SRC
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.aux
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.log
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.out
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.pdf
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.synctex.gz
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.tex
/Modules/Universal/UNISERIAL01A/DOC/SRC/UNISERIAL01A.cs.toc
/Modules/Universal/UNISERIAL01A/PrjInfo.txt
/Modules/Universal/UNISERIAL01A/sch&pcb/UNISERIAL01A_PCB1.pdf
/Modules/Universal/UNISERIAL01A/sch&pcb/UNISERIAL01A_PCB2.pdf
/Modules/Universal/UNISERIAL01A/sch&pcb/UNISERIAL01A_PCB4.pdf
/Modules/Universal/UNISERIAL01A/sch&pcb/UNISERIAL01A_SCH.pdf
/Designs/HAM Constructions/SDRX01B/DOC/SRC/SDRX01B.cs.tex
/Designs/Measuring_instruments/RMDS01B/SW/timemark/main.c
/Designs/Measuring_instruments/RMDS01B/SW/timemark/main.hex
/Designs/Measuring_instruments/RMDS01B/SW/timemark/main.pjt
/Modules/ARM/STM32F10xRxT01A/DOC/SRC/STM32F10xRxT.cs.tex
/Modules/Clock/CLKHUB02A/DOC/SRC/CLKHUB02A.cs.tex
3404 4027 d 16 h kaklik /Modules/Clock/CLKDIV01A/ vygenerovani nahledu. Diff
/Modules/Clock/CLKDIV01A/CAM_DOC/DRILL.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V1.pdf
/Modules/Clock/CLKDIV01A/CAM_DOC/V2.pdf
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3403 4027 d 17 h kaklik /Modules/Clock/CLKDIV01A/ oprava chyb z TODO. Diff
/Modules/Clock/CLKDIV01A/CAM_PROFI/DRILL.DRL
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3402 4027 d 18 h kaklik /Modules/Clock/CLKDIV01A/ zaznam nalezenych chyb.. Diff
/Modules/Clock/CLKDIV01A/TODO.txt
3401 4027 d 18 h kaklik /Modules/Clock/CLKDIV01A/ pridani popisu nalezenych chyb. Diff
/Modules/Clock/CLKDIV01A/TODO.txt
3398 4027 d 22 h kaklik /Modules/Clock/CLKDIV01A/SCH/ Diff
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
/Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf
3397 4027 d 22 h kaklik /Modules/Clock/CLKDIV01A/SCH/ Diff
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3396 4027 d 23 h kaklik /Modules/Clock/CLKDIV01A/ vygenerovanitechnologickych vystupu Diff
/Modules/Clock/CLKDIV01A/CAM_PROFI/BOARD.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/DRILL.DRL
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3395 4027 d 23 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
3394 4028 d 0 h kaklik /Modules/Clock/CLKDIV01A/ ulozeni verze pred otocenim konektoru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
3393 4028 d 1 h kaklik /Modules/Clock/CLKDIV01A/PCB/ zapojeni diff paru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3392 4028 d 1 h kaklik /Modules/Clock/CLKDIV01A/PCB/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3391 4028 d 1 h kaklik /Modules/Clock/CLKDIV01A/PCB/ prvni slusne zapojeni diferencialnich paru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3389 4028 d 2 h kaklik /Modules/Clock/CLKDIV01A/PCB/ otoceni a srovnani konektoru Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3388 4028 d 2 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3387 4028 d 3 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3386 4028 d 6 h kaklik /Modules/Clock/CLKDIV01A/ aktualizace podle noveho navrhu. Diff
/Modules/Clock/CLKDIV01A/pdf/NB6L239.PDF
/Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
3385 4028 d 22 h kaklik /Modules/Clock/CLKDIV01A/PCB/ zkouska zaroutovatelnosti. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3384 4028 d 22 h kaklik /Modules/Clock/CLKDIV01A/ prvni schema a plosny spoj modulu delicky. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3383 4029 d 1 h kaklik /Modules/ zalozeni noveho modulu pro delicku hodin. Diff
/Modules/CPLD_FPGA/S6AN01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A
/Modules/Clock/CLKDIV01A/CAM_AMA
/Modules/Clock/CLKDIV01A/CAM_DOC
/Modules/Clock/CLKDIV01A/CAM_PROFI
/Modules/Clock/CLKDIV01A/CAM_PROFI/Preview.gvp
/Modules/Clock/CLKDIV01A/DOC
/Modules/Clock/CLKDIV01A/DOC/HTML
/Modules/Clock/CLKDIV01A/DOC/SRC
/Modules/Clock/CLKDIV01A/PCB
/Modules/Clock/CLKDIV01A/PrjInfo.txt
/Modules/Clock/CLKDIV01A/SCH
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A/SW
/Modules/Clock/CLKDIV01A/pdf
/Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf