Rev Age Author Path Log message Diff
1572 5083 d 8 h kaklik / poznamky problemu Diff
1555 5111 d 16 h kaklik /Modules/Clock/ pokus s ladenim delky spoju Diff
1548 5122 d 4 h kaklik /Modules/Clock/ aktualizace popisu modulů. Diff
1547 5122 d 5 h kaklik /Modules/Clock/CLKGEN01A/ Fotky LO. Diff
1546 5125 d 1 h kaklik /Modules/Clock/CLKGEN01A/ seznam chyb. Diff
1545 5125 d 3 h kaklik /Modules/Clock/CLKGEN01A/ potisk Diff
1544 5126 d 3 h kaklik / Diff
1543 5126 d 4 h kaklik /Modules/Clock/CLKGEN01A/ vymena CAM vystupu Diff
1542 5126 d 5 h kaklik /Modules/Clock/CLKGEN01A/ generovani technologickych dat. Diff
1541 5126 d 18 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1540 5126 d 18 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1539 5126 d 18 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1531 5143 d 18 h kaklik /Modules/Clock/CLKGEN01A/ pridani chybejicich terminacnich odporu.. Diff
1530 5144 d 1 h kaklik /Modules/Clock/CLKGEN01A/ Temer konecna verze PCB pro Si570. Respektive Si5XX Diff
1529 5144 d 2 h kaklik /Modules/Clock/CLKGEN01A/ Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru. Diff
1528 5144 d 3 h kaklik /Modules/ Diff
1527 5144 d 5 h kaklik /Modules/Clock/CLKGEN01A/SCH/ pridani zapomenutych der a fidu znacek Diff
1526 5144 d 19 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1525 5144 d 20 h kaklik /Modules/Clock/CLKGEN01A/PCB/ zacatek prace na plosnem spoji. Diff
1524 5145 d 0 h kaklik /Modules/Clock/CLKGEN01A/SCH/ export dat pro PADs. Diff