| 4567 |
3135 d 10 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
oprava manipulace s listy. |
Diff |
| 4566 |
3135 d 11 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
oprava listu. |
Diff |
| 4565 |
3135 d 11 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
zmena parametru na list. |
Diff |
| 4563 |
3136 d 10 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
zmena nastaveni spi. |
Diff |
| 4561 |
3137 d 17 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
oprava adresace SPI rozhraní na ODROID-C1. |
Diff |
| 4557 |
3142 d 9 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
programovani testovaciho kodu pro prime pripojeni na SPI sbernici. |
Diff |
| 4552 |
3143 d 20 h |
jacho |
/Modules/ |
|
Diff |
| 4532 |
3161 d 16 h |
kaklik |
/Modules/H_Bridge/HBSTEP01B/SW/ |
testovaci kod pro hbstep. |
Diff |
| 4516 |
3165 d 19 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/ |
pregenerovani vyrobnich dat s pridanim potisku spodni strany. |
Diff |
| 4515 |
3165 d 19 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/CAM_PROFI/PANEL/ |
pridani spodniho potisku. |
Diff |
| 4514 |
3165 d 20 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/CAM_PROFI/PANEL/ |
vygenerovani panelu. |
Diff |
| 4513 |
3165 d 20 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/ |
oprava pahylu u hrebinku. |
Diff |
| 4512 |
3165 d 20 h |
kaklik |
/Modules/ |
pregenerovani vyrobnich dat. |
Diff |
| 4511 |
3165 d 20 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/CAM_PROFI/ |
odebrani spatneho souboru. |
Diff |
| 4510 |
3165 d 20 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/SCH_PCB/ |
odebrani nepotrebneho souboru. |
Diff |
| 4509 |
3165 d 20 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/ |
Vylepseni layoutu, popisku a vygenerovani vyrobnich podkladu. |
Diff |
| 4507 |
3165 d 23 h |
NojbyBE3D |
/Modules/H_Bridge/HBSTEP02A/SCH_PCB/ |
layout update |
Diff |
| 4506 |
3166 d 20 h |
NojbyBE3D |
/Modules/H_Bridge/HBSTEP02A/SCH_PCB/ |
prvni cast pcb |
Diff |
| 4505 |
3168 d 16 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/SCH_PCB/ |
ulozeni projektu. |
Diff |
| 4504 |
3168 d 16 h |
kaklik |
/Modules/H_Bridge/HBSTEP02A/ |
nakresleno schema.
Vygenerovan netlist a zalozen PCB. |
Diff |