Rev Age Author Path Log message Diff
1751 5059 d 8 h kaklik / zaznam nalezenych chyb Diff
1745 5062 d 10 h kakl /Modules/TDC/GP201A/SW/PICinterface/ prvni verze funkcni komunikace s TDC. Zbyva doresit nastavovani registru. Diff
1744 5063 d 2 h kakl /Modules/TDC/GP201A/ opravena chyba v popisu napajeni. zacatek psani firmwaru Diff
1743 5064 d 2 h kakl /Modules/CommSerial/ETH01A/ Vytvořena první část schéma pro Ethernet modul. Chybí PoE část a dokreslení ETH konektoru. Diff
1742 5064 d 13 h kaklik /Modules/ADconverters/ADCmonoPPI01A/ nalezene chyby Diff
1741 5064 d 15 h kakl /Modules/PIC/PIC18F8xTQ8001A/ vylepseni osazovaku Diff
1740 5065 d 11 h kakl /Modules/ opravy PCB Diff
1739 5066 d 3 h kakl /Modules/ARM/STM32F10xRxT/ Uprava PCB Diff
1738 5067 d 3 h kaklik /Modules/ARM/STM32F10xRxT/PCB/ zbyva vyhazet nove zmrsene cesty. Diff
1737 5067 d 4 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1736 5067 d 5 h kaklik /Modules/ARM/STM32F10xRxT/ meziverze se synchronizaci schematu a PCB. Diff
1727 5069 d 12 h kaklik /Modules/ARM/STM32F10xRxT/ vylepseni dokumentace. Diff
1718 5079 d 9 h kaklik / Opravy a doplneni Diff
1717 5080 d 4 h kaklik /Modules/PIC/PIC18F8xTQ8001A/ oprava potisku Diff
1715 5080 d 10 h kaklik /Modules/Clock/CLKGEN01A/ Diff
1714 5080 d 18 h kaklik /Modules/ARM/STM32F10xRxT/ priprava novych modulu. Diff
1713 5081 d 13 h kaklik / priprava novych modulu. Diff
1712 5082 d 3 h kaklik /Modules/Clock/CLKGEN01B/ Diff
1711 5082 d 3 h kaklik /Modules/Clock/CLKGEN01B/ uprava zemeni a rozlozeni soucastek Diff
1708 5083 d 12 h mija /Modules/ARM/STM32F10xRxT/ Diff