Rev Age Author Path Log message Diff
1898 4988 d 18 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4988 d 18 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4992 d 16 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4993 d 11 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 5002 d 11 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 5002 d 12 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff
1890 5004 d 16 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1888 5004 d 18 h kaklik / vygenerevani osazovaku Diff
1887 5009 d 16 h kaklik /Modules/CommSerial/ založen nový modul s ethernet konektorem. Diff
1886 5010 d 12 h kakl /Modules/TDC/GP201A/SW/PICinterface/ Prvni verze, co neco meri. Diff
1883 5013 d 13 h jacho /Modules/ pridani odkazu na UST Diff
1882 5013 d 13 h jacho /Modules/ADconverters/ADCmonoSPI01B/ pridani odkazu na ust Diff
1879 5015 d 17 h jacho / Diff
1878 5015 d 17 h jacho /Modules/AVR/ Diff
1877 5015 d 17 h jacho /Modules/AVR/ATmega801B/ Diff
1876 5015 d 17 h jacho /Modules/AVR/ATmegaTQ4401A/ Diff
1875 5015 d 18 h jacho /Modules/AVR/ATmega801B/ Diff
1874 5015 d 18 h kaklik /Modules/CommSerial/ETH01A/SCH/ vylepseni odruseni Diff
1871 5016 d 10 h kaklik /Modules/CommSerial/ETH01A/ vygenerovani zakladni obrazkove dokumentace. Diff
1870 5016 d 12 h kaklik /Modules/PIC/PIC16F87xTQ4401B/ pridani spravne cesty Diff