Rev Age Author Path Log message Diff
1932 4958 d 13 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
1931 4961 d 5 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
1930 4961 d 9 h kaklik / preklad kodu Diff
1914 4971 d 13 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
1913 4971 d 13 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1912 4971 d 14 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1911 4972 d 7 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
1910 4973 d 8 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
1908 4975 d 3 h klimma /Modules/PowerSupply/klimma/ Diff
1907 4975 d 7 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
1906 4976 d 19 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
1899 4977 d 11 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
1898 4977 d 11 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4977 d 11 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4981 d 9 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4982 d 3 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 4991 d 4 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 4991 d 5 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff
1890 4993 d 9 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1888 4993 d 11 h kaklik / vygenerevani osazovaku Diff