Rev Age Author Path Log message Diff
1934 4967 d 8 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1933 4967 d 8 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1932 4969 d 11 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
1931 4972 d 3 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
1930 4972 d 7 h kaklik / preklad kodu Diff
1914 4982 d 11 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
1913 4982 d 11 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1912 4982 d 12 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1911 4983 d 5 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
1910 4984 d 6 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
1908 4986 d 1 h klimma /Modules/PowerSupply/klimma/ Diff
1907 4986 d 6 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
1906 4987 d 17 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
1899 4988 d 9 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
1898 4988 d 9 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4988 d 9 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4992 d 7 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4993 d 2 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 5002 d 2 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 5002 d 3 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff